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nv50/ir: handle new DDIV op which will be used for double divisions
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "tgsi/tgsi_dump.h"
24 #include "tgsi/tgsi_scan.h"
25 #include "tgsi/tgsi_util.h"
26
27 #include <set>
28
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_util.h"
31 #include "codegen/nv50_ir_build_util.h"
32
33 namespace tgsi {
34
35 class Source;
36
37 static nv50_ir::operation translateOpcode(uint opcode);
38 static nv50_ir::DataFile translateFile(uint file);
39 static nv50_ir::TexTarget translateTexture(uint texTarg);
40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
41 static nv50_ir::CacheMode translateCacheMode(uint qualifier);
42 static nv50_ir::ImgFormat translateImgFormat(uint format);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 int getArrayId() const
101 {
102 if (isIndirect(0))
103 return fsr->Indirect.ArrayID;
104 return 0;
105 }
106
107 nv50_ir::Modifier getMod(int chan) const;
108
109 SrcRegister getIndirect(int dim) const
110 {
111 assert(fsr && isIndirect(dim));
112 if (dim)
113 return SrcRegister(fsr->DimIndirect);
114 return SrcRegister(fsr->Indirect);
115 }
116
117 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
118 {
119 assert(reg.File == TGSI_FILE_IMMEDIATE);
120 assert(!reg.Absolute);
121 assert(!reg.Negate);
122 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
123 }
124
125 private:
126 const struct tgsi_src_register reg;
127 const struct tgsi_full_src_register *fsr;
128 };
129
130 class DstRegister
131 {
132 public:
133 DstRegister(const struct tgsi_full_dst_register *dst)
134 : reg(dst->Register),
135 fdr(dst)
136 { }
137
138 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
139
140 uint getFile() const { return reg.File; }
141
142 bool is2D() const { return reg.Dimension; }
143
144 bool isIndirect(int dim) const
145 {
146 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
147 }
148
149 int getIndex(int dim) const
150 {
151 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
152 }
153
154 unsigned int getMask() const { return reg.WriteMask; }
155
156 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
157
158 SrcRegister getIndirect(int dim) const
159 {
160 assert(fdr && isIndirect(dim));
161 if (dim)
162 return SrcRegister(fdr->DimIndirect);
163 return SrcRegister(fdr->Indirect);
164 }
165
166 int getArrayId() const
167 {
168 if (isIndirect(0))
169 return fdr->Indirect.ArrayID;
170 return 0;
171 }
172
173 private:
174 const struct tgsi_dst_register reg;
175 const struct tgsi_full_dst_register *fdr;
176 };
177
178 inline uint getOpcode() const { return insn->Instruction.Opcode; }
179
180 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
181 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
182
183 // mask of used components of source s
184 unsigned int srcMask(unsigned int s) const;
185 unsigned int texOffsetMask() const;
186
187 SrcRegister getSrc(unsigned int s) const
188 {
189 assert(s < srcCount());
190 return SrcRegister(&insn->Src[s]);
191 }
192
193 DstRegister getDst(unsigned int d) const
194 {
195 assert(d < dstCount());
196 return DstRegister(&insn->Dst[d]);
197 }
198
199 SrcRegister getTexOffset(unsigned int i) const
200 {
201 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
202 return SrcRegister(insn->TexOffsets[i]);
203 }
204
205 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
206
207 bool checkDstSrcAliasing() const;
208
209 inline nv50_ir::operation getOP() const {
210 return translateOpcode(getOpcode()); }
211
212 nv50_ir::DataType inferSrcType() const;
213 nv50_ir::DataType inferDstType() const;
214
215 nv50_ir::CondCode getSetCond() const;
216
217 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
218
219 nv50_ir::CacheMode getCacheMode() const {
220 if (!insn->Instruction.Memory)
221 return nv50_ir::CACHE_CA;
222 return translateCacheMode(insn->Memory.Qualifier);
223 }
224
225 inline uint getLabel() { return insn->Label.Label; }
226
227 unsigned getSaturate() const { return insn->Instruction.Saturate; }
228
229 void print() const
230 {
231 tgsi_dump_instruction(insn, 1);
232 }
233
234 private:
235 const struct tgsi_full_instruction *insn;
236 };
237
238 unsigned int Instruction::texOffsetMask() const
239 {
240 const struct tgsi_instruction_texture *tex = &insn->Texture;
241 assert(insn->Instruction.Texture);
242
243 switch (tex->Texture) {
244 case TGSI_TEXTURE_BUFFER:
245 case TGSI_TEXTURE_1D:
246 case TGSI_TEXTURE_SHADOW1D:
247 case TGSI_TEXTURE_1D_ARRAY:
248 case TGSI_TEXTURE_SHADOW1D_ARRAY:
249 return 0x1;
250 case TGSI_TEXTURE_2D:
251 case TGSI_TEXTURE_SHADOW2D:
252 case TGSI_TEXTURE_2D_ARRAY:
253 case TGSI_TEXTURE_SHADOW2D_ARRAY:
254 case TGSI_TEXTURE_RECT:
255 case TGSI_TEXTURE_SHADOWRECT:
256 case TGSI_TEXTURE_2D_MSAA:
257 case TGSI_TEXTURE_2D_ARRAY_MSAA:
258 return 0x3;
259 case TGSI_TEXTURE_3D:
260 return 0x7;
261 default:
262 assert(!"Unexpected texture target");
263 return 0xf;
264 }
265 }
266
267 unsigned int Instruction::srcMask(unsigned int s) const
268 {
269 unsigned int mask = insn->Dst[0].Register.WriteMask;
270
271 switch (insn->Instruction.Opcode) {
272 case TGSI_OPCODE_COS:
273 case TGSI_OPCODE_SIN:
274 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
275 case TGSI_OPCODE_DP2:
276 return 0x3;
277 case TGSI_OPCODE_DP3:
278 return 0x7;
279 case TGSI_OPCODE_DP4:
280 case TGSI_OPCODE_DPH:
281 case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
282 return 0xf;
283 case TGSI_OPCODE_DST:
284 return mask & (s ? 0xa : 0x6);
285 case TGSI_OPCODE_EX2:
286 case TGSI_OPCODE_EXP:
287 case TGSI_OPCODE_LG2:
288 case TGSI_OPCODE_LOG:
289 case TGSI_OPCODE_POW:
290 case TGSI_OPCODE_RCP:
291 case TGSI_OPCODE_RSQ:
292 case TGSI_OPCODE_SCS:
293 return 0x1;
294 case TGSI_OPCODE_IF:
295 case TGSI_OPCODE_UIF:
296 return 0x1;
297 case TGSI_OPCODE_LIT:
298 return 0xb;
299 case TGSI_OPCODE_TEX2:
300 case TGSI_OPCODE_TXB2:
301 case TGSI_OPCODE_TXL2:
302 return (s == 0) ? 0xf : 0x3;
303 case TGSI_OPCODE_TEX:
304 case TGSI_OPCODE_TXB:
305 case TGSI_OPCODE_TXD:
306 case TGSI_OPCODE_TXL:
307 case TGSI_OPCODE_TXP:
308 case TGSI_OPCODE_LODQ:
309 {
310 const struct tgsi_instruction_texture *tex = &insn->Texture;
311
312 assert(insn->Instruction.Texture);
313
314 mask = 0x7;
315 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
316 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
317 mask |= 0x8; /* bias, lod or proj */
318
319 switch (tex->Texture) {
320 case TGSI_TEXTURE_1D:
321 mask &= 0x9;
322 break;
323 case TGSI_TEXTURE_SHADOW1D:
324 mask &= 0xd;
325 break;
326 case TGSI_TEXTURE_1D_ARRAY:
327 case TGSI_TEXTURE_2D:
328 case TGSI_TEXTURE_RECT:
329 mask &= 0xb;
330 break;
331 case TGSI_TEXTURE_CUBE_ARRAY:
332 case TGSI_TEXTURE_SHADOW2D_ARRAY:
333 case TGSI_TEXTURE_SHADOWCUBE:
334 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
335 mask |= 0x8;
336 break;
337 default:
338 break;
339 }
340 }
341 return mask;
342 case TGSI_OPCODE_XPD:
343 {
344 unsigned int x = 0;
345 if (mask & 1) x |= 0x6;
346 if (mask & 2) x |= 0x5;
347 if (mask & 4) x |= 0x3;
348 return x;
349 }
350 case TGSI_OPCODE_D2I:
351 case TGSI_OPCODE_D2U:
352 case TGSI_OPCODE_D2F:
353 case TGSI_OPCODE_DSLT:
354 case TGSI_OPCODE_DSGE:
355 case TGSI_OPCODE_DSEQ:
356 case TGSI_OPCODE_DSNE:
357 switch (util_bitcount(mask)) {
358 case 1: return 0x3;
359 case 2: return 0xf;
360 default:
361 assert(!"unexpected mask");
362 return 0xf;
363 }
364 case TGSI_OPCODE_I2D:
365 case TGSI_OPCODE_U2D:
366 case TGSI_OPCODE_F2D: {
367 unsigned int x = 0;
368 if ((mask & 0x3) == 0x3)
369 x |= 1;
370 if ((mask & 0xc) == 0xc)
371 x |= 2;
372 return x;
373 }
374 case TGSI_OPCODE_PK2H:
375 return 0x3;
376 case TGSI_OPCODE_UP2H:
377 return 0x1;
378 default:
379 break;
380 }
381
382 return mask;
383 }
384
385 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
386 {
387 nv50_ir::Modifier m(0);
388
389 if (reg.Absolute)
390 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
391 if (reg.Negate)
392 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
393 return m;
394 }
395
396 static nv50_ir::DataFile translateFile(uint file)
397 {
398 switch (file) {
399 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
400 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
401 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
402 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
403 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
404 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
405 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
406 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
407 case TGSI_FILE_BUFFER: return nv50_ir::FILE_MEMORY_BUFFER;
408 case TGSI_FILE_IMAGE: return nv50_ir::FILE_MEMORY_GLOBAL;
409 case TGSI_FILE_MEMORY: return nv50_ir::FILE_MEMORY_GLOBAL;
410 case TGSI_FILE_SAMPLER:
411 case TGSI_FILE_NULL:
412 default:
413 return nv50_ir::FILE_NULL;
414 }
415 }
416
417 static nv50_ir::SVSemantic translateSysVal(uint sysval)
418 {
419 switch (sysval) {
420 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
421 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
422 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
423 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
424 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
425 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
426 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
427 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
428 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
429 case TGSI_SEMANTIC_SAMPLEID: return nv50_ir::SV_SAMPLE_INDEX;
430 case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
431 case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
432 case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
433 case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD;
434 case TGSI_SEMANTIC_TESSOUTER: return nv50_ir::SV_TESS_OUTER;
435 case TGSI_SEMANTIC_TESSINNER: return nv50_ir::SV_TESS_INNER;
436 case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
437 case TGSI_SEMANTIC_HELPER_INVOCATION: return nv50_ir::SV_THREAD_KILL;
438 case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
439 case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
440 case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
441 case TGSI_SEMANTIC_WORK_DIM: return nv50_ir::SV_WORK_DIM;
442 default:
443 assert(0);
444 return nv50_ir::SV_CLOCK;
445 }
446 }
447
448 #define NV50_IR_TEX_TARG_CASE(a, b) \
449 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
450
451 static nv50_ir::TexTarget translateTexture(uint tex)
452 {
453 switch (tex) {
454 NV50_IR_TEX_TARG_CASE(1D, 1D);
455 NV50_IR_TEX_TARG_CASE(2D, 2D);
456 NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
457 NV50_IR_TEX_TARG_CASE(3D, 3D);
458 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
459 NV50_IR_TEX_TARG_CASE(RECT, RECT);
460 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
461 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
462 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
463 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
464 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
465 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
466 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
467 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
468 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
469 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
470 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
471 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
472
473 case TGSI_TEXTURE_UNKNOWN:
474 default:
475 assert(!"invalid texture target");
476 return nv50_ir::TEX_TARGET_2D;
477 }
478 }
479
480 static nv50_ir::CacheMode translateCacheMode(uint qualifier)
481 {
482 if (qualifier & TGSI_MEMORY_VOLATILE)
483 return nv50_ir::CACHE_CV;
484 if (qualifier & TGSI_MEMORY_COHERENT)
485 return nv50_ir::CACHE_CG;
486 return nv50_ir::CACHE_CA;
487 }
488
489 static nv50_ir::ImgFormat translateImgFormat(uint format)
490 {
491
492 #define FMT_CASE(a, b) \
493 case PIPE_FORMAT_ ## a: return nv50_ir::FMT_ ## b
494
495 switch (format) {
496 FMT_CASE(NONE, NONE);
497
498 FMT_CASE(R32G32B32A32_FLOAT, RGBA32F);
499 FMT_CASE(R16G16B16A16_FLOAT, RGBA16F);
500 FMT_CASE(R32G32_FLOAT, RG32F);
501 FMT_CASE(R16G16_FLOAT, RG16F);
502 FMT_CASE(R11G11B10_FLOAT, R11G11B10F);
503 FMT_CASE(R32_FLOAT, R32F);
504 FMT_CASE(R16_FLOAT, R16F);
505
506 FMT_CASE(R32G32B32A32_UINT, RGBA32UI);
507 FMT_CASE(R16G16B16A16_UINT, RGBA16UI);
508 FMT_CASE(R10G10B10A2_UINT, RGB10A2UI);
509 FMT_CASE(R8G8B8A8_UINT, RGBA8UI);
510 FMT_CASE(R32G32_UINT, RG32UI);
511 FMT_CASE(R16G16_UINT, RG16UI);
512 FMT_CASE(R8G8_UINT, RG8UI);
513 FMT_CASE(R32_UINT, R32UI);
514 FMT_CASE(R16_UINT, R16UI);
515 FMT_CASE(R8_UINT, R8UI);
516
517 FMT_CASE(R32G32B32A32_SINT, RGBA32I);
518 FMT_CASE(R16G16B16A16_SINT, RGBA16I);
519 FMT_CASE(R8G8B8A8_SINT, RGBA8I);
520 FMT_CASE(R32G32_SINT, RG32I);
521 FMT_CASE(R16G16_SINT, RG16I);
522 FMT_CASE(R8G8_SINT, RG8I);
523 FMT_CASE(R32_SINT, R32I);
524 FMT_CASE(R16_SINT, R16I);
525 FMT_CASE(R8_SINT, R8I);
526
527 FMT_CASE(R16G16B16A16_UNORM, RGBA16);
528 FMT_CASE(R10G10B10A2_UNORM, RGB10A2);
529 FMT_CASE(R8G8B8A8_UNORM, RGBA8);
530 FMT_CASE(R16G16_UNORM, RG16);
531 FMT_CASE(R8G8_UNORM, RG8);
532 FMT_CASE(R16_UNORM, R16);
533 FMT_CASE(R8_UNORM, R8);
534
535 FMT_CASE(R16G16B16A16_SNORM, RGBA16_SNORM);
536 FMT_CASE(R8G8B8A8_SNORM, RGBA8_SNORM);
537 FMT_CASE(R16G16_SNORM, RG16_SNORM);
538 FMT_CASE(R8G8_SNORM, RG8_SNORM);
539 FMT_CASE(R16_SNORM, R16_SNORM);
540 FMT_CASE(R8_SNORM, R8_SNORM);
541
542 FMT_CASE(B8G8R8A8_UNORM, BGRA8);
543 }
544
545 assert(!"Unexpected format");
546 return nv50_ir::FMT_NONE;
547 }
548
549 nv50_ir::DataType Instruction::inferSrcType() const
550 {
551 switch (getOpcode()) {
552 case TGSI_OPCODE_UIF:
553 case TGSI_OPCODE_AND:
554 case TGSI_OPCODE_OR:
555 case TGSI_OPCODE_XOR:
556 case TGSI_OPCODE_NOT:
557 case TGSI_OPCODE_SHL:
558 case TGSI_OPCODE_U2F:
559 case TGSI_OPCODE_U2D:
560 case TGSI_OPCODE_UADD:
561 case TGSI_OPCODE_UDIV:
562 case TGSI_OPCODE_UMOD:
563 case TGSI_OPCODE_UMAD:
564 case TGSI_OPCODE_UMUL:
565 case TGSI_OPCODE_UMUL_HI:
566 case TGSI_OPCODE_UMAX:
567 case TGSI_OPCODE_UMIN:
568 case TGSI_OPCODE_USEQ:
569 case TGSI_OPCODE_USGE:
570 case TGSI_OPCODE_USLT:
571 case TGSI_OPCODE_USNE:
572 case TGSI_OPCODE_USHR:
573 case TGSI_OPCODE_ATOMUADD:
574 case TGSI_OPCODE_ATOMXCHG:
575 case TGSI_OPCODE_ATOMCAS:
576 case TGSI_OPCODE_ATOMAND:
577 case TGSI_OPCODE_ATOMOR:
578 case TGSI_OPCODE_ATOMXOR:
579 case TGSI_OPCODE_ATOMUMIN:
580 case TGSI_OPCODE_ATOMUMAX:
581 case TGSI_OPCODE_UBFE:
582 case TGSI_OPCODE_UMSB:
583 case TGSI_OPCODE_UP2H:
584 case TGSI_OPCODE_VOTE_ALL:
585 case TGSI_OPCODE_VOTE_ANY:
586 case TGSI_OPCODE_VOTE_EQ:
587 return nv50_ir::TYPE_U32;
588 case TGSI_OPCODE_I2F:
589 case TGSI_OPCODE_I2D:
590 case TGSI_OPCODE_IDIV:
591 case TGSI_OPCODE_IMUL_HI:
592 case TGSI_OPCODE_IMAX:
593 case TGSI_OPCODE_IMIN:
594 case TGSI_OPCODE_IABS:
595 case TGSI_OPCODE_INEG:
596 case TGSI_OPCODE_ISGE:
597 case TGSI_OPCODE_ISHR:
598 case TGSI_OPCODE_ISLT:
599 case TGSI_OPCODE_ISSG:
600 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
601 case TGSI_OPCODE_MOD:
602 case TGSI_OPCODE_UARL:
603 case TGSI_OPCODE_ATOMIMIN:
604 case TGSI_OPCODE_ATOMIMAX:
605 case TGSI_OPCODE_IBFE:
606 case TGSI_OPCODE_IMSB:
607 return nv50_ir::TYPE_S32;
608 case TGSI_OPCODE_D2F:
609 case TGSI_OPCODE_D2I:
610 case TGSI_OPCODE_D2U:
611 case TGSI_OPCODE_DABS:
612 case TGSI_OPCODE_DNEG:
613 case TGSI_OPCODE_DADD:
614 case TGSI_OPCODE_DMUL:
615 case TGSI_OPCODE_DDIV:
616 case TGSI_OPCODE_DMAX:
617 case TGSI_OPCODE_DMIN:
618 case TGSI_OPCODE_DSLT:
619 case TGSI_OPCODE_DSGE:
620 case TGSI_OPCODE_DSEQ:
621 case TGSI_OPCODE_DSNE:
622 case TGSI_OPCODE_DRCP:
623 case TGSI_OPCODE_DSQRT:
624 case TGSI_OPCODE_DMAD:
625 case TGSI_OPCODE_DFMA:
626 case TGSI_OPCODE_DFRAC:
627 case TGSI_OPCODE_DRSQ:
628 case TGSI_OPCODE_DTRUNC:
629 case TGSI_OPCODE_DCEIL:
630 case TGSI_OPCODE_DFLR:
631 case TGSI_OPCODE_DROUND:
632 return nv50_ir::TYPE_F64;
633 default:
634 return nv50_ir::TYPE_F32;
635 }
636 }
637
638 nv50_ir::DataType Instruction::inferDstType() const
639 {
640 switch (getOpcode()) {
641 case TGSI_OPCODE_D2U:
642 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
643 case TGSI_OPCODE_D2I:
644 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
645 case TGSI_OPCODE_FSEQ:
646 case TGSI_OPCODE_FSGE:
647 case TGSI_OPCODE_FSLT:
648 case TGSI_OPCODE_FSNE:
649 case TGSI_OPCODE_DSEQ:
650 case TGSI_OPCODE_DSGE:
651 case TGSI_OPCODE_DSLT:
652 case TGSI_OPCODE_DSNE:
653 case TGSI_OPCODE_PK2H:
654 return nv50_ir::TYPE_U32;
655 case TGSI_OPCODE_I2F:
656 case TGSI_OPCODE_U2F:
657 case TGSI_OPCODE_D2F:
658 case TGSI_OPCODE_UP2H:
659 return nv50_ir::TYPE_F32;
660 case TGSI_OPCODE_I2D:
661 case TGSI_OPCODE_U2D:
662 case TGSI_OPCODE_F2D:
663 return nv50_ir::TYPE_F64;
664 default:
665 return inferSrcType();
666 }
667 }
668
669 nv50_ir::CondCode Instruction::getSetCond() const
670 {
671 using namespace nv50_ir;
672
673 switch (getOpcode()) {
674 case TGSI_OPCODE_SLT:
675 case TGSI_OPCODE_ISLT:
676 case TGSI_OPCODE_USLT:
677 case TGSI_OPCODE_FSLT:
678 case TGSI_OPCODE_DSLT:
679 return CC_LT;
680 case TGSI_OPCODE_SLE:
681 return CC_LE;
682 case TGSI_OPCODE_SGE:
683 case TGSI_OPCODE_ISGE:
684 case TGSI_OPCODE_USGE:
685 case TGSI_OPCODE_FSGE:
686 case TGSI_OPCODE_DSGE:
687 return CC_GE;
688 case TGSI_OPCODE_SGT:
689 return CC_GT;
690 case TGSI_OPCODE_SEQ:
691 case TGSI_OPCODE_USEQ:
692 case TGSI_OPCODE_FSEQ:
693 case TGSI_OPCODE_DSEQ:
694 return CC_EQ;
695 case TGSI_OPCODE_SNE:
696 case TGSI_OPCODE_FSNE:
697 case TGSI_OPCODE_DSNE:
698 return CC_NEU;
699 case TGSI_OPCODE_USNE:
700 return CC_NE;
701 default:
702 return CC_ALWAYS;
703 }
704 }
705
706 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
707
708 static nv50_ir::operation translateOpcode(uint opcode)
709 {
710 switch (opcode) {
711 NV50_IR_OPCODE_CASE(ARL, SHL);
712 NV50_IR_OPCODE_CASE(MOV, MOV);
713
714 NV50_IR_OPCODE_CASE(RCP, RCP);
715 NV50_IR_OPCODE_CASE(RSQ, RSQ);
716 NV50_IR_OPCODE_CASE(SQRT, SQRT);
717
718 NV50_IR_OPCODE_CASE(MUL, MUL);
719 NV50_IR_OPCODE_CASE(ADD, ADD);
720
721 NV50_IR_OPCODE_CASE(MIN, MIN);
722 NV50_IR_OPCODE_CASE(MAX, MAX);
723 NV50_IR_OPCODE_CASE(SLT, SET);
724 NV50_IR_OPCODE_CASE(SGE, SET);
725 NV50_IR_OPCODE_CASE(MAD, MAD);
726 NV50_IR_OPCODE_CASE(FMA, FMA);
727
728 NV50_IR_OPCODE_CASE(FLR, FLOOR);
729 NV50_IR_OPCODE_CASE(ROUND, CVT);
730 NV50_IR_OPCODE_CASE(EX2, EX2);
731 NV50_IR_OPCODE_CASE(LG2, LG2);
732 NV50_IR_OPCODE_CASE(POW, POW);
733
734 NV50_IR_OPCODE_CASE(COS, COS);
735 NV50_IR_OPCODE_CASE(DDX, DFDX);
736 NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
737 NV50_IR_OPCODE_CASE(DDY, DFDY);
738 NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
739 NV50_IR_OPCODE_CASE(KILL, DISCARD);
740
741 NV50_IR_OPCODE_CASE(SEQ, SET);
742 NV50_IR_OPCODE_CASE(SGT, SET);
743 NV50_IR_OPCODE_CASE(SIN, SIN);
744 NV50_IR_OPCODE_CASE(SLE, SET);
745 NV50_IR_OPCODE_CASE(SNE, SET);
746 NV50_IR_OPCODE_CASE(TEX, TEX);
747 NV50_IR_OPCODE_CASE(TXD, TXD);
748 NV50_IR_OPCODE_CASE(TXP, TEX);
749
750 NV50_IR_OPCODE_CASE(CAL, CALL);
751 NV50_IR_OPCODE_CASE(RET, RET);
752 NV50_IR_OPCODE_CASE(CMP, SLCT);
753
754 NV50_IR_OPCODE_CASE(TXB, TXB);
755
756 NV50_IR_OPCODE_CASE(DIV, DIV);
757
758 NV50_IR_OPCODE_CASE(TXL, TXL);
759
760 NV50_IR_OPCODE_CASE(CEIL, CEIL);
761 NV50_IR_OPCODE_CASE(I2F, CVT);
762 NV50_IR_OPCODE_CASE(NOT, NOT);
763 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
764 NV50_IR_OPCODE_CASE(SHL, SHL);
765
766 NV50_IR_OPCODE_CASE(AND, AND);
767 NV50_IR_OPCODE_CASE(OR, OR);
768 NV50_IR_OPCODE_CASE(MOD, MOD);
769 NV50_IR_OPCODE_CASE(XOR, XOR);
770 NV50_IR_OPCODE_CASE(SAD, SAD);
771 NV50_IR_OPCODE_CASE(TXF, TXF);
772 NV50_IR_OPCODE_CASE(TXQ, TXQ);
773 NV50_IR_OPCODE_CASE(TXQS, TXQ);
774 NV50_IR_OPCODE_CASE(TG4, TXG);
775 NV50_IR_OPCODE_CASE(LODQ, TXLQ);
776
777 NV50_IR_OPCODE_CASE(EMIT, EMIT);
778 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
779
780 NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
781
782 NV50_IR_OPCODE_CASE(F2I, CVT);
783 NV50_IR_OPCODE_CASE(FSEQ, SET);
784 NV50_IR_OPCODE_CASE(FSGE, SET);
785 NV50_IR_OPCODE_CASE(FSLT, SET);
786 NV50_IR_OPCODE_CASE(FSNE, SET);
787 NV50_IR_OPCODE_CASE(IDIV, DIV);
788 NV50_IR_OPCODE_CASE(IMAX, MAX);
789 NV50_IR_OPCODE_CASE(IMIN, MIN);
790 NV50_IR_OPCODE_CASE(IABS, ABS);
791 NV50_IR_OPCODE_CASE(INEG, NEG);
792 NV50_IR_OPCODE_CASE(ISGE, SET);
793 NV50_IR_OPCODE_CASE(ISHR, SHR);
794 NV50_IR_OPCODE_CASE(ISLT, SET);
795 NV50_IR_OPCODE_CASE(F2U, CVT);
796 NV50_IR_OPCODE_CASE(U2F, CVT);
797 NV50_IR_OPCODE_CASE(UADD, ADD);
798 NV50_IR_OPCODE_CASE(UDIV, DIV);
799 NV50_IR_OPCODE_CASE(UMAD, MAD);
800 NV50_IR_OPCODE_CASE(UMAX, MAX);
801 NV50_IR_OPCODE_CASE(UMIN, MIN);
802 NV50_IR_OPCODE_CASE(UMOD, MOD);
803 NV50_IR_OPCODE_CASE(UMUL, MUL);
804 NV50_IR_OPCODE_CASE(USEQ, SET);
805 NV50_IR_OPCODE_CASE(USGE, SET);
806 NV50_IR_OPCODE_CASE(USHR, SHR);
807 NV50_IR_OPCODE_CASE(USLT, SET);
808 NV50_IR_OPCODE_CASE(USNE, SET);
809
810 NV50_IR_OPCODE_CASE(DABS, ABS);
811 NV50_IR_OPCODE_CASE(DNEG, NEG);
812 NV50_IR_OPCODE_CASE(DADD, ADD);
813 NV50_IR_OPCODE_CASE(DMUL, MUL);
814 NV50_IR_OPCODE_CASE(DDIV, DIV);
815 NV50_IR_OPCODE_CASE(DMAX, MAX);
816 NV50_IR_OPCODE_CASE(DMIN, MIN);
817 NV50_IR_OPCODE_CASE(DSLT, SET);
818 NV50_IR_OPCODE_CASE(DSGE, SET);
819 NV50_IR_OPCODE_CASE(DSEQ, SET);
820 NV50_IR_OPCODE_CASE(DSNE, SET);
821 NV50_IR_OPCODE_CASE(DRCP, RCP);
822 NV50_IR_OPCODE_CASE(DSQRT, SQRT);
823 NV50_IR_OPCODE_CASE(DMAD, MAD);
824 NV50_IR_OPCODE_CASE(DFMA, FMA);
825 NV50_IR_OPCODE_CASE(D2I, CVT);
826 NV50_IR_OPCODE_CASE(D2U, CVT);
827 NV50_IR_OPCODE_CASE(I2D, CVT);
828 NV50_IR_OPCODE_CASE(U2D, CVT);
829 NV50_IR_OPCODE_CASE(DRSQ, RSQ);
830 NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
831 NV50_IR_OPCODE_CASE(DCEIL, CEIL);
832 NV50_IR_OPCODE_CASE(DFLR, FLOOR);
833 NV50_IR_OPCODE_CASE(DROUND, CVT);
834
835 NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
836 NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
837
838 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
839 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
840 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
841 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
842 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
843 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
844 NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
845 NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
846 NV50_IR_OPCODE_CASE(GATHER4, TXG);
847 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
848
849 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
850 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
851 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
852 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
853 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
854 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
855 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
856 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
857 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
858 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
859
860 NV50_IR_OPCODE_CASE(TEX2, TEX);
861 NV50_IR_OPCODE_CASE(TXB2, TXB);
862 NV50_IR_OPCODE_CASE(TXL2, TXL);
863
864 NV50_IR_OPCODE_CASE(IBFE, EXTBF);
865 NV50_IR_OPCODE_CASE(UBFE, EXTBF);
866 NV50_IR_OPCODE_CASE(BFI, INSBF);
867 NV50_IR_OPCODE_CASE(BREV, EXTBF);
868 NV50_IR_OPCODE_CASE(POPC, POPCNT);
869 NV50_IR_OPCODE_CASE(LSB, BFIND);
870 NV50_IR_OPCODE_CASE(IMSB, BFIND);
871 NV50_IR_OPCODE_CASE(UMSB, BFIND);
872
873 NV50_IR_OPCODE_CASE(VOTE_ALL, VOTE);
874 NV50_IR_OPCODE_CASE(VOTE_ANY, VOTE);
875 NV50_IR_OPCODE_CASE(VOTE_EQ, VOTE);
876
877 NV50_IR_OPCODE_CASE(END, EXIT);
878
879 default:
880 return nv50_ir::OP_NOP;
881 }
882 }
883
884 static uint16_t opcodeToSubOp(uint opcode)
885 {
886 switch (opcode) {
887 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
888 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
889 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
890 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
891 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
892 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
893 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
894 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
895 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
896 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
897 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
898 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
899 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
900 case TGSI_OPCODE_IMUL_HI:
901 case TGSI_OPCODE_UMUL_HI:
902 return NV50_IR_SUBOP_MUL_HIGH;
903 case TGSI_OPCODE_VOTE_ALL: return NV50_IR_SUBOP_VOTE_ALL;
904 case TGSI_OPCODE_VOTE_ANY: return NV50_IR_SUBOP_VOTE_ANY;
905 case TGSI_OPCODE_VOTE_EQ: return NV50_IR_SUBOP_VOTE_UNI;
906 default:
907 return 0;
908 }
909 }
910
911 bool Instruction::checkDstSrcAliasing() const
912 {
913 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
914 return false;
915
916 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
917 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
918 break;
919 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
920 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
921 return true;
922 }
923 return false;
924 }
925
926 class Source
927 {
928 public:
929 Source(struct nv50_ir_prog_info *);
930 ~Source();
931
932 public:
933 bool scanSource();
934 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
935
936 public:
937 struct tgsi_shader_info scan;
938 struct tgsi_full_instruction *insns;
939 const struct tgsi_token *tokens;
940 struct nv50_ir_prog_info *info;
941
942 nv50_ir::DynArray tempArrays;
943 nv50_ir::DynArray immdArrays;
944
945 typedef nv50_ir::BuildUtil::Location Location;
946 // these registers are per-subroutine, cannot be used for parameter passing
947 std::set<Location> locals;
948
949 std::set<int> indirectTempArrays;
950 std::map<int, int> indirectTempOffsets;
951 std::map<int, std::pair<int, int> > tempArrayInfo;
952 std::vector<int> tempArrayId;
953
954 int clipVertexOutput;
955
956 struct TextureView {
957 uint8_t target; // TGSI_TEXTURE_*
958 };
959 std::vector<TextureView> textureViews;
960
961 /*
962 struct Resource {
963 uint8_t target; // TGSI_TEXTURE_*
964 bool raw;
965 uint8_t slot; // $surface index
966 };
967 std::vector<Resource> resources;
968 */
969
970 struct Image {
971 uint8_t target; // TGSI_TEXTURE_*
972 bool raw;
973 uint8_t slot;
974 uint16_t format; // PIPE_FORMAT_*
975 };
976 std::vector<Image> images;
977
978 struct MemoryFile {
979 uint8_t mem_type; // TGSI_MEMORY_TYPE_*
980 };
981 std::vector<MemoryFile> memoryFiles;
982
983 private:
984 int inferSysValDirection(unsigned sn) const;
985 bool scanDeclaration(const struct tgsi_full_declaration *);
986 bool scanInstruction(const struct tgsi_full_instruction *);
987 void scanInstructionSrc(const Instruction& insn,
988 const Instruction::SrcRegister& src,
989 unsigned mask);
990 void scanProperty(const struct tgsi_full_property *);
991 void scanImmediate(const struct tgsi_full_immediate *);
992
993 inline bool isEdgeFlagPassthrough(const Instruction&) const;
994 };
995
996 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
997 {
998 tokens = (const struct tgsi_token *)info->bin.source;
999
1000 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
1001 tgsi_dump(tokens, 0);
1002 }
1003
1004 Source::~Source()
1005 {
1006 if (insns)
1007 FREE(insns);
1008
1009 if (info->immd.data)
1010 FREE(info->immd.data);
1011 if (info->immd.type)
1012 FREE(info->immd.type);
1013 }
1014
1015 bool Source::scanSource()
1016 {
1017 unsigned insnCount = 0;
1018 struct tgsi_parse_context parse;
1019
1020 tgsi_scan_shader(tokens, &scan);
1021
1022 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
1023 sizeof(insns[0]));
1024 if (!insns)
1025 return false;
1026
1027 clipVertexOutput = -1;
1028
1029 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
1030 //resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
1031 images.resize(scan.file_max[TGSI_FILE_IMAGE] + 1);
1032 tempArrayId.resize(scan.file_max[TGSI_FILE_TEMPORARY] + 1);
1033 memoryFiles.resize(scan.file_max[TGSI_FILE_MEMORY] + 1);
1034
1035 info->immd.bufSize = 0;
1036
1037 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
1038 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
1039 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
1040
1041 if (info->type == PIPE_SHADER_FRAGMENT) {
1042 info->prop.fp.writesDepth = scan.writes_z;
1043 info->prop.fp.usesDiscard = scan.uses_kill || info->io.alphaRefBase;
1044 } else
1045 if (info->type == PIPE_SHADER_GEOMETRY) {
1046 info->prop.gp.instanceCount = 1; // default value
1047 }
1048
1049 info->io.viewportId = -1;
1050 info->prop.cp.numThreads = 1;
1051
1052 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
1053 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
1054
1055 tgsi_parse_init(&parse, tokens);
1056 while (!tgsi_parse_end_of_tokens(&parse)) {
1057 tgsi_parse_token(&parse);
1058
1059 switch (parse.FullToken.Token.Type) {
1060 case TGSI_TOKEN_TYPE_IMMEDIATE:
1061 scanImmediate(&parse.FullToken.FullImmediate);
1062 break;
1063 case TGSI_TOKEN_TYPE_DECLARATION:
1064 scanDeclaration(&parse.FullToken.FullDeclaration);
1065 break;
1066 case TGSI_TOKEN_TYPE_INSTRUCTION:
1067 insns[insnCount++] = parse.FullToken.FullInstruction;
1068 scanInstruction(&parse.FullToken.FullInstruction);
1069 break;
1070 case TGSI_TOKEN_TYPE_PROPERTY:
1071 scanProperty(&parse.FullToken.FullProperty);
1072 break;
1073 default:
1074 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
1075 break;
1076 }
1077 }
1078 tgsi_parse_free(&parse);
1079
1080 if (indirectTempArrays.size()) {
1081 int tempBase = 0;
1082 for (std::set<int>::const_iterator it = indirectTempArrays.begin();
1083 it != indirectTempArrays.end(); ++it) {
1084 std::pair<int, int>& info = tempArrayInfo[*it];
1085 indirectTempOffsets.insert(std::make_pair(*it, tempBase - info.first));
1086 tempBase += info.second;
1087 }
1088 info->bin.tlsSpace += tempBase * 16;
1089 }
1090
1091 if (info->io.genUserClip > 0) {
1092 info->io.clipDistances = info->io.genUserClip;
1093
1094 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1095
1096 for (unsigned int n = 0; n < nOut; ++n) {
1097 unsigned int i = info->numOutputs++;
1098 info->out[i].id = i;
1099 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1100 info->out[i].si = n;
1101 info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1102 }
1103 }
1104
1105 return info->assignSlots(info) == 0;
1106 }
1107
1108 void Source::scanProperty(const struct tgsi_full_property *prop)
1109 {
1110 switch (prop->Property.PropertyName) {
1111 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1112 info->prop.gp.outputPrim = prop->u[0].Data;
1113 break;
1114 case TGSI_PROPERTY_GS_INPUT_PRIM:
1115 info->prop.gp.inputPrim = prop->u[0].Data;
1116 break;
1117 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1118 info->prop.gp.maxVertices = prop->u[0].Data;
1119 break;
1120 case TGSI_PROPERTY_GS_INVOCATIONS:
1121 info->prop.gp.instanceCount = prop->u[0].Data;
1122 break;
1123 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1124 info->prop.fp.separateFragData = true;
1125 break;
1126 case TGSI_PROPERTY_FS_COORD_ORIGIN:
1127 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
1128 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
1129 // we don't care
1130 break;
1131 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1132 info->io.genUserClip = -1;
1133 break;
1134 case TGSI_PROPERTY_TCS_VERTICES_OUT:
1135 info->prop.tp.outputPatchSize = prop->u[0].Data;
1136 break;
1137 case TGSI_PROPERTY_TES_PRIM_MODE:
1138 info->prop.tp.domain = prop->u[0].Data;
1139 break;
1140 case TGSI_PROPERTY_TES_SPACING:
1141 info->prop.tp.partitioning = prop->u[0].Data;
1142 break;
1143 case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
1144 info->prop.tp.winding = prop->u[0].Data;
1145 break;
1146 case TGSI_PROPERTY_TES_POINT_MODE:
1147 if (prop->u[0].Data)
1148 info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
1149 else
1150 info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
1151 break;
1152 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
1153 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
1154 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
1155 info->prop.cp.numThreads *= prop->u[0].Data;
1156 break;
1157 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
1158 info->io.clipDistances = prop->u[0].Data;
1159 break;
1160 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
1161 info->io.cullDistances = prop->u[0].Data;
1162 break;
1163 case TGSI_PROPERTY_NEXT_SHADER:
1164 /* Do not need to know the next shader stage. */
1165 break;
1166 case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
1167 info->prop.fp.earlyFragTests = prop->u[0].Data;
1168 break;
1169 default:
1170 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
1171 break;
1172 }
1173 }
1174
1175 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
1176 {
1177 const unsigned n = info->immd.count++;
1178
1179 assert(n < scan.immediate_count);
1180
1181 for (int c = 0; c < 4; ++c)
1182 info->immd.data[n * 4 + c] = imm->u[c].Uint;
1183
1184 info->immd.type[n] = imm->Immediate.DataType;
1185 }
1186
1187 int Source::inferSysValDirection(unsigned sn) const
1188 {
1189 switch (sn) {
1190 case TGSI_SEMANTIC_INSTANCEID:
1191 case TGSI_SEMANTIC_VERTEXID:
1192 return 1;
1193 case TGSI_SEMANTIC_LAYER:
1194 #if 0
1195 case TGSI_SEMANTIC_VIEWPORTINDEX:
1196 return 0;
1197 #endif
1198 case TGSI_SEMANTIC_PRIMID:
1199 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
1200 default:
1201 return 0;
1202 }
1203 }
1204
1205 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
1206 {
1207 unsigned i, c;
1208 unsigned sn = TGSI_SEMANTIC_GENERIC;
1209 unsigned si = 0;
1210 const unsigned first = decl->Range.First, last = decl->Range.Last;
1211 const int arrayId = decl->Array.ArrayID;
1212
1213 if (decl->Declaration.Semantic) {
1214 sn = decl->Semantic.Name;
1215 si = decl->Semantic.Index;
1216 }
1217
1218 if (decl->Declaration.Local || decl->Declaration.File == TGSI_FILE_ADDRESS) {
1219 for (i = first; i <= last; ++i) {
1220 for (c = 0; c < 4; ++c) {
1221 locals.insert(
1222 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1223 }
1224 }
1225 }
1226
1227 switch (decl->Declaration.File) {
1228 case TGSI_FILE_INPUT:
1229 if (info->type == PIPE_SHADER_VERTEX) {
1230 // all vertex attributes are equal
1231 for (i = first; i <= last; ++i) {
1232 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1233 info->in[i].si = i;
1234 }
1235 } else {
1236 for (i = first; i <= last; ++i, ++si) {
1237 info->in[i].id = i;
1238 info->in[i].sn = sn;
1239 info->in[i].si = si;
1240 if (info->type == PIPE_SHADER_FRAGMENT) {
1241 // translate interpolation mode
1242 switch (decl->Interp.Interpolate) {
1243 case TGSI_INTERPOLATE_CONSTANT:
1244 info->in[i].flat = 1;
1245 break;
1246 case TGSI_INTERPOLATE_COLOR:
1247 info->in[i].sc = 1;
1248 break;
1249 case TGSI_INTERPOLATE_LINEAR:
1250 info->in[i].linear = 1;
1251 break;
1252 default:
1253 break;
1254 }
1255 if (decl->Interp.Location)
1256 info->in[i].centroid = 1;
1257 }
1258
1259 if (sn == TGSI_SEMANTIC_PATCH)
1260 info->in[i].patch = 1;
1261 if (sn == TGSI_SEMANTIC_PATCH)
1262 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1263 }
1264 }
1265 break;
1266 case TGSI_FILE_OUTPUT:
1267 for (i = first; i <= last; ++i, ++si) {
1268 switch (sn) {
1269 case TGSI_SEMANTIC_POSITION:
1270 if (info->type == PIPE_SHADER_FRAGMENT)
1271 info->io.fragDepth = i;
1272 else
1273 if (clipVertexOutput < 0)
1274 clipVertexOutput = i;
1275 break;
1276 case TGSI_SEMANTIC_COLOR:
1277 if (info->type == PIPE_SHADER_FRAGMENT)
1278 info->prop.fp.numColourResults++;
1279 break;
1280 case TGSI_SEMANTIC_EDGEFLAG:
1281 info->io.edgeFlagOut = i;
1282 break;
1283 case TGSI_SEMANTIC_CLIPVERTEX:
1284 clipVertexOutput = i;
1285 break;
1286 case TGSI_SEMANTIC_CLIPDIST:
1287 info->io.genUserClip = -1;
1288 break;
1289 case TGSI_SEMANTIC_SAMPLEMASK:
1290 info->io.sampleMask = i;
1291 break;
1292 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1293 info->io.viewportId = i;
1294 break;
1295 case TGSI_SEMANTIC_PATCH:
1296 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1297 /* fallthrough */
1298 case TGSI_SEMANTIC_TESSOUTER:
1299 case TGSI_SEMANTIC_TESSINNER:
1300 info->out[i].patch = 1;
1301 break;
1302 default:
1303 break;
1304 }
1305 info->out[i].id = i;
1306 info->out[i].sn = sn;
1307 info->out[i].si = si;
1308 }
1309 break;
1310 case TGSI_FILE_SYSTEM_VALUE:
1311 switch (sn) {
1312 case TGSI_SEMANTIC_INSTANCEID:
1313 info->io.instanceId = first;
1314 break;
1315 case TGSI_SEMANTIC_VERTEXID:
1316 info->io.vertexId = first;
1317 break;
1318 case TGSI_SEMANTIC_BASEVERTEX:
1319 case TGSI_SEMANTIC_BASEINSTANCE:
1320 case TGSI_SEMANTIC_DRAWID:
1321 info->prop.vp.usesDrawParameters = true;
1322 break;
1323 case TGSI_SEMANTIC_SAMPLEID:
1324 case TGSI_SEMANTIC_SAMPLEPOS:
1325 info->prop.fp.persampleInvocation = true;
1326 break;
1327 case TGSI_SEMANTIC_SAMPLEMASK:
1328 info->prop.fp.usesSampleMaskIn = true;
1329 break;
1330 default:
1331 break;
1332 }
1333 for (i = first; i <= last; ++i, ++si) {
1334 info->sv[i].sn = sn;
1335 info->sv[i].si = si;
1336 info->sv[i].input = inferSysValDirection(sn);
1337
1338 switch (sn) {
1339 case TGSI_SEMANTIC_TESSOUTER:
1340 case TGSI_SEMANTIC_TESSINNER:
1341 info->sv[i].patch = 1;
1342 break;
1343 }
1344 }
1345 break;
1346 /*
1347 case TGSI_FILE_RESOURCE:
1348 for (i = first; i <= last; ++i) {
1349 resources[i].target = decl->Resource.Resource;
1350 resources[i].raw = decl->Resource.Raw;
1351 resources[i].slot = i;
1352 }
1353 break;
1354 */
1355 case TGSI_FILE_IMAGE:
1356 for (i = first; i <= last; ++i) {
1357 images[i].target = decl->Image.Resource;
1358 images[i].raw = decl->Image.Raw;
1359 images[i].format = decl->Image.Format;
1360 images[i].slot = i;
1361 }
1362 break;
1363 case TGSI_FILE_SAMPLER_VIEW:
1364 for (i = first; i <= last; ++i)
1365 textureViews[i].target = decl->SamplerView.Resource;
1366 break;
1367 case TGSI_FILE_MEMORY:
1368 for (i = first; i <= last; ++i)
1369 memoryFiles[i].mem_type = decl->Declaration.MemType;
1370 break;
1371 case TGSI_FILE_NULL:
1372 case TGSI_FILE_TEMPORARY:
1373 for (i = first; i <= last; ++i)
1374 tempArrayId[i] = arrayId;
1375 if (arrayId)
1376 tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
1377 first, last - first + 1)));
1378 break;
1379 case TGSI_FILE_ADDRESS:
1380 case TGSI_FILE_CONSTANT:
1381 case TGSI_FILE_IMMEDIATE:
1382 case TGSI_FILE_PREDICATE:
1383 case TGSI_FILE_SAMPLER:
1384 case TGSI_FILE_BUFFER:
1385 break;
1386 default:
1387 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1388 return false;
1389 }
1390 return true;
1391 }
1392
1393 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1394 {
1395 return insn.getOpcode() == TGSI_OPCODE_MOV &&
1396 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1397 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1398 }
1399
1400 void Source::scanInstructionSrc(const Instruction& insn,
1401 const Instruction::SrcRegister& src,
1402 unsigned mask)
1403 {
1404 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1405 if (src.isIndirect(0))
1406 indirectTempArrays.insert(src.getArrayId());
1407 } else
1408 if (src.getFile() == TGSI_FILE_BUFFER ||
1409 src.getFile() == TGSI_FILE_IMAGE ||
1410 (src.getFile() == TGSI_FILE_MEMORY &&
1411 memoryFiles[src.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1412 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1413 0x1 : 0x2;
1414 } else
1415 if (src.getFile() == TGSI_FILE_OUTPUT) {
1416 if (src.isIndirect(0)) {
1417 // We don't know which one is accessed, just mark everything for
1418 // reading. This is an extremely unlikely occurrence.
1419 for (unsigned i = 0; i < info->numOutputs; ++i)
1420 info->out[i].oread = 1;
1421 } else {
1422 info->out[src.getIndex(0)].oread = 1;
1423 }
1424 }
1425 if (src.getFile() != TGSI_FILE_INPUT)
1426 return;
1427
1428 if (src.isIndirect(0)) {
1429 for (unsigned i = 0; i < info->numInputs; ++i)
1430 info->in[i].mask = 0xf;
1431 } else {
1432 const int i = src.getIndex(0);
1433 for (unsigned c = 0; c < 4; ++c) {
1434 if (!(mask & (1 << c)))
1435 continue;
1436 int k = src.getSwizzle(c);
1437 if (k <= TGSI_SWIZZLE_W)
1438 info->in[i].mask |= 1 << k;
1439 }
1440 switch (info->in[i].sn) {
1441 case TGSI_SEMANTIC_PSIZE:
1442 case TGSI_SEMANTIC_PRIMID:
1443 case TGSI_SEMANTIC_FOG:
1444 info->in[i].mask &= 0x1;
1445 break;
1446 case TGSI_SEMANTIC_PCOORD:
1447 info->in[i].mask &= 0x3;
1448 break;
1449 default:
1450 break;
1451 }
1452 }
1453 }
1454
1455 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1456 {
1457 Instruction insn(inst);
1458
1459 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1460 info->numBarriers = 1;
1461
1462 if (insn.dstCount()) {
1463 Instruction::DstRegister dst = insn.getDst(0);
1464
1465 if (dst.getFile() == TGSI_FILE_OUTPUT) {
1466 if (dst.isIndirect(0))
1467 for (unsigned i = 0; i < info->numOutputs; ++i)
1468 info->out[i].mask = 0xf;
1469 else
1470 info->out[dst.getIndex(0)].mask |= dst.getMask();
1471
1472 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1473 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1474 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1475 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1476 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1477 info->out[dst.getIndex(0)].mask &= 1;
1478
1479 if (isEdgeFlagPassthrough(insn))
1480 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1481 } else
1482 if (dst.getFile() == TGSI_FILE_TEMPORARY) {
1483 if (dst.isIndirect(0))
1484 indirectTempArrays.insert(dst.getArrayId());
1485 } else
1486 if (dst.getFile() == TGSI_FILE_BUFFER ||
1487 dst.getFile() == TGSI_FILE_IMAGE ||
1488 (dst.getFile() == TGSI_FILE_MEMORY &&
1489 memoryFiles[dst.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1490 info->io.globalAccess |= 0x2;
1491 }
1492 }
1493
1494 for (unsigned s = 0; s < insn.srcCount(); ++s)
1495 scanInstructionSrc(insn, insn.getSrc(s), insn.srcMask(s));
1496
1497 for (unsigned s = 0; s < insn.getNumTexOffsets(); ++s)
1498 scanInstructionSrc(insn, insn.getTexOffset(s), insn.texOffsetMask());
1499
1500 return true;
1501 }
1502
1503 nv50_ir::TexInstruction::Target
1504 Instruction::getTexture(const tgsi::Source *code, int s) const
1505 {
1506 // XXX: indirect access
1507 unsigned int r;
1508
1509 switch (getSrc(s).getFile()) {
1510 /*
1511 case TGSI_FILE_RESOURCE:
1512 r = getSrc(s).getIndex(0);
1513 return translateTexture(code->resources.at(r).target);
1514 */
1515 case TGSI_FILE_SAMPLER_VIEW:
1516 r = getSrc(s).getIndex(0);
1517 return translateTexture(code->textureViews.at(r).target);
1518 default:
1519 return translateTexture(insn->Texture.Texture);
1520 }
1521 }
1522
1523 } // namespace tgsi
1524
1525 namespace {
1526
1527 using namespace nv50_ir;
1528
1529 class Converter : public BuildUtil
1530 {
1531 public:
1532 Converter(Program *, const tgsi::Source *);
1533 ~Converter();
1534
1535 bool run();
1536
1537 private:
1538 struct Subroutine
1539 {
1540 Subroutine(Function *f) : f(f) { }
1541 Function *f;
1542 ValueMap values;
1543 };
1544
1545 Value *shiftAddress(Value *);
1546 Value *getVertexBase(int s);
1547 Value *getOutputBase(int s);
1548 DataArray *getArrayForFile(unsigned file, int idx);
1549 Value *fetchSrc(int s, int c);
1550 Value *acquireDst(int d, int c);
1551 void storeDst(int d, int c, Value *);
1552
1553 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1554 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1555 Value *val, Value *ptr);
1556
1557 void adjustTempIndex(int arrayId, int &idx, int &idx2d) const;
1558 Value *applySrcMod(Value *, int s, int c);
1559
1560 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1561 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1562 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1563
1564 bool handleInstruction(const struct tgsi_full_instruction *);
1565 void exportOutputs();
1566 inline Subroutine *getSubroutine(unsigned ip);
1567 inline Subroutine *getSubroutine(Function *);
1568 inline bool isEndOfSubroutine(uint ip);
1569
1570 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1571
1572 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1573 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1574 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1575 void handleTXF(Value *dst0[4], int R, int L_M);
1576 void handleTXQ(Value *dst0[4], enum TexQuery, int R);
1577 void handleLIT(Value *dst0[4]);
1578 void handleUserClipPlanes();
1579
1580 // Symbol *getResourceBase(int r);
1581 void getImageCoords(std::vector<Value *>&, int r, int s);
1582
1583 void handleLOAD(Value *dst0[4]);
1584 void handleSTORE();
1585 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1586
1587 void handleINTERP(Value *dst0[4]);
1588
1589 uint8_t translateInterpMode(const struct nv50_ir_varying *var,
1590 operation& op);
1591 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1592
1593 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1594
1595 Value *buildDot(int dim);
1596
1597 class BindArgumentsPass : public Pass {
1598 public:
1599 BindArgumentsPass(Converter &conv) : conv(conv) { }
1600
1601 private:
1602 Converter &conv;
1603 Subroutine *sub;
1604
1605 inline const Location *getValueLocation(Subroutine *, Value *);
1606
1607 template<typename T> inline void
1608 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1609 T (Function::*proto));
1610
1611 template<typename T> inline void
1612 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1613 T (Function::*proto));
1614
1615 protected:
1616 bool visit(Function *);
1617 bool visit(BasicBlock *bb) { return false; }
1618 };
1619
1620 private:
1621 const tgsi::Source *code;
1622 const struct nv50_ir_prog_info *info;
1623
1624 struct {
1625 std::map<unsigned, Subroutine> map;
1626 Subroutine *cur;
1627 } sub;
1628
1629 uint ip; // instruction pointer
1630
1631 tgsi::Instruction tgsi;
1632
1633 DataType dstTy;
1634 DataType srcTy;
1635
1636 DataArray tData; // TGSI_FILE_TEMPORARY
1637 DataArray lData; // TGSI_FILE_TEMPORARY, for indirect arrays
1638 DataArray aData; // TGSI_FILE_ADDRESS
1639 DataArray pData; // TGSI_FILE_PREDICATE
1640 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1641
1642 Value *zero;
1643 Value *fragCoord[4];
1644 Value *clipVtx[4];
1645
1646 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1647 uint8_t vtxBaseValid;
1648
1649 Value *outBase; // base address of vertex out patch (for TCP)
1650
1651 Stack condBBs; // fork BB, then else clause BB
1652 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1653 Stack loopBBs; // loop headers
1654 Stack breakBBs; // end of / after loop
1655
1656 Value *viewport;
1657 };
1658
1659 Symbol *
1660 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1661 {
1662 const int swz = src.getSwizzle(c);
1663
1664 /* TODO: Use Array ID when it's available for the index */
1665 return makeSym(src.getFile(),
1666 src.is2D() ? src.getIndex(1) : 0,
1667 src.getIndex(0), swz,
1668 src.getIndex(0) * 16 + swz * 4);
1669 }
1670
1671 Symbol *
1672 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1673 {
1674 /* TODO: Use Array ID when it's available for the index */
1675 return makeSym(dst.getFile(),
1676 dst.is2D() ? dst.getIndex(1) : 0,
1677 dst.getIndex(0), c,
1678 dst.getIndex(0) * 16 + c * 4);
1679 }
1680
1681 Symbol *
1682 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1683 {
1684 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1685
1686 sym->reg.fileIndex = fileIdx;
1687
1688 if (tgsiFile == TGSI_FILE_MEMORY) {
1689 switch (code->memoryFiles[fileIdx].mem_type) {
1690 case TGSI_MEMORY_TYPE_GLOBAL:
1691 /* No-op this is the default for TGSI_FILE_MEMORY */
1692 sym->setFile(FILE_MEMORY_GLOBAL);
1693 break;
1694 case TGSI_MEMORY_TYPE_SHARED:
1695 sym->setFile(FILE_MEMORY_SHARED);
1696 break;
1697 case TGSI_MEMORY_TYPE_INPUT:
1698 assert(prog->getType() == Program::TYPE_COMPUTE);
1699 assert(idx == -1);
1700 sym->setFile(FILE_SHADER_INPUT);
1701 address += info->prop.cp.inputOffset;
1702 break;
1703 default:
1704 assert(0); /* TODO: Add support for global and private memory */
1705 }
1706 }
1707
1708 if (idx >= 0) {
1709 if (sym->reg.file == FILE_SHADER_INPUT)
1710 sym->setOffset(info->in[idx].slot[c] * 4);
1711 else
1712 if (sym->reg.file == FILE_SHADER_OUTPUT)
1713 sym->setOffset(info->out[idx].slot[c] * 4);
1714 else
1715 if (sym->reg.file == FILE_SYSTEM_VALUE)
1716 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1717 else
1718 sym->setOffset(address);
1719 } else {
1720 sym->setOffset(address);
1721 }
1722 return sym;
1723 }
1724
1725 uint8_t
1726 Converter::translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1727 {
1728 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1729
1730 if (var->flat)
1731 mode = NV50_IR_INTERP_FLAT;
1732 else
1733 if (var->linear)
1734 mode = NV50_IR_INTERP_LINEAR;
1735 else
1736 if (var->sc)
1737 mode = NV50_IR_INTERP_SC;
1738
1739 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1740 ? OP_PINTERP : OP_LINTERP;
1741
1742 if (var->centroid)
1743 mode |= NV50_IR_INTERP_CENTROID;
1744
1745 return mode;
1746 }
1747
1748 Value *
1749 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1750 {
1751 operation op;
1752
1753 // XXX: no way to know interpolation mode if we don't know what's accessed
1754 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1755 src.getIndex(0)], op);
1756
1757 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1758
1759 insn->setDef(0, getScratch());
1760 insn->setSrc(0, srcToSym(src, c));
1761 if (op == OP_PINTERP)
1762 insn->setSrc(1, fragCoord[3]);
1763 if (ptr)
1764 insn->setIndirect(0, 0, ptr);
1765
1766 insn->setInterpolate(mode);
1767
1768 bb->insertTail(insn);
1769 return insn->getDef(0);
1770 }
1771
1772 Value *
1773 Converter::applySrcMod(Value *val, int s, int c)
1774 {
1775 Modifier m = tgsi.getSrc(s).getMod(c);
1776 DataType ty = tgsi.inferSrcType();
1777
1778 if (m & Modifier(NV50_IR_MOD_ABS))
1779 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1780
1781 if (m & Modifier(NV50_IR_MOD_NEG))
1782 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1783
1784 return val;
1785 }
1786
1787 Value *
1788 Converter::getVertexBase(int s)
1789 {
1790 assert(s < 5);
1791 if (!(vtxBaseValid & (1 << s))) {
1792 const int index = tgsi.getSrc(s).getIndex(1);
1793 Value *rel = NULL;
1794 if (tgsi.getSrc(s).isIndirect(1))
1795 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1796 vtxBaseValid |= 1 << s;
1797 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1798 mkImm(index), rel);
1799 }
1800 return vtxBase[s];
1801 }
1802
1803 Value *
1804 Converter::getOutputBase(int s)
1805 {
1806 assert(s < 5);
1807 if (!(vtxBaseValid & (1 << s))) {
1808 Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1));
1809 if (tgsi.getSrc(s).isIndirect(1))
1810 offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(),
1811 fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL),
1812 offset);
1813 vtxBaseValid |= 1 << s;
1814 vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset);
1815 }
1816 return vtxBase[s];
1817 }
1818
1819 Value *
1820 Converter::fetchSrc(int s, int c)
1821 {
1822 Value *res;
1823 Value *ptr = NULL, *dimRel = NULL;
1824
1825 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1826
1827 if (src.isIndirect(0))
1828 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1829
1830 if (src.is2D()) {
1831 switch (src.getFile()) {
1832 case TGSI_FILE_OUTPUT:
1833 dimRel = getOutputBase(s);
1834 break;
1835 case TGSI_FILE_INPUT:
1836 dimRel = getVertexBase(s);
1837 break;
1838 case TGSI_FILE_CONSTANT:
1839 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1840 if (src.isIndirect(1))
1841 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1842 break;
1843 default:
1844 break;
1845 }
1846 }
1847
1848 res = fetchSrc(src, c, ptr);
1849
1850 if (dimRel)
1851 res->getInsn()->setIndirect(0, 1, dimRel);
1852
1853 return applySrcMod(res, s, c);
1854 }
1855
1856 Converter::DataArray *
1857 Converter::getArrayForFile(unsigned file, int idx)
1858 {
1859 switch (file) {
1860 case TGSI_FILE_TEMPORARY:
1861 return idx == 0 ? &tData : &lData;
1862 case TGSI_FILE_PREDICATE:
1863 return &pData;
1864 case TGSI_FILE_ADDRESS:
1865 return &aData;
1866 case TGSI_FILE_OUTPUT:
1867 assert(prog->getType() == Program::TYPE_FRAGMENT);
1868 return &oData;
1869 default:
1870 assert(!"invalid/unhandled TGSI source file");
1871 return NULL;
1872 }
1873 }
1874
1875 Value *
1876 Converter::shiftAddress(Value *index)
1877 {
1878 if (!index)
1879 return NULL;
1880 return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1881 }
1882
1883 void
1884 Converter::adjustTempIndex(int arrayId, int &idx, int &idx2d) const
1885 {
1886 std::map<int, int>::const_iterator it =
1887 code->indirectTempOffsets.find(arrayId);
1888 if (it == code->indirectTempOffsets.end())
1889 return;
1890
1891 idx2d = 1;
1892 idx += it->second;
1893 }
1894
1895 Value *
1896 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1897 {
1898 int idx2d = src.is2D() ? src.getIndex(1) : 0;
1899 int idx = src.getIndex(0);
1900 const int swz = src.getSwizzle(c);
1901 Instruction *ld;
1902
1903 switch (src.getFile()) {
1904 case TGSI_FILE_IMMEDIATE:
1905 assert(!ptr);
1906 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1907 case TGSI_FILE_CONSTANT:
1908 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1909 case TGSI_FILE_INPUT:
1910 if (prog->getType() == Program::TYPE_FRAGMENT) {
1911 // don't load masked inputs, won't be assigned a slot
1912 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1913 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1914 return interpolate(src, c, shiftAddress(ptr));
1915 } else
1916 if (prog->getType() == Program::TYPE_GEOMETRY) {
1917 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1918 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1919 // XXX: This is going to be a problem with scalar arrays, i.e. when
1920 // we cannot assume that the address is given in units of vec4.
1921 //
1922 // nv50 and nvc0 need different things here, so let the lowering
1923 // passes decide what to do with the address
1924 if (ptr)
1925 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1926 }
1927 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1928 ld->perPatch = info->in[idx].patch;
1929 return ld->getDef(0);
1930 case TGSI_FILE_OUTPUT:
1931 assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
1932 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1933 ld->perPatch = info->out[idx].patch;
1934 return ld->getDef(0);
1935 case TGSI_FILE_SYSTEM_VALUE:
1936 assert(!ptr);
1937 ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1938 ld->perPatch = info->sv[idx].patch;
1939 return ld->getDef(0);
1940 case TGSI_FILE_TEMPORARY: {
1941 int arrayid = src.getArrayId();
1942 if (!arrayid)
1943 arrayid = code->tempArrayId[idx];
1944 adjustTempIndex(arrayid, idx, idx2d);
1945 }
1946 /* fallthrough */
1947 default:
1948 return getArrayForFile(src.getFile(), idx2d)->load(
1949 sub.cur->values, idx, swz, shiftAddress(ptr));
1950 }
1951 }
1952
1953 Value *
1954 Converter::acquireDst(int d, int c)
1955 {
1956 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1957 const unsigned f = dst.getFile();
1958 int idx = dst.getIndex(0);
1959 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1960
1961 if (dst.isMasked(c) || f == TGSI_FILE_BUFFER || f == TGSI_FILE_MEMORY ||
1962 f == TGSI_FILE_IMAGE)
1963 return NULL;
1964
1965 if (dst.isIndirect(0) ||
1966 f == TGSI_FILE_SYSTEM_VALUE ||
1967 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1968 return getScratch();
1969
1970 if (f == TGSI_FILE_TEMPORARY) {
1971 int arrayid = dst.getArrayId();
1972 if (!arrayid)
1973 arrayid = code->tempArrayId[idx];
1974 adjustTempIndex(arrayid, idx, idx2d);
1975 }
1976
1977 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1978 }
1979
1980 void
1981 Converter::storeDst(int d, int c, Value *val)
1982 {
1983 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1984
1985 if (tgsi.getSaturate()) {
1986 mkOp1(OP_SAT, dstTy, val, val);
1987 }
1988
1989 Value *ptr = NULL;
1990 if (dst.isIndirect(0))
1991 ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1992
1993 if (info->io.genUserClip > 0 &&
1994 dst.getFile() == TGSI_FILE_OUTPUT &&
1995 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1996 mkMov(clipVtx[c], val);
1997 val = clipVtx[c];
1998 }
1999
2000 storeDst(dst, c, val, ptr);
2001 }
2002
2003 void
2004 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
2005 Value *val, Value *ptr)
2006 {
2007 const unsigned f = dst.getFile();
2008 int idx = dst.getIndex(0);
2009 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
2010
2011 if (f == TGSI_FILE_SYSTEM_VALUE) {
2012 assert(!ptr);
2013 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
2014 } else
2015 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
2016
2017 if (ptr || (info->out[idx].mask & (1 << c))) {
2018 /* Save the viewport index into a scratch register so that it can be
2019 exported at EMIT time */
2020 if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
2021 viewport != NULL)
2022 mkOp1(OP_MOV, TYPE_U32, viewport, val);
2023 else
2024 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
2025 info->out[idx].patch;
2026 }
2027 } else
2028 if (f == TGSI_FILE_TEMPORARY ||
2029 f == TGSI_FILE_PREDICATE ||
2030 f == TGSI_FILE_ADDRESS ||
2031 f == TGSI_FILE_OUTPUT) {
2032 if (f == TGSI_FILE_TEMPORARY) {
2033 int arrayid = dst.getArrayId();
2034 if (!arrayid)
2035 arrayid = code->tempArrayId[idx];
2036 adjustTempIndex(arrayid, idx, idx2d);
2037 }
2038
2039 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
2040 } else {
2041 assert(!"invalid dst file");
2042 }
2043 }
2044
2045 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
2046 for (chan = 0; chan < 4; ++chan) \
2047 if (!inst.getDst(d).isMasked(chan))
2048
2049 Value *
2050 Converter::buildDot(int dim)
2051 {
2052 assert(dim > 0);
2053
2054 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
2055 Value *dotp = getScratch();
2056
2057 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
2058
2059 for (int c = 1; c < dim; ++c) {
2060 src0 = fetchSrc(0, c);
2061 src1 = fetchSrc(1, c);
2062 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
2063 }
2064 return dotp;
2065 }
2066
2067 void
2068 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
2069 {
2070 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
2071 join->fixed = 1;
2072 conv->insertHead(join);
2073
2074 assert(!fork->joinAt);
2075 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
2076 fork->insertBefore(fork->getExit(), fork->joinAt);
2077 }
2078
2079 void
2080 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
2081 {
2082 unsigned rIdx = 0, sIdx = 0;
2083
2084 if (R >= 0)
2085 rIdx = tgsi.getSrc(R).getIndex(0);
2086 if (S >= 0)
2087 sIdx = tgsi.getSrc(S).getIndex(0);
2088
2089 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
2090
2091 if (tgsi.getSrc(R).isIndirect(0)) {
2092 tex->tex.rIndirectSrc = s;
2093 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
2094 }
2095 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
2096 tex->tex.sIndirectSrc = s;
2097 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
2098 }
2099 }
2100
2101 void
2102 Converter::handleTXQ(Value *dst0[4], enum TexQuery query, int R)
2103 {
2104 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
2105 tex->tex.query = query;
2106 unsigned int c, d;
2107
2108 for (d = 0, c = 0; c < 4; ++c) {
2109 if (!dst0[c])
2110 continue;
2111 tex->tex.mask |= 1 << c;
2112 tex->setDef(d++, dst0[c]);
2113 }
2114 if (query == TXQ_DIMS)
2115 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
2116 else
2117 tex->setSrc((c = 0), zero);
2118
2119 setTexRS(tex, ++c, R, -1);
2120
2121 bb->insertTail(tex);
2122 }
2123
2124 void
2125 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
2126 {
2127 Value *proj = fetchSrc(0, 3);
2128 Instruction *insn = proj->getUniqueInsn();
2129 int c;
2130
2131 if (insn->op == OP_PINTERP) {
2132 bb->insertTail(insn = cloneForward(func, insn));
2133 insn->op = OP_LINTERP;
2134 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
2135 insn->setSrc(1, NULL);
2136 proj = insn->getDef(0);
2137 }
2138 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
2139
2140 for (c = 0; c < 4; ++c) {
2141 if (!(mask & (1 << c)))
2142 continue;
2143 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
2144 continue;
2145 mask &= ~(1 << c);
2146
2147 bb->insertTail(insn = cloneForward(func, insn));
2148 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
2149 insn->setSrc(1, proj);
2150 dst[c] = insn->getDef(0);
2151 }
2152 if (!mask)
2153 return;
2154
2155 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
2156
2157 for (c = 0; c < 4; ++c)
2158 if (mask & (1 << c))
2159 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
2160 }
2161
2162 // order of nv50 ir sources: x y z layer lod/bias shadow
2163 // order of TGSI TEX sources: x y z layer shadow lod/bias
2164 // lowering will finally set the hw specific order (like array first on nvc0)
2165 void
2166 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
2167 {
2168 Value *arg[4], *src[8];
2169 Value *lod = NULL, *shd = NULL;
2170 unsigned int s, c, d;
2171 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2172
2173 TexInstruction::Target tgt = tgsi.getTexture(code, R);
2174
2175 for (s = 0; s < tgt.getArgCount(); ++s)
2176 arg[s] = src[s] = fetchSrc(0, s);
2177
2178 if (texi->op == OP_TXL || texi->op == OP_TXB)
2179 lod = fetchSrc(L >> 4, L & 3);
2180
2181 if (C == 0x0f)
2182 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
2183
2184 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
2185 tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
2186 shd = fetchSrc(1, 0);
2187 else if (tgt.isShadow())
2188 shd = fetchSrc(C >> 4, C & 3);
2189
2190 if (texi->op == OP_TXD) {
2191 for (c = 0; c < tgt.getDim() + tgt.isCube(); ++c) {
2192 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
2193 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
2194 }
2195 }
2196
2197 // cube textures don't care about projection value, it's divided out
2198 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
2199 unsigned int n = tgt.getDim();
2200 if (shd) {
2201 arg[n] = shd;
2202 ++n;
2203 assert(tgt.getDim() == tgt.getArgCount());
2204 }
2205 loadProjTexCoords(src, arg, (1 << n) - 1);
2206 if (shd)
2207 shd = src[n - 1];
2208 }
2209
2210 for (c = 0, d = 0; c < 4; ++c) {
2211 if (dst[c]) {
2212 texi->setDef(d++, dst[c]);
2213 texi->tex.mask |= 1 << c;
2214 } else {
2215 // NOTE: maybe hook up def too, for CSE
2216 }
2217 }
2218 for (s = 0; s < tgt.getArgCount(); ++s)
2219 texi->setSrc(s, src[s]);
2220 if (lod)
2221 texi->setSrc(s++, lod);
2222 if (shd)
2223 texi->setSrc(s++, shd);
2224
2225 setTexRS(texi, s, R, S);
2226
2227 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
2228 texi->tex.levelZero = true;
2229 if (prog->getType() != Program::TYPE_FRAGMENT &&
2230 (tgsi.getOpcode() == TGSI_OPCODE_TEX ||
2231 tgsi.getOpcode() == TGSI_OPCODE_TEX2 ||
2232 tgsi.getOpcode() == TGSI_OPCODE_TXP))
2233 texi->tex.levelZero = true;
2234 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
2235 texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
2236
2237 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2238 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2239 for (c = 0; c < 3; ++c) {
2240 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2241 texi->offset[s][c].setInsn(texi);
2242 }
2243 }
2244
2245 bb->insertTail(texi);
2246 }
2247
2248 // 1st source: xyz = coordinates, w = lod/sample
2249 // 2nd source: offset
2250 void
2251 Converter::handleTXF(Value *dst[4], int R, int L_M)
2252 {
2253 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2254 int ms;
2255 unsigned int c, d, s;
2256
2257 texi->tex.target = tgsi.getTexture(code, R);
2258
2259 ms = texi->tex.target.isMS() ? 1 : 0;
2260 texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
2261
2262 for (c = 0, d = 0; c < 4; ++c) {
2263 if (dst[c]) {
2264 texi->setDef(d++, dst[c]);
2265 texi->tex.mask |= 1 << c;
2266 }
2267 }
2268 for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
2269 texi->setSrc(c, fetchSrc(0, c));
2270 texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
2271
2272 setTexRS(texi, c, R, -1);
2273
2274 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2275 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2276 for (c = 0; c < 3; ++c) {
2277 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2278 texi->offset[s][c].setInsn(texi);
2279 }
2280 }
2281
2282 bb->insertTail(texi);
2283 }
2284
2285 void
2286 Converter::handleLIT(Value *dst0[4])
2287 {
2288 Value *val0 = NULL;
2289 unsigned int mask = tgsi.getDst(0).getMask();
2290
2291 if (mask & (1 << 0))
2292 loadImm(dst0[0], 1.0f);
2293
2294 if (mask & (1 << 3))
2295 loadImm(dst0[3], 1.0f);
2296
2297 if (mask & (3 << 1)) {
2298 val0 = getScratch();
2299 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
2300 if (mask & (1 << 1))
2301 mkMov(dst0[1], val0);
2302 }
2303
2304 if (mask & (1 << 2)) {
2305 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
2306 Value *val1 = getScratch(), *val3 = getScratch();
2307
2308 Value *pos128 = loadImm(NULL, +127.999999f);
2309 Value *neg128 = loadImm(NULL, -127.999999f);
2310
2311 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
2312 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
2313 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
2314 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
2315
2316 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
2317 }
2318 }
2319
2320 /* Keep this around for now as reference when adding img support
2321 static inline bool
2322 isResourceSpecial(const int r)
2323 {
2324 return (r == TGSI_RESOURCE_GLOBAL ||
2325 r == TGSI_RESOURCE_LOCAL ||
2326 r == TGSI_RESOURCE_PRIVATE ||
2327 r == TGSI_RESOURCE_INPUT);
2328 }
2329
2330 static inline bool
2331 isResourceRaw(const tgsi::Source *code, const int r)
2332 {
2333 return isResourceSpecial(r) || code->resources[r].raw;
2334 }
2335
2336 static inline nv50_ir::TexTarget
2337 getResourceTarget(const tgsi::Source *code, int r)
2338 {
2339 if (isResourceSpecial(r))
2340 return nv50_ir::TEX_TARGET_BUFFER;
2341 return tgsi::translateTexture(code->resources.at(r).target);
2342 }
2343
2344 Symbol *
2345 Converter::getResourceBase(const int r)
2346 {
2347 Symbol *sym = NULL;
2348
2349 switch (r) {
2350 case TGSI_RESOURCE_GLOBAL:
2351 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL,
2352 info->io.auxCBSlot);
2353 break;
2354 case TGSI_RESOURCE_LOCAL:
2355 assert(prog->getType() == Program::TYPE_COMPUTE);
2356 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2357 info->prop.cp.sharedOffset);
2358 break;
2359 case TGSI_RESOURCE_PRIVATE:
2360 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2361 info->bin.tlsSpace);
2362 break;
2363 case TGSI_RESOURCE_INPUT:
2364 assert(prog->getType() == Program::TYPE_COMPUTE);
2365 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2366 info->prop.cp.inputOffset);
2367 break;
2368 default:
2369 sym = new_Symbol(prog,
2370 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2371 break;
2372 }
2373 return sym;
2374 }
2375
2376 void
2377 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2378 {
2379 const int arg =
2380 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2381
2382 for (int c = 0; c < arg; ++c)
2383 coords.push_back(fetchSrc(s, c));
2384
2385 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2386 if (r == TGSI_RESOURCE_LOCAL ||
2387 r == TGSI_RESOURCE_PRIVATE ||
2388 r == TGSI_RESOURCE_INPUT)
2389 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2390 coords[0]);
2391 }
2392 */
2393 static inline int
2394 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2395 {
2396 int n = 0;
2397
2398 while (mask) {
2399 if (mask & 1) {
2400 size[n]++;
2401 } else {
2402 if (size[n])
2403 comp[n = 1] = size[0] + 1;
2404 else
2405 comp[n]++;
2406 }
2407 mask >>= 1;
2408 }
2409 if (size[0] == 3) {
2410 n = 1;
2411 size[0] = (comp[0] == 1) ? 1 : 2;
2412 size[1] = 3 - size[0];
2413 comp[1] = comp[0] + size[0];
2414 }
2415 return n + 1;
2416 }
2417
2418 static inline nv50_ir::TexTarget
2419 getImageTarget(const tgsi::Source *code, int r)
2420 {
2421 return tgsi::translateTexture(code->images.at(r).target);
2422 }
2423
2424 static inline const nv50_ir::TexInstruction::ImgFormatDesc *
2425 getImageFormat(const tgsi::Source *code, int r)
2426 {
2427 return &nv50_ir::TexInstruction::formatTable[
2428 tgsi::translateImgFormat(code->images.at(r).format)];
2429 }
2430
2431 void
2432 Converter::getImageCoords(std::vector<Value *> &coords, int r, int s)
2433 {
2434 TexInstruction::Target t =
2435 TexInstruction::Target(getImageTarget(code, r));
2436 const int arg = t.getDim() + (t.isArray() || t.isCube());
2437
2438 for (int c = 0; c < arg; ++c)
2439 coords.push_back(fetchSrc(s, c));
2440
2441 if (t.isMS())
2442 coords.push_back(fetchSrc(s, 3));
2443 }
2444
2445 // For raw loads, granularity is 4 byte.
2446 // Usage of the texture read mask on OP_SULDP is not allowed.
2447 void
2448 Converter::handleLOAD(Value *dst0[4])
2449 {
2450 const int r = tgsi.getSrc(0).getIndex(0);
2451 int c;
2452 std::vector<Value *> off, src, ldv, def;
2453
2454 switch (tgsi.getSrc(0).getFile()) {
2455 case TGSI_FILE_BUFFER:
2456 case TGSI_FILE_MEMORY:
2457 for (c = 0; c < 4; ++c) {
2458 if (!dst0[c])
2459 continue;
2460
2461 Value *off;
2462 Symbol *sym;
2463 uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
2464
2465 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
2466 off = NULL;
2467 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2468 tgsi.getSrc(1).getValueU32(0, info) +
2469 src0_component_offset);
2470 } else {
2471 // yzw are ignored for buffers
2472 off = fetchSrc(1, 0);
2473 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2474 src0_component_offset);
2475 }
2476
2477 Instruction *ld = mkLoad(TYPE_U32, dst0[c], sym, off);
2478 ld->cache = tgsi.getCacheMode();
2479 if (tgsi.getSrc(0).isIndirect(0))
2480 ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
2481 }
2482 break;
2483 case TGSI_FILE_IMAGE: {
2484 assert(!code->images[r].raw);
2485
2486 getImageCoords(off, r, 1);
2487 def.resize(4);
2488
2489 for (c = 0; c < 4; ++c) {
2490 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2491 def[c] = getScratch();
2492 else
2493 def[c] = dst0[c];
2494 }
2495
2496 TexInstruction *ld =
2497 mkTex(OP_SULDP, getImageTarget(code, r), code->images[r].slot, 0,
2498 def, off);
2499 ld->tex.mask = tgsi.getDst(0).getMask();
2500 ld->tex.format = getImageFormat(code, r);
2501 ld->cache = tgsi.getCacheMode();
2502 if (tgsi.getSrc(0).isIndirect(0))
2503 ld->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2504
2505 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2506 if (dst0[c] != def[c])
2507 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2508 }
2509 break;
2510 default:
2511 assert(!"Unsupported srcFile for LOAD");
2512 }
2513
2514 /* Keep this around for now as reference when adding img support
2515 getResourceCoords(off, r, 1);
2516
2517 if (isResourceRaw(code, r)) {
2518 uint8_t mask = 0;
2519 uint8_t comp[2] = { 0, 0 };
2520 uint8_t size[2] = { 0, 0 };
2521
2522 Symbol *base = getResourceBase(r);
2523
2524 // determine the base and size of the at most 2 load ops
2525 for (c = 0; c < 4; ++c)
2526 if (!tgsi.getDst(0).isMasked(c))
2527 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2528
2529 int n = partitionLoadStore(comp, size, mask);
2530
2531 src = off;
2532
2533 def.resize(4); // index by component, the ones we need will be non-NULL
2534 for (c = 0; c < 4; ++c) {
2535 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2536 def[c] = dst0[c];
2537 else
2538 if (mask & (1 << c))
2539 def[c] = getScratch();
2540 }
2541
2542 const bool useLd = isResourceSpecial(r) ||
2543 (info->io.nv50styleSurfaces &&
2544 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2545
2546 for (int i = 0; i < n; ++i) {
2547 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2548
2549 if (comp[i]) // adjust x component of source address if necessary
2550 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2551 off[0], mkImm(comp[i] * 4));
2552 else
2553 src[0] = off[0];
2554
2555 if (useLd) {
2556 Instruction *ld =
2557 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2558 for (size_t c = 1; c < ldv.size(); ++c)
2559 ld->setDef(c, ldv[c]);
2560 } else {
2561 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2562 0, ldv, src)->dType = typeOfSize(size[i] * 4);
2563 }
2564 }
2565 } else {
2566 def.resize(4);
2567 for (c = 0; c < 4; ++c) {
2568 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2569 def[c] = getScratch();
2570 else
2571 def[c] = dst0[c];
2572 }
2573
2574 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2575 def, off);
2576 }
2577 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2578 if (dst0[c] != def[c])
2579 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2580 */
2581 }
2582
2583 // For formatted stores, the write mask on OP_SUSTP can be used.
2584 // Raw stores have to be split.
2585 void
2586 Converter::handleSTORE()
2587 {
2588 const int r = tgsi.getDst(0).getIndex(0);
2589 int c;
2590 std::vector<Value *> off, src, dummy;
2591
2592 switch (tgsi.getDst(0).getFile()) {
2593 case TGSI_FILE_BUFFER:
2594 case TGSI_FILE_MEMORY:
2595 for (c = 0; c < 4; ++c) {
2596 if (!(tgsi.getDst(0).getMask() & (1 << c)))
2597 continue;
2598
2599 Symbol *sym;
2600 Value *off;
2601 if (tgsi.getSrc(0).getFile() == TGSI_FILE_IMMEDIATE) {
2602 off = NULL;
2603 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c,
2604 tgsi.getSrc(0).getValueU32(0, info) + 4 * c);
2605 } else {
2606 // yzw are ignored for buffers
2607 off = fetchSrc(0, 0);
2608 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c, 4 * c);
2609 }
2610
2611 Instruction *st = mkStore(OP_STORE, TYPE_U32, sym, off, fetchSrc(1, c));
2612 st->cache = tgsi.getCacheMode();
2613 if (tgsi.getDst(0).isIndirect(0))
2614 st->setIndirect(0, 1, fetchSrc(tgsi.getDst(0).getIndirect(0), 0, 0));
2615 }
2616 break;
2617 case TGSI_FILE_IMAGE: {
2618 assert(!code->images[r].raw);
2619
2620 getImageCoords(off, r, 0);
2621 src = off;
2622
2623 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2624 src.push_back(fetchSrc(1, c));
2625
2626 TexInstruction *st =
2627 mkTex(OP_SUSTP, getImageTarget(code, r), code->images[r].slot,
2628 0, dummy, src);
2629 st->tex.mask = tgsi.getDst(0).getMask();
2630 st->tex.format = getImageFormat(code, r);
2631 st->cache = tgsi.getCacheMode();
2632 if (tgsi.getDst(0).isIndirect(0))
2633 st->setIndirectR(fetchSrc(tgsi.getDst(0).getIndirect(0), 0, NULL));
2634 }
2635 break;
2636 default:
2637 assert(!"Unsupported dstFile for STORE");
2638 }
2639
2640 /* Keep this around for now as reference when adding img support
2641 getResourceCoords(off, r, 0);
2642 src = off;
2643 const int s = src.size();
2644
2645 if (isResourceRaw(code, r)) {
2646 uint8_t comp[2] = { 0, 0 };
2647 uint8_t size[2] = { 0, 0 };
2648
2649 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2650
2651 Symbol *base = getResourceBase(r);
2652
2653 const bool useSt = isResourceSpecial(r) ||
2654 (info->io.nv50styleSurfaces &&
2655 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2656
2657 for (int i = 0; i < n; ++i) {
2658 if (comp[i]) // adjust x component of source address if necessary
2659 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2660 off[0], mkImm(comp[i] * 4));
2661 else
2662 src[0] = off[0];
2663
2664 const DataType stTy = typeOfSize(size[i] * 4);
2665
2666 if (useSt) {
2667 Instruction *st =
2668 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2669 for (c = 1; c < size[i]; ++c)
2670 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2671 st->setIndirect(0, 0, src[0]);
2672 } else {
2673 // attach values to be stored
2674 src.resize(s + size[i]);
2675 for (c = 0; c < size[i]; ++c)
2676 src[s + c] = fetchSrc(1, comp[i] + c);
2677 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2678 0, dummy, src)->setType(stTy);
2679 }
2680 }
2681 } else {
2682 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2683 src.push_back(fetchSrc(1, c));
2684
2685 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2686 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2687 }
2688 */
2689 }
2690
2691 // XXX: These only work on resources with the single-component u32/s32 formats.
2692 // Therefore the result is replicated. This might not be intended by TGSI, but
2693 // operating on more than 1 component would produce undefined results because
2694 // they do not exist.
2695 void
2696 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2697 {
2698 const int r = tgsi.getSrc(0).getIndex(0);
2699 std::vector<Value *> srcv;
2700 std::vector<Value *> defv;
2701 LValue *dst = getScratch();
2702
2703 switch (tgsi.getSrc(0).getFile()) {
2704 case TGSI_FILE_BUFFER:
2705 case TGSI_FILE_MEMORY:
2706 for (int c = 0; c < 4; ++c) {
2707 if (!dst0[c])
2708 continue;
2709
2710 Instruction *insn;
2711 Value *off = fetchSrc(1, c), *off2 = NULL;
2712 Value *sym;
2713 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE)
2714 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2715 tgsi.getSrc(1).getValueU32(c, info));
2716 else
2717 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c, 0);
2718 if (tgsi.getSrc(0).isIndirect(0))
2719 off2 = fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0);
2720 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2721 insn = mkOp3(OP_ATOM, ty, dst, sym, fetchSrc(2, c), fetchSrc(3, c));
2722 else
2723 insn = mkOp2(OP_ATOM, ty, dst, sym, fetchSrc(2, c));
2724 if (tgsi.getSrc(1).getFile() != TGSI_FILE_IMMEDIATE)
2725 insn->setIndirect(0, 0, off);
2726 if (off2)
2727 insn->setIndirect(0, 1, off2);
2728 insn->subOp = subOp;
2729 }
2730 for (int c = 0; c < 4; ++c)
2731 if (dst0[c])
2732 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2733 break;
2734 case TGSI_FILE_IMAGE: {
2735 assert(!code->images[r].raw);
2736
2737 getImageCoords(srcv, r, 1);
2738 defv.push_back(dst);
2739 srcv.push_back(fetchSrc(2, 0));
2740
2741 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2742 srcv.push_back(fetchSrc(3, 0));
2743
2744 TexInstruction *tex = mkTex(OP_SUREDP, getImageTarget(code, r),
2745 code->images[r].slot, 0, defv, srcv);
2746 tex->subOp = subOp;
2747 tex->tex.mask = 1;
2748 tex->tex.format = getImageFormat(code, r);
2749 tex->setType(ty);
2750 if (tgsi.getSrc(0).isIndirect(0))
2751 tex->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2752
2753 for (int c = 0; c < 4; ++c)
2754 if (dst0[c])
2755 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2756 }
2757 break;
2758 default:
2759 assert(!"Unsupported srcFile for ATOM");
2760 }
2761
2762 /* Keep this around for now as reference when adding img support
2763 getResourceCoords(srcv, r, 1);
2764
2765 if (isResourceSpecial(r)) {
2766 assert(r != TGSI_RESOURCE_INPUT);
2767 Instruction *insn;
2768 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2769 insn->subOp = subOp;
2770 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2771 insn->setSrc(2, fetchSrc(3, 0));
2772 insn->setIndirect(0, 0, srcv.at(0));
2773 } else {
2774 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2775 TexTarget targ = getResourceTarget(code, r);
2776 int idx = code->resources[r].slot;
2777 defv.push_back(dst);
2778 srcv.push_back(fetchSrc(2, 0));
2779 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2780 srcv.push_back(fetchSrc(3, 0));
2781 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2782 tex->subOp = subOp;
2783 tex->tex.mask = 1;
2784 tex->setType(ty);
2785 }
2786
2787 for (int c = 0; c < 4; ++c)
2788 if (dst0[c])
2789 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2790 */
2791 }
2792
2793 void
2794 Converter::handleINTERP(Value *dst[4])
2795 {
2796 // Check whether the input is linear. All other attributes ignored.
2797 Instruction *insn;
2798 Value *offset = NULL, *ptr = NULL, *w = NULL;
2799 Symbol *sym[4] = { NULL };
2800 bool linear;
2801 operation op = OP_NOP;
2802 int c, mode = 0;
2803
2804 tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2805
2806 // In some odd cases, in large part due to varying packing, the source
2807 // might not actually be an input. This is illegal TGSI, but it's easier to
2808 // account for it here than it is to fix it where the TGSI is being
2809 // generated. In that case, it's going to be a straight up mov (or sequence
2810 // of mov's) from the input in question. We follow the mov chain to see
2811 // which input we need to use.
2812 if (src.getFile() != TGSI_FILE_INPUT) {
2813 if (src.isIndirect(0)) {
2814 ERROR("Ignoring indirect input interpolation\n");
2815 return;
2816 }
2817 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2818 Value *val = fetchSrc(0, c);
2819 assert(val->defs.size() == 1);
2820 insn = val->getInsn();
2821 while (insn->op == OP_MOV) {
2822 assert(insn->getSrc(0)->defs.size() == 1);
2823 insn = insn->getSrc(0)->getInsn();
2824 if (!insn) {
2825 ERROR("Miscompiling shader due to unhandled INTERP\n");
2826 return;
2827 }
2828 }
2829 if (insn->op != OP_LINTERP && insn->op != OP_PINTERP) {
2830 ERROR("Trying to interpolate non-input, this is not allowed.\n");
2831 return;
2832 }
2833 sym[c] = insn->getSrc(0)->asSym();
2834 assert(sym[c]);
2835 op = insn->op;
2836 mode = insn->ipa;
2837 }
2838 } else {
2839 if (src.isIndirect(0))
2840 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2841
2842 // We can assume that the fixed index will point to an input of the same
2843 // interpolation type in case of an indirect.
2844 // TODO: Make use of ArrayID.
2845 linear = info->in[src.getIndex(0)].linear;
2846 if (linear) {
2847 op = OP_LINTERP;
2848 mode = NV50_IR_INTERP_LINEAR;
2849 } else {
2850 op = OP_PINTERP;
2851 mode = NV50_IR_INTERP_PERSPECTIVE;
2852 }
2853 }
2854
2855 switch (tgsi.getOpcode()) {
2856 case TGSI_OPCODE_INTERP_CENTROID:
2857 mode |= NV50_IR_INTERP_CENTROID;
2858 break;
2859 case TGSI_OPCODE_INTERP_SAMPLE:
2860 insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2861 insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2862 mode |= NV50_IR_INTERP_OFFSET;
2863 break;
2864 case TGSI_OPCODE_INTERP_OFFSET: {
2865 // The input in src1.xy is float, but we need a single 32-bit value
2866 // where the upper and lower 16 bits are encoded in S0.12 format. We need
2867 // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2868 // and then convert to s32.
2869 Value *offs[2];
2870 for (c = 0; c < 2; c++) {
2871 offs[c] = fetchSrc(1, c);
2872 mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2873 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2874 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2875 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2876 }
2877 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2878 offs[1], mkImm(0x1010), offs[0]);
2879 mode |= NV50_IR_INTERP_OFFSET;
2880 break;
2881 }
2882 }
2883
2884 if (op == OP_PINTERP) {
2885 if (offset) {
2886 w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2887 mkOp1(OP_RCP, TYPE_F32, w, w);
2888 } else {
2889 w = fragCoord[3];
2890 }
2891 }
2892
2893
2894 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2895 insn = mkOp1(op, TYPE_F32, dst[c], sym[c] ? sym[c] : srcToSym(src, c));
2896 if (op == OP_PINTERP)
2897 insn->setSrc(1, w);
2898 if (ptr)
2899 insn->setIndirect(0, 0, ptr);
2900 if (offset)
2901 insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2902
2903 insn->setInterpolate(mode);
2904 }
2905 }
2906
2907 Converter::Subroutine *
2908 Converter::getSubroutine(unsigned ip)
2909 {
2910 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2911
2912 if (it == sub.map.end())
2913 it = sub.map.insert(std::make_pair(
2914 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2915
2916 return &it->second;
2917 }
2918
2919 Converter::Subroutine *
2920 Converter::getSubroutine(Function *f)
2921 {
2922 unsigned ip = f->getLabel();
2923 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2924
2925 if (it == sub.map.end())
2926 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2927
2928 return &it->second;
2929 }
2930
2931 bool
2932 Converter::isEndOfSubroutine(uint ip)
2933 {
2934 assert(ip < code->scan.num_instructions);
2935 tgsi::Instruction insn(&code->insns[ip]);
2936 return (insn.getOpcode() == TGSI_OPCODE_END ||
2937 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2938 // does END occur at end of main or the very end ?
2939 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2940 }
2941
2942 bool
2943 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2944 {
2945 Instruction *geni;
2946
2947 Value *dst0[4], *rDst0[4];
2948 Value *src0, *src1, *src2, *src3;
2949 Value *val0, *val1;
2950 int c;
2951
2952 tgsi = tgsi::Instruction(insn);
2953
2954 bool useScratchDst = tgsi.checkDstSrcAliasing();
2955
2956 operation op = tgsi.getOP();
2957 dstTy = tgsi.inferDstType();
2958 srcTy = tgsi.inferSrcType();
2959
2960 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2961
2962 if (tgsi.dstCount()) {
2963 for (c = 0; c < 4; ++c) {
2964 rDst0[c] = acquireDst(0, c);
2965 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2966 }
2967 }
2968
2969 switch (tgsi.getOpcode()) {
2970 case TGSI_OPCODE_ADD:
2971 case TGSI_OPCODE_UADD:
2972 case TGSI_OPCODE_AND:
2973 case TGSI_OPCODE_DIV:
2974 case TGSI_OPCODE_IDIV:
2975 case TGSI_OPCODE_UDIV:
2976 case TGSI_OPCODE_MAX:
2977 case TGSI_OPCODE_MIN:
2978 case TGSI_OPCODE_IMAX:
2979 case TGSI_OPCODE_IMIN:
2980 case TGSI_OPCODE_UMAX:
2981 case TGSI_OPCODE_UMIN:
2982 case TGSI_OPCODE_MOD:
2983 case TGSI_OPCODE_UMOD:
2984 case TGSI_OPCODE_MUL:
2985 case TGSI_OPCODE_UMUL:
2986 case TGSI_OPCODE_IMUL_HI:
2987 case TGSI_OPCODE_UMUL_HI:
2988 case TGSI_OPCODE_OR:
2989 case TGSI_OPCODE_SHL:
2990 case TGSI_OPCODE_ISHR:
2991 case TGSI_OPCODE_USHR:
2992 case TGSI_OPCODE_XOR:
2993 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2994 src0 = fetchSrc(0, c);
2995 src1 = fetchSrc(1, c);
2996 geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2997 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2998 }
2999 break;
3000 case TGSI_OPCODE_MAD:
3001 case TGSI_OPCODE_UMAD:
3002 case TGSI_OPCODE_SAD:
3003 case TGSI_OPCODE_FMA:
3004 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3005 src0 = fetchSrc(0, c);
3006 src1 = fetchSrc(1, c);
3007 src2 = fetchSrc(2, c);
3008 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
3009 }
3010 break;
3011 case TGSI_OPCODE_MOV:
3012 case TGSI_OPCODE_CEIL:
3013 case TGSI_OPCODE_FLR:
3014 case TGSI_OPCODE_TRUNC:
3015 case TGSI_OPCODE_RCP:
3016 case TGSI_OPCODE_SQRT:
3017 case TGSI_OPCODE_IABS:
3018 case TGSI_OPCODE_INEG:
3019 case TGSI_OPCODE_NOT:
3020 case TGSI_OPCODE_DDX:
3021 case TGSI_OPCODE_DDY:
3022 case TGSI_OPCODE_DDX_FINE:
3023 case TGSI_OPCODE_DDY_FINE:
3024 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3025 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
3026 break;
3027 case TGSI_OPCODE_RSQ:
3028 src0 = fetchSrc(0, 0);
3029 val0 = getScratch();
3030 mkOp1(OP_ABS, TYPE_F32, val0, src0);
3031 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
3032 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3033 mkMov(dst0[c], val0);
3034 break;
3035 case TGSI_OPCODE_ARL:
3036 case TGSI_OPCODE_ARR:
3037 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3038 const RoundMode rnd =
3039 tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
3040 src0 = fetchSrc(0, c);
3041 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
3042 }
3043 break;
3044 case TGSI_OPCODE_UARL:
3045 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3046 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
3047 break;
3048 case TGSI_OPCODE_POW:
3049 val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
3050 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3051 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3052 break;
3053 case TGSI_OPCODE_EX2:
3054 case TGSI_OPCODE_LG2:
3055 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
3056 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3057 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3058 break;
3059 case TGSI_OPCODE_COS:
3060 case TGSI_OPCODE_SIN:
3061 val0 = getScratch();
3062 if (mask & 7) {
3063 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
3064 mkOp1(op, TYPE_F32, val0, val0);
3065 for (c = 0; c < 3; ++c)
3066 if (dst0[c])
3067 mkMov(dst0[c], val0);
3068 }
3069 if (dst0[3]) {
3070 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
3071 mkOp1(op, TYPE_F32, dst0[3], val0);
3072 }
3073 break;
3074 case TGSI_OPCODE_SCS:
3075 if (mask & 3) {
3076 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
3077 if (dst0[0])
3078 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
3079 if (dst0[1])
3080 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
3081 }
3082 if (dst0[2])
3083 loadImm(dst0[2], 0.0f);
3084 if (dst0[3])
3085 loadImm(dst0[3], 1.0f);
3086 break;
3087 case TGSI_OPCODE_EXP:
3088 src0 = fetchSrc(0, 0);
3089 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
3090 if (dst0[1])
3091 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
3092 if (dst0[0])
3093 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
3094 if (dst0[2])
3095 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
3096 if (dst0[3])
3097 loadImm(dst0[3], 1.0f);
3098 break;
3099 case TGSI_OPCODE_LOG:
3100 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
3101 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
3102 if (dst0[0] || dst0[1])
3103 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
3104 if (dst0[1]) {
3105 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
3106 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
3107 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
3108 }
3109 if (dst0[3])
3110 loadImm(dst0[3], 1.0f);
3111 break;
3112 case TGSI_OPCODE_DP2:
3113 val0 = buildDot(2);
3114 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3115 mkMov(dst0[c], val0);
3116 break;
3117 case TGSI_OPCODE_DP3:
3118 val0 = buildDot(3);
3119 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3120 mkMov(dst0[c], val0);
3121 break;
3122 case TGSI_OPCODE_DP4:
3123 val0 = buildDot(4);
3124 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3125 mkMov(dst0[c], val0);
3126 break;
3127 case TGSI_OPCODE_DPH:
3128 val0 = buildDot(3);
3129 src1 = fetchSrc(1, 3);
3130 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
3131 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3132 mkMov(dst0[c], val0);
3133 break;
3134 case TGSI_OPCODE_DST:
3135 if (dst0[0])
3136 loadImm(dst0[0], 1.0f);
3137 if (dst0[1]) {
3138 src0 = fetchSrc(0, 1);
3139 src1 = fetchSrc(1, 1);
3140 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
3141 }
3142 if (dst0[2])
3143 mkMov(dst0[2], fetchSrc(0, 2));
3144 if (dst0[3])
3145 mkMov(dst0[3], fetchSrc(1, 3));
3146 break;
3147 case TGSI_OPCODE_LRP:
3148 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3149 src0 = fetchSrc(0, c);
3150 src1 = fetchSrc(1, c);
3151 src2 = fetchSrc(2, c);
3152 mkOp3(OP_MAD, TYPE_F32, dst0[c],
3153 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
3154 }
3155 break;
3156 case TGSI_OPCODE_LIT:
3157 handleLIT(dst0);
3158 break;
3159 case TGSI_OPCODE_XPD:
3160 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3161 if (c < 3) {
3162 val0 = getSSA();
3163 src0 = fetchSrc(1, (c + 1) % 3);
3164 src1 = fetchSrc(0, (c + 2) % 3);
3165 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
3166 mkOp1(OP_NEG, TYPE_F32, val0, val0);
3167
3168 src0 = fetchSrc(0, (c + 1) % 3);
3169 src1 = fetchSrc(1, (c + 2) % 3);
3170 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
3171 } else {
3172 loadImm(dst0[c], 1.0f);
3173 }
3174 }
3175 break;
3176 case TGSI_OPCODE_ISSG:
3177 case TGSI_OPCODE_SSG:
3178 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3179 src0 = fetchSrc(0, c);
3180 val0 = getScratch();
3181 val1 = getScratch();
3182 mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
3183 mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
3184 if (srcTy == TYPE_F32)
3185 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
3186 else
3187 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
3188 }
3189 break;
3190 case TGSI_OPCODE_UCMP:
3191 srcTy = TYPE_U32;
3192 /* fallthrough */
3193 case TGSI_OPCODE_CMP:
3194 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3195 src0 = fetchSrc(0, c);
3196 src1 = fetchSrc(1, c);
3197 src2 = fetchSrc(2, c);
3198 if (src1 == src2)
3199 mkMov(dst0[c], src1);
3200 else
3201 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
3202 srcTy, dst0[c], srcTy, src1, src2, src0);
3203 }
3204 break;
3205 case TGSI_OPCODE_FRC:
3206 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3207 src0 = fetchSrc(0, c);
3208 val0 = getScratch();
3209 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
3210 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
3211 }
3212 break;
3213 case TGSI_OPCODE_ROUND:
3214 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3215 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
3216 ->rnd = ROUND_NI;
3217 break;
3218 case TGSI_OPCODE_CLAMP:
3219 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3220 src0 = fetchSrc(0, c);
3221 src1 = fetchSrc(1, c);
3222 src2 = fetchSrc(2, c);
3223 val0 = getScratch();
3224 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
3225 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
3226 }
3227 break;
3228 case TGSI_OPCODE_SLT:
3229 case TGSI_OPCODE_SGE:
3230 case TGSI_OPCODE_SEQ:
3231 case TGSI_OPCODE_SGT:
3232 case TGSI_OPCODE_SLE:
3233 case TGSI_OPCODE_SNE:
3234 case TGSI_OPCODE_FSEQ:
3235 case TGSI_OPCODE_FSGE:
3236 case TGSI_OPCODE_FSLT:
3237 case TGSI_OPCODE_FSNE:
3238 case TGSI_OPCODE_ISGE:
3239 case TGSI_OPCODE_ISLT:
3240 case TGSI_OPCODE_USEQ:
3241 case TGSI_OPCODE_USGE:
3242 case TGSI_OPCODE_USLT:
3243 case TGSI_OPCODE_USNE:
3244 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3245 src0 = fetchSrc(0, c);
3246 src1 = fetchSrc(1, c);
3247 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3248 }
3249 break;
3250 case TGSI_OPCODE_VOTE_ALL:
3251 case TGSI_OPCODE_VOTE_ANY:
3252 case TGSI_OPCODE_VOTE_EQ:
3253 val0 = new_LValue(func, FILE_PREDICATE);
3254 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3255 mkCmp(OP_SET, CC_NE, TYPE_U32, val0, TYPE_U32, fetchSrc(0, c), zero);
3256 mkOp1(op, dstTy, val0, val0)
3257 ->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3258 mkCvt(OP_CVT, TYPE_U32, dst0[c], TYPE_U8, val0);
3259 }
3260 break;
3261 case TGSI_OPCODE_KILL_IF:
3262 val0 = new_LValue(func, FILE_PREDICATE);
3263 mask = 0;
3264 for (c = 0; c < 4; ++c) {
3265 const int s = tgsi.getSrc(0).getSwizzle(c);
3266 if (mask & (1 << s))
3267 continue;
3268 mask |= 1 << s;
3269 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
3270 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
3271 }
3272 break;
3273 case TGSI_OPCODE_KILL:
3274 mkOp(OP_DISCARD, TYPE_NONE, NULL);
3275 break;
3276 case TGSI_OPCODE_TEX:
3277 case TGSI_OPCODE_TXB:
3278 case TGSI_OPCODE_TXL:
3279 case TGSI_OPCODE_TXP:
3280 case TGSI_OPCODE_LODQ:
3281 // R S L C Dx Dy
3282 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
3283 break;
3284 case TGSI_OPCODE_TXD:
3285 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
3286 break;
3287 case TGSI_OPCODE_TG4:
3288 handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
3289 break;
3290 case TGSI_OPCODE_TEX2:
3291 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
3292 break;
3293 case TGSI_OPCODE_TXB2:
3294 case TGSI_OPCODE_TXL2:
3295 handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
3296 break;
3297 case TGSI_OPCODE_SAMPLE:
3298 case TGSI_OPCODE_SAMPLE_B:
3299 case TGSI_OPCODE_SAMPLE_D:
3300 case TGSI_OPCODE_SAMPLE_L:
3301 case TGSI_OPCODE_SAMPLE_C:
3302 case TGSI_OPCODE_SAMPLE_C_LZ:
3303 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
3304 break;
3305 case TGSI_OPCODE_TXF:
3306 handleTXF(dst0, 1, 0x03);
3307 break;
3308 case TGSI_OPCODE_SAMPLE_I:
3309 handleTXF(dst0, 1, 0x03);
3310 break;
3311 case TGSI_OPCODE_SAMPLE_I_MS:
3312 handleTXF(dst0, 1, 0x20);
3313 break;
3314 case TGSI_OPCODE_TXQ:
3315 case TGSI_OPCODE_SVIEWINFO:
3316 handleTXQ(dst0, TXQ_DIMS, 1);
3317 break;
3318 case TGSI_OPCODE_TXQS:
3319 // The TXQ_TYPE query returns samples in its 3rd arg, but we need it to
3320 // be in .x
3321 dst0[1] = dst0[2] = dst0[3] = NULL;
3322 std::swap(dst0[0], dst0[2]);
3323 handleTXQ(dst0, TXQ_TYPE, 0);
3324 std::swap(dst0[0], dst0[2]);
3325 break;
3326 case TGSI_OPCODE_F2I:
3327 case TGSI_OPCODE_F2U:
3328 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3329 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
3330 break;
3331 case TGSI_OPCODE_I2F:
3332 case TGSI_OPCODE_U2F:
3333 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3334 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
3335 break;
3336 case TGSI_OPCODE_PK2H:
3337 val0 = getScratch();
3338 val1 = getScratch();
3339 mkCvt(OP_CVT, TYPE_F16, val0, TYPE_F32, fetchSrc(0, 0));
3340 mkCvt(OP_CVT, TYPE_F16, val1, TYPE_F32, fetchSrc(0, 1));
3341 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3342 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3343 break;
3344 case TGSI_OPCODE_UP2H:
3345 src0 = fetchSrc(0, 0);
3346 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3347 geni = mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F16, src0);
3348 geni->subOp = c & 1;
3349 }
3350 break;
3351 case TGSI_OPCODE_EMIT:
3352 /* export the saved viewport index */
3353 if (viewport != NULL) {
3354 Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
3355 info->out[info->io.viewportId].slot[0] * 4);
3356 mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
3357 }
3358 /* fallthrough */
3359 case TGSI_OPCODE_ENDPRIM:
3360 {
3361 // get vertex stream (must be immediate)
3362 unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
3363 if (stream && op == OP_RESTART)
3364 break;
3365 if (info->prop.gp.maxVertices == 0)
3366 break;
3367 src0 = mkImm(stream);
3368 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
3369 break;
3370 }
3371 case TGSI_OPCODE_IF:
3372 case TGSI_OPCODE_UIF:
3373 {
3374 BasicBlock *ifBB = new BasicBlock(func);
3375
3376 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
3377 condBBs.push(bb);
3378 joinBBs.push(bb);
3379
3380 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
3381
3382 setPosition(ifBB, true);
3383 }
3384 break;
3385 case TGSI_OPCODE_ELSE:
3386 {
3387 BasicBlock *elseBB = new BasicBlock(func);
3388 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3389
3390 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
3391 condBBs.push(bb);
3392
3393 forkBB->getExit()->asFlow()->target.bb = elseBB;
3394 if (!bb->isTerminated())
3395 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
3396
3397 setPosition(elseBB, true);
3398 }
3399 break;
3400 case TGSI_OPCODE_ENDIF:
3401 {
3402 BasicBlock *convBB = new BasicBlock(func);
3403 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3404 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
3405
3406 if (!bb->isTerminated()) {
3407 // we only want join if none of the clauses ended with CONT/BREAK/RET
3408 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
3409 insertConvergenceOps(convBB, forkBB);
3410 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
3411 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3412 }
3413
3414 if (prevBB->getExit()->op == OP_BRA) {
3415 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3416 prevBB->getExit()->asFlow()->target.bb = convBB;
3417 }
3418 setPosition(convBB, true);
3419 }
3420 break;
3421 case TGSI_OPCODE_BGNLOOP:
3422 {
3423 BasicBlock *lbgnBB = new BasicBlock(func);
3424 BasicBlock *lbrkBB = new BasicBlock(func);
3425
3426 loopBBs.push(lbgnBB);
3427 breakBBs.push(lbrkBB);
3428 if (loopBBs.getSize() > func->loopNestingBound)
3429 func->loopNestingBound++;
3430
3431 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
3432
3433 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
3434 setPosition(lbgnBB, true);
3435 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
3436 }
3437 break;
3438 case TGSI_OPCODE_ENDLOOP:
3439 {
3440 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
3441
3442 if (!bb->isTerminated()) {
3443 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
3444 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
3445 }
3446 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
3447
3448 // If the loop never breaks (e.g. only has RET's inside), then there
3449 // will be no way to get to the break bb. However BGNLOOP will have
3450 // already made a PREBREAK to it, so it must be in the CFG.
3451 if (getBB()->cfg.incidentCount() == 0)
3452 loopBB->cfg.attach(&getBB()->cfg, Graph::Edge::TREE);
3453 }
3454 break;
3455 case TGSI_OPCODE_BRK:
3456 {
3457 if (bb->isTerminated())
3458 break;
3459 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
3460 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
3461 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
3462 }
3463 break;
3464 case TGSI_OPCODE_CONT:
3465 {
3466 if (bb->isTerminated())
3467 break;
3468 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
3469 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
3470 contBB->explicitCont = true;
3471 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
3472 }
3473 break;
3474 case TGSI_OPCODE_BGNSUB:
3475 {
3476 Subroutine *s = getSubroutine(ip);
3477 BasicBlock *entry = new BasicBlock(s->f);
3478 BasicBlock *leave = new BasicBlock(s->f);
3479
3480 // multiple entrypoints possible, keep the graph connected
3481 if (prog->getType() == Program::TYPE_COMPUTE)
3482 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
3483
3484 sub.cur = s;
3485 s->f->setEntry(entry);
3486 s->f->setExit(leave);
3487 setPosition(entry, true);
3488 return true;
3489 }
3490 case TGSI_OPCODE_ENDSUB:
3491 {
3492 sub.cur = getSubroutine(prog->main);
3493 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
3494 return true;
3495 }
3496 case TGSI_OPCODE_CAL:
3497 {
3498 Subroutine *s = getSubroutine(tgsi.getLabel());
3499 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
3500 func->call.attach(&s->f->call, Graph::Edge::TREE);
3501 return true;
3502 }
3503 case TGSI_OPCODE_RET:
3504 {
3505 if (bb->isTerminated())
3506 return true;
3507 BasicBlock *leave = BasicBlock::get(func->cfgExit);
3508
3509 if (!isEndOfSubroutine(ip + 1)) {
3510 // insert a PRERET at the entry if this is an early return
3511 // (only needed for sharing code in the epilogue)
3512 BasicBlock *root = BasicBlock::get(func->cfg.getRoot());
3513 if (root->getEntry() == NULL || root->getEntry()->op != OP_PRERET) {
3514 BasicBlock *pos = getBB();
3515 setPosition(root, false);
3516 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
3517 setPosition(pos, true);
3518 }
3519 }
3520 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
3521 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
3522 }
3523 break;
3524 case TGSI_OPCODE_END:
3525 {
3526 // attach and generate epilogue code
3527 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
3528 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
3529 setPosition(epilogue, true);
3530 if (prog->getType() == Program::TYPE_FRAGMENT)
3531 exportOutputs();
3532 if (info->io.genUserClip > 0)
3533 handleUserClipPlanes();
3534 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
3535 }
3536 break;
3537 case TGSI_OPCODE_SWITCH:
3538 case TGSI_OPCODE_CASE:
3539 ERROR("switch/case opcode encountered, should have been lowered\n");
3540 abort();
3541 break;
3542 case TGSI_OPCODE_LOAD:
3543 handleLOAD(dst0);
3544 break;
3545 case TGSI_OPCODE_STORE:
3546 handleSTORE();
3547 break;
3548 case TGSI_OPCODE_BARRIER:
3549 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
3550 geni->fixed = 1;
3551 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
3552 break;
3553 case TGSI_OPCODE_MFENCE:
3554 case TGSI_OPCODE_LFENCE:
3555 case TGSI_OPCODE_SFENCE:
3556 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3557 geni->fixed = 1;
3558 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3559 break;
3560 case TGSI_OPCODE_MEMBAR:
3561 {
3562 uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
3563 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3564 geni->fixed = 1;
3565 if (!(level & ~(TGSI_MEMBAR_THREAD_GROUP | TGSI_MEMBAR_SHARED)))
3566 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
3567 else
3568 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
3569 }
3570 break;
3571 case TGSI_OPCODE_ATOMUADD:
3572 case TGSI_OPCODE_ATOMXCHG:
3573 case TGSI_OPCODE_ATOMCAS:
3574 case TGSI_OPCODE_ATOMAND:
3575 case TGSI_OPCODE_ATOMOR:
3576 case TGSI_OPCODE_ATOMXOR:
3577 case TGSI_OPCODE_ATOMUMIN:
3578 case TGSI_OPCODE_ATOMIMIN:
3579 case TGSI_OPCODE_ATOMUMAX:
3580 case TGSI_OPCODE_ATOMIMAX:
3581 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
3582 break;
3583 case TGSI_OPCODE_RESQ:
3584 if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER) {
3585 geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
3586 makeSym(tgsi.getSrc(0).getFile(),
3587 tgsi.getSrc(0).getIndex(0), -1, 0, 0));
3588 if (tgsi.getSrc(0).isIndirect(0))
3589 geni->setIndirect(0, 1,
3590 fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
3591 } else {
3592 assert(tgsi.getSrc(0).getFile() == TGSI_FILE_IMAGE);
3593
3594 TexInstruction *texi = new_TexInstruction(func, OP_SUQ);
3595 for (int c = 0, d = 0; c < 4; ++c) {
3596 if (dst0[c]) {
3597 texi->setDef(d++, dst0[c]);
3598 texi->tex.mask |= 1 << c;
3599 }
3600 }
3601 texi->tex.r = tgsi.getSrc(0).getIndex(0);
3602 texi->tex.target = getImageTarget(code, texi->tex.r);
3603 bb->insertTail(texi);
3604
3605 if (tgsi.getSrc(0).isIndirect(0))
3606 texi->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
3607 }
3608 break;
3609 case TGSI_OPCODE_IBFE:
3610 case TGSI_OPCODE_UBFE:
3611 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3612 src0 = fetchSrc(0, c);
3613 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
3614 tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
3615 src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
3616 tgsi.getSrc(1).getValueU32(c, info));
3617 } else {
3618 src1 = fetchSrc(1, c);
3619 src2 = fetchSrc(2, c);
3620 mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
3621 }
3622 mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
3623 }
3624 break;
3625 case TGSI_OPCODE_BFI:
3626 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3627 src0 = fetchSrc(0, c);
3628 src1 = fetchSrc(1, c);
3629 src2 = fetchSrc(2, c);
3630 src3 = fetchSrc(3, c);
3631 mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
3632 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
3633 }
3634 break;
3635 case TGSI_OPCODE_LSB:
3636 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3637 src0 = fetchSrc(0, c);
3638 geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
3639 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3640 geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
3641 geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3642 }
3643 break;
3644 case TGSI_OPCODE_IMSB:
3645 case TGSI_OPCODE_UMSB:
3646 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3647 src0 = fetchSrc(0, c);
3648 mkOp1(OP_BFIND, srcTy, dst0[c], src0);
3649 }
3650 break;
3651 case TGSI_OPCODE_BREV:
3652 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3653 src0 = fetchSrc(0, c);
3654 geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
3655 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3656 }
3657 break;
3658 case TGSI_OPCODE_POPC:
3659 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3660 src0 = fetchSrc(0, c);
3661 mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
3662 }
3663 break;
3664 case TGSI_OPCODE_INTERP_CENTROID:
3665 case TGSI_OPCODE_INTERP_SAMPLE:
3666 case TGSI_OPCODE_INTERP_OFFSET:
3667 handleINTERP(dst0);
3668 break;
3669 case TGSI_OPCODE_D2I:
3670 case TGSI_OPCODE_D2U:
3671 case TGSI_OPCODE_D2F: {
3672 int pos = 0;
3673 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3674 Value *dreg = getSSA(8);
3675 src0 = fetchSrc(0, pos);
3676 src1 = fetchSrc(0, pos + 1);
3677 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3678 Instruction *cvt = mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
3679 if (!isFloatType(dstTy))
3680 cvt->rnd = ROUND_Z;
3681 pos += 2;
3682 }
3683 break;
3684 }
3685 case TGSI_OPCODE_I2D:
3686 case TGSI_OPCODE_U2D:
3687 case TGSI_OPCODE_F2D:
3688 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3689 Value *dreg = getSSA(8);
3690 mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
3691 mkSplit(&dst0[c], 4, dreg);
3692 c++;
3693 }
3694 break;
3695 case TGSI_OPCODE_DABS:
3696 case TGSI_OPCODE_DNEG:
3697 case TGSI_OPCODE_DRCP:
3698 case TGSI_OPCODE_DSQRT:
3699 case TGSI_OPCODE_DRSQ:
3700 case TGSI_OPCODE_DTRUNC:
3701 case TGSI_OPCODE_DCEIL:
3702 case TGSI_OPCODE_DFLR:
3703 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3704 src0 = getSSA(8);
3705 Value *dst = getSSA(8), *tmp[2];
3706 tmp[0] = fetchSrc(0, c);
3707 tmp[1] = fetchSrc(0, c + 1);
3708 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3709 mkOp1(op, dstTy, dst, src0);
3710 mkSplit(&dst0[c], 4, dst);
3711 c++;
3712 }
3713 break;
3714 case TGSI_OPCODE_DFRAC:
3715 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3716 src0 = getSSA(8);
3717 Value *dst = getSSA(8), *tmp[2];
3718 tmp[0] = fetchSrc(0, c);
3719 tmp[1] = fetchSrc(0, c + 1);
3720 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3721 mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3722 mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3723 mkSplit(&dst0[c], 4, dst);
3724 c++;
3725 }
3726 break;
3727 case TGSI_OPCODE_DSLT:
3728 case TGSI_OPCODE_DSGE:
3729 case TGSI_OPCODE_DSEQ:
3730 case TGSI_OPCODE_DSNE: {
3731 int pos = 0;
3732 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3733 Value *tmp[2];
3734
3735 src0 = getSSA(8);
3736 src1 = getSSA(8);
3737 tmp[0] = fetchSrc(0, pos);
3738 tmp[1] = fetchSrc(0, pos + 1);
3739 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3740 tmp[0] = fetchSrc(1, pos);
3741 tmp[1] = fetchSrc(1, pos + 1);
3742 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3743 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3744 pos += 2;
3745 }
3746 break;
3747 }
3748 case TGSI_OPCODE_DADD:
3749 case TGSI_OPCODE_DMUL:
3750 case TGSI_OPCODE_DDIV:
3751 case TGSI_OPCODE_DMAX:
3752 case TGSI_OPCODE_DMIN:
3753 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3754 src0 = getSSA(8);
3755 src1 = getSSA(8);
3756 Value *dst = getSSA(8), *tmp[2];
3757 tmp[0] = fetchSrc(0, c);
3758 tmp[1] = fetchSrc(0, c + 1);
3759 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3760 tmp[0] = fetchSrc(1, c);
3761 tmp[1] = fetchSrc(1, c + 1);
3762 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3763 mkOp2(op, dstTy, dst, src0, src1);
3764 mkSplit(&dst0[c], 4, dst);
3765 c++;
3766 }
3767 break;
3768 case TGSI_OPCODE_DMAD:
3769 case TGSI_OPCODE_DFMA:
3770 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3771 src0 = getSSA(8);
3772 src1 = getSSA(8);
3773 src2 = getSSA(8);
3774 Value *dst = getSSA(8), *tmp[2];
3775 tmp[0] = fetchSrc(0, c);
3776 tmp[1] = fetchSrc(0, c + 1);
3777 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3778 tmp[0] = fetchSrc(1, c);
3779 tmp[1] = fetchSrc(1, c + 1);
3780 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3781 tmp[0] = fetchSrc(2, c);
3782 tmp[1] = fetchSrc(2, c + 1);
3783 mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3784 mkOp3(op, dstTy, dst, src0, src1, src2);
3785 mkSplit(&dst0[c], 4, dst);
3786 c++;
3787 }
3788 break;
3789 case TGSI_OPCODE_DROUND:
3790 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3791 src0 = getSSA(8);
3792 Value *dst = getSSA(8), *tmp[2];
3793 tmp[0] = fetchSrc(0, c);
3794 tmp[1] = fetchSrc(0, c + 1);
3795 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3796 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3797 ->rnd = ROUND_NI;
3798 mkSplit(&dst0[c], 4, dst);
3799 c++;
3800 }
3801 break;
3802 case TGSI_OPCODE_DSSG:
3803 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3804 src0 = getSSA(8);
3805 Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3806 tmp[0] = fetchSrc(0, c);
3807 tmp[1] = fetchSrc(0, c + 1);
3808 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3809
3810 val0 = getScratch();
3811 val1 = getScratch();
3812 // The zero is wrong here since it's only 32-bit, but it works out in
3813 // the end since it gets replaced with $r63.
3814 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3815 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3816 mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3817 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3818 mkSplit(&dst0[c], 4, dst);
3819 c++;
3820 }
3821 break;
3822 default:
3823 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3824 assert(0);
3825 break;
3826 }
3827
3828 if (tgsi.dstCount()) {
3829 for (c = 0; c < 4; ++c) {
3830 if (!dst0[c])
3831 continue;
3832 if (dst0[c] != rDst0[c])
3833 mkMov(rDst0[c], dst0[c]);
3834 storeDst(0, c, rDst0[c]);
3835 }
3836 }
3837 vtxBaseValid = 0;
3838
3839 return true;
3840 }
3841
3842 void
3843 Converter::handleUserClipPlanes()
3844 {
3845 Value *res[8];
3846 int n, i, c;
3847
3848 for (c = 0; c < 4; ++c) {
3849 for (i = 0; i < info->io.genUserClip; ++i) {
3850 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3851 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3852 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3853 if (c == 0)
3854 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3855 else
3856 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3857 }
3858 }
3859
3860 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3861
3862 for (i = 0; i < info->io.genUserClip; ++i) {
3863 n = i / 4 + first;
3864 c = i % 4;
3865 Symbol *sym =
3866 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3867 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3868 }
3869 }
3870
3871 void
3872 Converter::exportOutputs()
3873 {
3874 if (info->io.alphaRefBase) {
3875 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3876 if (info->out[i].sn != TGSI_SEMANTIC_COLOR ||
3877 info->out[i].si != 0)
3878 continue;
3879 const unsigned int c = 3;
3880 if (!oData.exists(sub.cur->values, i, c))
3881 continue;
3882 Value *val = oData.load(sub.cur->values, i, c, NULL);
3883 if (!val)
3884 continue;
3885
3886 Symbol *ref = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3887 TYPE_U32, info->io.alphaRefBase);
3888 Value *pred = new_LValue(func, FILE_PREDICATE);
3889 mkCmp(OP_SET, CC_TR, TYPE_U32, pred, TYPE_F32, val,
3890 mkLoadv(TYPE_U32, ref, NULL))
3891 ->subOp = 1;
3892 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_NOT_P, pred);
3893 }
3894 }
3895
3896 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3897 for (unsigned int c = 0; c < 4; ++c) {
3898 if (!oData.exists(sub.cur->values, i, c))
3899 continue;
3900 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3901 info->out[i].slot[c] * 4);
3902 Value *val = oData.load(sub.cur->values, i, c, NULL);
3903 if (val) {
3904 if (info->out[i].sn == TGSI_SEMANTIC_POSITION)
3905 mkOp1(OP_SAT, TYPE_F32, val, val);
3906 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3907 }
3908 }
3909 }
3910 }
3911
3912 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3913 code(code),
3914 tgsi(NULL),
3915 tData(this), lData(this), aData(this), pData(this), oData(this)
3916 {
3917 info = code->info;
3918
3919 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3920 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3921 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3922 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3923
3924 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, FILE_GPR, 0);
3925 lData.setup(TGSI_FILE_TEMPORARY, 1, 0, tSize, 4, 4, FILE_MEMORY_LOCAL, 0);
3926 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3927 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3928 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3929
3930 zero = mkImm((uint32_t)0);
3931
3932 vtxBaseValid = 0;
3933 }
3934
3935 Converter::~Converter()
3936 {
3937 }
3938
3939 inline const Converter::Location *
3940 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3941 {
3942 ValueMap::l_iterator it = s->values.l.find(v);
3943 return it == s->values.l.end() ? NULL : &it->second;
3944 }
3945
3946 template<typename T> inline void
3947 Converter::BindArgumentsPass::updateCallArgs(
3948 Instruction *i, void (Instruction::*setArg)(int, Value *),
3949 T (Function::*proto))
3950 {
3951 Function *g = i->asFlow()->target.fn;
3952 Subroutine *subg = conv.getSubroutine(g);
3953
3954 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3955 Value *v = (g->*proto)[a].get();
3956 const Converter::Location &l = *getValueLocation(subg, v);
3957 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3958
3959 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3960 }
3961 }
3962
3963 template<typename T> inline void
3964 Converter::BindArgumentsPass::updatePrototype(
3965 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3966 {
3967 (func->*updateSet)();
3968
3969 for (unsigned i = 0; i < set->getSize(); ++i) {
3970 Value *v = func->getLValue(i);
3971 const Converter::Location *l = getValueLocation(sub, v);
3972
3973 // only include values with a matching TGSI register
3974 if (set->test(i) && l && !conv.code->locals.count(*l))
3975 (func->*proto).push_back(v);
3976 }
3977 }
3978
3979 bool
3980 Converter::BindArgumentsPass::visit(Function *f)
3981 {
3982 sub = conv.getSubroutine(f);
3983
3984 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3985 !bi.end(); bi.next()) {
3986 for (Instruction *i = BasicBlock::get(bi)->getFirst();
3987 i; i = i->next) {
3988 if (i->op == OP_CALL && !i->asFlow()->builtin) {
3989 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3990 updateCallArgs(i, &Instruction::setDef, &Function::outs);
3991 }
3992 }
3993 }
3994
3995 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3996 return true;
3997 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3998 &Function::buildLiveSets, &Function::ins);
3999 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
4000 &Function::buildDefSets, &Function::outs);
4001
4002 return true;
4003 }
4004
4005 bool
4006 Converter::run()
4007 {
4008 BasicBlock *entry = new BasicBlock(prog->main);
4009 BasicBlock *leave = new BasicBlock(prog->main);
4010
4011 prog->main->setEntry(entry);
4012 prog->main->setExit(leave);
4013
4014 setPosition(entry, true);
4015 sub.cur = getSubroutine(prog->main);
4016
4017 if (info->io.genUserClip > 0) {
4018 for (int c = 0; c < 4; ++c)
4019 clipVtx[c] = getScratch();
4020 }
4021
4022 switch (prog->getType()) {
4023 case Program::TYPE_TESSELLATION_CONTROL:
4024 outBase = mkOp2v(
4025 OP_SUB, TYPE_U32, getSSA(),
4026 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
4027 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
4028 break;
4029 case Program::TYPE_FRAGMENT: {
4030 Symbol *sv = mkSysVal(SV_POSITION, 3);
4031 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
4032 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
4033 break;
4034 }
4035 default:
4036 break;
4037 }
4038
4039 if (info->io.viewportId >= 0)
4040 viewport = getScratch();
4041 else
4042 viewport = NULL;
4043
4044 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
4045 if (!handleInstruction(&code->insns[ip]))
4046 return false;
4047 }
4048
4049 if (!BindArgumentsPass(*this).run(prog))
4050 return false;
4051
4052 return true;
4053 }
4054
4055 } // unnamed namespace
4056
4057 namespace nv50_ir {
4058
4059 bool
4060 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
4061 {
4062 tgsi::Source src(info);
4063 if (!src.scanSource())
4064 return false;
4065 tlsSize = info->bin.tlsSpace;
4066
4067 Converter builder(this, &src);
4068 return builder.run();
4069 }
4070
4071 } // namespace nv50_ir