nv50/ir: fix comments about instructions info
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "tgsi/tgsi_dump.h"
24 #include "tgsi/tgsi_scan.h"
25 #include "tgsi/tgsi_util.h"
26
27 #include <set>
28
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_util.h"
31 #include "codegen/nv50_ir_build_util.h"
32
33 namespace tgsi {
34
35 class Source;
36
37 static nv50_ir::operation translateOpcode(uint opcode);
38 static nv50_ir::DataFile translateFile(uint file);
39 static nv50_ir::TexTarget translateTexture(uint texTarg);
40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
41 static nv50_ir::CacheMode translateCacheMode(uint qualifier);
42 static nv50_ir::ImgFormat translateImgFormat(uint format);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 int getArrayId() const
101 {
102 if (isIndirect(0))
103 return fsr->Indirect.ArrayID;
104 return 0;
105 }
106
107 nv50_ir::Modifier getMod(int chan) const;
108
109 SrcRegister getIndirect(int dim) const
110 {
111 assert(fsr && isIndirect(dim));
112 if (dim)
113 return SrcRegister(fsr->DimIndirect);
114 return SrcRegister(fsr->Indirect);
115 }
116
117 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
118 {
119 assert(reg.File == TGSI_FILE_IMMEDIATE);
120 assert(!reg.Absolute);
121 assert(!reg.Negate);
122 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
123 }
124
125 private:
126 const struct tgsi_src_register reg;
127 const struct tgsi_full_src_register *fsr;
128 };
129
130 class DstRegister
131 {
132 public:
133 DstRegister(const struct tgsi_full_dst_register *dst)
134 : reg(dst->Register),
135 fdr(dst)
136 { }
137
138 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
139
140 uint getFile() const { return reg.File; }
141
142 bool is2D() const { return reg.Dimension; }
143
144 bool isIndirect(int dim) const
145 {
146 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
147 }
148
149 int getIndex(int dim) const
150 {
151 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
152 }
153
154 unsigned int getMask() const { return reg.WriteMask; }
155
156 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
157
158 SrcRegister getIndirect(int dim) const
159 {
160 assert(fdr && isIndirect(dim));
161 if (dim)
162 return SrcRegister(fdr->DimIndirect);
163 return SrcRegister(fdr->Indirect);
164 }
165
166 int getArrayId() const
167 {
168 if (isIndirect(0))
169 return fdr->Indirect.ArrayID;
170 return 0;
171 }
172
173 private:
174 const struct tgsi_dst_register reg;
175 const struct tgsi_full_dst_register *fdr;
176 };
177
178 inline uint getOpcode() const { return insn->Instruction.Opcode; }
179
180 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
181 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
182
183 // mask of used components of source s
184 unsigned int srcMask(unsigned int s) const;
185
186 SrcRegister getSrc(unsigned int s) const
187 {
188 assert(s < srcCount());
189 return SrcRegister(&insn->Src[s]);
190 }
191
192 DstRegister getDst(unsigned int d) const
193 {
194 assert(d < dstCount());
195 return DstRegister(&insn->Dst[d]);
196 }
197
198 SrcRegister getTexOffset(unsigned int i) const
199 {
200 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
201 return SrcRegister(insn->TexOffsets[i]);
202 }
203
204 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
205
206 bool checkDstSrcAliasing() const;
207
208 inline nv50_ir::operation getOP() const {
209 return translateOpcode(getOpcode()); }
210
211 nv50_ir::DataType inferSrcType() const;
212 nv50_ir::DataType inferDstType() const;
213
214 nv50_ir::CondCode getSetCond() const;
215
216 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
217
218 nv50_ir::CacheMode getCacheMode() const {
219 if (!insn->Instruction.Memory)
220 return nv50_ir::CACHE_CA;
221 return translateCacheMode(insn->Memory.Qualifier);
222 }
223
224 inline uint getLabel() { return insn->Label.Label; }
225
226 unsigned getSaturate() const { return insn->Instruction.Saturate; }
227
228 void print() const
229 {
230 tgsi_dump_instruction(insn, 1);
231 }
232
233 private:
234 const struct tgsi_full_instruction *insn;
235 };
236
237 unsigned int Instruction::srcMask(unsigned int s) const
238 {
239 unsigned int mask = insn->Dst[0].Register.WriteMask;
240
241 switch (insn->Instruction.Opcode) {
242 case TGSI_OPCODE_COS:
243 case TGSI_OPCODE_SIN:
244 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
245 case TGSI_OPCODE_DP2:
246 return 0x3;
247 case TGSI_OPCODE_DP3:
248 return 0x7;
249 case TGSI_OPCODE_DP4:
250 case TGSI_OPCODE_DPH:
251 case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
252 return 0xf;
253 case TGSI_OPCODE_DST:
254 return mask & (s ? 0xa : 0x6);
255 case TGSI_OPCODE_EX2:
256 case TGSI_OPCODE_EXP:
257 case TGSI_OPCODE_LG2:
258 case TGSI_OPCODE_LOG:
259 case TGSI_OPCODE_POW:
260 case TGSI_OPCODE_RCP:
261 case TGSI_OPCODE_RSQ:
262 case TGSI_OPCODE_SCS:
263 return 0x1;
264 case TGSI_OPCODE_IF:
265 case TGSI_OPCODE_UIF:
266 return 0x1;
267 case TGSI_OPCODE_LIT:
268 return 0xb;
269 case TGSI_OPCODE_TEX2:
270 case TGSI_OPCODE_TXB2:
271 case TGSI_OPCODE_TXL2:
272 return (s == 0) ? 0xf : 0x3;
273 case TGSI_OPCODE_TEX:
274 case TGSI_OPCODE_TXB:
275 case TGSI_OPCODE_TXD:
276 case TGSI_OPCODE_TXL:
277 case TGSI_OPCODE_TXP:
278 case TGSI_OPCODE_LODQ:
279 {
280 const struct tgsi_instruction_texture *tex = &insn->Texture;
281
282 assert(insn->Instruction.Texture);
283
284 mask = 0x7;
285 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
286 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
287 mask |= 0x8; /* bias, lod or proj */
288
289 switch (tex->Texture) {
290 case TGSI_TEXTURE_1D:
291 mask &= 0x9;
292 break;
293 case TGSI_TEXTURE_SHADOW1D:
294 mask &= 0xd;
295 break;
296 case TGSI_TEXTURE_1D_ARRAY:
297 case TGSI_TEXTURE_2D:
298 case TGSI_TEXTURE_RECT:
299 mask &= 0xb;
300 break;
301 case TGSI_TEXTURE_CUBE_ARRAY:
302 case TGSI_TEXTURE_SHADOW2D_ARRAY:
303 case TGSI_TEXTURE_SHADOWCUBE:
304 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
305 mask |= 0x8;
306 break;
307 default:
308 break;
309 }
310 }
311 return mask;
312 case TGSI_OPCODE_XPD:
313 {
314 unsigned int x = 0;
315 if (mask & 1) x |= 0x6;
316 if (mask & 2) x |= 0x5;
317 if (mask & 4) x |= 0x3;
318 return x;
319 }
320 case TGSI_OPCODE_D2I:
321 case TGSI_OPCODE_D2U:
322 case TGSI_OPCODE_D2F:
323 case TGSI_OPCODE_DSLT:
324 case TGSI_OPCODE_DSGE:
325 case TGSI_OPCODE_DSEQ:
326 case TGSI_OPCODE_DSNE:
327 switch (util_bitcount(mask)) {
328 case 1: return 0x3;
329 case 2: return 0xf;
330 default:
331 assert(!"unexpected mask");
332 return 0xf;
333 }
334 case TGSI_OPCODE_I2D:
335 case TGSI_OPCODE_U2D:
336 case TGSI_OPCODE_F2D: {
337 unsigned int x = 0;
338 if ((mask & 0x3) == 0x3)
339 x |= 1;
340 if ((mask & 0xc) == 0xc)
341 x |= 2;
342 return x;
343 }
344 case TGSI_OPCODE_PK2H:
345 return 0x3;
346 case TGSI_OPCODE_UP2H:
347 return 0x1;
348 default:
349 break;
350 }
351
352 return mask;
353 }
354
355 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
356 {
357 nv50_ir::Modifier m(0);
358
359 if (reg.Absolute)
360 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
361 if (reg.Negate)
362 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
363 return m;
364 }
365
366 static nv50_ir::DataFile translateFile(uint file)
367 {
368 switch (file) {
369 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
370 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
371 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
372 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
373 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
374 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
375 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
376 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
377 case TGSI_FILE_BUFFER: return nv50_ir::FILE_MEMORY_BUFFER;
378 case TGSI_FILE_IMAGE: return nv50_ir::FILE_MEMORY_GLOBAL;
379 case TGSI_FILE_MEMORY: return nv50_ir::FILE_MEMORY_GLOBAL;
380 case TGSI_FILE_SAMPLER:
381 case TGSI_FILE_NULL:
382 default:
383 return nv50_ir::FILE_NULL;
384 }
385 }
386
387 static nv50_ir::SVSemantic translateSysVal(uint sysval)
388 {
389 switch (sysval) {
390 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
391 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
392 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
393 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
394 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
395 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
396 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
397 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
398 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
399 case TGSI_SEMANTIC_SAMPLEID: return nv50_ir::SV_SAMPLE_INDEX;
400 case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
401 case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
402 case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
403 case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD;
404 case TGSI_SEMANTIC_TESSOUTER: return nv50_ir::SV_TESS_OUTER;
405 case TGSI_SEMANTIC_TESSINNER: return nv50_ir::SV_TESS_INNER;
406 case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
407 case TGSI_SEMANTIC_HELPER_INVOCATION: return nv50_ir::SV_THREAD_KILL;
408 case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
409 case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
410 case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
411 case TGSI_SEMANTIC_WORK_DIM: return nv50_ir::SV_WORK_DIM;
412 default:
413 assert(0);
414 return nv50_ir::SV_CLOCK;
415 }
416 }
417
418 #define NV50_IR_TEX_TARG_CASE(a, b) \
419 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
420
421 static nv50_ir::TexTarget translateTexture(uint tex)
422 {
423 switch (tex) {
424 NV50_IR_TEX_TARG_CASE(1D, 1D);
425 NV50_IR_TEX_TARG_CASE(2D, 2D);
426 NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
427 NV50_IR_TEX_TARG_CASE(3D, 3D);
428 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
429 NV50_IR_TEX_TARG_CASE(RECT, RECT);
430 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
431 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
432 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
433 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
434 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
435 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
436 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
437 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
438 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
439 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
440 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
441 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
442
443 case TGSI_TEXTURE_UNKNOWN:
444 default:
445 assert(!"invalid texture target");
446 return nv50_ir::TEX_TARGET_2D;
447 }
448 }
449
450 static nv50_ir::CacheMode translateCacheMode(uint qualifier)
451 {
452 if (qualifier & TGSI_MEMORY_VOLATILE)
453 return nv50_ir::CACHE_CV;
454 if (qualifier & TGSI_MEMORY_COHERENT)
455 return nv50_ir::CACHE_CG;
456 return nv50_ir::CACHE_CA;
457 }
458
459 static nv50_ir::ImgFormat translateImgFormat(uint format)
460 {
461
462 #define FMT_CASE(a, b) \
463 case PIPE_FORMAT_ ## a: return nv50_ir::FMT_ ## b
464
465 switch (format) {
466 FMT_CASE(NONE, NONE);
467
468 FMT_CASE(R32G32B32A32_FLOAT, RGBA32F);
469 FMT_CASE(R16G16B16A16_FLOAT, RGBA16F);
470 FMT_CASE(R32G32_FLOAT, RG32F);
471 FMT_CASE(R16G16_FLOAT, RG16F);
472 FMT_CASE(R11G11B10_FLOAT, R11G11B10F);
473 FMT_CASE(R32_FLOAT, R32F);
474 FMT_CASE(R16_FLOAT, R16F);
475
476 FMT_CASE(R32G32B32A32_UINT, RGBA32UI);
477 FMT_CASE(R16G16B16A16_UINT, RGBA16UI);
478 FMT_CASE(R10G10B10A2_UINT, RGB10A2UI);
479 FMT_CASE(R8G8B8A8_UINT, RGBA8UI);
480 FMT_CASE(R32G32_UINT, RG32UI);
481 FMT_CASE(R16G16_UINT, RG16UI);
482 FMT_CASE(R8G8_UINT, RG8UI);
483 FMT_CASE(R32_UINT, R32UI);
484 FMT_CASE(R16_UINT, R16UI);
485 FMT_CASE(R8_UINT, R8UI);
486
487 FMT_CASE(R32G32B32A32_SINT, RGBA32I);
488 FMT_CASE(R16G16B16A16_SINT, RGBA16I);
489 FMT_CASE(R8G8B8A8_SINT, RGBA8I);
490 FMT_CASE(R32G32_SINT, RG32I);
491 FMT_CASE(R16G16_SINT, RG16I);
492 FMT_CASE(R8G8_SINT, RG8I);
493 FMT_CASE(R32_SINT, R32I);
494 FMT_CASE(R16_SINT, R16I);
495 FMT_CASE(R8_SINT, R8I);
496
497 FMT_CASE(R16G16B16A16_UNORM, RGBA16);
498 FMT_CASE(R10G10B10A2_UNORM, RGB10A2);
499 FMT_CASE(R8G8B8A8_UNORM, RGBA8);
500 FMT_CASE(R16G16_UNORM, RG16);
501 FMT_CASE(R8G8_UNORM, RG8);
502 FMT_CASE(R16_UNORM, R16);
503 FMT_CASE(R8_UNORM, R8);
504
505 FMT_CASE(R16G16B16A16_SNORM, RGBA16_SNORM);
506 FMT_CASE(R8G8B8A8_SNORM, RGBA8_SNORM);
507 FMT_CASE(R16G16_SNORM, RG16_SNORM);
508 FMT_CASE(R8G8_SNORM, RG8_SNORM);
509 FMT_CASE(R16_SNORM, R16_SNORM);
510 FMT_CASE(R8_SNORM, R8_SNORM);
511
512 FMT_CASE(B8G8R8A8_UNORM, BGRA8);
513 }
514
515 assert(!"Unexpected format");
516 return nv50_ir::FMT_NONE;
517 }
518
519 nv50_ir::DataType Instruction::inferSrcType() const
520 {
521 switch (getOpcode()) {
522 case TGSI_OPCODE_UIF:
523 case TGSI_OPCODE_AND:
524 case TGSI_OPCODE_OR:
525 case TGSI_OPCODE_XOR:
526 case TGSI_OPCODE_NOT:
527 case TGSI_OPCODE_SHL:
528 case TGSI_OPCODE_U2F:
529 case TGSI_OPCODE_U2D:
530 case TGSI_OPCODE_UADD:
531 case TGSI_OPCODE_UDIV:
532 case TGSI_OPCODE_UMOD:
533 case TGSI_OPCODE_UMAD:
534 case TGSI_OPCODE_UMUL:
535 case TGSI_OPCODE_UMUL_HI:
536 case TGSI_OPCODE_UMAX:
537 case TGSI_OPCODE_UMIN:
538 case TGSI_OPCODE_USEQ:
539 case TGSI_OPCODE_USGE:
540 case TGSI_OPCODE_USLT:
541 case TGSI_OPCODE_USNE:
542 case TGSI_OPCODE_USHR:
543 case TGSI_OPCODE_ATOMUADD:
544 case TGSI_OPCODE_ATOMXCHG:
545 case TGSI_OPCODE_ATOMCAS:
546 case TGSI_OPCODE_ATOMAND:
547 case TGSI_OPCODE_ATOMOR:
548 case TGSI_OPCODE_ATOMXOR:
549 case TGSI_OPCODE_ATOMUMIN:
550 case TGSI_OPCODE_ATOMUMAX:
551 case TGSI_OPCODE_UBFE:
552 case TGSI_OPCODE_UMSB:
553 case TGSI_OPCODE_UP2H:
554 case TGSI_OPCODE_VOTE_ALL:
555 case TGSI_OPCODE_VOTE_ANY:
556 case TGSI_OPCODE_VOTE_EQ:
557 return nv50_ir::TYPE_U32;
558 case TGSI_OPCODE_I2F:
559 case TGSI_OPCODE_I2D:
560 case TGSI_OPCODE_IDIV:
561 case TGSI_OPCODE_IMUL_HI:
562 case TGSI_OPCODE_IMAX:
563 case TGSI_OPCODE_IMIN:
564 case TGSI_OPCODE_IABS:
565 case TGSI_OPCODE_INEG:
566 case TGSI_OPCODE_ISGE:
567 case TGSI_OPCODE_ISHR:
568 case TGSI_OPCODE_ISLT:
569 case TGSI_OPCODE_ISSG:
570 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
571 case TGSI_OPCODE_MOD:
572 case TGSI_OPCODE_UARL:
573 case TGSI_OPCODE_ATOMIMIN:
574 case TGSI_OPCODE_ATOMIMAX:
575 case TGSI_OPCODE_IBFE:
576 case TGSI_OPCODE_IMSB:
577 return nv50_ir::TYPE_S32;
578 case TGSI_OPCODE_D2F:
579 case TGSI_OPCODE_D2I:
580 case TGSI_OPCODE_D2U:
581 case TGSI_OPCODE_DABS:
582 case TGSI_OPCODE_DNEG:
583 case TGSI_OPCODE_DADD:
584 case TGSI_OPCODE_DMUL:
585 case TGSI_OPCODE_DMAX:
586 case TGSI_OPCODE_DMIN:
587 case TGSI_OPCODE_DSLT:
588 case TGSI_OPCODE_DSGE:
589 case TGSI_OPCODE_DSEQ:
590 case TGSI_OPCODE_DSNE:
591 case TGSI_OPCODE_DRCP:
592 case TGSI_OPCODE_DSQRT:
593 case TGSI_OPCODE_DMAD:
594 case TGSI_OPCODE_DFMA:
595 case TGSI_OPCODE_DFRAC:
596 case TGSI_OPCODE_DRSQ:
597 case TGSI_OPCODE_DTRUNC:
598 case TGSI_OPCODE_DCEIL:
599 case TGSI_OPCODE_DFLR:
600 case TGSI_OPCODE_DROUND:
601 return nv50_ir::TYPE_F64;
602 default:
603 return nv50_ir::TYPE_F32;
604 }
605 }
606
607 nv50_ir::DataType Instruction::inferDstType() const
608 {
609 switch (getOpcode()) {
610 case TGSI_OPCODE_D2U:
611 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
612 case TGSI_OPCODE_D2I:
613 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
614 case TGSI_OPCODE_FSEQ:
615 case TGSI_OPCODE_FSGE:
616 case TGSI_OPCODE_FSLT:
617 case TGSI_OPCODE_FSNE:
618 case TGSI_OPCODE_DSEQ:
619 case TGSI_OPCODE_DSGE:
620 case TGSI_OPCODE_DSLT:
621 case TGSI_OPCODE_DSNE:
622 case TGSI_OPCODE_PK2H:
623 return nv50_ir::TYPE_U32;
624 case TGSI_OPCODE_I2F:
625 case TGSI_OPCODE_U2F:
626 case TGSI_OPCODE_D2F:
627 case TGSI_OPCODE_UP2H:
628 return nv50_ir::TYPE_F32;
629 case TGSI_OPCODE_I2D:
630 case TGSI_OPCODE_U2D:
631 case TGSI_OPCODE_F2D:
632 return nv50_ir::TYPE_F64;
633 default:
634 return inferSrcType();
635 }
636 }
637
638 nv50_ir::CondCode Instruction::getSetCond() const
639 {
640 using namespace nv50_ir;
641
642 switch (getOpcode()) {
643 case TGSI_OPCODE_SLT:
644 case TGSI_OPCODE_ISLT:
645 case TGSI_OPCODE_USLT:
646 case TGSI_OPCODE_FSLT:
647 case TGSI_OPCODE_DSLT:
648 return CC_LT;
649 case TGSI_OPCODE_SLE:
650 return CC_LE;
651 case TGSI_OPCODE_SGE:
652 case TGSI_OPCODE_ISGE:
653 case TGSI_OPCODE_USGE:
654 case TGSI_OPCODE_FSGE:
655 case TGSI_OPCODE_DSGE:
656 return CC_GE;
657 case TGSI_OPCODE_SGT:
658 return CC_GT;
659 case TGSI_OPCODE_SEQ:
660 case TGSI_OPCODE_USEQ:
661 case TGSI_OPCODE_FSEQ:
662 case TGSI_OPCODE_DSEQ:
663 return CC_EQ;
664 case TGSI_OPCODE_SNE:
665 case TGSI_OPCODE_FSNE:
666 case TGSI_OPCODE_DSNE:
667 return CC_NEU;
668 case TGSI_OPCODE_USNE:
669 return CC_NE;
670 default:
671 return CC_ALWAYS;
672 }
673 }
674
675 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
676
677 static nv50_ir::operation translateOpcode(uint opcode)
678 {
679 switch (opcode) {
680 NV50_IR_OPCODE_CASE(ARL, SHL);
681 NV50_IR_OPCODE_CASE(MOV, MOV);
682
683 NV50_IR_OPCODE_CASE(RCP, RCP);
684 NV50_IR_OPCODE_CASE(RSQ, RSQ);
685 NV50_IR_OPCODE_CASE(SQRT, SQRT);
686
687 NV50_IR_OPCODE_CASE(MUL, MUL);
688 NV50_IR_OPCODE_CASE(ADD, ADD);
689
690 NV50_IR_OPCODE_CASE(MIN, MIN);
691 NV50_IR_OPCODE_CASE(MAX, MAX);
692 NV50_IR_OPCODE_CASE(SLT, SET);
693 NV50_IR_OPCODE_CASE(SGE, SET);
694 NV50_IR_OPCODE_CASE(MAD, MAD);
695 NV50_IR_OPCODE_CASE(FMA, FMA);
696 NV50_IR_OPCODE_CASE(SUB, SUB);
697
698 NV50_IR_OPCODE_CASE(FLR, FLOOR);
699 NV50_IR_OPCODE_CASE(ROUND, CVT);
700 NV50_IR_OPCODE_CASE(EX2, EX2);
701 NV50_IR_OPCODE_CASE(LG2, LG2);
702 NV50_IR_OPCODE_CASE(POW, POW);
703
704 NV50_IR_OPCODE_CASE(ABS, ABS);
705
706 NV50_IR_OPCODE_CASE(COS, COS);
707 NV50_IR_OPCODE_CASE(DDX, DFDX);
708 NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
709 NV50_IR_OPCODE_CASE(DDY, DFDY);
710 NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
711 NV50_IR_OPCODE_CASE(KILL, DISCARD);
712
713 NV50_IR_OPCODE_CASE(SEQ, SET);
714 NV50_IR_OPCODE_CASE(SGT, SET);
715 NV50_IR_OPCODE_CASE(SIN, SIN);
716 NV50_IR_OPCODE_CASE(SLE, SET);
717 NV50_IR_OPCODE_CASE(SNE, SET);
718 NV50_IR_OPCODE_CASE(TEX, TEX);
719 NV50_IR_OPCODE_CASE(TXD, TXD);
720 NV50_IR_OPCODE_CASE(TXP, TEX);
721
722 NV50_IR_OPCODE_CASE(CAL, CALL);
723 NV50_IR_OPCODE_CASE(RET, RET);
724 NV50_IR_OPCODE_CASE(CMP, SLCT);
725
726 NV50_IR_OPCODE_CASE(TXB, TXB);
727
728 NV50_IR_OPCODE_CASE(DIV, DIV);
729
730 NV50_IR_OPCODE_CASE(TXL, TXL);
731
732 NV50_IR_OPCODE_CASE(CEIL, CEIL);
733 NV50_IR_OPCODE_CASE(I2F, CVT);
734 NV50_IR_OPCODE_CASE(NOT, NOT);
735 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
736 NV50_IR_OPCODE_CASE(SHL, SHL);
737
738 NV50_IR_OPCODE_CASE(AND, AND);
739 NV50_IR_OPCODE_CASE(OR, OR);
740 NV50_IR_OPCODE_CASE(MOD, MOD);
741 NV50_IR_OPCODE_CASE(XOR, XOR);
742 NV50_IR_OPCODE_CASE(SAD, SAD);
743 NV50_IR_OPCODE_CASE(TXF, TXF);
744 NV50_IR_OPCODE_CASE(TXQ, TXQ);
745 NV50_IR_OPCODE_CASE(TXQS, TXQ);
746 NV50_IR_OPCODE_CASE(TG4, TXG);
747 NV50_IR_OPCODE_CASE(LODQ, TXLQ);
748
749 NV50_IR_OPCODE_CASE(EMIT, EMIT);
750 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
751
752 NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
753
754 NV50_IR_OPCODE_CASE(F2I, CVT);
755 NV50_IR_OPCODE_CASE(FSEQ, SET);
756 NV50_IR_OPCODE_CASE(FSGE, SET);
757 NV50_IR_OPCODE_CASE(FSLT, SET);
758 NV50_IR_OPCODE_CASE(FSNE, SET);
759 NV50_IR_OPCODE_CASE(IDIV, DIV);
760 NV50_IR_OPCODE_CASE(IMAX, MAX);
761 NV50_IR_OPCODE_CASE(IMIN, MIN);
762 NV50_IR_OPCODE_CASE(IABS, ABS);
763 NV50_IR_OPCODE_CASE(INEG, NEG);
764 NV50_IR_OPCODE_CASE(ISGE, SET);
765 NV50_IR_OPCODE_CASE(ISHR, SHR);
766 NV50_IR_OPCODE_CASE(ISLT, SET);
767 NV50_IR_OPCODE_CASE(F2U, CVT);
768 NV50_IR_OPCODE_CASE(U2F, CVT);
769 NV50_IR_OPCODE_CASE(UADD, ADD);
770 NV50_IR_OPCODE_CASE(UDIV, DIV);
771 NV50_IR_OPCODE_CASE(UMAD, MAD);
772 NV50_IR_OPCODE_CASE(UMAX, MAX);
773 NV50_IR_OPCODE_CASE(UMIN, MIN);
774 NV50_IR_OPCODE_CASE(UMOD, MOD);
775 NV50_IR_OPCODE_CASE(UMUL, MUL);
776 NV50_IR_OPCODE_CASE(USEQ, SET);
777 NV50_IR_OPCODE_CASE(USGE, SET);
778 NV50_IR_OPCODE_CASE(USHR, SHR);
779 NV50_IR_OPCODE_CASE(USLT, SET);
780 NV50_IR_OPCODE_CASE(USNE, SET);
781
782 NV50_IR_OPCODE_CASE(DABS, ABS);
783 NV50_IR_OPCODE_CASE(DNEG, NEG);
784 NV50_IR_OPCODE_CASE(DADD, ADD);
785 NV50_IR_OPCODE_CASE(DMUL, MUL);
786 NV50_IR_OPCODE_CASE(DMAX, MAX);
787 NV50_IR_OPCODE_CASE(DMIN, MIN);
788 NV50_IR_OPCODE_CASE(DSLT, SET);
789 NV50_IR_OPCODE_CASE(DSGE, SET);
790 NV50_IR_OPCODE_CASE(DSEQ, SET);
791 NV50_IR_OPCODE_CASE(DSNE, SET);
792 NV50_IR_OPCODE_CASE(DRCP, RCP);
793 NV50_IR_OPCODE_CASE(DSQRT, SQRT);
794 NV50_IR_OPCODE_CASE(DMAD, MAD);
795 NV50_IR_OPCODE_CASE(DFMA, FMA);
796 NV50_IR_OPCODE_CASE(D2I, CVT);
797 NV50_IR_OPCODE_CASE(D2U, CVT);
798 NV50_IR_OPCODE_CASE(I2D, CVT);
799 NV50_IR_OPCODE_CASE(U2D, CVT);
800 NV50_IR_OPCODE_CASE(DRSQ, RSQ);
801 NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
802 NV50_IR_OPCODE_CASE(DCEIL, CEIL);
803 NV50_IR_OPCODE_CASE(DFLR, FLOOR);
804 NV50_IR_OPCODE_CASE(DROUND, CVT);
805
806 NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
807 NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
808
809 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
810 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
811 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
812 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
813 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
814 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
815 NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
816 NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
817 NV50_IR_OPCODE_CASE(GATHER4, TXG);
818 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
819
820 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
821 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
822 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
823 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
824 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
825 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
826 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
827 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
828 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
829 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
830
831 NV50_IR_OPCODE_CASE(TEX2, TEX);
832 NV50_IR_OPCODE_CASE(TXB2, TXB);
833 NV50_IR_OPCODE_CASE(TXL2, TXL);
834
835 NV50_IR_OPCODE_CASE(IBFE, EXTBF);
836 NV50_IR_OPCODE_CASE(UBFE, EXTBF);
837 NV50_IR_OPCODE_CASE(BFI, INSBF);
838 NV50_IR_OPCODE_CASE(BREV, EXTBF);
839 NV50_IR_OPCODE_CASE(POPC, POPCNT);
840 NV50_IR_OPCODE_CASE(LSB, BFIND);
841 NV50_IR_OPCODE_CASE(IMSB, BFIND);
842 NV50_IR_OPCODE_CASE(UMSB, BFIND);
843
844 NV50_IR_OPCODE_CASE(VOTE_ALL, VOTE);
845 NV50_IR_OPCODE_CASE(VOTE_ANY, VOTE);
846 NV50_IR_OPCODE_CASE(VOTE_EQ, VOTE);
847
848 NV50_IR_OPCODE_CASE(END, EXIT);
849
850 default:
851 return nv50_ir::OP_NOP;
852 }
853 }
854
855 static uint16_t opcodeToSubOp(uint opcode)
856 {
857 switch (opcode) {
858 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
859 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
860 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
861 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
862 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
863 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
864 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
865 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
866 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
867 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
868 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
869 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
870 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
871 case TGSI_OPCODE_IMUL_HI:
872 case TGSI_OPCODE_UMUL_HI:
873 return NV50_IR_SUBOP_MUL_HIGH;
874 case TGSI_OPCODE_VOTE_ALL: return NV50_IR_SUBOP_VOTE_ALL;
875 case TGSI_OPCODE_VOTE_ANY: return NV50_IR_SUBOP_VOTE_ANY;
876 case TGSI_OPCODE_VOTE_EQ: return NV50_IR_SUBOP_VOTE_UNI;
877 default:
878 return 0;
879 }
880 }
881
882 bool Instruction::checkDstSrcAliasing() const
883 {
884 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
885 return false;
886
887 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
888 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
889 break;
890 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
891 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
892 return true;
893 }
894 return false;
895 }
896
897 class Source
898 {
899 public:
900 Source(struct nv50_ir_prog_info *);
901 ~Source();
902
903 public:
904 bool scanSource();
905 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
906
907 public:
908 struct tgsi_shader_info scan;
909 struct tgsi_full_instruction *insns;
910 const struct tgsi_token *tokens;
911 struct nv50_ir_prog_info *info;
912
913 nv50_ir::DynArray tempArrays;
914 nv50_ir::DynArray immdArrays;
915
916 typedef nv50_ir::BuildUtil::Location Location;
917 // these registers are per-subroutine, cannot be used for parameter passing
918 std::set<Location> locals;
919
920 std::set<int> indirectTempArrays;
921 std::map<int, int> indirectTempOffsets;
922 std::map<int, std::pair<int, int> > tempArrayInfo;
923 std::vector<int> tempArrayId;
924
925 int clipVertexOutput;
926
927 struct TextureView {
928 uint8_t target; // TGSI_TEXTURE_*
929 };
930 std::vector<TextureView> textureViews;
931
932 /*
933 struct Resource {
934 uint8_t target; // TGSI_TEXTURE_*
935 bool raw;
936 uint8_t slot; // $surface index
937 };
938 std::vector<Resource> resources;
939 */
940
941 struct Image {
942 uint8_t target; // TGSI_TEXTURE_*
943 bool raw;
944 uint8_t slot;
945 uint16_t format; // PIPE_FORMAT_*
946 };
947 std::vector<Image> images;
948
949 struct MemoryFile {
950 uint8_t mem_type; // TGSI_MEMORY_TYPE_*
951 };
952 std::vector<MemoryFile> memoryFiles;
953
954 private:
955 int inferSysValDirection(unsigned sn) const;
956 bool scanDeclaration(const struct tgsi_full_declaration *);
957 bool scanInstruction(const struct tgsi_full_instruction *);
958 void scanProperty(const struct tgsi_full_property *);
959 void scanImmediate(const struct tgsi_full_immediate *);
960
961 inline bool isEdgeFlagPassthrough(const Instruction&) const;
962 };
963
964 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
965 {
966 tokens = (const struct tgsi_token *)info->bin.source;
967
968 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
969 tgsi_dump(tokens, 0);
970 }
971
972 Source::~Source()
973 {
974 if (insns)
975 FREE(insns);
976
977 if (info->immd.data)
978 FREE(info->immd.data);
979 if (info->immd.type)
980 FREE(info->immd.type);
981 }
982
983 bool Source::scanSource()
984 {
985 unsigned insnCount = 0;
986 struct tgsi_parse_context parse;
987
988 tgsi_scan_shader(tokens, &scan);
989
990 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
991 sizeof(insns[0]));
992 if (!insns)
993 return false;
994
995 clipVertexOutput = -1;
996
997 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
998 //resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
999 images.resize(scan.file_max[TGSI_FILE_IMAGE] + 1);
1000 tempArrayId.resize(scan.file_max[TGSI_FILE_TEMPORARY] + 1);
1001 memoryFiles.resize(scan.file_max[TGSI_FILE_MEMORY] + 1);
1002
1003 info->immd.bufSize = 0;
1004
1005 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
1006 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
1007 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
1008
1009 if (info->type == PIPE_SHADER_FRAGMENT) {
1010 info->prop.fp.writesDepth = scan.writes_z;
1011 info->prop.fp.usesDiscard = scan.uses_kill || info->io.alphaRefBase;
1012 } else
1013 if (info->type == PIPE_SHADER_GEOMETRY) {
1014 info->prop.gp.instanceCount = 1; // default value
1015 }
1016
1017 info->io.viewportId = -1;
1018 info->prop.cp.numThreads = 1;
1019
1020 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
1021 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
1022
1023 tgsi_parse_init(&parse, tokens);
1024 while (!tgsi_parse_end_of_tokens(&parse)) {
1025 tgsi_parse_token(&parse);
1026
1027 switch (parse.FullToken.Token.Type) {
1028 case TGSI_TOKEN_TYPE_IMMEDIATE:
1029 scanImmediate(&parse.FullToken.FullImmediate);
1030 break;
1031 case TGSI_TOKEN_TYPE_DECLARATION:
1032 scanDeclaration(&parse.FullToken.FullDeclaration);
1033 break;
1034 case TGSI_TOKEN_TYPE_INSTRUCTION:
1035 insns[insnCount++] = parse.FullToken.FullInstruction;
1036 scanInstruction(&parse.FullToken.FullInstruction);
1037 break;
1038 case TGSI_TOKEN_TYPE_PROPERTY:
1039 scanProperty(&parse.FullToken.FullProperty);
1040 break;
1041 default:
1042 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
1043 break;
1044 }
1045 }
1046 tgsi_parse_free(&parse);
1047
1048 if (indirectTempArrays.size()) {
1049 int tempBase = 0;
1050 for (std::set<int>::const_iterator it = indirectTempArrays.begin();
1051 it != indirectTempArrays.end(); ++it) {
1052 std::pair<int, int>& info = tempArrayInfo[*it];
1053 indirectTempOffsets.insert(std::make_pair(*it, tempBase - info.first));
1054 tempBase += info.second;
1055 }
1056 info->bin.tlsSpace += tempBase * 16;
1057 }
1058
1059 if (info->io.genUserClip > 0) {
1060 info->io.clipDistances = info->io.genUserClip;
1061
1062 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1063
1064 for (unsigned int n = 0; n < nOut; ++n) {
1065 unsigned int i = info->numOutputs++;
1066 info->out[i].id = i;
1067 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1068 info->out[i].si = n;
1069 info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1070 }
1071 }
1072
1073 return info->assignSlots(info) == 0;
1074 }
1075
1076 void Source::scanProperty(const struct tgsi_full_property *prop)
1077 {
1078 switch (prop->Property.PropertyName) {
1079 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1080 info->prop.gp.outputPrim = prop->u[0].Data;
1081 break;
1082 case TGSI_PROPERTY_GS_INPUT_PRIM:
1083 info->prop.gp.inputPrim = prop->u[0].Data;
1084 break;
1085 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1086 info->prop.gp.maxVertices = prop->u[0].Data;
1087 break;
1088 case TGSI_PROPERTY_GS_INVOCATIONS:
1089 info->prop.gp.instanceCount = prop->u[0].Data;
1090 break;
1091 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1092 info->prop.fp.separateFragData = true;
1093 break;
1094 case TGSI_PROPERTY_FS_COORD_ORIGIN:
1095 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
1096 // we don't care
1097 break;
1098 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1099 info->io.genUserClip = -1;
1100 break;
1101 case TGSI_PROPERTY_TCS_VERTICES_OUT:
1102 info->prop.tp.outputPatchSize = prop->u[0].Data;
1103 break;
1104 case TGSI_PROPERTY_TES_PRIM_MODE:
1105 info->prop.tp.domain = prop->u[0].Data;
1106 break;
1107 case TGSI_PROPERTY_TES_SPACING:
1108 info->prop.tp.partitioning = prop->u[0].Data;
1109 break;
1110 case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
1111 info->prop.tp.winding = prop->u[0].Data;
1112 break;
1113 case TGSI_PROPERTY_TES_POINT_MODE:
1114 if (prop->u[0].Data)
1115 info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
1116 else
1117 info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
1118 break;
1119 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
1120 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
1121 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
1122 info->prop.cp.numThreads *= prop->u[0].Data;
1123 break;
1124 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
1125 info->io.clipDistances = prop->u[0].Data;
1126 break;
1127 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
1128 info->io.cullDistances = prop->u[0].Data;
1129 break;
1130 case TGSI_PROPERTY_NEXT_SHADER:
1131 /* Do not need to know the next shader stage. */
1132 break;
1133 case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
1134 info->prop.fp.earlyFragTests = prop->u[0].Data;
1135 break;
1136 default:
1137 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
1138 break;
1139 }
1140 }
1141
1142 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
1143 {
1144 const unsigned n = info->immd.count++;
1145
1146 assert(n < scan.immediate_count);
1147
1148 for (int c = 0; c < 4; ++c)
1149 info->immd.data[n * 4 + c] = imm->u[c].Uint;
1150
1151 info->immd.type[n] = imm->Immediate.DataType;
1152 }
1153
1154 int Source::inferSysValDirection(unsigned sn) const
1155 {
1156 switch (sn) {
1157 case TGSI_SEMANTIC_INSTANCEID:
1158 case TGSI_SEMANTIC_VERTEXID:
1159 return 1;
1160 case TGSI_SEMANTIC_LAYER:
1161 #if 0
1162 case TGSI_SEMANTIC_VIEWPORTINDEX:
1163 return 0;
1164 #endif
1165 case TGSI_SEMANTIC_PRIMID:
1166 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
1167 default:
1168 return 0;
1169 }
1170 }
1171
1172 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
1173 {
1174 unsigned i, c;
1175 unsigned sn = TGSI_SEMANTIC_GENERIC;
1176 unsigned si = 0;
1177 const unsigned first = decl->Range.First, last = decl->Range.Last;
1178 const int arrayId = decl->Array.ArrayID;
1179
1180 if (decl->Declaration.Semantic) {
1181 sn = decl->Semantic.Name;
1182 si = decl->Semantic.Index;
1183 }
1184
1185 if (decl->Declaration.Local || decl->Declaration.File == TGSI_FILE_ADDRESS) {
1186 for (i = first; i <= last; ++i) {
1187 for (c = 0; c < 4; ++c) {
1188 locals.insert(
1189 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1190 }
1191 }
1192 }
1193
1194 switch (decl->Declaration.File) {
1195 case TGSI_FILE_INPUT:
1196 if (info->type == PIPE_SHADER_VERTEX) {
1197 // all vertex attributes are equal
1198 for (i = first; i <= last; ++i) {
1199 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1200 info->in[i].si = i;
1201 }
1202 } else {
1203 for (i = first; i <= last; ++i, ++si) {
1204 info->in[i].id = i;
1205 info->in[i].sn = sn;
1206 info->in[i].si = si;
1207 if (info->type == PIPE_SHADER_FRAGMENT) {
1208 // translate interpolation mode
1209 switch (decl->Interp.Interpolate) {
1210 case TGSI_INTERPOLATE_CONSTANT:
1211 info->in[i].flat = 1;
1212 break;
1213 case TGSI_INTERPOLATE_COLOR:
1214 info->in[i].sc = 1;
1215 break;
1216 case TGSI_INTERPOLATE_LINEAR:
1217 info->in[i].linear = 1;
1218 break;
1219 default:
1220 break;
1221 }
1222 if (decl->Interp.Location)
1223 info->in[i].centroid = 1;
1224 }
1225
1226 if (sn == TGSI_SEMANTIC_PATCH)
1227 info->in[i].patch = 1;
1228 if (sn == TGSI_SEMANTIC_PATCH)
1229 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1230 }
1231 }
1232 break;
1233 case TGSI_FILE_OUTPUT:
1234 for (i = first; i <= last; ++i, ++si) {
1235 switch (sn) {
1236 case TGSI_SEMANTIC_POSITION:
1237 if (info->type == PIPE_SHADER_FRAGMENT)
1238 info->io.fragDepth = i;
1239 else
1240 if (clipVertexOutput < 0)
1241 clipVertexOutput = i;
1242 break;
1243 case TGSI_SEMANTIC_COLOR:
1244 if (info->type == PIPE_SHADER_FRAGMENT)
1245 info->prop.fp.numColourResults++;
1246 break;
1247 case TGSI_SEMANTIC_EDGEFLAG:
1248 info->io.edgeFlagOut = i;
1249 break;
1250 case TGSI_SEMANTIC_CLIPVERTEX:
1251 clipVertexOutput = i;
1252 break;
1253 case TGSI_SEMANTIC_CLIPDIST:
1254 info->io.genUserClip = -1;
1255 break;
1256 case TGSI_SEMANTIC_SAMPLEMASK:
1257 info->io.sampleMask = i;
1258 break;
1259 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1260 info->io.viewportId = i;
1261 break;
1262 case TGSI_SEMANTIC_PATCH:
1263 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1264 /* fallthrough */
1265 case TGSI_SEMANTIC_TESSOUTER:
1266 case TGSI_SEMANTIC_TESSINNER:
1267 info->out[i].patch = 1;
1268 break;
1269 default:
1270 break;
1271 }
1272 info->out[i].id = i;
1273 info->out[i].sn = sn;
1274 info->out[i].si = si;
1275 }
1276 break;
1277 case TGSI_FILE_SYSTEM_VALUE:
1278 switch (sn) {
1279 case TGSI_SEMANTIC_INSTANCEID:
1280 info->io.instanceId = first;
1281 break;
1282 case TGSI_SEMANTIC_VERTEXID:
1283 info->io.vertexId = first;
1284 break;
1285 case TGSI_SEMANTIC_BASEVERTEX:
1286 case TGSI_SEMANTIC_BASEINSTANCE:
1287 case TGSI_SEMANTIC_DRAWID:
1288 info->prop.vp.usesDrawParameters = true;
1289 break;
1290 case TGSI_SEMANTIC_SAMPLEID:
1291 case TGSI_SEMANTIC_SAMPLEPOS:
1292 info->prop.fp.persampleInvocation = true;
1293 break;
1294 case TGSI_SEMANTIC_SAMPLEMASK:
1295 info->prop.fp.usesSampleMaskIn = true;
1296 break;
1297 default:
1298 break;
1299 }
1300 for (i = first; i <= last; ++i, ++si) {
1301 info->sv[i].sn = sn;
1302 info->sv[i].si = si;
1303 info->sv[i].input = inferSysValDirection(sn);
1304
1305 switch (sn) {
1306 case TGSI_SEMANTIC_TESSOUTER:
1307 case TGSI_SEMANTIC_TESSINNER:
1308 info->sv[i].patch = 1;
1309 break;
1310 }
1311 }
1312 break;
1313 /*
1314 case TGSI_FILE_RESOURCE:
1315 for (i = first; i <= last; ++i) {
1316 resources[i].target = decl->Resource.Resource;
1317 resources[i].raw = decl->Resource.Raw;
1318 resources[i].slot = i;
1319 }
1320 break;
1321 */
1322 case TGSI_FILE_IMAGE:
1323 for (i = first; i <= last; ++i) {
1324 images[i].target = decl->Image.Resource;
1325 images[i].raw = decl->Image.Raw;
1326 images[i].format = decl->Image.Format;
1327 images[i].slot = i;
1328 }
1329 break;
1330 case TGSI_FILE_SAMPLER_VIEW:
1331 for (i = first; i <= last; ++i)
1332 textureViews[i].target = decl->SamplerView.Resource;
1333 break;
1334 case TGSI_FILE_MEMORY:
1335 for (i = first; i <= last; ++i)
1336 memoryFiles[i].mem_type = decl->Declaration.MemType;
1337 break;
1338 case TGSI_FILE_NULL:
1339 case TGSI_FILE_TEMPORARY:
1340 for (i = first; i <= last; ++i)
1341 tempArrayId[i] = arrayId;
1342 if (arrayId)
1343 tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
1344 first, last - first + 1)));
1345 break;
1346 case TGSI_FILE_ADDRESS:
1347 case TGSI_FILE_CONSTANT:
1348 case TGSI_FILE_IMMEDIATE:
1349 case TGSI_FILE_PREDICATE:
1350 case TGSI_FILE_SAMPLER:
1351 case TGSI_FILE_BUFFER:
1352 break;
1353 default:
1354 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1355 return false;
1356 }
1357 return true;
1358 }
1359
1360 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1361 {
1362 return insn.getOpcode() == TGSI_OPCODE_MOV &&
1363 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1364 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1365 }
1366
1367 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1368 {
1369 Instruction insn(inst);
1370
1371 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1372 info->numBarriers = 1;
1373
1374 if (insn.dstCount()) {
1375 Instruction::DstRegister dst = insn.getDst(0);
1376
1377 if (dst.getFile() == TGSI_FILE_OUTPUT) {
1378 if (dst.isIndirect(0))
1379 for (unsigned i = 0; i < info->numOutputs; ++i)
1380 info->out[i].mask = 0xf;
1381 else
1382 info->out[dst.getIndex(0)].mask |= dst.getMask();
1383
1384 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1385 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1386 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1387 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1388 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1389 info->out[dst.getIndex(0)].mask &= 1;
1390
1391 if (isEdgeFlagPassthrough(insn))
1392 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1393 } else
1394 if (dst.getFile() == TGSI_FILE_TEMPORARY) {
1395 if (dst.isIndirect(0))
1396 indirectTempArrays.insert(dst.getArrayId());
1397 } else
1398 if (dst.getFile() == TGSI_FILE_BUFFER ||
1399 dst.getFile() == TGSI_FILE_IMAGE ||
1400 (dst.getFile() == TGSI_FILE_MEMORY &&
1401 memoryFiles[dst.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1402 info->io.globalAccess |= 0x2;
1403 }
1404 }
1405
1406 for (unsigned s = 0; s < insn.srcCount(); ++s) {
1407 Instruction::SrcRegister src = insn.getSrc(s);
1408 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1409 if (src.isIndirect(0))
1410 indirectTempArrays.insert(src.getArrayId());
1411 } else
1412 if (src.getFile() == TGSI_FILE_BUFFER ||
1413 src.getFile() == TGSI_FILE_IMAGE ||
1414 (src.getFile() == TGSI_FILE_MEMORY &&
1415 memoryFiles[src.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1416 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1417 0x1 : 0x2;
1418 } else
1419 if (src.getFile() == TGSI_FILE_OUTPUT) {
1420 if (src.isIndirect(0)) {
1421 // We don't know which one is accessed, just mark everything for
1422 // reading. This is an extremely unlikely occurrence.
1423 for (unsigned i = 0; i < info->numOutputs; ++i)
1424 info->out[i].oread = 1;
1425 } else {
1426 info->out[src.getIndex(0)].oread = 1;
1427 }
1428 }
1429 if (src.getFile() != TGSI_FILE_INPUT)
1430 continue;
1431 unsigned mask = insn.srcMask(s);
1432
1433 if (src.isIndirect(0)) {
1434 for (unsigned i = 0; i < info->numInputs; ++i)
1435 info->in[i].mask = 0xf;
1436 } else {
1437 const int i = src.getIndex(0);
1438 for (unsigned c = 0; c < 4; ++c) {
1439 if (!(mask & (1 << c)))
1440 continue;
1441 int k = src.getSwizzle(c);
1442 if (k <= TGSI_SWIZZLE_W)
1443 info->in[i].mask |= 1 << k;
1444 }
1445 switch (info->in[i].sn) {
1446 case TGSI_SEMANTIC_PSIZE:
1447 case TGSI_SEMANTIC_PRIMID:
1448 case TGSI_SEMANTIC_FOG:
1449 info->in[i].mask &= 0x1;
1450 break;
1451 case TGSI_SEMANTIC_PCOORD:
1452 info->in[i].mask &= 0x3;
1453 break;
1454 default:
1455 break;
1456 }
1457 }
1458 }
1459 return true;
1460 }
1461
1462 nv50_ir::TexInstruction::Target
1463 Instruction::getTexture(const tgsi::Source *code, int s) const
1464 {
1465 // XXX: indirect access
1466 unsigned int r;
1467
1468 switch (getSrc(s).getFile()) {
1469 /*
1470 case TGSI_FILE_RESOURCE:
1471 r = getSrc(s).getIndex(0);
1472 return translateTexture(code->resources.at(r).target);
1473 */
1474 case TGSI_FILE_SAMPLER_VIEW:
1475 r = getSrc(s).getIndex(0);
1476 return translateTexture(code->textureViews.at(r).target);
1477 default:
1478 return translateTexture(insn->Texture.Texture);
1479 }
1480 }
1481
1482 } // namespace tgsi
1483
1484 namespace {
1485
1486 using namespace nv50_ir;
1487
1488 class Converter : public BuildUtil
1489 {
1490 public:
1491 Converter(Program *, const tgsi::Source *);
1492 ~Converter();
1493
1494 bool run();
1495
1496 private:
1497 struct Subroutine
1498 {
1499 Subroutine(Function *f) : f(f) { }
1500 Function *f;
1501 ValueMap values;
1502 };
1503
1504 Value *shiftAddress(Value *);
1505 Value *getVertexBase(int s);
1506 Value *getOutputBase(int s);
1507 DataArray *getArrayForFile(unsigned file, int idx);
1508 Value *fetchSrc(int s, int c);
1509 Value *acquireDst(int d, int c);
1510 void storeDst(int d, int c, Value *);
1511
1512 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1513 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1514 Value *val, Value *ptr);
1515
1516 void adjustTempIndex(int arrayId, int &idx, int &idx2d) const;
1517 Value *applySrcMod(Value *, int s, int c);
1518
1519 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1520 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1521 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1522
1523 bool handleInstruction(const struct tgsi_full_instruction *);
1524 void exportOutputs();
1525 inline Subroutine *getSubroutine(unsigned ip);
1526 inline Subroutine *getSubroutine(Function *);
1527 inline bool isEndOfSubroutine(uint ip);
1528
1529 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1530
1531 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1532 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1533 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1534 void handleTXF(Value *dst0[4], int R, int L_M);
1535 void handleTXQ(Value *dst0[4], enum TexQuery, int R);
1536 void handleLIT(Value *dst0[4]);
1537 void handleUserClipPlanes();
1538
1539 // Symbol *getResourceBase(int r);
1540 void getImageCoords(std::vector<Value *>&, int r, int s);
1541
1542 void handleLOAD(Value *dst0[4]);
1543 void handleSTORE();
1544 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1545
1546 void handleINTERP(Value *dst0[4]);
1547
1548 uint8_t translateInterpMode(const struct nv50_ir_varying *var,
1549 operation& op);
1550 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1551
1552 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1553
1554 Value *buildDot(int dim);
1555
1556 class BindArgumentsPass : public Pass {
1557 public:
1558 BindArgumentsPass(Converter &conv) : conv(conv) { }
1559
1560 private:
1561 Converter &conv;
1562 Subroutine *sub;
1563
1564 inline const Location *getValueLocation(Subroutine *, Value *);
1565
1566 template<typename T> inline void
1567 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1568 T (Function::*proto));
1569
1570 template<typename T> inline void
1571 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1572 T (Function::*proto));
1573
1574 protected:
1575 bool visit(Function *);
1576 bool visit(BasicBlock *bb) { return false; }
1577 };
1578
1579 private:
1580 const tgsi::Source *code;
1581 const struct nv50_ir_prog_info *info;
1582
1583 struct {
1584 std::map<unsigned, Subroutine> map;
1585 Subroutine *cur;
1586 } sub;
1587
1588 uint ip; // instruction pointer
1589
1590 tgsi::Instruction tgsi;
1591
1592 DataType dstTy;
1593 DataType srcTy;
1594
1595 DataArray tData; // TGSI_FILE_TEMPORARY
1596 DataArray lData; // TGSI_FILE_TEMPORARY, for indirect arrays
1597 DataArray aData; // TGSI_FILE_ADDRESS
1598 DataArray pData; // TGSI_FILE_PREDICATE
1599 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1600
1601 Value *zero;
1602 Value *fragCoord[4];
1603 Value *clipVtx[4];
1604
1605 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1606 uint8_t vtxBaseValid;
1607
1608 Value *outBase; // base address of vertex out patch (for TCP)
1609
1610 Stack condBBs; // fork BB, then else clause BB
1611 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1612 Stack loopBBs; // loop headers
1613 Stack breakBBs; // end of / after loop
1614
1615 Value *viewport;
1616 };
1617
1618 Symbol *
1619 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1620 {
1621 const int swz = src.getSwizzle(c);
1622
1623 /* TODO: Use Array ID when it's available for the index */
1624 return makeSym(src.getFile(),
1625 src.is2D() ? src.getIndex(1) : 0,
1626 src.getIndex(0), swz,
1627 src.getIndex(0) * 16 + swz * 4);
1628 }
1629
1630 Symbol *
1631 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1632 {
1633 /* TODO: Use Array ID when it's available for the index */
1634 return makeSym(dst.getFile(),
1635 dst.is2D() ? dst.getIndex(1) : 0,
1636 dst.getIndex(0), c,
1637 dst.getIndex(0) * 16 + c * 4);
1638 }
1639
1640 Symbol *
1641 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1642 {
1643 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1644
1645 sym->reg.fileIndex = fileIdx;
1646
1647 if (tgsiFile == TGSI_FILE_MEMORY) {
1648 switch (code->memoryFiles[fileIdx].mem_type) {
1649 case TGSI_MEMORY_TYPE_GLOBAL:
1650 /* No-op this is the default for TGSI_FILE_MEMORY */
1651 sym->setFile(FILE_MEMORY_GLOBAL);
1652 break;
1653 case TGSI_MEMORY_TYPE_SHARED:
1654 sym->setFile(FILE_MEMORY_SHARED);
1655 break;
1656 case TGSI_MEMORY_TYPE_INPUT:
1657 assert(prog->getType() == Program::TYPE_COMPUTE);
1658 assert(idx == -1);
1659 sym->setFile(FILE_SHADER_INPUT);
1660 address += info->prop.cp.inputOffset;
1661 break;
1662 default:
1663 assert(0); /* TODO: Add support for global and private memory */
1664 }
1665 }
1666
1667 if (idx >= 0) {
1668 if (sym->reg.file == FILE_SHADER_INPUT)
1669 sym->setOffset(info->in[idx].slot[c] * 4);
1670 else
1671 if (sym->reg.file == FILE_SHADER_OUTPUT)
1672 sym->setOffset(info->out[idx].slot[c] * 4);
1673 else
1674 if (sym->reg.file == FILE_SYSTEM_VALUE)
1675 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1676 else
1677 sym->setOffset(address);
1678 } else {
1679 sym->setOffset(address);
1680 }
1681 return sym;
1682 }
1683
1684 uint8_t
1685 Converter::translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1686 {
1687 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1688
1689 if (var->flat)
1690 mode = NV50_IR_INTERP_FLAT;
1691 else
1692 if (var->linear)
1693 mode = NV50_IR_INTERP_LINEAR;
1694 else
1695 if (var->sc)
1696 mode = NV50_IR_INTERP_SC;
1697
1698 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1699 ? OP_PINTERP : OP_LINTERP;
1700
1701 if (var->centroid)
1702 mode |= NV50_IR_INTERP_CENTROID;
1703
1704 return mode;
1705 }
1706
1707 Value *
1708 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1709 {
1710 operation op;
1711
1712 // XXX: no way to know interpolation mode if we don't know what's accessed
1713 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1714 src.getIndex(0)], op);
1715
1716 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1717
1718 insn->setDef(0, getScratch());
1719 insn->setSrc(0, srcToSym(src, c));
1720 if (op == OP_PINTERP)
1721 insn->setSrc(1, fragCoord[3]);
1722 if (ptr)
1723 insn->setIndirect(0, 0, ptr);
1724
1725 insn->setInterpolate(mode);
1726
1727 bb->insertTail(insn);
1728 return insn->getDef(0);
1729 }
1730
1731 Value *
1732 Converter::applySrcMod(Value *val, int s, int c)
1733 {
1734 Modifier m = tgsi.getSrc(s).getMod(c);
1735 DataType ty = tgsi.inferSrcType();
1736
1737 if (m & Modifier(NV50_IR_MOD_ABS))
1738 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1739
1740 if (m & Modifier(NV50_IR_MOD_NEG))
1741 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1742
1743 return val;
1744 }
1745
1746 Value *
1747 Converter::getVertexBase(int s)
1748 {
1749 assert(s < 5);
1750 if (!(vtxBaseValid & (1 << s))) {
1751 const int index = tgsi.getSrc(s).getIndex(1);
1752 Value *rel = NULL;
1753 if (tgsi.getSrc(s).isIndirect(1))
1754 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1755 vtxBaseValid |= 1 << s;
1756 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1757 mkImm(index), rel);
1758 }
1759 return vtxBase[s];
1760 }
1761
1762 Value *
1763 Converter::getOutputBase(int s)
1764 {
1765 assert(s < 5);
1766 if (!(vtxBaseValid & (1 << s))) {
1767 Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1));
1768 if (tgsi.getSrc(s).isIndirect(1))
1769 offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(),
1770 fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL),
1771 offset);
1772 vtxBaseValid |= 1 << s;
1773 vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset);
1774 }
1775 return vtxBase[s];
1776 }
1777
1778 Value *
1779 Converter::fetchSrc(int s, int c)
1780 {
1781 Value *res;
1782 Value *ptr = NULL, *dimRel = NULL;
1783
1784 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1785
1786 if (src.isIndirect(0))
1787 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1788
1789 if (src.is2D()) {
1790 switch (src.getFile()) {
1791 case TGSI_FILE_OUTPUT:
1792 dimRel = getOutputBase(s);
1793 break;
1794 case TGSI_FILE_INPUT:
1795 dimRel = getVertexBase(s);
1796 break;
1797 case TGSI_FILE_CONSTANT:
1798 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1799 if (src.isIndirect(1))
1800 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1801 break;
1802 default:
1803 break;
1804 }
1805 }
1806
1807 res = fetchSrc(src, c, ptr);
1808
1809 if (dimRel)
1810 res->getInsn()->setIndirect(0, 1, dimRel);
1811
1812 return applySrcMod(res, s, c);
1813 }
1814
1815 Converter::DataArray *
1816 Converter::getArrayForFile(unsigned file, int idx)
1817 {
1818 switch (file) {
1819 case TGSI_FILE_TEMPORARY:
1820 return idx == 0 ? &tData : &lData;
1821 case TGSI_FILE_PREDICATE:
1822 return &pData;
1823 case TGSI_FILE_ADDRESS:
1824 return &aData;
1825 case TGSI_FILE_OUTPUT:
1826 assert(prog->getType() == Program::TYPE_FRAGMENT);
1827 return &oData;
1828 default:
1829 assert(!"invalid/unhandled TGSI source file");
1830 return NULL;
1831 }
1832 }
1833
1834 Value *
1835 Converter::shiftAddress(Value *index)
1836 {
1837 if (!index)
1838 return NULL;
1839 return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1840 }
1841
1842 void
1843 Converter::adjustTempIndex(int arrayId, int &idx, int &idx2d) const
1844 {
1845 std::map<int, int>::const_iterator it =
1846 code->indirectTempOffsets.find(arrayId);
1847 if (it == code->indirectTempOffsets.end())
1848 return;
1849
1850 idx2d = 1;
1851 idx += it->second;
1852 }
1853
1854 Value *
1855 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1856 {
1857 int idx2d = src.is2D() ? src.getIndex(1) : 0;
1858 int idx = src.getIndex(0);
1859 const int swz = src.getSwizzle(c);
1860 Instruction *ld;
1861
1862 switch (src.getFile()) {
1863 case TGSI_FILE_IMMEDIATE:
1864 assert(!ptr);
1865 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1866 case TGSI_FILE_CONSTANT:
1867 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1868 case TGSI_FILE_INPUT:
1869 if (prog->getType() == Program::TYPE_FRAGMENT) {
1870 // don't load masked inputs, won't be assigned a slot
1871 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1872 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1873 return interpolate(src, c, shiftAddress(ptr));
1874 } else
1875 if (prog->getType() == Program::TYPE_GEOMETRY) {
1876 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1877 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1878 // XXX: This is going to be a problem with scalar arrays, i.e. when
1879 // we cannot assume that the address is given in units of vec4.
1880 //
1881 // nv50 and nvc0 need different things here, so let the lowering
1882 // passes decide what to do with the address
1883 if (ptr)
1884 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1885 }
1886 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1887 ld->perPatch = info->in[idx].patch;
1888 return ld->getDef(0);
1889 case TGSI_FILE_OUTPUT:
1890 assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
1891 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1892 ld->perPatch = info->out[idx].patch;
1893 return ld->getDef(0);
1894 case TGSI_FILE_SYSTEM_VALUE:
1895 assert(!ptr);
1896 ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1897 ld->perPatch = info->sv[idx].patch;
1898 return ld->getDef(0);
1899 case TGSI_FILE_TEMPORARY: {
1900 int arrayid = src.getArrayId();
1901 if (!arrayid)
1902 arrayid = code->tempArrayId[idx];
1903 adjustTempIndex(arrayid, idx, idx2d);
1904 }
1905 /* fallthrough */
1906 default:
1907 return getArrayForFile(src.getFile(), idx2d)->load(
1908 sub.cur->values, idx, swz, shiftAddress(ptr));
1909 }
1910 }
1911
1912 Value *
1913 Converter::acquireDst(int d, int c)
1914 {
1915 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1916 const unsigned f = dst.getFile();
1917 int idx = dst.getIndex(0);
1918 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1919
1920 if (dst.isMasked(c) || f == TGSI_FILE_BUFFER || f == TGSI_FILE_MEMORY ||
1921 f == TGSI_FILE_IMAGE)
1922 return NULL;
1923
1924 if (dst.isIndirect(0) ||
1925 f == TGSI_FILE_SYSTEM_VALUE ||
1926 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1927 return getScratch();
1928
1929 if (f == TGSI_FILE_TEMPORARY) {
1930 int arrayid = dst.getArrayId();
1931 if (!arrayid)
1932 arrayid = code->tempArrayId[idx];
1933 adjustTempIndex(arrayid, idx, idx2d);
1934 }
1935
1936 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1937 }
1938
1939 void
1940 Converter::storeDst(int d, int c, Value *val)
1941 {
1942 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1943
1944 if (tgsi.getSaturate()) {
1945 mkOp1(OP_SAT, dstTy, val, val);
1946 }
1947
1948 Value *ptr = NULL;
1949 if (dst.isIndirect(0))
1950 ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1951
1952 if (info->io.genUserClip > 0 &&
1953 dst.getFile() == TGSI_FILE_OUTPUT &&
1954 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1955 mkMov(clipVtx[c], val);
1956 val = clipVtx[c];
1957 }
1958
1959 storeDst(dst, c, val, ptr);
1960 }
1961
1962 void
1963 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1964 Value *val, Value *ptr)
1965 {
1966 const unsigned f = dst.getFile();
1967 int idx = dst.getIndex(0);
1968 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1969
1970 if (f == TGSI_FILE_SYSTEM_VALUE) {
1971 assert(!ptr);
1972 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1973 } else
1974 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1975
1976 if (ptr || (info->out[idx].mask & (1 << c))) {
1977 /* Save the viewport index into a scratch register so that it can be
1978 exported at EMIT time */
1979 if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
1980 viewport != NULL)
1981 mkOp1(OP_MOV, TYPE_U32, viewport, val);
1982 else
1983 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
1984 info->out[idx].patch;
1985 }
1986 } else
1987 if (f == TGSI_FILE_TEMPORARY ||
1988 f == TGSI_FILE_PREDICATE ||
1989 f == TGSI_FILE_ADDRESS ||
1990 f == TGSI_FILE_OUTPUT) {
1991 if (f == TGSI_FILE_TEMPORARY) {
1992 int arrayid = dst.getArrayId();
1993 if (!arrayid)
1994 arrayid = code->tempArrayId[idx];
1995 adjustTempIndex(arrayid, idx, idx2d);
1996 }
1997
1998 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1999 } else {
2000 assert(!"invalid dst file");
2001 }
2002 }
2003
2004 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
2005 for (chan = 0; chan < 4; ++chan) \
2006 if (!inst.getDst(d).isMasked(chan))
2007
2008 Value *
2009 Converter::buildDot(int dim)
2010 {
2011 assert(dim > 0);
2012
2013 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
2014 Value *dotp = getScratch();
2015
2016 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
2017
2018 for (int c = 1; c < dim; ++c) {
2019 src0 = fetchSrc(0, c);
2020 src1 = fetchSrc(1, c);
2021 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
2022 }
2023 return dotp;
2024 }
2025
2026 void
2027 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
2028 {
2029 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
2030 join->fixed = 1;
2031 conv->insertHead(join);
2032
2033 assert(!fork->joinAt);
2034 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
2035 fork->insertBefore(fork->getExit(), fork->joinAt);
2036 }
2037
2038 void
2039 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
2040 {
2041 unsigned rIdx = 0, sIdx = 0;
2042
2043 if (R >= 0)
2044 rIdx = tgsi.getSrc(R).getIndex(0);
2045 if (S >= 0)
2046 sIdx = tgsi.getSrc(S).getIndex(0);
2047
2048 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
2049
2050 if (tgsi.getSrc(R).isIndirect(0)) {
2051 tex->tex.rIndirectSrc = s;
2052 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
2053 }
2054 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
2055 tex->tex.sIndirectSrc = s;
2056 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
2057 }
2058 }
2059
2060 void
2061 Converter::handleTXQ(Value *dst0[4], enum TexQuery query, int R)
2062 {
2063 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
2064 tex->tex.query = query;
2065 unsigned int c, d;
2066
2067 for (d = 0, c = 0; c < 4; ++c) {
2068 if (!dst0[c])
2069 continue;
2070 tex->tex.mask |= 1 << c;
2071 tex->setDef(d++, dst0[c]);
2072 }
2073 if (query == TXQ_DIMS)
2074 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
2075 else
2076 tex->setSrc((c = 0), zero);
2077
2078 setTexRS(tex, ++c, R, -1);
2079
2080 bb->insertTail(tex);
2081 }
2082
2083 void
2084 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
2085 {
2086 Value *proj = fetchSrc(0, 3);
2087 Instruction *insn = proj->getUniqueInsn();
2088 int c;
2089
2090 if (insn->op == OP_PINTERP) {
2091 bb->insertTail(insn = cloneForward(func, insn));
2092 insn->op = OP_LINTERP;
2093 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
2094 insn->setSrc(1, NULL);
2095 proj = insn->getDef(0);
2096 }
2097 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
2098
2099 for (c = 0; c < 4; ++c) {
2100 if (!(mask & (1 << c)))
2101 continue;
2102 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
2103 continue;
2104 mask &= ~(1 << c);
2105
2106 bb->insertTail(insn = cloneForward(func, insn));
2107 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
2108 insn->setSrc(1, proj);
2109 dst[c] = insn->getDef(0);
2110 }
2111 if (!mask)
2112 return;
2113
2114 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
2115
2116 for (c = 0; c < 4; ++c)
2117 if (mask & (1 << c))
2118 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
2119 }
2120
2121 // order of nv50 ir sources: x y z layer lod/bias shadow
2122 // order of TGSI TEX sources: x y z layer shadow lod/bias
2123 // lowering will finally set the hw specific order (like array first on nvc0)
2124 void
2125 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
2126 {
2127 Value *arg[4], *src[8];
2128 Value *lod = NULL, *shd = NULL;
2129 unsigned int s, c, d;
2130 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2131
2132 TexInstruction::Target tgt = tgsi.getTexture(code, R);
2133
2134 for (s = 0; s < tgt.getArgCount(); ++s)
2135 arg[s] = src[s] = fetchSrc(0, s);
2136
2137 if (texi->op == OP_TXL || texi->op == OP_TXB)
2138 lod = fetchSrc(L >> 4, L & 3);
2139
2140 if (C == 0x0f)
2141 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
2142
2143 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
2144 tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
2145 shd = fetchSrc(1, 0);
2146 else if (tgt.isShadow())
2147 shd = fetchSrc(C >> 4, C & 3);
2148
2149 if (texi->op == OP_TXD) {
2150 for (c = 0; c < tgt.getDim() + tgt.isCube(); ++c) {
2151 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
2152 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
2153 }
2154 }
2155
2156 // cube textures don't care about projection value, it's divided out
2157 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
2158 unsigned int n = tgt.getDim();
2159 if (shd) {
2160 arg[n] = shd;
2161 ++n;
2162 assert(tgt.getDim() == tgt.getArgCount());
2163 }
2164 loadProjTexCoords(src, arg, (1 << n) - 1);
2165 if (shd)
2166 shd = src[n - 1];
2167 }
2168
2169 for (c = 0, d = 0; c < 4; ++c) {
2170 if (dst[c]) {
2171 texi->setDef(d++, dst[c]);
2172 texi->tex.mask |= 1 << c;
2173 } else {
2174 // NOTE: maybe hook up def too, for CSE
2175 }
2176 }
2177 for (s = 0; s < tgt.getArgCount(); ++s)
2178 texi->setSrc(s, src[s]);
2179 if (lod)
2180 texi->setSrc(s++, lod);
2181 if (shd)
2182 texi->setSrc(s++, shd);
2183
2184 setTexRS(texi, s, R, S);
2185
2186 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
2187 texi->tex.levelZero = true;
2188 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
2189 texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
2190
2191 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2192 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2193 for (c = 0; c < 3; ++c) {
2194 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2195 texi->offset[s][c].setInsn(texi);
2196 }
2197 }
2198
2199 bb->insertTail(texi);
2200 }
2201
2202 // 1st source: xyz = coordinates, w = lod/sample
2203 // 2nd source: offset
2204 void
2205 Converter::handleTXF(Value *dst[4], int R, int L_M)
2206 {
2207 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2208 int ms;
2209 unsigned int c, d, s;
2210
2211 texi->tex.target = tgsi.getTexture(code, R);
2212
2213 ms = texi->tex.target.isMS() ? 1 : 0;
2214 texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
2215
2216 for (c = 0, d = 0; c < 4; ++c) {
2217 if (dst[c]) {
2218 texi->setDef(d++, dst[c]);
2219 texi->tex.mask |= 1 << c;
2220 }
2221 }
2222 for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
2223 texi->setSrc(c, fetchSrc(0, c));
2224 texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
2225
2226 setTexRS(texi, c, R, -1);
2227
2228 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2229 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2230 for (c = 0; c < 3; ++c) {
2231 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2232 texi->offset[s][c].setInsn(texi);
2233 }
2234 }
2235
2236 bb->insertTail(texi);
2237 }
2238
2239 void
2240 Converter::handleLIT(Value *dst0[4])
2241 {
2242 Value *val0 = NULL;
2243 unsigned int mask = tgsi.getDst(0).getMask();
2244
2245 if (mask & (1 << 0))
2246 loadImm(dst0[0], 1.0f);
2247
2248 if (mask & (1 << 3))
2249 loadImm(dst0[3], 1.0f);
2250
2251 if (mask & (3 << 1)) {
2252 val0 = getScratch();
2253 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
2254 if (mask & (1 << 1))
2255 mkMov(dst0[1], val0);
2256 }
2257
2258 if (mask & (1 << 2)) {
2259 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
2260 Value *val1 = getScratch(), *val3 = getScratch();
2261
2262 Value *pos128 = loadImm(NULL, +127.999999f);
2263 Value *neg128 = loadImm(NULL, -127.999999f);
2264
2265 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
2266 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
2267 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
2268 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
2269
2270 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
2271 }
2272 }
2273
2274 /* Keep this around for now as reference when adding img support
2275 static inline bool
2276 isResourceSpecial(const int r)
2277 {
2278 return (r == TGSI_RESOURCE_GLOBAL ||
2279 r == TGSI_RESOURCE_LOCAL ||
2280 r == TGSI_RESOURCE_PRIVATE ||
2281 r == TGSI_RESOURCE_INPUT);
2282 }
2283
2284 static inline bool
2285 isResourceRaw(const tgsi::Source *code, const int r)
2286 {
2287 return isResourceSpecial(r) || code->resources[r].raw;
2288 }
2289
2290 static inline nv50_ir::TexTarget
2291 getResourceTarget(const tgsi::Source *code, int r)
2292 {
2293 if (isResourceSpecial(r))
2294 return nv50_ir::TEX_TARGET_BUFFER;
2295 return tgsi::translateTexture(code->resources.at(r).target);
2296 }
2297
2298 Symbol *
2299 Converter::getResourceBase(const int r)
2300 {
2301 Symbol *sym = NULL;
2302
2303 switch (r) {
2304 case TGSI_RESOURCE_GLOBAL:
2305 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL,
2306 info->io.auxCBSlot);
2307 break;
2308 case TGSI_RESOURCE_LOCAL:
2309 assert(prog->getType() == Program::TYPE_COMPUTE);
2310 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2311 info->prop.cp.sharedOffset);
2312 break;
2313 case TGSI_RESOURCE_PRIVATE:
2314 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2315 info->bin.tlsSpace);
2316 break;
2317 case TGSI_RESOURCE_INPUT:
2318 assert(prog->getType() == Program::TYPE_COMPUTE);
2319 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2320 info->prop.cp.inputOffset);
2321 break;
2322 default:
2323 sym = new_Symbol(prog,
2324 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2325 break;
2326 }
2327 return sym;
2328 }
2329
2330 void
2331 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2332 {
2333 const int arg =
2334 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2335
2336 for (int c = 0; c < arg; ++c)
2337 coords.push_back(fetchSrc(s, c));
2338
2339 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2340 if (r == TGSI_RESOURCE_LOCAL ||
2341 r == TGSI_RESOURCE_PRIVATE ||
2342 r == TGSI_RESOURCE_INPUT)
2343 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2344 coords[0]);
2345 }
2346 */
2347 static inline int
2348 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2349 {
2350 int n = 0;
2351
2352 while (mask) {
2353 if (mask & 1) {
2354 size[n]++;
2355 } else {
2356 if (size[n])
2357 comp[n = 1] = size[0] + 1;
2358 else
2359 comp[n]++;
2360 }
2361 mask >>= 1;
2362 }
2363 if (size[0] == 3) {
2364 n = 1;
2365 size[0] = (comp[0] == 1) ? 1 : 2;
2366 size[1] = 3 - size[0];
2367 comp[1] = comp[0] + size[0];
2368 }
2369 return n + 1;
2370 }
2371
2372 static inline nv50_ir::TexTarget
2373 getImageTarget(const tgsi::Source *code, int r)
2374 {
2375 return tgsi::translateTexture(code->images.at(r).target);
2376 }
2377
2378 static inline const nv50_ir::TexInstruction::ImgFormatDesc *
2379 getImageFormat(const tgsi::Source *code, int r)
2380 {
2381 return &nv50_ir::TexInstruction::formatTable[
2382 tgsi::translateImgFormat(code->images.at(r).format)];
2383 }
2384
2385 void
2386 Converter::getImageCoords(std::vector<Value *> &coords, int r, int s)
2387 {
2388 TexInstruction::Target t =
2389 TexInstruction::Target(getImageTarget(code, r));
2390 const int arg = t.getDim() + (t.isArray() || t.isCube());
2391
2392 for (int c = 0; c < arg; ++c)
2393 coords.push_back(fetchSrc(s, c));
2394
2395 if (t.isMS())
2396 coords.push_back(fetchSrc(s, 3));
2397 }
2398
2399 // For raw loads, granularity is 4 byte.
2400 // Usage of the texture read mask on OP_SULDP is not allowed.
2401 void
2402 Converter::handleLOAD(Value *dst0[4])
2403 {
2404 const int r = tgsi.getSrc(0).getIndex(0);
2405 int c;
2406 std::vector<Value *> off, src, ldv, def;
2407
2408 switch (tgsi.getSrc(0).getFile()) {
2409 case TGSI_FILE_BUFFER:
2410 case TGSI_FILE_MEMORY:
2411 for (c = 0; c < 4; ++c) {
2412 if (!dst0[c])
2413 continue;
2414
2415 Value *off;
2416 Symbol *sym;
2417 uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
2418
2419 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
2420 off = NULL;
2421 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2422 tgsi.getSrc(1).getValueU32(0, info) +
2423 src0_component_offset);
2424 } else {
2425 // yzw are ignored for buffers
2426 off = fetchSrc(1, 0);
2427 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2428 src0_component_offset);
2429 }
2430
2431 Instruction *ld = mkLoad(TYPE_U32, dst0[c], sym, off);
2432 ld->cache = tgsi.getCacheMode();
2433 if (tgsi.getSrc(0).isIndirect(0))
2434 ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
2435 }
2436 break;
2437 case TGSI_FILE_IMAGE: {
2438 assert(!code->images[r].raw);
2439
2440 getImageCoords(off, r, 1);
2441 def.resize(4);
2442
2443 for (c = 0; c < 4; ++c) {
2444 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2445 def[c] = getScratch();
2446 else
2447 def[c] = dst0[c];
2448 }
2449
2450 TexInstruction *ld =
2451 mkTex(OP_SULDP, getImageTarget(code, r), code->images[r].slot, 0,
2452 def, off);
2453 ld->tex.mask = tgsi.getDst(0).getMask();
2454 ld->tex.format = getImageFormat(code, r);
2455 ld->cache = tgsi.getCacheMode();
2456 if (tgsi.getSrc(0).isIndirect(0))
2457 ld->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2458
2459 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2460 if (dst0[c] != def[c])
2461 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2462 }
2463 break;
2464 default:
2465 assert(!"Unsupported srcFile for LOAD");
2466 }
2467
2468 /* Keep this around for now as reference when adding img support
2469 getResourceCoords(off, r, 1);
2470
2471 if (isResourceRaw(code, r)) {
2472 uint8_t mask = 0;
2473 uint8_t comp[2] = { 0, 0 };
2474 uint8_t size[2] = { 0, 0 };
2475
2476 Symbol *base = getResourceBase(r);
2477
2478 // determine the base and size of the at most 2 load ops
2479 for (c = 0; c < 4; ++c)
2480 if (!tgsi.getDst(0).isMasked(c))
2481 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2482
2483 int n = partitionLoadStore(comp, size, mask);
2484
2485 src = off;
2486
2487 def.resize(4); // index by component, the ones we need will be non-NULL
2488 for (c = 0; c < 4; ++c) {
2489 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2490 def[c] = dst0[c];
2491 else
2492 if (mask & (1 << c))
2493 def[c] = getScratch();
2494 }
2495
2496 const bool useLd = isResourceSpecial(r) ||
2497 (info->io.nv50styleSurfaces &&
2498 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2499
2500 for (int i = 0; i < n; ++i) {
2501 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2502
2503 if (comp[i]) // adjust x component of source address if necessary
2504 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2505 off[0], mkImm(comp[i] * 4));
2506 else
2507 src[0] = off[0];
2508
2509 if (useLd) {
2510 Instruction *ld =
2511 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2512 for (size_t c = 1; c < ldv.size(); ++c)
2513 ld->setDef(c, ldv[c]);
2514 } else {
2515 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2516 0, ldv, src)->dType = typeOfSize(size[i] * 4);
2517 }
2518 }
2519 } else {
2520 def.resize(4);
2521 for (c = 0; c < 4; ++c) {
2522 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2523 def[c] = getScratch();
2524 else
2525 def[c] = dst0[c];
2526 }
2527
2528 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2529 def, off);
2530 }
2531 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2532 if (dst0[c] != def[c])
2533 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2534 */
2535 }
2536
2537 // For formatted stores, the write mask on OP_SUSTP can be used.
2538 // Raw stores have to be split.
2539 void
2540 Converter::handleSTORE()
2541 {
2542 const int r = tgsi.getDst(0).getIndex(0);
2543 int c;
2544 std::vector<Value *> off, src, dummy;
2545
2546 switch (tgsi.getDst(0).getFile()) {
2547 case TGSI_FILE_BUFFER:
2548 case TGSI_FILE_MEMORY:
2549 for (c = 0; c < 4; ++c) {
2550 if (!(tgsi.getDst(0).getMask() & (1 << c)))
2551 continue;
2552
2553 Symbol *sym;
2554 Value *off;
2555 if (tgsi.getSrc(0).getFile() == TGSI_FILE_IMMEDIATE) {
2556 off = NULL;
2557 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c,
2558 tgsi.getSrc(0).getValueU32(0, info) + 4 * c);
2559 } else {
2560 // yzw are ignored for buffers
2561 off = fetchSrc(0, 0);
2562 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c, 4 * c);
2563 }
2564
2565 Instruction *st = mkStore(OP_STORE, TYPE_U32, sym, off, fetchSrc(1, c));
2566 st->cache = tgsi.getCacheMode();
2567 if (tgsi.getDst(0).isIndirect(0))
2568 st->setIndirect(0, 1, fetchSrc(tgsi.getDst(0).getIndirect(0), 0, 0));
2569 }
2570 break;
2571 case TGSI_FILE_IMAGE: {
2572 assert(!code->images[r].raw);
2573
2574 getImageCoords(off, r, 0);
2575 src = off;
2576
2577 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2578 src.push_back(fetchSrc(1, c));
2579
2580 TexInstruction *st =
2581 mkTex(OP_SUSTP, getImageTarget(code, r), code->images[r].slot,
2582 0, dummy, src);
2583 st->tex.mask = tgsi.getDst(0).getMask();
2584 st->tex.format = getImageFormat(code, r);
2585 st->cache = tgsi.getCacheMode();
2586 if (tgsi.getDst(0).isIndirect(0))
2587 st->setIndirectR(fetchSrc(tgsi.getDst(0).getIndirect(0), 0, NULL));
2588 }
2589 break;
2590 default:
2591 assert(!"Unsupported dstFile for STORE");
2592 }
2593
2594 /* Keep this around for now as reference when adding img support
2595 getResourceCoords(off, r, 0);
2596 src = off;
2597 const int s = src.size();
2598
2599 if (isResourceRaw(code, r)) {
2600 uint8_t comp[2] = { 0, 0 };
2601 uint8_t size[2] = { 0, 0 };
2602
2603 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2604
2605 Symbol *base = getResourceBase(r);
2606
2607 const bool useSt = isResourceSpecial(r) ||
2608 (info->io.nv50styleSurfaces &&
2609 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2610
2611 for (int i = 0; i < n; ++i) {
2612 if (comp[i]) // adjust x component of source address if necessary
2613 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2614 off[0], mkImm(comp[i] * 4));
2615 else
2616 src[0] = off[0];
2617
2618 const DataType stTy = typeOfSize(size[i] * 4);
2619
2620 if (useSt) {
2621 Instruction *st =
2622 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2623 for (c = 1; c < size[i]; ++c)
2624 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2625 st->setIndirect(0, 0, src[0]);
2626 } else {
2627 // attach values to be stored
2628 src.resize(s + size[i]);
2629 for (c = 0; c < size[i]; ++c)
2630 src[s + c] = fetchSrc(1, comp[i] + c);
2631 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2632 0, dummy, src)->setType(stTy);
2633 }
2634 }
2635 } else {
2636 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2637 src.push_back(fetchSrc(1, c));
2638
2639 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2640 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2641 }
2642 */
2643 }
2644
2645 // XXX: These only work on resources with the single-component u32/s32 formats.
2646 // Therefore the result is replicated. This might not be intended by TGSI, but
2647 // operating on more than 1 component would produce undefined results because
2648 // they do not exist.
2649 void
2650 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2651 {
2652 const int r = tgsi.getSrc(0).getIndex(0);
2653 std::vector<Value *> srcv;
2654 std::vector<Value *> defv;
2655 LValue *dst = getScratch();
2656
2657 switch (tgsi.getSrc(0).getFile()) {
2658 case TGSI_FILE_BUFFER:
2659 case TGSI_FILE_MEMORY:
2660 for (int c = 0; c < 4; ++c) {
2661 if (!dst0[c])
2662 continue;
2663
2664 Instruction *insn;
2665 Value *off = fetchSrc(1, c), *off2 = NULL;
2666 Value *sym;
2667 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE)
2668 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2669 tgsi.getSrc(1).getValueU32(c, info));
2670 else
2671 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c, 0);
2672 if (tgsi.getSrc(0).isIndirect(0))
2673 off2 = fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0);
2674 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2675 insn = mkOp3(OP_ATOM, ty, dst, sym, fetchSrc(2, c), fetchSrc(3, c));
2676 else
2677 insn = mkOp2(OP_ATOM, ty, dst, sym, fetchSrc(2, c));
2678 if (tgsi.getSrc(1).getFile() != TGSI_FILE_IMMEDIATE)
2679 insn->setIndirect(0, 0, off);
2680 if (off2)
2681 insn->setIndirect(0, 1, off2);
2682 insn->subOp = subOp;
2683 }
2684 for (int c = 0; c < 4; ++c)
2685 if (dst0[c])
2686 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2687 break;
2688 case TGSI_FILE_IMAGE: {
2689 assert(!code->images[r].raw);
2690
2691 getImageCoords(srcv, r, 1);
2692 defv.push_back(dst);
2693 srcv.push_back(fetchSrc(2, 0));
2694
2695 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2696 srcv.push_back(fetchSrc(3, 0));
2697
2698 TexInstruction *tex = mkTex(OP_SUREDP, getImageTarget(code, r),
2699 code->images[r].slot, 0, defv, srcv);
2700 tex->subOp = subOp;
2701 tex->tex.mask = 1;
2702 tex->tex.format = getImageFormat(code, r);
2703 tex->setType(ty);
2704 if (tgsi.getSrc(0).isIndirect(0))
2705 tex->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2706
2707 for (int c = 0; c < 4; ++c)
2708 if (dst0[c])
2709 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2710 }
2711 break;
2712 default:
2713 assert(!"Unsupported srcFile for ATOM");
2714 }
2715
2716 /* Keep this around for now as reference when adding img support
2717 getResourceCoords(srcv, r, 1);
2718
2719 if (isResourceSpecial(r)) {
2720 assert(r != TGSI_RESOURCE_INPUT);
2721 Instruction *insn;
2722 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2723 insn->subOp = subOp;
2724 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2725 insn->setSrc(2, fetchSrc(3, 0));
2726 insn->setIndirect(0, 0, srcv.at(0));
2727 } else {
2728 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2729 TexTarget targ = getResourceTarget(code, r);
2730 int idx = code->resources[r].slot;
2731 defv.push_back(dst);
2732 srcv.push_back(fetchSrc(2, 0));
2733 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2734 srcv.push_back(fetchSrc(3, 0));
2735 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2736 tex->subOp = subOp;
2737 tex->tex.mask = 1;
2738 tex->setType(ty);
2739 }
2740
2741 for (int c = 0; c < 4; ++c)
2742 if (dst0[c])
2743 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2744 */
2745 }
2746
2747 void
2748 Converter::handleINTERP(Value *dst[4])
2749 {
2750 // Check whether the input is linear. All other attributes ignored.
2751 Instruction *insn;
2752 Value *offset = NULL, *ptr = NULL, *w = NULL;
2753 Symbol *sym[4] = { NULL };
2754 bool linear;
2755 operation op = OP_NOP;
2756 int c, mode = 0;
2757
2758 tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2759
2760 // In some odd cases, in large part due to varying packing, the source
2761 // might not actually be an input. This is illegal TGSI, but it's easier to
2762 // account for it here than it is to fix it where the TGSI is being
2763 // generated. In that case, it's going to be a straight up mov (or sequence
2764 // of mov's) from the input in question. We follow the mov chain to see
2765 // which input we need to use.
2766 if (src.getFile() != TGSI_FILE_INPUT) {
2767 if (src.isIndirect(0)) {
2768 ERROR("Ignoring indirect input interpolation\n");
2769 return;
2770 }
2771 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2772 Value *val = fetchSrc(0, c);
2773 assert(val->defs.size() == 1);
2774 insn = val->getInsn();
2775 while (insn->op == OP_MOV) {
2776 assert(insn->getSrc(0)->defs.size() == 1);
2777 insn = insn->getSrc(0)->getInsn();
2778 if (!insn) {
2779 ERROR("Miscompiling shader due to unhandled INTERP\n");
2780 return;
2781 }
2782 }
2783 if (insn->op != OP_LINTERP && insn->op != OP_PINTERP) {
2784 ERROR("Trying to interpolate non-input, this is not allowed.\n");
2785 return;
2786 }
2787 sym[c] = insn->getSrc(0)->asSym();
2788 assert(sym[c]);
2789 op = insn->op;
2790 mode = insn->ipa;
2791 }
2792 } else {
2793 if (src.isIndirect(0))
2794 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2795
2796 // We can assume that the fixed index will point to an input of the same
2797 // interpolation type in case of an indirect.
2798 // TODO: Make use of ArrayID.
2799 linear = info->in[src.getIndex(0)].linear;
2800 if (linear) {
2801 op = OP_LINTERP;
2802 mode = NV50_IR_INTERP_LINEAR;
2803 } else {
2804 op = OP_PINTERP;
2805 mode = NV50_IR_INTERP_PERSPECTIVE;
2806 }
2807 }
2808
2809 switch (tgsi.getOpcode()) {
2810 case TGSI_OPCODE_INTERP_CENTROID:
2811 mode |= NV50_IR_INTERP_CENTROID;
2812 break;
2813 case TGSI_OPCODE_INTERP_SAMPLE:
2814 insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2815 insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2816 mode |= NV50_IR_INTERP_OFFSET;
2817 break;
2818 case TGSI_OPCODE_INTERP_OFFSET: {
2819 // The input in src1.xy is float, but we need a single 32-bit value
2820 // where the upper and lower 16 bits are encoded in S0.12 format. We need
2821 // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2822 // and then convert to s32.
2823 Value *offs[2];
2824 for (c = 0; c < 2; c++) {
2825 offs[c] = fetchSrc(1, c);
2826 mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2827 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2828 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2829 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2830 }
2831 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2832 offs[1], mkImm(0x1010), offs[0]);
2833 mode |= NV50_IR_INTERP_OFFSET;
2834 break;
2835 }
2836 }
2837
2838 if (op == OP_PINTERP) {
2839 if (offset) {
2840 w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2841 mkOp1(OP_RCP, TYPE_F32, w, w);
2842 } else {
2843 w = fragCoord[3];
2844 }
2845 }
2846
2847
2848 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2849 insn = mkOp1(op, TYPE_F32, dst[c], sym[c] ? sym[c] : srcToSym(src, c));
2850 if (op == OP_PINTERP)
2851 insn->setSrc(1, w);
2852 if (ptr)
2853 insn->setIndirect(0, 0, ptr);
2854 if (offset)
2855 insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2856
2857 insn->setInterpolate(mode);
2858 }
2859 }
2860
2861 Converter::Subroutine *
2862 Converter::getSubroutine(unsigned ip)
2863 {
2864 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2865
2866 if (it == sub.map.end())
2867 it = sub.map.insert(std::make_pair(
2868 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2869
2870 return &it->second;
2871 }
2872
2873 Converter::Subroutine *
2874 Converter::getSubroutine(Function *f)
2875 {
2876 unsigned ip = f->getLabel();
2877 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2878
2879 if (it == sub.map.end())
2880 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2881
2882 return &it->second;
2883 }
2884
2885 bool
2886 Converter::isEndOfSubroutine(uint ip)
2887 {
2888 assert(ip < code->scan.num_instructions);
2889 tgsi::Instruction insn(&code->insns[ip]);
2890 return (insn.getOpcode() == TGSI_OPCODE_END ||
2891 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2892 // does END occur at end of main or the very end ?
2893 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2894 }
2895
2896 bool
2897 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2898 {
2899 Instruction *geni;
2900
2901 Value *dst0[4], *rDst0[4];
2902 Value *src0, *src1, *src2, *src3;
2903 Value *val0, *val1;
2904 int c;
2905
2906 tgsi = tgsi::Instruction(insn);
2907
2908 bool useScratchDst = tgsi.checkDstSrcAliasing();
2909
2910 operation op = tgsi.getOP();
2911 dstTy = tgsi.inferDstType();
2912 srcTy = tgsi.inferSrcType();
2913
2914 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2915
2916 if (tgsi.dstCount()) {
2917 for (c = 0; c < 4; ++c) {
2918 rDst0[c] = acquireDst(0, c);
2919 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2920 }
2921 }
2922
2923 switch (tgsi.getOpcode()) {
2924 case TGSI_OPCODE_ADD:
2925 case TGSI_OPCODE_UADD:
2926 case TGSI_OPCODE_AND:
2927 case TGSI_OPCODE_DIV:
2928 case TGSI_OPCODE_IDIV:
2929 case TGSI_OPCODE_UDIV:
2930 case TGSI_OPCODE_MAX:
2931 case TGSI_OPCODE_MIN:
2932 case TGSI_OPCODE_IMAX:
2933 case TGSI_OPCODE_IMIN:
2934 case TGSI_OPCODE_UMAX:
2935 case TGSI_OPCODE_UMIN:
2936 case TGSI_OPCODE_MOD:
2937 case TGSI_OPCODE_UMOD:
2938 case TGSI_OPCODE_MUL:
2939 case TGSI_OPCODE_UMUL:
2940 case TGSI_OPCODE_IMUL_HI:
2941 case TGSI_OPCODE_UMUL_HI:
2942 case TGSI_OPCODE_OR:
2943 case TGSI_OPCODE_SHL:
2944 case TGSI_OPCODE_ISHR:
2945 case TGSI_OPCODE_USHR:
2946 case TGSI_OPCODE_SUB:
2947 case TGSI_OPCODE_XOR:
2948 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2949 src0 = fetchSrc(0, c);
2950 src1 = fetchSrc(1, c);
2951 geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2952 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2953 }
2954 break;
2955 case TGSI_OPCODE_MAD:
2956 case TGSI_OPCODE_UMAD:
2957 case TGSI_OPCODE_SAD:
2958 case TGSI_OPCODE_FMA:
2959 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2960 src0 = fetchSrc(0, c);
2961 src1 = fetchSrc(1, c);
2962 src2 = fetchSrc(2, c);
2963 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2964 }
2965 break;
2966 case TGSI_OPCODE_MOV:
2967 case TGSI_OPCODE_ABS:
2968 case TGSI_OPCODE_CEIL:
2969 case TGSI_OPCODE_FLR:
2970 case TGSI_OPCODE_TRUNC:
2971 case TGSI_OPCODE_RCP:
2972 case TGSI_OPCODE_SQRT:
2973 case TGSI_OPCODE_IABS:
2974 case TGSI_OPCODE_INEG:
2975 case TGSI_OPCODE_NOT:
2976 case TGSI_OPCODE_DDX:
2977 case TGSI_OPCODE_DDY:
2978 case TGSI_OPCODE_DDX_FINE:
2979 case TGSI_OPCODE_DDY_FINE:
2980 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2981 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2982 break;
2983 case TGSI_OPCODE_RSQ:
2984 src0 = fetchSrc(0, 0);
2985 val0 = getScratch();
2986 mkOp1(OP_ABS, TYPE_F32, val0, src0);
2987 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2988 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2989 mkMov(dst0[c], val0);
2990 break;
2991 case TGSI_OPCODE_ARL:
2992 case TGSI_OPCODE_ARR:
2993 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2994 const RoundMode rnd =
2995 tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
2996 src0 = fetchSrc(0, c);
2997 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
2998 }
2999 break;
3000 case TGSI_OPCODE_UARL:
3001 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3002 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
3003 break;
3004 case TGSI_OPCODE_POW:
3005 val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
3006 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3007 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3008 break;
3009 case TGSI_OPCODE_EX2:
3010 case TGSI_OPCODE_LG2:
3011 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
3012 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3013 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3014 break;
3015 case TGSI_OPCODE_COS:
3016 case TGSI_OPCODE_SIN:
3017 val0 = getScratch();
3018 if (mask & 7) {
3019 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
3020 mkOp1(op, TYPE_F32, val0, val0);
3021 for (c = 0; c < 3; ++c)
3022 if (dst0[c])
3023 mkMov(dst0[c], val0);
3024 }
3025 if (dst0[3]) {
3026 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
3027 mkOp1(op, TYPE_F32, dst0[3], val0);
3028 }
3029 break;
3030 case TGSI_OPCODE_SCS:
3031 if (mask & 3) {
3032 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
3033 if (dst0[0])
3034 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
3035 if (dst0[1])
3036 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
3037 }
3038 if (dst0[2])
3039 loadImm(dst0[2], 0.0f);
3040 if (dst0[3])
3041 loadImm(dst0[3], 1.0f);
3042 break;
3043 case TGSI_OPCODE_EXP:
3044 src0 = fetchSrc(0, 0);
3045 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
3046 if (dst0[1])
3047 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
3048 if (dst0[0])
3049 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
3050 if (dst0[2])
3051 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
3052 if (dst0[3])
3053 loadImm(dst0[3], 1.0f);
3054 break;
3055 case TGSI_OPCODE_LOG:
3056 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
3057 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
3058 if (dst0[0] || dst0[1])
3059 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
3060 if (dst0[1]) {
3061 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
3062 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
3063 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
3064 }
3065 if (dst0[3])
3066 loadImm(dst0[3], 1.0f);
3067 break;
3068 case TGSI_OPCODE_DP2:
3069 val0 = buildDot(2);
3070 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3071 mkMov(dst0[c], val0);
3072 break;
3073 case TGSI_OPCODE_DP3:
3074 val0 = buildDot(3);
3075 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3076 mkMov(dst0[c], val0);
3077 break;
3078 case TGSI_OPCODE_DP4:
3079 val0 = buildDot(4);
3080 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3081 mkMov(dst0[c], val0);
3082 break;
3083 case TGSI_OPCODE_DPH:
3084 val0 = buildDot(3);
3085 src1 = fetchSrc(1, 3);
3086 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
3087 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3088 mkMov(dst0[c], val0);
3089 break;
3090 case TGSI_OPCODE_DST:
3091 if (dst0[0])
3092 loadImm(dst0[0], 1.0f);
3093 if (dst0[1]) {
3094 src0 = fetchSrc(0, 1);
3095 src1 = fetchSrc(1, 1);
3096 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
3097 }
3098 if (dst0[2])
3099 mkMov(dst0[2], fetchSrc(0, 2));
3100 if (dst0[3])
3101 mkMov(dst0[3], fetchSrc(1, 3));
3102 break;
3103 case TGSI_OPCODE_LRP:
3104 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3105 src0 = fetchSrc(0, c);
3106 src1 = fetchSrc(1, c);
3107 src2 = fetchSrc(2, c);
3108 mkOp3(OP_MAD, TYPE_F32, dst0[c],
3109 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
3110 }
3111 break;
3112 case TGSI_OPCODE_LIT:
3113 handleLIT(dst0);
3114 break;
3115 case TGSI_OPCODE_XPD:
3116 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3117 if (c < 3) {
3118 val0 = getSSA();
3119 src0 = fetchSrc(1, (c + 1) % 3);
3120 src1 = fetchSrc(0, (c + 2) % 3);
3121 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
3122 mkOp1(OP_NEG, TYPE_F32, val0, val0);
3123
3124 src0 = fetchSrc(0, (c + 1) % 3);
3125 src1 = fetchSrc(1, (c + 2) % 3);
3126 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
3127 } else {
3128 loadImm(dst0[c], 1.0f);
3129 }
3130 }
3131 break;
3132 case TGSI_OPCODE_ISSG:
3133 case TGSI_OPCODE_SSG:
3134 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3135 src0 = fetchSrc(0, c);
3136 val0 = getScratch();
3137 val1 = getScratch();
3138 mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
3139 mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
3140 if (srcTy == TYPE_F32)
3141 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
3142 else
3143 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
3144 }
3145 break;
3146 case TGSI_OPCODE_UCMP:
3147 srcTy = TYPE_U32;
3148 /* fallthrough */
3149 case TGSI_OPCODE_CMP:
3150 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3151 src0 = fetchSrc(0, c);
3152 src1 = fetchSrc(1, c);
3153 src2 = fetchSrc(2, c);
3154 if (src1 == src2)
3155 mkMov(dst0[c], src1);
3156 else
3157 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
3158 srcTy, dst0[c], srcTy, src1, src2, src0);
3159 }
3160 break;
3161 case TGSI_OPCODE_FRC:
3162 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3163 src0 = fetchSrc(0, c);
3164 val0 = getScratch();
3165 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
3166 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
3167 }
3168 break;
3169 case TGSI_OPCODE_ROUND:
3170 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3171 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
3172 ->rnd = ROUND_NI;
3173 break;
3174 case TGSI_OPCODE_CLAMP:
3175 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3176 src0 = fetchSrc(0, c);
3177 src1 = fetchSrc(1, c);
3178 src2 = fetchSrc(2, c);
3179 val0 = getScratch();
3180 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
3181 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
3182 }
3183 break;
3184 case TGSI_OPCODE_SLT:
3185 case TGSI_OPCODE_SGE:
3186 case TGSI_OPCODE_SEQ:
3187 case TGSI_OPCODE_SGT:
3188 case TGSI_OPCODE_SLE:
3189 case TGSI_OPCODE_SNE:
3190 case TGSI_OPCODE_FSEQ:
3191 case TGSI_OPCODE_FSGE:
3192 case TGSI_OPCODE_FSLT:
3193 case TGSI_OPCODE_FSNE:
3194 case TGSI_OPCODE_ISGE:
3195 case TGSI_OPCODE_ISLT:
3196 case TGSI_OPCODE_USEQ:
3197 case TGSI_OPCODE_USGE:
3198 case TGSI_OPCODE_USLT:
3199 case TGSI_OPCODE_USNE:
3200 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3201 src0 = fetchSrc(0, c);
3202 src1 = fetchSrc(1, c);
3203 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3204 }
3205 break;
3206 case TGSI_OPCODE_VOTE_ALL:
3207 case TGSI_OPCODE_VOTE_ANY:
3208 case TGSI_OPCODE_VOTE_EQ:
3209 val0 = new_LValue(func, FILE_PREDICATE);
3210 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3211 mkCmp(OP_SET, CC_NE, TYPE_U32, val0, TYPE_U32, fetchSrc(0, c), zero);
3212 mkOp1(op, dstTy, val0, val0)
3213 ->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3214 mkCvt(OP_CVT, TYPE_U32, dst0[c], TYPE_U8, val0);
3215 }
3216 break;
3217 case TGSI_OPCODE_KILL_IF:
3218 val0 = new_LValue(func, FILE_PREDICATE);
3219 mask = 0;
3220 for (c = 0; c < 4; ++c) {
3221 const int s = tgsi.getSrc(0).getSwizzle(c);
3222 if (mask & (1 << s))
3223 continue;
3224 mask |= 1 << s;
3225 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
3226 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
3227 }
3228 break;
3229 case TGSI_OPCODE_KILL:
3230 mkOp(OP_DISCARD, TYPE_NONE, NULL);
3231 break;
3232 case TGSI_OPCODE_TEX:
3233 case TGSI_OPCODE_TXB:
3234 case TGSI_OPCODE_TXL:
3235 case TGSI_OPCODE_TXP:
3236 case TGSI_OPCODE_LODQ:
3237 // R S L C Dx Dy
3238 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
3239 break;
3240 case TGSI_OPCODE_TXD:
3241 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
3242 break;
3243 case TGSI_OPCODE_TG4:
3244 handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
3245 break;
3246 case TGSI_OPCODE_TEX2:
3247 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
3248 break;
3249 case TGSI_OPCODE_TXB2:
3250 case TGSI_OPCODE_TXL2:
3251 handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
3252 break;
3253 case TGSI_OPCODE_SAMPLE:
3254 case TGSI_OPCODE_SAMPLE_B:
3255 case TGSI_OPCODE_SAMPLE_D:
3256 case TGSI_OPCODE_SAMPLE_L:
3257 case TGSI_OPCODE_SAMPLE_C:
3258 case TGSI_OPCODE_SAMPLE_C_LZ:
3259 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
3260 break;
3261 case TGSI_OPCODE_TXF:
3262 handleTXF(dst0, 1, 0x03);
3263 break;
3264 case TGSI_OPCODE_SAMPLE_I:
3265 handleTXF(dst0, 1, 0x03);
3266 break;
3267 case TGSI_OPCODE_SAMPLE_I_MS:
3268 handleTXF(dst0, 1, 0x20);
3269 break;
3270 case TGSI_OPCODE_TXQ:
3271 case TGSI_OPCODE_SVIEWINFO:
3272 handleTXQ(dst0, TXQ_DIMS, 1);
3273 break;
3274 case TGSI_OPCODE_TXQS:
3275 // The TXQ_TYPE query returns samples in its 3rd arg, but we need it to
3276 // be in .x
3277 dst0[1] = dst0[2] = dst0[3] = NULL;
3278 std::swap(dst0[0], dst0[2]);
3279 handleTXQ(dst0, TXQ_TYPE, 0);
3280 std::swap(dst0[0], dst0[2]);
3281 break;
3282 case TGSI_OPCODE_F2I:
3283 case TGSI_OPCODE_F2U:
3284 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3285 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
3286 break;
3287 case TGSI_OPCODE_I2F:
3288 case TGSI_OPCODE_U2F:
3289 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3290 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
3291 break;
3292 case TGSI_OPCODE_PK2H:
3293 val0 = getScratch();
3294 val1 = getScratch();
3295 mkCvt(OP_CVT, TYPE_F16, val0, TYPE_F32, fetchSrc(0, 0));
3296 mkCvt(OP_CVT, TYPE_F16, val1, TYPE_F32, fetchSrc(0, 1));
3297 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3298 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3299 break;
3300 case TGSI_OPCODE_UP2H:
3301 src0 = fetchSrc(0, 0);
3302 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3303 geni = mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F16, src0);
3304 geni->subOp = c & 1;
3305 }
3306 break;
3307 case TGSI_OPCODE_EMIT:
3308 /* export the saved viewport index */
3309 if (viewport != NULL) {
3310 Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
3311 info->out[info->io.viewportId].slot[0] * 4);
3312 mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
3313 }
3314 /* fallthrough */
3315 case TGSI_OPCODE_ENDPRIM:
3316 {
3317 // get vertex stream (must be immediate)
3318 unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
3319 if (stream && op == OP_RESTART)
3320 break;
3321 if (info->prop.gp.maxVertices == 0)
3322 break;
3323 src0 = mkImm(stream);
3324 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
3325 break;
3326 }
3327 case TGSI_OPCODE_IF:
3328 case TGSI_OPCODE_UIF:
3329 {
3330 BasicBlock *ifBB = new BasicBlock(func);
3331
3332 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
3333 condBBs.push(bb);
3334 joinBBs.push(bb);
3335
3336 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
3337
3338 setPosition(ifBB, true);
3339 }
3340 break;
3341 case TGSI_OPCODE_ELSE:
3342 {
3343 BasicBlock *elseBB = new BasicBlock(func);
3344 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3345
3346 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
3347 condBBs.push(bb);
3348
3349 forkBB->getExit()->asFlow()->target.bb = elseBB;
3350 if (!bb->isTerminated())
3351 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
3352
3353 setPosition(elseBB, true);
3354 }
3355 break;
3356 case TGSI_OPCODE_ENDIF:
3357 {
3358 BasicBlock *convBB = new BasicBlock(func);
3359 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3360 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
3361
3362 if (!bb->isTerminated()) {
3363 // we only want join if none of the clauses ended with CONT/BREAK/RET
3364 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
3365 insertConvergenceOps(convBB, forkBB);
3366 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
3367 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3368 }
3369
3370 if (prevBB->getExit()->op == OP_BRA) {
3371 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3372 prevBB->getExit()->asFlow()->target.bb = convBB;
3373 }
3374 setPosition(convBB, true);
3375 }
3376 break;
3377 case TGSI_OPCODE_BGNLOOP:
3378 {
3379 BasicBlock *lbgnBB = new BasicBlock(func);
3380 BasicBlock *lbrkBB = new BasicBlock(func);
3381
3382 loopBBs.push(lbgnBB);
3383 breakBBs.push(lbrkBB);
3384 if (loopBBs.getSize() > func->loopNestingBound)
3385 func->loopNestingBound++;
3386
3387 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
3388
3389 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
3390 setPosition(lbgnBB, true);
3391 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
3392 }
3393 break;
3394 case TGSI_OPCODE_ENDLOOP:
3395 {
3396 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
3397
3398 if (!bb->isTerminated()) {
3399 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
3400 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
3401 }
3402 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
3403
3404 // If the loop never breaks (e.g. only has RET's inside), then there
3405 // will be no way to get to the break bb. However BGNLOOP will have
3406 // already made a PREBREAK to it, so it must be in the CFG.
3407 if (getBB()->cfg.incidentCount() == 0)
3408 loopBB->cfg.attach(&getBB()->cfg, Graph::Edge::TREE);
3409 }
3410 break;
3411 case TGSI_OPCODE_BRK:
3412 {
3413 if (bb->isTerminated())
3414 break;
3415 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
3416 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
3417 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
3418 }
3419 break;
3420 case TGSI_OPCODE_CONT:
3421 {
3422 if (bb->isTerminated())
3423 break;
3424 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
3425 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
3426 contBB->explicitCont = true;
3427 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
3428 }
3429 break;
3430 case TGSI_OPCODE_BGNSUB:
3431 {
3432 Subroutine *s = getSubroutine(ip);
3433 BasicBlock *entry = new BasicBlock(s->f);
3434 BasicBlock *leave = new BasicBlock(s->f);
3435
3436 // multiple entrypoints possible, keep the graph connected
3437 if (prog->getType() == Program::TYPE_COMPUTE)
3438 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
3439
3440 sub.cur = s;
3441 s->f->setEntry(entry);
3442 s->f->setExit(leave);
3443 setPosition(entry, true);
3444 return true;
3445 }
3446 case TGSI_OPCODE_ENDSUB:
3447 {
3448 sub.cur = getSubroutine(prog->main);
3449 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
3450 return true;
3451 }
3452 case TGSI_OPCODE_CAL:
3453 {
3454 Subroutine *s = getSubroutine(tgsi.getLabel());
3455 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
3456 func->call.attach(&s->f->call, Graph::Edge::TREE);
3457 return true;
3458 }
3459 case TGSI_OPCODE_RET:
3460 {
3461 if (bb->isTerminated())
3462 return true;
3463 BasicBlock *leave = BasicBlock::get(func->cfgExit);
3464
3465 if (!isEndOfSubroutine(ip + 1)) {
3466 // insert a PRERET at the entry if this is an early return
3467 // (only needed for sharing code in the epilogue)
3468 BasicBlock *pos = getBB();
3469 setPosition(BasicBlock::get(func->cfg.getRoot()), false);
3470 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
3471 setPosition(pos, true);
3472 }
3473 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
3474 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
3475 }
3476 break;
3477 case TGSI_OPCODE_END:
3478 {
3479 // attach and generate epilogue code
3480 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
3481 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
3482 setPosition(epilogue, true);
3483 if (prog->getType() == Program::TYPE_FRAGMENT)
3484 exportOutputs();
3485 if (info->io.genUserClip > 0)
3486 handleUserClipPlanes();
3487 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
3488 }
3489 break;
3490 case TGSI_OPCODE_SWITCH:
3491 case TGSI_OPCODE_CASE:
3492 ERROR("switch/case opcode encountered, should have been lowered\n");
3493 abort();
3494 break;
3495 case TGSI_OPCODE_LOAD:
3496 handleLOAD(dst0);
3497 break;
3498 case TGSI_OPCODE_STORE:
3499 handleSTORE();
3500 break;
3501 case TGSI_OPCODE_BARRIER:
3502 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
3503 geni->fixed = 1;
3504 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
3505 break;
3506 case TGSI_OPCODE_MFENCE:
3507 case TGSI_OPCODE_LFENCE:
3508 case TGSI_OPCODE_SFENCE:
3509 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3510 geni->fixed = 1;
3511 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3512 break;
3513 case TGSI_OPCODE_MEMBAR:
3514 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3515 geni->fixed = 1;
3516 if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
3517 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
3518 else
3519 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
3520 break;
3521 case TGSI_OPCODE_ATOMUADD:
3522 case TGSI_OPCODE_ATOMXCHG:
3523 case TGSI_OPCODE_ATOMCAS:
3524 case TGSI_OPCODE_ATOMAND:
3525 case TGSI_OPCODE_ATOMOR:
3526 case TGSI_OPCODE_ATOMXOR:
3527 case TGSI_OPCODE_ATOMUMIN:
3528 case TGSI_OPCODE_ATOMIMIN:
3529 case TGSI_OPCODE_ATOMUMAX:
3530 case TGSI_OPCODE_ATOMIMAX:
3531 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
3532 break;
3533 case TGSI_OPCODE_RESQ:
3534 if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER) {
3535 geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
3536 makeSym(tgsi.getSrc(0).getFile(),
3537 tgsi.getSrc(0).getIndex(0), -1, 0, 0));
3538 if (tgsi.getSrc(0).isIndirect(0))
3539 geni->setIndirect(0, 1,
3540 fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
3541 } else {
3542 assert(tgsi.getSrc(0).getFile() == TGSI_FILE_IMAGE);
3543
3544 TexInstruction *texi = new_TexInstruction(func, OP_SUQ);
3545 for (int c = 0, d = 0; c < 4; ++c) {
3546 if (dst0[c]) {
3547 texi->setDef(d++, dst0[c]);
3548 texi->tex.mask |= 1 << c;
3549 }
3550 }
3551 texi->tex.r = tgsi.getSrc(0).getIndex(0);
3552 texi->tex.target = getImageTarget(code, texi->tex.r);
3553 bb->insertTail(texi);
3554
3555 if (tgsi.getSrc(0).isIndirect(0))
3556 texi->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
3557 }
3558 break;
3559 case TGSI_OPCODE_IBFE:
3560 case TGSI_OPCODE_UBFE:
3561 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3562 src0 = fetchSrc(0, c);
3563 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
3564 tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
3565 src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
3566 tgsi.getSrc(1).getValueU32(c, info));
3567 } else {
3568 src1 = fetchSrc(1, c);
3569 src2 = fetchSrc(2, c);
3570 mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
3571 }
3572 mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
3573 }
3574 break;
3575 case TGSI_OPCODE_BFI:
3576 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3577 src0 = fetchSrc(0, c);
3578 src1 = fetchSrc(1, c);
3579 src2 = fetchSrc(2, c);
3580 src3 = fetchSrc(3, c);
3581 mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
3582 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
3583 }
3584 break;
3585 case TGSI_OPCODE_LSB:
3586 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3587 src0 = fetchSrc(0, c);
3588 geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
3589 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3590 geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
3591 geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3592 }
3593 break;
3594 case TGSI_OPCODE_IMSB:
3595 case TGSI_OPCODE_UMSB:
3596 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3597 src0 = fetchSrc(0, c);
3598 mkOp1(OP_BFIND, srcTy, dst0[c], src0);
3599 }
3600 break;
3601 case TGSI_OPCODE_BREV:
3602 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3603 src0 = fetchSrc(0, c);
3604 geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
3605 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3606 }
3607 break;
3608 case TGSI_OPCODE_POPC:
3609 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3610 src0 = fetchSrc(0, c);
3611 mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
3612 }
3613 break;
3614 case TGSI_OPCODE_INTERP_CENTROID:
3615 case TGSI_OPCODE_INTERP_SAMPLE:
3616 case TGSI_OPCODE_INTERP_OFFSET:
3617 handleINTERP(dst0);
3618 break;
3619 case TGSI_OPCODE_D2I:
3620 case TGSI_OPCODE_D2U:
3621 case TGSI_OPCODE_D2F: {
3622 int pos = 0;
3623 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3624 Value *dreg = getSSA(8);
3625 src0 = fetchSrc(0, pos);
3626 src1 = fetchSrc(0, pos + 1);
3627 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3628 Instruction *cvt = mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
3629 if (!isFloatType(dstTy))
3630 cvt->rnd = ROUND_Z;
3631 pos += 2;
3632 }
3633 break;
3634 }
3635 case TGSI_OPCODE_I2D:
3636 case TGSI_OPCODE_U2D:
3637 case TGSI_OPCODE_F2D:
3638 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3639 Value *dreg = getSSA(8);
3640 mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
3641 mkSplit(&dst0[c], 4, dreg);
3642 c++;
3643 }
3644 break;
3645 case TGSI_OPCODE_DABS:
3646 case TGSI_OPCODE_DNEG:
3647 case TGSI_OPCODE_DRCP:
3648 case TGSI_OPCODE_DSQRT:
3649 case TGSI_OPCODE_DRSQ:
3650 case TGSI_OPCODE_DTRUNC:
3651 case TGSI_OPCODE_DCEIL:
3652 case TGSI_OPCODE_DFLR:
3653 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3654 src0 = getSSA(8);
3655 Value *dst = getSSA(8), *tmp[2];
3656 tmp[0] = fetchSrc(0, c);
3657 tmp[1] = fetchSrc(0, c + 1);
3658 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3659 mkOp1(op, dstTy, dst, src0);
3660 mkSplit(&dst0[c], 4, dst);
3661 c++;
3662 }
3663 break;
3664 case TGSI_OPCODE_DFRAC:
3665 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3666 src0 = getSSA(8);
3667 Value *dst = getSSA(8), *tmp[2];
3668 tmp[0] = fetchSrc(0, c);
3669 tmp[1] = fetchSrc(0, c + 1);
3670 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3671 mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3672 mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3673 mkSplit(&dst0[c], 4, dst);
3674 c++;
3675 }
3676 break;
3677 case TGSI_OPCODE_DSLT:
3678 case TGSI_OPCODE_DSGE:
3679 case TGSI_OPCODE_DSEQ:
3680 case TGSI_OPCODE_DSNE: {
3681 int pos = 0;
3682 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3683 Value *tmp[2];
3684
3685 src0 = getSSA(8);
3686 src1 = getSSA(8);
3687 tmp[0] = fetchSrc(0, pos);
3688 tmp[1] = fetchSrc(0, pos + 1);
3689 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3690 tmp[0] = fetchSrc(1, pos);
3691 tmp[1] = fetchSrc(1, pos + 1);
3692 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3693 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3694 pos += 2;
3695 }
3696 break;
3697 }
3698 case TGSI_OPCODE_DADD:
3699 case TGSI_OPCODE_DMUL:
3700 case TGSI_OPCODE_DMAX:
3701 case TGSI_OPCODE_DMIN:
3702 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3703 src0 = getSSA(8);
3704 src1 = getSSA(8);
3705 Value *dst = getSSA(8), *tmp[2];
3706 tmp[0] = fetchSrc(0, c);
3707 tmp[1] = fetchSrc(0, c + 1);
3708 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3709 tmp[0] = fetchSrc(1, c);
3710 tmp[1] = fetchSrc(1, c + 1);
3711 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3712 mkOp2(op, dstTy, dst, src0, src1);
3713 mkSplit(&dst0[c], 4, dst);
3714 c++;
3715 }
3716 break;
3717 case TGSI_OPCODE_DMAD:
3718 case TGSI_OPCODE_DFMA:
3719 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3720 src0 = getSSA(8);
3721 src1 = getSSA(8);
3722 src2 = getSSA(8);
3723 Value *dst = getSSA(8), *tmp[2];
3724 tmp[0] = fetchSrc(0, c);
3725 tmp[1] = fetchSrc(0, c + 1);
3726 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3727 tmp[0] = fetchSrc(1, c);
3728 tmp[1] = fetchSrc(1, c + 1);
3729 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3730 tmp[0] = fetchSrc(2, c);
3731 tmp[1] = fetchSrc(2, c + 1);
3732 mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3733 mkOp3(op, dstTy, dst, src0, src1, src2);
3734 mkSplit(&dst0[c], 4, dst);
3735 c++;
3736 }
3737 break;
3738 case TGSI_OPCODE_DROUND:
3739 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3740 src0 = getSSA(8);
3741 Value *dst = getSSA(8), *tmp[2];
3742 tmp[0] = fetchSrc(0, c);
3743 tmp[1] = fetchSrc(0, c + 1);
3744 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3745 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3746 ->rnd = ROUND_NI;
3747 mkSplit(&dst0[c], 4, dst);
3748 c++;
3749 }
3750 break;
3751 case TGSI_OPCODE_DSSG:
3752 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3753 src0 = getSSA(8);
3754 Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3755 tmp[0] = fetchSrc(0, c);
3756 tmp[1] = fetchSrc(0, c + 1);
3757 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3758
3759 val0 = getScratch();
3760 val1 = getScratch();
3761 // The zero is wrong here since it's only 32-bit, but it works out in
3762 // the end since it gets replaced with $r63.
3763 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3764 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3765 mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3766 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3767 mkSplit(&dst0[c], 4, dst);
3768 c++;
3769 }
3770 break;
3771 default:
3772 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3773 assert(0);
3774 break;
3775 }
3776
3777 if (tgsi.dstCount()) {
3778 for (c = 0; c < 4; ++c) {
3779 if (!dst0[c])
3780 continue;
3781 if (dst0[c] != rDst0[c])
3782 mkMov(rDst0[c], dst0[c]);
3783 storeDst(0, c, rDst0[c]);
3784 }
3785 }
3786 vtxBaseValid = 0;
3787
3788 return true;
3789 }
3790
3791 void
3792 Converter::handleUserClipPlanes()
3793 {
3794 Value *res[8];
3795 int n, i, c;
3796
3797 for (c = 0; c < 4; ++c) {
3798 for (i = 0; i < info->io.genUserClip; ++i) {
3799 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3800 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3801 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3802 if (c == 0)
3803 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3804 else
3805 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3806 }
3807 }
3808
3809 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3810
3811 for (i = 0; i < info->io.genUserClip; ++i) {
3812 n = i / 4 + first;
3813 c = i % 4;
3814 Symbol *sym =
3815 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3816 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3817 }
3818 }
3819
3820 void
3821 Converter::exportOutputs()
3822 {
3823 if (info->io.alphaRefBase) {
3824 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3825 if (info->out[i].sn != TGSI_SEMANTIC_COLOR ||
3826 info->out[i].si != 0)
3827 continue;
3828 const unsigned int c = 3;
3829 if (!oData.exists(sub.cur->values, i, c))
3830 continue;
3831 Value *val = oData.load(sub.cur->values, i, c, NULL);
3832 if (!val)
3833 continue;
3834
3835 Symbol *ref = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3836 TYPE_U32, info->io.alphaRefBase);
3837 Value *pred = new_LValue(func, FILE_PREDICATE);
3838 mkCmp(OP_SET, CC_TR, TYPE_U32, pred, TYPE_F32, val,
3839 mkLoadv(TYPE_U32, ref, NULL))
3840 ->subOp = 1;
3841 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_NOT_P, pred);
3842 }
3843 }
3844
3845 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3846 for (unsigned int c = 0; c < 4; ++c) {
3847 if (!oData.exists(sub.cur->values, i, c))
3848 continue;
3849 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3850 info->out[i].slot[c] * 4);
3851 Value *val = oData.load(sub.cur->values, i, c, NULL);
3852 if (val) {
3853 if (info->out[i].sn == TGSI_SEMANTIC_POSITION)
3854 mkOp1(OP_SAT, TYPE_F32, val, val);
3855 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3856 }
3857 }
3858 }
3859 }
3860
3861 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3862 code(code),
3863 tgsi(NULL),
3864 tData(this), lData(this), aData(this), pData(this), oData(this)
3865 {
3866 info = code->info;
3867
3868 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3869 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3870 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3871 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3872
3873 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, FILE_GPR, 0);
3874 lData.setup(TGSI_FILE_TEMPORARY, 1, 0, tSize, 4, 4, FILE_MEMORY_LOCAL, 0);
3875 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3876 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3877 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3878
3879 zero = mkImm((uint32_t)0);
3880
3881 vtxBaseValid = 0;
3882 }
3883
3884 Converter::~Converter()
3885 {
3886 }
3887
3888 inline const Converter::Location *
3889 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3890 {
3891 ValueMap::l_iterator it = s->values.l.find(v);
3892 return it == s->values.l.end() ? NULL : &it->second;
3893 }
3894
3895 template<typename T> inline void
3896 Converter::BindArgumentsPass::updateCallArgs(
3897 Instruction *i, void (Instruction::*setArg)(int, Value *),
3898 T (Function::*proto))
3899 {
3900 Function *g = i->asFlow()->target.fn;
3901 Subroutine *subg = conv.getSubroutine(g);
3902
3903 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3904 Value *v = (g->*proto)[a].get();
3905 const Converter::Location &l = *getValueLocation(subg, v);
3906 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3907
3908 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3909 }
3910 }
3911
3912 template<typename T> inline void
3913 Converter::BindArgumentsPass::updatePrototype(
3914 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3915 {
3916 (func->*updateSet)();
3917
3918 for (unsigned i = 0; i < set->getSize(); ++i) {
3919 Value *v = func->getLValue(i);
3920 const Converter::Location *l = getValueLocation(sub, v);
3921
3922 // only include values with a matching TGSI register
3923 if (set->test(i) && l && !conv.code->locals.count(*l))
3924 (func->*proto).push_back(v);
3925 }
3926 }
3927
3928 bool
3929 Converter::BindArgumentsPass::visit(Function *f)
3930 {
3931 sub = conv.getSubroutine(f);
3932
3933 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3934 !bi.end(); bi.next()) {
3935 for (Instruction *i = BasicBlock::get(bi)->getFirst();
3936 i; i = i->next) {
3937 if (i->op == OP_CALL && !i->asFlow()->builtin) {
3938 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3939 updateCallArgs(i, &Instruction::setDef, &Function::outs);
3940 }
3941 }
3942 }
3943
3944 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3945 return true;
3946 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3947 &Function::buildLiveSets, &Function::ins);
3948 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3949 &Function::buildDefSets, &Function::outs);
3950
3951 return true;
3952 }
3953
3954 bool
3955 Converter::run()
3956 {
3957 BasicBlock *entry = new BasicBlock(prog->main);
3958 BasicBlock *leave = new BasicBlock(prog->main);
3959
3960 prog->main->setEntry(entry);
3961 prog->main->setExit(leave);
3962
3963 setPosition(entry, true);
3964 sub.cur = getSubroutine(prog->main);
3965
3966 if (info->io.genUserClip > 0) {
3967 for (int c = 0; c < 4; ++c)
3968 clipVtx[c] = getScratch();
3969 }
3970
3971 switch (prog->getType()) {
3972 case Program::TYPE_TESSELLATION_CONTROL:
3973 outBase = mkOp2v(
3974 OP_SUB, TYPE_U32, getSSA(),
3975 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
3976 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
3977 break;
3978 case Program::TYPE_FRAGMENT: {
3979 Symbol *sv = mkSysVal(SV_POSITION, 3);
3980 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
3981 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
3982 break;
3983 }
3984 default:
3985 break;
3986 }
3987
3988 if (info->io.viewportId >= 0)
3989 viewport = getScratch();
3990 else
3991 viewport = NULL;
3992
3993 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
3994 if (!handleInstruction(&code->insns[ip]))
3995 return false;
3996 }
3997
3998 if (!BindArgumentsPass(*this).run(prog))
3999 return false;
4000
4001 return true;
4002 }
4003
4004 } // unnamed namespace
4005
4006 namespace nv50_ir {
4007
4008 bool
4009 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
4010 {
4011 tgsi::Source src(info);
4012 if (!src.scanSource())
4013 return false;
4014 tlsSize = info->bin.tlsSpace;
4015
4016 Converter builder(this, &src);
4017 return builder.run();
4018 }
4019
4020 } // namespace nv50_ir