src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "tgsi/tgsi_dump.h"
  24 #include "tgsi/tgsi_scan.h"
  25 #include "tgsi/tgsi_util.h"
  26
  27 #include <set>
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_util.h"
  31 #include "codegen/nv50_ir_build_util.h"
  32
  33 namespace tgsi {
  34
  35 class Source;
  36
  37 static nv50_ir::operation translateOpcode(uint opcode);
  38 static nv50_ir::DataFile translateFile(uint file);
  39 static nv50_ir::TexTarget translateTexture(uint texTarg);
  40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  41
  42 class Instruction
  43 {
  44 public:
  45    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  46
  47    class SrcRegister
  48    {
  49    public:
  50       SrcRegister(const struct tgsi_full_src_register *src)
  51          : reg(src->Register),
  52            fsr(src)
  53       { }
  54
  55       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  56
  57       SrcRegister(const struct tgsi_ind_register& ind)
  58          : reg(tgsi_util_get_src_from_ind(&ind)),
  59            fsr(NULL)
  60       { }
  61
  62       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  63       {
  64          struct tgsi_src_register reg;
  65          memset(&reg, 0, sizeof(reg));
  66          reg.Index = off.Index;
  67          reg.File = off.File;
  68          reg.SwizzleX = off.SwizzleX;
  69          reg.SwizzleY = off.SwizzleY;
  70          reg.SwizzleZ = off.SwizzleZ;
  71          return reg;
  72       }
  73
  74       SrcRegister(const struct tgsi_texture_offset& off) :
  75          reg(offsetToSrc(off)),
  76          fsr(NULL)
  77       { }
  78
  79       uint getFile() const { return reg.File; }
  80
  81       bool is2D() const { return reg.Dimension; }
  82
  83       bool isIndirect(int dim) const
  84       {
  85          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  86       }
  87
  88       int getIndex(int dim) const
  89       {
  90          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  91       }
  92
  93       int getSwizzle(int chan) const
  94       {
  95          return tgsi_util_get_src_register_swizzle(&reg, chan);
  96       }
  97
  98       nv50_ir::Modifier getMod(int chan) const;
  99
 100       SrcRegister getIndirect(int dim) const
 101       {
 102          assert(fsr && isIndirect(dim));
 103          if (dim)
 104             return SrcRegister(fsr->DimIndirect);
 105          return SrcRegister(fsr->Indirect);
 106       }
 107
 108       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 109       {
 110          assert(reg.File == TGSI_FILE_IMMEDIATE);
 111          assert(!reg.Absolute);
 112          assert(!reg.Negate);
 113          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 114       }
 115
 116    private:
 117       const struct tgsi_src_register reg;
 118       const struct tgsi_full_src_register *fsr;
 119    };
 120
 121    class DstRegister
 122    {
 123    public:
 124       DstRegister(const struct tgsi_full_dst_register *dst)
 125          : reg(dst->Register),
 126            fdr(dst)
 127       { }
 128
 129       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 130
 131       uint getFile() const { return reg.File; }
 132
 133       bool is2D() const { return reg.Dimension; }
 134
 135       bool isIndirect(int dim) const
 136       {
 137          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 138       }
 139
 140       int getIndex(int dim) const
 141       {
 142          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 143       }
 144
 145       unsigned int getMask() const { return reg.WriteMask; }
 146
 147       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 148
 149       SrcRegister getIndirect(int dim) const
 150       {
 151          assert(fdr && isIndirect(dim));
 152          if (dim)
 153             return SrcRegister(fdr->DimIndirect);
 154          return SrcRegister(fdr->Indirect);
 155       }
 156
 157    private:
 158       const struct tgsi_dst_register reg;
 159       const struct tgsi_full_dst_register *fdr;
 160    };
 161
 162    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 163
 164    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 165    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 166
 167    // mask of used components of source s
 168    unsigned int srcMask(unsigned int s) const;
 169
 170    SrcRegister getSrc(unsigned int s) const
 171    {
 172       assert(s < srcCount());
 173       return SrcRegister(&insn->Src[s]);
 174    }
 175
 176    DstRegister getDst(unsigned int d) const
 177    {
 178       assert(d < dstCount());
 179       return DstRegister(&insn->Dst[d]);
 180    }
 181
 182    SrcRegister getTexOffset(unsigned int i) const
 183    {
 184       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 185       return SrcRegister(insn->TexOffsets[i]);
 186    }
 187
 188    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 189
 190    bool checkDstSrcAliasing() const;
 191
 192    inline nv50_ir::operation getOP() const {
 193       return translateOpcode(getOpcode()); }
 194
 195    nv50_ir::DataType inferSrcType() const;
 196    nv50_ir::DataType inferDstType() const;
 197
 198    nv50_ir::CondCode getSetCond() const;
 199
 200    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 201
 202    inline uint getLabel() { return insn->Label.Label; }
 203
 204    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 205
 206    void print() const
 207    {
 208       tgsi_dump_instruction(insn, 1);
 209    }
 210
 211 private:
 212    const struct tgsi_full_instruction *insn;
 213 };
 214
 215 unsigned int Instruction::srcMask(unsigned int s) const
 216 {
 217    unsigned int mask = insn->Dst[0].Register.WriteMask;
 218
 219    switch (insn->Instruction.Opcode) {
 220    case TGSI_OPCODE_COS:
 221    case TGSI_OPCODE_SIN:
 222       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 223    case TGSI_OPCODE_DP2:
 224       return 0x3;
 225    case TGSI_OPCODE_DP3:
 226       return 0x7;
 227    case TGSI_OPCODE_DP4:
 228    case TGSI_OPCODE_DPH:
 229    case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
 230       return 0xf;
 231    case TGSI_OPCODE_DST:
 232       return mask & (s ? 0xa : 0x6);
 233    case TGSI_OPCODE_EX2:
 234    case TGSI_OPCODE_EXP:
 235    case TGSI_OPCODE_LG2:
 236    case TGSI_OPCODE_LOG:
 237    case TGSI_OPCODE_POW:
 238    case TGSI_OPCODE_RCP:
 239    case TGSI_OPCODE_RSQ:
 240    case TGSI_OPCODE_SCS:
 241       return 0x1;
 242    case TGSI_OPCODE_IF:
 243    case TGSI_OPCODE_UIF:
 244       return 0x1;
 245    case TGSI_OPCODE_LIT:
 246       return 0xb;
 247    case TGSI_OPCODE_TEX2:
 248    case TGSI_OPCODE_TXB2:
 249    case TGSI_OPCODE_TXL2:
 250       return (s == 0) ? 0xf : 0x3;
 251    case TGSI_OPCODE_TEX:
 252    case TGSI_OPCODE_TXB:
 253    case TGSI_OPCODE_TXD:
 254    case TGSI_OPCODE_TXL:
 255    case TGSI_OPCODE_TXP:
 256    case TGSI_OPCODE_LODQ:
 257    {
 258       const struct tgsi_instruction_texture *tex = &insn->Texture;
 259
 260       assert(insn->Instruction.Texture);
 261
 262       mask = 0x7;
 263       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 264           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 265          mask |= 0x8; /* bias, lod or proj */
 266
 267       switch (tex->Texture) {
 268       case TGSI_TEXTURE_1D:
 269          mask &= 0x9;
 270          break;
 271       case TGSI_TEXTURE_SHADOW1D:
 272          mask &= 0xd;
 273          break;
 274       case TGSI_TEXTURE_1D_ARRAY:
 275       case TGSI_TEXTURE_2D:
 276       case TGSI_TEXTURE_RECT:
 277          mask &= 0xb;
 278          break;
 279       case TGSI_TEXTURE_CUBE_ARRAY:
 280       case TGSI_TEXTURE_SHADOW2D_ARRAY:
 281       case TGSI_TEXTURE_SHADOWCUBE:
 282       case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
 283          mask |= 0x8;
 284          break;
 285       default:
 286          break;
 287       }
 288    }
 289       return mask;
 290    case TGSI_OPCODE_XPD:
 291    {
 292       unsigned int x = 0;
 293       if (mask & 1) x |= 0x6;
 294       if (mask & 2) x |= 0x5;
 295       if (mask & 4) x |= 0x3;
 296       return x;
 297    }
 298    case TGSI_OPCODE_D2I:
 299    case TGSI_OPCODE_D2U:
 300    case TGSI_OPCODE_D2F:
 301    case TGSI_OPCODE_DSLT:
 302    case TGSI_OPCODE_DSGE:
 303    case TGSI_OPCODE_DSEQ:
 304    case TGSI_OPCODE_DSNE:
 305       switch (util_bitcount(mask)) {
 306       case 1: return 0x3;
 307       case 2: return 0xf;
 308       default:
 309          assert(!"unexpected mask");
 310          return 0xf;
 311       }
 312    case TGSI_OPCODE_I2D:
 313    case TGSI_OPCODE_U2D:
 314    case TGSI_OPCODE_F2D: {
 315       unsigned int x = 0;
 316       if ((mask & 0x3) == 0x3)
 317          x |= 1;
 318       if ((mask & 0xc) == 0xc)
 319          x |= 2;
 320       return x;
 321    }
 322    default:
 323       break;
 324    }
 325
 326    return mask;
 327 }
 328
 329 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 330 {
 331    nv50_ir::Modifier m(0);
 332
 333    if (reg.Absolute)
 334       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 335    if (reg.Negate)
 336       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 337    return m;
 338 }
 339
 340 static nv50_ir::DataFile translateFile(uint file)
 341 {
 342    switch (file) {
 343    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 344    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 345    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 346    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 347    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 348    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 349    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 350    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 351    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 352    case TGSI_FILE_SAMPLER:
 353    case TGSI_FILE_NULL:
 354    default:
 355       return nv50_ir::FILE_NULL;
 356    }
 357 }
 358
 359 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 360 {
 361    switch (sysval) {
 362    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 363    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 364    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 365    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 366    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 367    case TGSI_SEMANTIC_GRID_SIZE:  return nv50_ir::SV_NCTAID;
 368    case TGSI_SEMANTIC_BLOCK_ID:   return nv50_ir::SV_CTAID;
 369    case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
 370    case TGSI_SEMANTIC_THREAD_ID:  return nv50_ir::SV_TID;
 371    case TGSI_SEMANTIC_SAMPLEID:   return nv50_ir::SV_SAMPLE_INDEX;
 372    case TGSI_SEMANTIC_SAMPLEPOS:  return nv50_ir::SV_SAMPLE_POS;
 373    case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
 374    case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
 375    default:
 376       assert(0);
 377       return nv50_ir::SV_CLOCK;
 378    }
 379 }
 380
 381 #define NV50_IR_TEX_TARG_CASE(a, b) \
 382    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 383
 384 static nv50_ir::TexTarget translateTexture(uint tex)
 385 {
 386    switch (tex) {
 387    NV50_IR_TEX_TARG_CASE(1D, 1D);
 388    NV50_IR_TEX_TARG_CASE(2D, 2D);
 389    NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
 390    NV50_IR_TEX_TARG_CASE(3D, 3D);
 391    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 392    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 393    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 394    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 395    NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
 396    NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
 397    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 398    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 399    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 400    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 401    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 402    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 403    NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
 404    NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
 405
 406    case TGSI_TEXTURE_UNKNOWN:
 407    default:
 408       assert(!"invalid texture target");
 409       return nv50_ir::TEX_TARGET_2D;
 410    }
 411 }
 412
 413 nv50_ir::DataType Instruction::inferSrcType() const
 414 {
 415    switch (getOpcode()) {
 416    case TGSI_OPCODE_UIF:
 417    case TGSI_OPCODE_AND:
 418    case TGSI_OPCODE_OR:
 419    case TGSI_OPCODE_XOR:
 420    case TGSI_OPCODE_NOT:
 421    case TGSI_OPCODE_SHL:
 422    case TGSI_OPCODE_U2F:
 423    case TGSI_OPCODE_U2D:
 424    case TGSI_OPCODE_UADD:
 425    case TGSI_OPCODE_UDIV:
 426    case TGSI_OPCODE_UMOD:
 427    case TGSI_OPCODE_UMAD:
 428    case TGSI_OPCODE_UMUL:
 429    case TGSI_OPCODE_UMUL_HI:
 430    case TGSI_OPCODE_UMAX:
 431    case TGSI_OPCODE_UMIN:
 432    case TGSI_OPCODE_USEQ:
 433    case TGSI_OPCODE_USGE:
 434    case TGSI_OPCODE_USLT:
 435    case TGSI_OPCODE_USNE:
 436    case TGSI_OPCODE_USHR:
 437    case TGSI_OPCODE_ATOMUADD:
 438    case TGSI_OPCODE_ATOMXCHG:
 439    case TGSI_OPCODE_ATOMCAS:
 440    case TGSI_OPCODE_ATOMAND:
 441    case TGSI_OPCODE_ATOMOR:
 442    case TGSI_OPCODE_ATOMXOR:
 443    case TGSI_OPCODE_ATOMUMIN:
 444    case TGSI_OPCODE_ATOMUMAX:
 445    case TGSI_OPCODE_UBFE:
 446    case TGSI_OPCODE_UMSB:
 447       return nv50_ir::TYPE_U32;
 448    case TGSI_OPCODE_I2F:
 449    case TGSI_OPCODE_I2D:
 450    case TGSI_OPCODE_IDIV:
 451    case TGSI_OPCODE_IMUL_HI:
 452    case TGSI_OPCODE_IMAX:
 453    case TGSI_OPCODE_IMIN:
 454    case TGSI_OPCODE_IABS:
 455    case TGSI_OPCODE_INEG:
 456    case TGSI_OPCODE_ISGE:
 457    case TGSI_OPCODE_ISHR:
 458    case TGSI_OPCODE_ISLT:
 459    case TGSI_OPCODE_ISSG:
 460    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 461    case TGSI_OPCODE_MOD:
 462    case TGSI_OPCODE_UARL:
 463    case TGSI_OPCODE_ATOMIMIN:
 464    case TGSI_OPCODE_ATOMIMAX:
 465    case TGSI_OPCODE_IBFE:
 466    case TGSI_OPCODE_IMSB:
 467       return nv50_ir::TYPE_S32;
 468    case TGSI_OPCODE_D2F:
 469    case TGSI_OPCODE_D2I:
 470    case TGSI_OPCODE_D2U:
 471    case TGSI_OPCODE_DABS:
 472    case TGSI_OPCODE_DNEG:
 473    case TGSI_OPCODE_DADD:
 474    case TGSI_OPCODE_DMUL:
 475    case TGSI_OPCODE_DMAX:
 476    case TGSI_OPCODE_DMIN:
 477    case TGSI_OPCODE_DSLT:
 478    case TGSI_OPCODE_DSGE:
 479    case TGSI_OPCODE_DSEQ:
 480    case TGSI_OPCODE_DSNE:
 481    case TGSI_OPCODE_DRCP:
 482    case TGSI_OPCODE_DSQRT:
 483    case TGSI_OPCODE_DMAD:
 484    case TGSI_OPCODE_DFRAC:
 485    case TGSI_OPCODE_DRSQ:
 486    case TGSI_OPCODE_DTRUNC:
 487    case TGSI_OPCODE_DCEIL:
 488    case TGSI_OPCODE_DFLR:
 489    case TGSI_OPCODE_DROUND:
 490       return nv50_ir::TYPE_F64;
 491    default:
 492       return nv50_ir::TYPE_F32;
 493    }
 494 }
 495
 496 nv50_ir::DataType Instruction::inferDstType() const
 497 {
 498    switch (getOpcode()) {
 499    case TGSI_OPCODE_D2U:
 500    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 501    case TGSI_OPCODE_D2I:
 502    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 503    case TGSI_OPCODE_FSEQ:
 504    case TGSI_OPCODE_FSGE:
 505    case TGSI_OPCODE_FSLT:
 506    case TGSI_OPCODE_FSNE:
 507    case TGSI_OPCODE_DSEQ:
 508    case TGSI_OPCODE_DSGE:
 509    case TGSI_OPCODE_DSLT:
 510    case TGSI_OPCODE_DSNE:
 511       return nv50_ir::TYPE_U32;
 512    case TGSI_OPCODE_I2F:
 513    case TGSI_OPCODE_U2F:
 514    case TGSI_OPCODE_D2F:
 515       return nv50_ir::TYPE_F32;
 516    case TGSI_OPCODE_I2D:
 517    case TGSI_OPCODE_U2D:
 518    case TGSI_OPCODE_F2D:
 519       return nv50_ir::TYPE_F64;
 520    default:
 521       return inferSrcType();
 522    }
 523 }
 524
 525 nv50_ir::CondCode Instruction::getSetCond() const
 526 {
 527    using namespace nv50_ir;
 528
 529    switch (getOpcode()) {
 530    case TGSI_OPCODE_SLT:
 531    case TGSI_OPCODE_ISLT:
 532    case TGSI_OPCODE_USLT:
 533    case TGSI_OPCODE_FSLT:
 534    case TGSI_OPCODE_DSLT:
 535       return CC_LT;
 536    case TGSI_OPCODE_SLE:
 537       return CC_LE;
 538    case TGSI_OPCODE_SGE:
 539    case TGSI_OPCODE_ISGE:
 540    case TGSI_OPCODE_USGE:
 541    case TGSI_OPCODE_FSGE:
 542    case TGSI_OPCODE_DSGE:
 543       return CC_GE;
 544    case TGSI_OPCODE_SGT:
 545       return CC_GT;
 546    case TGSI_OPCODE_SEQ:
 547    case TGSI_OPCODE_USEQ:
 548    case TGSI_OPCODE_FSEQ:
 549    case TGSI_OPCODE_DSEQ:
 550       return CC_EQ;
 551    case TGSI_OPCODE_SNE:
 552    case TGSI_OPCODE_FSNE:
 553    case TGSI_OPCODE_DSNE:
 554       return CC_NEU;
 555    case TGSI_OPCODE_USNE:
 556       return CC_NE;
 557    default:
 558       return CC_ALWAYS;
 559    }
 560 }
 561
 562 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 563
 564 static nv50_ir::operation translateOpcode(uint opcode)
 565 {
 566    switch (opcode) {
 567    NV50_IR_OPCODE_CASE(ARL, SHL);
 568    NV50_IR_OPCODE_CASE(MOV, MOV);
 569
 570    NV50_IR_OPCODE_CASE(RCP, RCP);
 571    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 572
 573    NV50_IR_OPCODE_CASE(MUL, MUL);
 574    NV50_IR_OPCODE_CASE(ADD, ADD);
 575
 576    NV50_IR_OPCODE_CASE(MIN, MIN);
 577    NV50_IR_OPCODE_CASE(MAX, MAX);
 578    NV50_IR_OPCODE_CASE(SLT, SET);
 579    NV50_IR_OPCODE_CASE(SGE, SET);
 580    NV50_IR_OPCODE_CASE(MAD, MAD);
 581    NV50_IR_OPCODE_CASE(SUB, SUB);
 582
 583    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 584    NV50_IR_OPCODE_CASE(ROUND, CVT);
 585    NV50_IR_OPCODE_CASE(EX2, EX2);
 586    NV50_IR_OPCODE_CASE(LG2, LG2);
 587    NV50_IR_OPCODE_CASE(POW, POW);
 588
 589    NV50_IR_OPCODE_CASE(ABS, ABS);
 590
 591    NV50_IR_OPCODE_CASE(COS, COS);
 592    NV50_IR_OPCODE_CASE(DDX, DFDX);
 593    NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
 594    NV50_IR_OPCODE_CASE(DDY, DFDY);
 595    NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
 596    NV50_IR_OPCODE_CASE(KILL, DISCARD);
 597
 598    NV50_IR_OPCODE_CASE(SEQ, SET);
 599    NV50_IR_OPCODE_CASE(SGT, SET);
 600    NV50_IR_OPCODE_CASE(SIN, SIN);
 601    NV50_IR_OPCODE_CASE(SLE, SET);
 602    NV50_IR_OPCODE_CASE(SNE, SET);
 603    NV50_IR_OPCODE_CASE(TEX, TEX);
 604    NV50_IR_OPCODE_CASE(TXD, TXD);
 605    NV50_IR_OPCODE_CASE(TXP, TEX);
 606
 607    NV50_IR_OPCODE_CASE(CAL, CALL);
 608    NV50_IR_OPCODE_CASE(RET, RET);
 609    NV50_IR_OPCODE_CASE(CMP, SLCT);
 610
 611    NV50_IR_OPCODE_CASE(TXB, TXB);
 612
 613    NV50_IR_OPCODE_CASE(DIV, DIV);
 614
 615    NV50_IR_OPCODE_CASE(TXL, TXL);
 616
 617    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 618    NV50_IR_OPCODE_CASE(I2F, CVT);
 619    NV50_IR_OPCODE_CASE(NOT, NOT);
 620    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 621    NV50_IR_OPCODE_CASE(SHL, SHL);
 622
 623    NV50_IR_OPCODE_CASE(AND, AND);
 624    NV50_IR_OPCODE_CASE(OR, OR);
 625    NV50_IR_OPCODE_CASE(MOD, MOD);
 626    NV50_IR_OPCODE_CASE(XOR, XOR);
 627    NV50_IR_OPCODE_CASE(SAD, SAD);
 628    NV50_IR_OPCODE_CASE(TXF, TXF);
 629    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 630    NV50_IR_OPCODE_CASE(TG4, TXG);
 631    NV50_IR_OPCODE_CASE(LODQ, TXLQ);
 632
 633    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 634    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 635
 636    NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
 637
 638    NV50_IR_OPCODE_CASE(F2I, CVT);
 639    NV50_IR_OPCODE_CASE(FSEQ, SET);
 640    NV50_IR_OPCODE_CASE(FSGE, SET);
 641    NV50_IR_OPCODE_CASE(FSLT, SET);
 642    NV50_IR_OPCODE_CASE(FSNE, SET);
 643    NV50_IR_OPCODE_CASE(IDIV, DIV);
 644    NV50_IR_OPCODE_CASE(IMAX, MAX);
 645    NV50_IR_OPCODE_CASE(IMIN, MIN);
 646    NV50_IR_OPCODE_CASE(IABS, ABS);
 647    NV50_IR_OPCODE_CASE(INEG, NEG);
 648    NV50_IR_OPCODE_CASE(ISGE, SET);
 649    NV50_IR_OPCODE_CASE(ISHR, SHR);
 650    NV50_IR_OPCODE_CASE(ISLT, SET);
 651    NV50_IR_OPCODE_CASE(F2U, CVT);
 652    NV50_IR_OPCODE_CASE(U2F, CVT);
 653    NV50_IR_OPCODE_CASE(UADD, ADD);
 654    NV50_IR_OPCODE_CASE(UDIV, DIV);
 655    NV50_IR_OPCODE_CASE(UMAD, MAD);
 656    NV50_IR_OPCODE_CASE(UMAX, MAX);
 657    NV50_IR_OPCODE_CASE(UMIN, MIN);
 658    NV50_IR_OPCODE_CASE(UMOD, MOD);
 659    NV50_IR_OPCODE_CASE(UMUL, MUL);
 660    NV50_IR_OPCODE_CASE(USEQ, SET);
 661    NV50_IR_OPCODE_CASE(USGE, SET);
 662    NV50_IR_OPCODE_CASE(USHR, SHR);
 663    NV50_IR_OPCODE_CASE(USLT, SET);
 664    NV50_IR_OPCODE_CASE(USNE, SET);
 665
 666    NV50_IR_OPCODE_CASE(DABS, ABS);
 667    NV50_IR_OPCODE_CASE(DNEG, NEG);
 668    NV50_IR_OPCODE_CASE(DADD, ADD);
 669    NV50_IR_OPCODE_CASE(DMUL, MUL);
 670    NV50_IR_OPCODE_CASE(DMAX, MAX);
 671    NV50_IR_OPCODE_CASE(DMIN, MIN);
 672    NV50_IR_OPCODE_CASE(DSLT, SET);
 673    NV50_IR_OPCODE_CASE(DSGE, SET);
 674    NV50_IR_OPCODE_CASE(DSEQ, SET);
 675    NV50_IR_OPCODE_CASE(DSNE, SET);
 676    NV50_IR_OPCODE_CASE(DRCP, RCP);
 677    NV50_IR_OPCODE_CASE(DSQRT, SQRT);
 678    NV50_IR_OPCODE_CASE(DMAD, MAD);
 679    NV50_IR_OPCODE_CASE(D2I, CVT);
 680    NV50_IR_OPCODE_CASE(D2U, CVT);
 681    NV50_IR_OPCODE_CASE(I2D, CVT);
 682    NV50_IR_OPCODE_CASE(U2D, CVT);
 683    NV50_IR_OPCODE_CASE(DRSQ, RSQ);
 684    NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
 685    NV50_IR_OPCODE_CASE(DCEIL, CEIL);
 686    NV50_IR_OPCODE_CASE(DFLR, FLOOR);
 687    NV50_IR_OPCODE_CASE(DROUND, CVT);
 688
 689    NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
 690    NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
 691
 692    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 693    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 694    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 695    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 696    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 697    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 698    NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
 699    NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
 700    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 701    NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
 702
 703    NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
 704    NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
 705    NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
 706    NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
 707    NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
 708    NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
 709    NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
 710    NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
 711    NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
 712    NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
 713
 714    NV50_IR_OPCODE_CASE(TEX2, TEX);
 715    NV50_IR_OPCODE_CASE(TXB2, TXB);
 716    NV50_IR_OPCODE_CASE(TXL2, TXL);
 717
 718    NV50_IR_OPCODE_CASE(IBFE, EXTBF);
 719    NV50_IR_OPCODE_CASE(UBFE, EXTBF);
 720    NV50_IR_OPCODE_CASE(BFI, INSBF);
 721    NV50_IR_OPCODE_CASE(BREV, EXTBF);
 722    NV50_IR_OPCODE_CASE(POPC, POPCNT);
 723    NV50_IR_OPCODE_CASE(LSB, BFIND);
 724    NV50_IR_OPCODE_CASE(IMSB, BFIND);
 725    NV50_IR_OPCODE_CASE(UMSB, BFIND);
 726
 727    NV50_IR_OPCODE_CASE(END, EXIT);
 728
 729    default:
 730       return nv50_ir::OP_NOP;
 731    }
 732 }
 733
 734 static uint16_t opcodeToSubOp(uint opcode)
 735 {
 736    switch (opcode) {
 737    case TGSI_OPCODE_LFENCE:   return NV50_IR_SUBOP_MEMBAR(L, GL);
 738    case TGSI_OPCODE_SFENCE:   return NV50_IR_SUBOP_MEMBAR(S, GL);
 739    case TGSI_OPCODE_MFENCE:   return NV50_IR_SUBOP_MEMBAR(M, GL);
 740    case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
 741    case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
 742    case TGSI_OPCODE_ATOMCAS:  return NV50_IR_SUBOP_ATOM_CAS;
 743    case TGSI_OPCODE_ATOMAND:  return NV50_IR_SUBOP_ATOM_AND;
 744    case TGSI_OPCODE_ATOMOR:   return NV50_IR_SUBOP_ATOM_OR;
 745    case TGSI_OPCODE_ATOMXOR:  return NV50_IR_SUBOP_ATOM_XOR;
 746    case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
 747    case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
 748    case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
 749    case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
 750    case TGSI_OPCODE_IMUL_HI:
 751    case TGSI_OPCODE_UMUL_HI:
 752       return NV50_IR_SUBOP_MUL_HIGH;
 753    default:
 754       return 0;
 755    }
 756 }
 757
 758 bool Instruction::checkDstSrcAliasing() const
 759 {
 760    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 761       return false;
 762
 763    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 764       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 765          break;
 766       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 767           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 768          return true;
 769    }
 770    return false;
 771 }
 772
 773 class Source
 774 {
 775 public:
 776    Source(struct nv50_ir_prog_info *);
 777    ~Source();
 778
 779 public:
 780    bool scanSource();
 781    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 782
 783 public:
 784    struct tgsi_shader_info scan;
 785    struct tgsi_full_instruction *insns;
 786    const struct tgsi_token *tokens;
 787    struct nv50_ir_prog_info *info;
 788
 789    nv50_ir::DynArray tempArrays;
 790    nv50_ir::DynArray immdArrays;
 791
 792    typedef nv50_ir::BuildUtil::Location Location;
 793    // these registers are per-subroutine, cannot be used for parameter passing
 794    std::set<Location> locals;
 795
 796    bool mainTempsInLMem;
 797
 798    int clipVertexOutput;
 799
 800    struct TextureView {
 801       uint8_t target; // TGSI_TEXTURE_*
 802    };
 803    std::vector<TextureView> textureViews;
 804
 805    struct Resource {
 806       uint8_t target; // TGSI_TEXTURE_*
 807       bool raw;
 808       uint8_t slot; // $surface index
 809    };
 810    std::vector<Resource> resources;
 811
 812 private:
 813    int inferSysValDirection(unsigned sn) const;
 814    bool scanDeclaration(const struct tgsi_full_declaration *);
 815    bool scanInstruction(const struct tgsi_full_instruction *);
 816    void scanProperty(const struct tgsi_full_property *);
 817    void scanImmediate(const struct tgsi_full_immediate *);
 818
 819    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 820 };
 821
 822 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 823 {
 824    tokens = (const struct tgsi_token *)info->bin.source;
 825
 826    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 827       tgsi_dump(tokens, 0);
 828
 829    mainTempsInLMem = false;
 830 }
 831
 832 Source::~Source()
 833 {
 834    if (insns)
 835       FREE(insns);
 836
 837    if (info->immd.data)
 838       FREE(info->immd.data);
 839    if (info->immd.type)
 840       FREE(info->immd.type);
 841 }
 842
 843 bool Source::scanSource()
 844 {
 845    unsigned insnCount = 0;
 846    struct tgsi_parse_context parse;
 847
 848    tgsi_scan_shader(tokens, &scan);
 849
 850    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 851                                                   sizeof(insns[0]));
 852    if (!insns)
 853       return false;
 854
 855    clipVertexOutput = -1;
 856
 857    textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
 858    resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
 859
 860    info->immd.bufSize = 0;
 861
 862    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 863    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 864    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 865
 866    if (info->type == PIPE_SHADER_FRAGMENT) {
 867       info->prop.fp.writesDepth = scan.writes_z;
 868       info->prop.fp.usesDiscard = scan.uses_kill;
 869    } else
 870    if (info->type == PIPE_SHADER_GEOMETRY) {
 871       info->prop.gp.instanceCount = 1; // default value
 872    }
 873
 874    info->io.viewportId = -1;
 875
 876    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 877    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 878
 879    tgsi_parse_init(&parse, tokens);
 880    while (!tgsi_parse_end_of_tokens(&parse)) {
 881       tgsi_parse_token(&parse);
 882
 883       switch (parse.FullToken.Token.Type) {
 884       case TGSI_TOKEN_TYPE_IMMEDIATE:
 885          scanImmediate(&parse.FullToken.FullImmediate);
 886          break;
 887       case TGSI_TOKEN_TYPE_DECLARATION:
 888          scanDeclaration(&parse.FullToken.FullDeclaration);
 889          break;
 890       case TGSI_TOKEN_TYPE_INSTRUCTION:
 891          insns[insnCount++] = parse.FullToken.FullInstruction;
 892          scanInstruction(&parse.FullToken.FullInstruction);
 893          break;
 894       case TGSI_TOKEN_TYPE_PROPERTY:
 895          scanProperty(&parse.FullToken.FullProperty);
 896          break;
 897       default:
 898          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 899          break;
 900       }
 901    }
 902    tgsi_parse_free(&parse);
 903
 904    if (mainTempsInLMem)
 905       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 906
 907    if (info->io.genUserClip > 0) {
 908       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 909
 910       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 911
 912       for (unsigned int n = 0; n < nOut; ++n) {
 913          unsigned int i = info->numOutputs++;
 914          info->out[i].id = i;
 915          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 916          info->out[i].si = n;
 917          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 918       }
 919    }
 920
 921    return info->assignSlots(info) == 0;
 922 }
 923
 924 void Source::scanProperty(const struct tgsi_full_property *prop)
 925 {
 926    switch (prop->Property.PropertyName) {
 927    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 928       info->prop.gp.outputPrim = prop->u[0].Data;
 929       break;
 930    case TGSI_PROPERTY_GS_INPUT_PRIM:
 931       info->prop.gp.inputPrim = prop->u[0].Data;
 932       break;
 933    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 934       info->prop.gp.maxVertices = prop->u[0].Data;
 935       break;
 936    case TGSI_PROPERTY_GS_INVOCATIONS:
 937       info->prop.gp.instanceCount = prop->u[0].Data;
 938       break;
 939    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 940       info->prop.fp.separateFragData = true;
 941       break;
 942    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 943    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 944       // we don't care
 945       break;
 946    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 947       info->io.genUserClip = -1;
 948       break;
 949    default:
 950       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 951       break;
 952    }
 953 }
 954
 955 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 956 {
 957    const unsigned n = info->immd.count++;
 958
 959    assert(n < scan.immediate_count);
 960
 961    for (int c = 0; c < 4; ++c)
 962       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 963
 964    info->immd.type[n] = imm->Immediate.DataType;
 965 }
 966
 967 int Source::inferSysValDirection(unsigned sn) const
 968 {
 969    switch (sn) {
 970    case TGSI_SEMANTIC_INSTANCEID:
 971    case TGSI_SEMANTIC_VERTEXID:
 972       return 1;
 973    case TGSI_SEMANTIC_LAYER:
 974 #if 0
 975    case TGSI_SEMANTIC_VIEWPORTINDEX:
 976       return 0;
 977 #endif
 978    case TGSI_SEMANTIC_PRIMID:
 979       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
 980    default:
 981       return 0;
 982    }
 983 }
 984
 985 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
 986 {
 987    unsigned i, c;
 988    unsigned sn = TGSI_SEMANTIC_GENERIC;
 989    unsigned si = 0;
 990    const unsigned first = decl->Range.First, last = decl->Range.Last;
 991
 992    if (decl->Declaration.Semantic) {
 993       sn = decl->Semantic.Name;
 994       si = decl->Semantic.Index;
 995    }
 996
 997    if (decl->Declaration.Local) {
 998       for (i = first; i <= last; ++i) {
 999          for (c = 0; c < 4; ++c) {
1000             locals.insert(
1001                Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1002          }
1003       }
1004    }
1005
1006    switch (decl->Declaration.File) {
1007    case TGSI_FILE_INPUT:
1008       if (info->type == PIPE_SHADER_VERTEX) {
1009          // all vertex attributes are equal
1010          for (i = first; i <= last; ++i) {
1011             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1012             info->in[i].si = i;
1013          }
1014       } else {
1015          for (i = first; i <= last; ++i, ++si) {
1016             info->in[i].id = i;
1017             info->in[i].sn = sn;
1018             info->in[i].si = si;
1019             if (info->type == PIPE_SHADER_FRAGMENT) {
1020                // translate interpolation mode
1021                switch (decl->Interp.Interpolate) {
1022                case TGSI_INTERPOLATE_CONSTANT:
1023                   info->in[i].flat = 1;
1024                   break;
1025                case TGSI_INTERPOLATE_COLOR:
1026                   info->in[i].sc = 1;
1027                   break;
1028                case TGSI_INTERPOLATE_LINEAR:
1029                   info->in[i].linear = 1;
1030                   break;
1031                default:
1032                   break;
1033                }
1034                if (decl->Interp.Location || info->io.sampleInterp)
1035                   info->in[i].centroid = 1;
1036             }
1037          }
1038       }
1039       break;
1040    case TGSI_FILE_OUTPUT:
1041       for (i = first; i <= last; ++i, ++si) {
1042          switch (sn) {
1043          case TGSI_SEMANTIC_POSITION:
1044             if (info->type == PIPE_SHADER_FRAGMENT)
1045                info->io.fragDepth = i;
1046             else
1047             if (clipVertexOutput < 0)
1048                clipVertexOutput = i;
1049             break;
1050          case TGSI_SEMANTIC_COLOR:
1051             if (info->type == PIPE_SHADER_FRAGMENT)
1052                info->prop.fp.numColourResults++;
1053             break;
1054          case TGSI_SEMANTIC_EDGEFLAG:
1055             info->io.edgeFlagOut = i;
1056             break;
1057          case TGSI_SEMANTIC_CLIPVERTEX:
1058             clipVertexOutput = i;
1059             break;
1060          case TGSI_SEMANTIC_CLIPDIST:
1061             info->io.clipDistanceMask |=
1062                decl->Declaration.UsageMask << (si * 4);
1063             info->io.genUserClip = -1;
1064             break;
1065          case TGSI_SEMANTIC_SAMPLEMASK:
1066             info->io.sampleMask = i;
1067             break;
1068          case TGSI_SEMANTIC_VIEWPORT_INDEX:
1069             info->io.viewportId = i;
1070             break;
1071          default:
1072             break;
1073          }
1074          info->out[i].id = i;
1075          info->out[i].sn = sn;
1076          info->out[i].si = si;
1077       }
1078       break;
1079    case TGSI_FILE_SYSTEM_VALUE:
1080       switch (sn) {
1081       case TGSI_SEMANTIC_INSTANCEID:
1082          info->io.instanceId = first;
1083          break;
1084       case TGSI_SEMANTIC_VERTEXID:
1085          info->io.vertexId = first;
1086          break;
1087       default:
1088          break;
1089       }
1090       for (i = first; i <= last; ++i, ++si) {
1091          info->sv[i].sn = sn;
1092          info->sv[i].si = si;
1093          info->sv[i].input = inferSysValDirection(sn);
1094       }
1095       break;
1096    case TGSI_FILE_RESOURCE:
1097       for (i = first; i <= last; ++i) {
1098          resources[i].target = decl->Resource.Resource;
1099          resources[i].raw = decl->Resource.Raw;
1100          resources[i].slot = i;
1101       }
1102       break;
1103    case TGSI_FILE_SAMPLER_VIEW:
1104       for (i = first; i <= last; ++i)
1105          textureViews[i].target = decl->SamplerView.Resource;
1106       break;
1107    case TGSI_FILE_NULL:
1108    case TGSI_FILE_TEMPORARY:
1109    case TGSI_FILE_ADDRESS:
1110    case TGSI_FILE_CONSTANT:
1111    case TGSI_FILE_IMMEDIATE:
1112    case TGSI_FILE_PREDICATE:
1113    case TGSI_FILE_SAMPLER:
1114       break;
1115    default:
1116       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1117       return false;
1118    }
1119    return true;
1120 }
1121
1122 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1123 {
1124    return insn.getOpcode() == TGSI_OPCODE_MOV &&
1125       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1126       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1127 }
1128
1129 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1130 {
1131    Instruction insn(inst);
1132
1133    if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1134       info->numBarriers = 1;
1135
1136    if (insn.dstCount()) {
1137       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1138          Instruction::DstRegister dst = insn.getDst(0);
1139
1140          if (dst.isIndirect(0))
1141             for (unsigned i = 0; i < info->numOutputs; ++i)
1142                info->out[i].mask = 0xf;
1143          else
1144             info->out[dst.getIndex(0)].mask |= dst.getMask();
1145
1146          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1147              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1148              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1149              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1150              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1151             info->out[dst.getIndex(0)].mask &= 1;
1152
1153          if (isEdgeFlagPassthrough(insn))
1154             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1155       } else
1156       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1157          if (insn.getDst(0).isIndirect(0))
1158             mainTempsInLMem = true;
1159       }
1160    }
1161
1162    for (unsigned s = 0; s < insn.srcCount(); ++s) {
1163       Instruction::SrcRegister src = insn.getSrc(s);
1164       if (src.getFile() == TGSI_FILE_TEMPORARY) {
1165          if (src.isIndirect(0))
1166             mainTempsInLMem = true;
1167       } else
1168       if (src.getFile() == TGSI_FILE_RESOURCE) {
1169          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1170             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1171                0x1 : 0x2;
1172       }
1173       if (src.getFile() != TGSI_FILE_INPUT)
1174          continue;
1175       unsigned mask = insn.srcMask(s);
1176
1177       if (src.isIndirect(0)) {
1178          for (unsigned i = 0; i < info->numInputs; ++i)
1179             info->in[i].mask = 0xf;
1180       } else {
1181          const int i = src.getIndex(0);
1182          for (unsigned c = 0; c < 4; ++c) {
1183             if (!(mask & (1 << c)))
1184                continue;
1185             int k = src.getSwizzle(c);
1186             if (k <= TGSI_SWIZZLE_W)
1187                info->in[i].mask |= 1 << k;
1188          }
1189          switch (info->in[i].sn) {
1190          case TGSI_SEMANTIC_PSIZE:
1191          case TGSI_SEMANTIC_PRIMID:
1192          case TGSI_SEMANTIC_FOG:
1193             info->in[i].mask &= 0x1;
1194             break;
1195          case TGSI_SEMANTIC_PCOORD:
1196             info->in[i].mask &= 0x3;
1197             break;
1198          default:
1199             break;
1200          }
1201       }
1202    }
1203    return true;
1204 }
1205
1206 nv50_ir::TexInstruction::Target
1207 Instruction::getTexture(const tgsi::Source *code, int s) const
1208 {
1209    // XXX: indirect access
1210    unsigned int r;
1211
1212    switch (getSrc(s).getFile()) {
1213    case TGSI_FILE_RESOURCE:
1214       r = getSrc(s).getIndex(0);
1215       return translateTexture(code->resources.at(r).target);
1216    case TGSI_FILE_SAMPLER_VIEW:
1217       r = getSrc(s).getIndex(0);
1218       return translateTexture(code->textureViews.at(r).target);
1219    default:
1220       return translateTexture(insn->Texture.Texture);
1221    }
1222 }
1223
1224 } // namespace tgsi
1225
1226 namespace {
1227
1228 using namespace nv50_ir;
1229
1230 class Converter : public BuildUtil
1231 {
1232 public:
1233    Converter(Program *, const tgsi::Source *);
1234    ~Converter();
1235
1236    bool run();
1237
1238 private:
1239    struct Subroutine
1240    {
1241       Subroutine(Function *f) : f(f) { }
1242       Function *f;
1243       ValueMap values;
1244    };
1245
1246    Value *shiftAddress(Value *);
1247    Value *getVertexBase(int s);
1248    DataArray *getArrayForFile(unsigned file, int idx);
1249    Value *fetchSrc(int s, int c);
1250    Value *acquireDst(int d, int c);
1251    void storeDst(int d, int c, Value *);
1252
1253    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1254    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1255                  Value *val, Value *ptr);
1256
1257    Value *applySrcMod(Value *, int s, int c);
1258
1259    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1260    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1261    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1262
1263    bool handleInstruction(const struct tgsi_full_instruction *);
1264    void exportOutputs();
1265    inline Subroutine *getSubroutine(unsigned ip);
1266    inline Subroutine *getSubroutine(Function *);
1267    inline bool isEndOfSubroutine(uint ip);
1268
1269    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1270
1271    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1272    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1273    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1274    void handleTXF(Value *dst0[4], int R, int L_M);
1275    void handleTXQ(Value *dst0[4], enum TexQuery);
1276    void handleLIT(Value *dst0[4]);
1277    void handleUserClipPlanes();
1278
1279    Symbol *getResourceBase(int r);
1280    void getResourceCoords(std::vector<Value *>&, int r, int s);
1281
1282    void handleLOAD(Value *dst0[4]);
1283    void handleSTORE();
1284    void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1285
1286    void handleINTERP(Value *dst0[4]);
1287
1288    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1289
1290    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1291
1292    Value *buildDot(int dim);
1293
1294    class BindArgumentsPass : public Pass {
1295    public:
1296       BindArgumentsPass(Converter &conv) : conv(conv) { }
1297
1298    private:
1299       Converter &conv;
1300       Subroutine *sub;
1301
1302       inline const Location *getValueLocation(Subroutine *, Value *);
1303
1304       template<typename T> inline void
1305       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1306                      T (Function::*proto));
1307
1308       template<typename T> inline void
1309       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1310                       T (Function::*proto));
1311
1312    protected:
1313       bool visit(Function *);
1314       bool visit(BasicBlock *bb) { return false; }
1315    };
1316
1317 private:
1318    const tgsi::Source *code;
1319    const struct nv50_ir_prog_info *info;
1320
1321    struct {
1322       std::map<unsigned, Subroutine> map;
1323       Subroutine *cur;
1324    } sub;
1325
1326    uint ip; // instruction pointer
1327
1328    tgsi::Instruction tgsi;
1329
1330    DataType dstTy;
1331    DataType srcTy;
1332
1333    DataArray tData; // TGSI_FILE_TEMPORARY
1334    DataArray aData; // TGSI_FILE_ADDRESS
1335    DataArray pData; // TGSI_FILE_PREDICATE
1336    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1337
1338    Value *zero;
1339    Value *fragCoord[4];
1340    Value *clipVtx[4];
1341
1342    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1343    uint8_t vtxBaseValid;
1344
1345    Stack condBBs;  // fork BB, then else clause BB
1346    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1347    Stack loopBBs;  // loop headers
1348    Stack breakBBs; // end of / after loop
1349
1350    Value *viewport;
1351 };
1352
1353 Symbol *
1354 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1355 {
1356    const int swz = src.getSwizzle(c);
1357
1358    /* TODO: Use Array ID when it's available for the index */
1359    return makeSym(src.getFile(),
1360                   src.is2D() ? src.getIndex(1) : 0,
1361                   src.getIndex(0), swz,
1362                   src.getIndex(0) * 16 + swz * 4);
1363 }
1364
1365 Symbol *
1366 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1367 {
1368    /* TODO: Use Array ID when it's available for the index */
1369    return makeSym(dst.getFile(),
1370                   dst.is2D() ? dst.getIndex(1) : 0,
1371                   dst.getIndex(0), c,
1372                   dst.getIndex(0) * 16 + c * 4);
1373 }
1374
1375 Symbol *
1376 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1377 {
1378    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1379
1380    sym->reg.fileIndex = fileIdx;
1381
1382    if (idx >= 0) {
1383       if (sym->reg.file == FILE_SHADER_INPUT)
1384          sym->setOffset(info->in[idx].slot[c] * 4);
1385       else
1386       if (sym->reg.file == FILE_SHADER_OUTPUT)
1387          sym->setOffset(info->out[idx].slot[c] * 4);
1388       else
1389       if (sym->reg.file == FILE_SYSTEM_VALUE)
1390          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1391       else
1392          sym->setOffset(address);
1393    } else {
1394       sym->setOffset(address);
1395    }
1396    return sym;
1397 }
1398
1399 static inline uint8_t
1400 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1401 {
1402    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1403
1404    if (var->flat)
1405       mode = NV50_IR_INTERP_FLAT;
1406    else
1407    if (var->linear)
1408       mode = NV50_IR_INTERP_LINEAR;
1409    else
1410    if (var->sc)
1411       mode = NV50_IR_INTERP_SC;
1412
1413    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1414       ? OP_PINTERP : OP_LINTERP;
1415
1416    if (var->centroid)
1417       mode |= NV50_IR_INTERP_CENTROID;
1418
1419    return mode;
1420 }
1421
1422 Value *
1423 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1424 {
1425    operation op;
1426
1427    // XXX: no way to know interpolation mode if we don't know what's accessed
1428    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1429                                                       src.getIndex(0)], op);
1430
1431    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1432
1433    insn->setDef(0, getScratch());
1434    insn->setSrc(0, srcToSym(src, c));
1435    if (op == OP_PINTERP)
1436       insn->setSrc(1, fragCoord[3]);
1437    if (ptr)
1438       insn->setIndirect(0, 0, ptr);
1439
1440    insn->setInterpolate(mode);
1441
1442    bb->insertTail(insn);
1443    return insn->getDef(0);
1444 }
1445
1446 Value *
1447 Converter::applySrcMod(Value *val, int s, int c)
1448 {
1449    Modifier m = tgsi.getSrc(s).getMod(c);
1450    DataType ty = tgsi.inferSrcType();
1451
1452    if (m & Modifier(NV50_IR_MOD_ABS))
1453       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1454
1455    if (m & Modifier(NV50_IR_MOD_NEG))
1456       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1457
1458    return val;
1459 }
1460
1461 Value *
1462 Converter::getVertexBase(int s)
1463 {
1464    assert(s < 5);
1465    if (!(vtxBaseValid & (1 << s))) {
1466       const int index = tgsi.getSrc(s).getIndex(1);
1467       Value *rel = NULL;
1468       if (tgsi.getSrc(s).isIndirect(1))
1469          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1470       vtxBaseValid |= 1 << s;
1471       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1472                           mkImm(index), rel);
1473    }
1474    return vtxBase[s];
1475 }
1476
1477 Value *
1478 Converter::fetchSrc(int s, int c)
1479 {
1480    Value *res;
1481    Value *ptr = NULL, *dimRel = NULL;
1482
1483    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1484
1485    if (src.isIndirect(0))
1486       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1487
1488    if (src.is2D()) {
1489       switch (src.getFile()) {
1490       case TGSI_FILE_INPUT:
1491          dimRel = getVertexBase(s);
1492          break;
1493       case TGSI_FILE_CONSTANT:
1494          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1495          if (src.isIndirect(1))
1496             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1497          break;
1498       default:
1499          break;
1500       }
1501    }
1502
1503    res = fetchSrc(src, c, ptr);
1504
1505    if (dimRel)
1506       res->getInsn()->setIndirect(0, 1, dimRel);
1507
1508    return applySrcMod(res, s, c);
1509 }
1510
1511 Converter::DataArray *
1512 Converter::getArrayForFile(unsigned file, int idx)
1513 {
1514    switch (file) {
1515    case TGSI_FILE_TEMPORARY:
1516       return &tData;
1517    case TGSI_FILE_PREDICATE:
1518       return &pData;
1519    case TGSI_FILE_ADDRESS:
1520       return &aData;
1521    case TGSI_FILE_OUTPUT:
1522       assert(prog->getType() == Program::TYPE_FRAGMENT);
1523       return &oData;
1524    default:
1525       assert(!"invalid/unhandled TGSI source file");
1526       return NULL;
1527    }
1528 }
1529
1530 Value *
1531 Converter::shiftAddress(Value *index)
1532 {
1533    if (!index)
1534       return NULL;
1535    return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1536 }
1537
1538 Value *
1539 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1540 {
1541    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1542    const int idx = src.getIndex(0);
1543    const int swz = src.getSwizzle(c);
1544
1545    switch (src.getFile()) {
1546    case TGSI_FILE_IMMEDIATE:
1547       assert(!ptr);
1548       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1549    case TGSI_FILE_CONSTANT:
1550       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1551    case TGSI_FILE_INPUT:
1552       if (prog->getType() == Program::TYPE_FRAGMENT) {
1553          // don't load masked inputs, won't be assigned a slot
1554          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1555             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1556          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1557             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1558          return interpolate(src, c, shiftAddress(ptr));
1559       } else
1560       if (prog->getType() == Program::TYPE_GEOMETRY) {
1561          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1562             return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1563          // XXX: This is going to be a problem with scalar arrays, i.e. when
1564          // we cannot assume that the address is given in units of vec4.
1565          //
1566          // nv50 and nvc0 need different things here, so let the lowering
1567          // passes decide what to do with the address
1568          if (ptr)
1569             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1570       }
1571       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1572    case TGSI_FILE_OUTPUT:
1573       assert(!"load from output file");
1574       return NULL;
1575    case TGSI_FILE_SYSTEM_VALUE:
1576       assert(!ptr);
1577       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1578    default:
1579       return getArrayForFile(src.getFile(), idx2d)->load(
1580          sub.cur->values, idx, swz, shiftAddress(ptr));
1581    }
1582 }
1583
1584 Value *
1585 Converter::acquireDst(int d, int c)
1586 {
1587    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1588    const unsigned f = dst.getFile();
1589    const int idx = dst.getIndex(0);
1590    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1591
1592    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1593       return NULL;
1594
1595    if (dst.isIndirect(0) ||
1596        f == TGSI_FILE_SYSTEM_VALUE ||
1597        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1598       return getScratch();
1599
1600    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1601 }
1602
1603 void
1604 Converter::storeDst(int d, int c, Value *val)
1605 {
1606    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1607
1608    if (tgsi.getSaturate()) {
1609       mkOp1(OP_SAT, dstTy, val, val);
1610    }
1611
1612    Value *ptr = NULL;
1613    if (dst.isIndirect(0))
1614       ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1615
1616    if (info->io.genUserClip > 0 &&
1617        dst.getFile() == TGSI_FILE_OUTPUT &&
1618        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1619       mkMov(clipVtx[c], val);
1620       val = clipVtx[c];
1621    }
1622
1623    storeDst(dst, c, val, ptr);
1624 }
1625
1626 void
1627 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1628                     Value *val, Value *ptr)
1629 {
1630    const unsigned f = dst.getFile();
1631    const int idx = dst.getIndex(0);
1632    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1633
1634    if (f == TGSI_FILE_SYSTEM_VALUE) {
1635       assert(!ptr);
1636       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1637    } else
1638    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1639
1640       if (ptr || (info->out[idx].mask & (1 << c))) {
1641          /* Save the viewport index into a scratch register so that it can be
1642             exported at EMIT time */
1643          if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
1644              viewport != NULL)
1645             mkOp1(OP_MOV, TYPE_U32, viewport, val);
1646          else
1647             mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1648       }
1649    } else
1650    if (f == TGSI_FILE_TEMPORARY ||
1651        f == TGSI_FILE_PREDICATE ||
1652        f == TGSI_FILE_ADDRESS ||
1653        f == TGSI_FILE_OUTPUT) {
1654       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1655    } else {
1656       assert(!"invalid dst file");
1657    }
1658 }
1659
1660 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1661    for (chan = 0; chan < 4; ++chan)                 \
1662       if (!inst.getDst(d).isMasked(chan))
1663
1664 Value *
1665 Converter::buildDot(int dim)
1666 {
1667    assert(dim > 0);
1668
1669    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1670    Value *dotp = getScratch();
1671
1672    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1673
1674    for (int c = 1; c < dim; ++c) {
1675       src0 = fetchSrc(0, c);
1676       src1 = fetchSrc(1, c);
1677       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1678    }
1679    return dotp;
1680 }
1681
1682 void
1683 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1684 {
1685    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1686    join->fixed = 1;
1687    conv->insertHead(join);
1688
1689    assert(!fork->joinAt);
1690    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1691    fork->insertBefore(fork->getExit(), fork->joinAt);
1692 }
1693
1694 void
1695 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1696 {
1697    unsigned rIdx = 0, sIdx = 0;
1698
1699    if (R >= 0)
1700       rIdx = tgsi.getSrc(R).getIndex(0);
1701    if (S >= 0)
1702       sIdx = tgsi.getSrc(S).getIndex(0);
1703
1704    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1705
1706    if (tgsi.getSrc(R).isIndirect(0)) {
1707       tex->tex.rIndirectSrc = s;
1708       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1709    }
1710    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1711       tex->tex.sIndirectSrc = s;
1712       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1713    }
1714 }
1715
1716 void
1717 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1718 {
1719    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1720    tex->tex.query = query;
1721    unsigned int c, d;
1722
1723    for (d = 0, c = 0; c < 4; ++c) {
1724       if (!dst0[c])
1725          continue;
1726       tex->tex.mask |= 1 << c;
1727       tex->setDef(d++, dst0[c]);
1728    }
1729    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1730
1731    setTexRS(tex, ++c, 1, -1);
1732
1733    bb->insertTail(tex);
1734 }
1735
1736 void
1737 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1738 {
1739    Value *proj = fetchSrc(0, 3);
1740    Instruction *insn = proj->getUniqueInsn();
1741    int c;
1742
1743    if (insn->op == OP_PINTERP) {
1744       bb->insertTail(insn = cloneForward(func, insn));
1745       insn->op = OP_LINTERP;
1746       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1747       insn->setSrc(1, NULL);
1748       proj = insn->getDef(0);
1749    }
1750    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1751
1752    for (c = 0; c < 4; ++c) {
1753       if (!(mask & (1 << c)))
1754          continue;
1755       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1756          continue;
1757       mask &= ~(1 << c);
1758
1759       bb->insertTail(insn = cloneForward(func, insn));
1760       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1761       insn->setSrc(1, proj);
1762       dst[c] = insn->getDef(0);
1763    }
1764    if (!mask)
1765       return;
1766
1767    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1768
1769    for (c = 0; c < 4; ++c)
1770       if (mask & (1 << c))
1771          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1772 }
1773
1774 // order of nv50 ir sources: x y z layer lod/bias shadow
1775 // order of TGSI TEX sources: x y z layer shadow lod/bias
1776 //  lowering will finally set the hw specific order (like array first on nvc0)
1777 void
1778 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1779 {
1780    Value *val;
1781    Value *arg[4], *src[8];
1782    Value *lod = NULL, *shd = NULL;
1783    unsigned int s, c, d;
1784    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1785
1786    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1787
1788    for (s = 0; s < tgt.getArgCount(); ++s)
1789       arg[s] = src[s] = fetchSrc(0, s);
1790
1791    if (texi->op == OP_TXL || texi->op == OP_TXB)
1792       lod = fetchSrc(L >> 4, L & 3);
1793
1794    if (C == 0x0f)
1795       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1796
1797    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
1798        tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
1799       shd = fetchSrc(1, 0);
1800    else if (tgt.isShadow())
1801       shd = fetchSrc(C >> 4, C & 3);
1802
1803    if (texi->op == OP_TXD) {
1804       for (c = 0; c < tgt.getDim(); ++c) {
1805          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1806          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1807       }
1808    }
1809
1810    // cube textures don't care about projection value, it's divided out
1811    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1812       unsigned int n = tgt.getDim();
1813       if (shd) {
1814          arg[n] = shd;
1815          ++n;
1816          assert(tgt.getDim() == tgt.getArgCount());
1817       }
1818       loadProjTexCoords(src, arg, (1 << n) - 1);
1819       if (shd)
1820          shd = src[n - 1];
1821    }
1822
1823    if (tgt.isCube()) {
1824       for (c = 0; c < 3; ++c)
1825          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1826       val = getScratch();
1827       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1828       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1829       mkOp1(OP_RCP, TYPE_F32, val, val);
1830       for (c = 0; c < 3; ++c)
1831          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1832    }
1833
1834    for (c = 0, d = 0; c < 4; ++c) {
1835       if (dst[c]) {
1836          texi->setDef(d++, dst[c]);
1837          texi->tex.mask |= 1 << c;
1838       } else {
1839          // NOTE: maybe hook up def too, for CSE
1840       }
1841    }
1842    for (s = 0; s < tgt.getArgCount(); ++s)
1843       texi->setSrc(s, src[s]);
1844    if (lod)
1845       texi->setSrc(s++, lod);
1846    if (shd)
1847       texi->setSrc(s++, shd);
1848
1849    setTexRS(texi, s, R, S);
1850
1851    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1852       texi->tex.levelZero = true;
1853    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
1854       texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
1855
1856    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1857    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1858       for (c = 0; c < 3; ++c) {
1859          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1860          texi->offset[s][c].setInsn(texi);
1861       }
1862    }
1863
1864    bb->insertTail(texi);
1865 }
1866
1867 // 1st source: xyz = coordinates, w = lod/sample
1868 // 2nd source: offset
1869 void
1870 Converter::handleTXF(Value *dst[4], int R, int L_M)
1871 {
1872    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1873    int ms;
1874    unsigned int c, d, s;
1875
1876    texi->tex.target = tgsi.getTexture(code, R);
1877
1878    ms = texi->tex.target.isMS() ? 1 : 0;
1879    texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1880
1881    for (c = 0, d = 0; c < 4; ++c) {
1882       if (dst[c]) {
1883          texi->setDef(d++, dst[c]);
1884          texi->tex.mask |= 1 << c;
1885       }
1886    }
1887    for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1888       texi->setSrc(c, fetchSrc(0, c));
1889    texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1890
1891    setTexRS(texi, c, R, -1);
1892
1893    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1894    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1895       for (c = 0; c < 3; ++c) {
1896          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1897          texi->offset[s][c].setInsn(texi);
1898       }
1899    }
1900
1901    bb->insertTail(texi);
1902 }
1903
1904 void
1905 Converter::handleLIT(Value *dst0[4])
1906 {
1907    Value *val0 = NULL;
1908    unsigned int mask = tgsi.getDst(0).getMask();
1909
1910    if (mask & (1 << 0))
1911       loadImm(dst0[0], 1.0f);
1912
1913    if (mask & (1 << 3))
1914       loadImm(dst0[3], 1.0f);
1915
1916    if (mask & (3 << 1)) {
1917       val0 = getScratch();
1918       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1919       if (mask & (1 << 1))
1920          mkMov(dst0[1], val0);
1921    }
1922
1923    if (mask & (1 << 2)) {
1924       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1925       Value *val1 = getScratch(), *val3 = getScratch();
1926
1927       Value *pos128 = loadImm(NULL, +127.999999f);
1928       Value *neg128 = loadImm(NULL, -127.999999f);
1929
1930       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1931       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1932       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1933       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1934
1935       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
1936    }
1937 }
1938
1939 static inline bool
1940 isResourceSpecial(const int r)
1941 {
1942    return (r == TGSI_RESOURCE_GLOBAL ||
1943            r == TGSI_RESOURCE_LOCAL ||
1944            r == TGSI_RESOURCE_PRIVATE ||
1945            r == TGSI_RESOURCE_INPUT);
1946 }
1947
1948 static inline bool
1949 isResourceRaw(const tgsi::Source *code, const int r)
1950 {
1951    return isResourceSpecial(r) || code->resources[r].raw;
1952 }
1953
1954 static inline nv50_ir::TexTarget
1955 getResourceTarget(const tgsi::Source *code, int r)
1956 {
1957    if (isResourceSpecial(r))
1958       return nv50_ir::TEX_TARGET_BUFFER;
1959    return tgsi::translateTexture(code->resources.at(r).target);
1960 }
1961
1962 Symbol *
1963 Converter::getResourceBase(const int r)
1964 {
1965    Symbol *sym = NULL;
1966
1967    switch (r) {
1968    case TGSI_RESOURCE_GLOBAL:
1969       sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1970       break;
1971    case TGSI_RESOURCE_LOCAL:
1972       assert(prog->getType() == Program::TYPE_COMPUTE);
1973       sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1974                      info->prop.cp.sharedOffset);
1975       break;
1976    case TGSI_RESOURCE_PRIVATE:
1977       sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1978                      info->bin.tlsSpace);
1979       break;
1980    case TGSI_RESOURCE_INPUT:
1981       assert(prog->getType() == Program::TYPE_COMPUTE);
1982       sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1983                      info->prop.cp.inputOffset);
1984       break;
1985    default:
1986       sym = new_Symbol(prog,
1987                        nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1988       break;
1989    }
1990    return sym;
1991 }
1992
1993 void
1994 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
1995 {
1996    const int arg =
1997       TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
1998
1999    for (int c = 0; c < arg; ++c)
2000       coords.push_back(fetchSrc(s, c));
2001
2002    // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2003    if (r == TGSI_RESOURCE_LOCAL ||
2004        r == TGSI_RESOURCE_PRIVATE ||
2005        r == TGSI_RESOURCE_INPUT)
2006       coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2007                          coords[0]);
2008 }
2009
2010 static inline int
2011 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2012 {
2013    int n = 0;
2014
2015    while (mask) {
2016       if (mask & 1) {
2017          size[n]++;
2018       } else {
2019          if (size[n])
2020             comp[n = 1] = size[0] + 1;
2021          else
2022             comp[n]++;
2023       }
2024       mask >>= 1;
2025    }
2026    if (size[0] == 3) {
2027       n = 1;
2028       size[0] = (comp[0] == 1) ? 1 : 2;
2029       size[1] = 3 - size[0];
2030       comp[1] = comp[0] + size[0];
2031    }
2032    return n + 1;
2033 }
2034
2035 // For raw loads, granularity is 4 byte.
2036 // Usage of the texture read mask on OP_SULDP is not allowed.
2037 void
2038 Converter::handleLOAD(Value *dst0[4])
2039 {
2040    const int r = tgsi.getSrc(0).getIndex(0);
2041    int c;
2042    std::vector<Value *> off, src, ldv, def;
2043
2044    getResourceCoords(off, r, 1);
2045
2046    if (isResourceRaw(code, r)) {
2047       uint8_t mask = 0;
2048       uint8_t comp[2] = { 0, 0 };
2049       uint8_t size[2] = { 0, 0 };
2050
2051       Symbol *base = getResourceBase(r);
2052
2053       // determine the base and size of the at most 2 load ops
2054       for (c = 0; c < 4; ++c)
2055          if (!tgsi.getDst(0).isMasked(c))
2056             mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2057
2058       int n = partitionLoadStore(comp, size, mask);
2059
2060       src = off;
2061
2062       def.resize(4); // index by component, the ones we need will be non-NULL
2063       for (c = 0; c < 4; ++c) {
2064          if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2065             def[c] = dst0[c];
2066          else
2067          if (mask & (1 << c))
2068             def[c] = getScratch();
2069       }
2070
2071       const bool useLd = isResourceSpecial(r) ||
2072          (info->io.nv50styleSurfaces &&
2073           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2074
2075       for (int i = 0; i < n; ++i) {
2076          ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2077
2078          if (comp[i]) // adjust x component of source address if necessary
2079             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2080                             off[0], mkImm(comp[i] * 4));
2081          else
2082             src[0] = off[0];
2083
2084          if (useLd) {
2085             Instruction *ld =
2086                mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2087             for (size_t c = 1; c < ldv.size(); ++c)
2088                ld->setDef(c, ldv[c]);
2089          } else {
2090             mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2091                   0, ldv, src)->dType = typeOfSize(size[i] * 4);
2092          }
2093       }
2094    } else {
2095       def.resize(4);
2096       for (c = 0; c < 4; ++c) {
2097          if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2098             def[c] = getScratch();
2099          else
2100             def[c] = dst0[c];
2101       }
2102
2103       mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2104             def, off);
2105    }
2106    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2107       if (dst0[c] != def[c])
2108          mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2109 }
2110
2111 // For formatted stores, the write mask on OP_SUSTP can be used.
2112 // Raw stores have to be split.
2113 void
2114 Converter::handleSTORE()
2115 {
2116    const int r = tgsi.getDst(0).getIndex(0);
2117    int c;
2118    std::vector<Value *> off, src, dummy;
2119
2120    getResourceCoords(off, r, 0);
2121    src = off;
2122    const int s = src.size();
2123
2124    if (isResourceRaw(code, r)) {
2125       uint8_t comp[2] = { 0, 0 };
2126       uint8_t size[2] = { 0, 0 };
2127
2128       int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2129
2130       Symbol *base = getResourceBase(r);
2131
2132       const bool useSt = isResourceSpecial(r) ||
2133          (info->io.nv50styleSurfaces &&
2134           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2135
2136       for (int i = 0; i < n; ++i) {
2137          if (comp[i]) // adjust x component of source address if necessary
2138             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2139                             off[0], mkImm(comp[i] * 4));
2140          else
2141             src[0] = off[0];
2142
2143          const DataType stTy = typeOfSize(size[i] * 4);
2144
2145          if (useSt) {
2146             Instruction *st =
2147                mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2148             for (c = 1; c < size[i]; ++c)
2149                st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2150             st->setIndirect(0, 0, src[0]);
2151          } else {
2152             // attach values to be stored
2153             src.resize(s + size[i]);
2154             for (c = 0; c < size[i]; ++c)
2155                src[s + c] = fetchSrc(1, comp[i] + c);
2156             mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2157                   0, dummy, src)->setType(stTy);
2158          }
2159       }
2160    } else {
2161       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2162          src.push_back(fetchSrc(1, c));
2163
2164       mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2165             dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2166    }
2167 }
2168
2169 // XXX: These only work on resources with the single-component u32/s32 formats.
2170 // Therefore the result is replicated. This might not be intended by TGSI, but
2171 // operating on more than 1 component would produce undefined results because
2172 // they do not exist.
2173 void
2174 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2175 {
2176    const int r = tgsi.getSrc(0).getIndex(0);
2177    std::vector<Value *> srcv;
2178    std::vector<Value *> defv;
2179    LValue *dst = getScratch();
2180
2181    getResourceCoords(srcv, r, 1);
2182
2183    if (isResourceSpecial(r)) {
2184       assert(r != TGSI_RESOURCE_INPUT);
2185       Instruction *insn;
2186       insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2187       insn->subOp = subOp;
2188       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2189          insn->setSrc(2, fetchSrc(3, 0));
2190       insn->setIndirect(0, 0, srcv.at(0));
2191    } else {
2192       operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2193       TexTarget targ = getResourceTarget(code, r);
2194       int idx = code->resources[r].slot;
2195       defv.push_back(dst);
2196       srcv.push_back(fetchSrc(2, 0));
2197       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2198          srcv.push_back(fetchSrc(3, 0));
2199       TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2200       tex->subOp = subOp;
2201       tex->tex.mask = 1;
2202       tex->setType(ty);
2203    }
2204
2205    for (int c = 0; c < 4; ++c)
2206       if (dst0[c])
2207          dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2208 }
2209
2210 void
2211 Converter::handleINTERP(Value *dst[4])
2212 {
2213    // Check whether the input is linear. All other attributes ignored.
2214    Instruction *insn;
2215    Value *offset = NULL, *ptr = NULL, *w = NULL;
2216    bool linear;
2217    operation op;
2218    int c, mode;
2219
2220    tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2221    assert(src.getFile() == TGSI_FILE_INPUT);
2222
2223    if (src.isIndirect(0))
2224       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2225
2226    // XXX: no way to know interp mode if we don't know the index
2227    linear = info->in[ptr ? 0 : src.getIndex(0)].linear;
2228    if (linear) {
2229       op = OP_LINTERP;
2230       mode = NV50_IR_INTERP_LINEAR;
2231    } else {
2232       op = OP_PINTERP;
2233       mode = NV50_IR_INTERP_PERSPECTIVE;
2234    }
2235
2236    switch (tgsi.getOpcode()) {
2237    case TGSI_OPCODE_INTERP_CENTROID:
2238       mode |= NV50_IR_INTERP_CENTROID;
2239       break;
2240    case TGSI_OPCODE_INTERP_SAMPLE:
2241       insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2242       insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2243       mode |= NV50_IR_INTERP_OFFSET;
2244       break;
2245    case TGSI_OPCODE_INTERP_OFFSET: {
2246       // The input in src1.xy is float, but we need a single 32-bit value
2247       // where the upper and lower 16 bits are encoded in S0.12 format. We need
2248       // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2249       // and then convert to s32.
2250       Value *offs[2];
2251       for (c = 0; c < 2; c++) {
2252          offs[c] = fetchSrc(1, c);
2253          mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2254          mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2255          mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2256          mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2257       }
2258       offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2259                       offs[1], mkImm(0x1010), offs[0]);
2260       mode |= NV50_IR_INTERP_OFFSET;
2261       break;
2262    }
2263    }
2264
2265    if (op == OP_PINTERP) {
2266       if (offset) {
2267          w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2268          mkOp1(OP_RCP, TYPE_F32, w, w);
2269       } else {
2270          w = fragCoord[3];
2271       }
2272    }
2273
2274
2275    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2276       insn = mkOp1(op, TYPE_F32, dst[c], srcToSym(src, c));
2277       if (op == OP_PINTERP)
2278          insn->setSrc(1, w);
2279       if (ptr)
2280          insn->setIndirect(0, 0, ptr);
2281       if (offset)
2282          insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2283
2284       insn->setInterpolate(mode);
2285    }
2286 }
2287
2288 Converter::Subroutine *
2289 Converter::getSubroutine(unsigned ip)
2290 {
2291    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2292
2293    if (it == sub.map.end())
2294       it = sub.map.insert(std::make_pair(
2295               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2296
2297    return &it->second;
2298 }
2299
2300 Converter::Subroutine *
2301 Converter::getSubroutine(Function *f)
2302 {
2303    unsigned ip = f->getLabel();
2304    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2305
2306    if (it == sub.map.end())
2307       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2308
2309    return &it->second;
2310 }
2311
2312 bool
2313 Converter::isEndOfSubroutine(uint ip)
2314 {
2315    assert(ip < code->scan.num_instructions);
2316    tgsi::Instruction insn(&code->insns[ip]);
2317    return (insn.getOpcode() == TGSI_OPCODE_END ||
2318            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2319            // does END occur at end of main or the very end ?
2320            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2321 }
2322
2323 bool
2324 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2325 {
2326    Instruction *geni;
2327
2328    Value *dst0[4], *rDst0[4];
2329    Value *src0, *src1, *src2, *src3;
2330    Value *val0, *val1;
2331    int c;
2332
2333    tgsi = tgsi::Instruction(insn);
2334
2335    bool useScratchDst = tgsi.checkDstSrcAliasing();
2336
2337    operation op = tgsi.getOP();
2338    dstTy = tgsi.inferDstType();
2339    srcTy = tgsi.inferSrcType();
2340
2341    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2342
2343    if (tgsi.dstCount()) {
2344       for (c = 0; c < 4; ++c) {
2345          rDst0[c] = acquireDst(0, c);
2346          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2347       }
2348    }
2349
2350    switch (tgsi.getOpcode()) {
2351    case TGSI_OPCODE_ADD:
2352    case TGSI_OPCODE_UADD:
2353    case TGSI_OPCODE_AND:
2354    case TGSI_OPCODE_DIV:
2355    case TGSI_OPCODE_IDIV:
2356    case TGSI_OPCODE_UDIV:
2357    case TGSI_OPCODE_MAX:
2358    case TGSI_OPCODE_MIN:
2359    case TGSI_OPCODE_IMAX:
2360    case TGSI_OPCODE_IMIN:
2361    case TGSI_OPCODE_UMAX:
2362    case TGSI_OPCODE_UMIN:
2363    case TGSI_OPCODE_MOD:
2364    case TGSI_OPCODE_UMOD:
2365    case TGSI_OPCODE_MUL:
2366    case TGSI_OPCODE_UMUL:
2367    case TGSI_OPCODE_IMUL_HI:
2368    case TGSI_OPCODE_UMUL_HI:
2369    case TGSI_OPCODE_OR:
2370    case TGSI_OPCODE_SHL:
2371    case TGSI_OPCODE_ISHR:
2372    case TGSI_OPCODE_USHR:
2373    case TGSI_OPCODE_SUB:
2374    case TGSI_OPCODE_XOR:
2375       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2376          src0 = fetchSrc(0, c);
2377          src1 = fetchSrc(1, c);
2378          geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2379          geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2380       }
2381       break;
2382    case TGSI_OPCODE_MAD:
2383    case TGSI_OPCODE_UMAD:
2384    case TGSI_OPCODE_SAD:
2385       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2386          src0 = fetchSrc(0, c);
2387          src1 = fetchSrc(1, c);
2388          src2 = fetchSrc(2, c);
2389          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2390       }
2391       break;
2392    case TGSI_OPCODE_MOV:
2393    case TGSI_OPCODE_ABS:
2394    case TGSI_OPCODE_CEIL:
2395    case TGSI_OPCODE_FLR:
2396    case TGSI_OPCODE_TRUNC:
2397    case TGSI_OPCODE_RCP:
2398    case TGSI_OPCODE_IABS:
2399    case TGSI_OPCODE_INEG:
2400    case TGSI_OPCODE_NOT:
2401    case TGSI_OPCODE_DDX:
2402    case TGSI_OPCODE_DDY:
2403    case TGSI_OPCODE_DDX_FINE:
2404    case TGSI_OPCODE_DDY_FINE:
2405       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2406          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2407       break;
2408    case TGSI_OPCODE_RSQ:
2409       src0 = fetchSrc(0, 0);
2410       val0 = getScratch();
2411       mkOp1(OP_ABS, TYPE_F32, val0, src0);
2412       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2413       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2414          mkMov(dst0[c], val0);
2415       break;
2416    case TGSI_OPCODE_ARL:
2417    case TGSI_OPCODE_ARR:
2418       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2419          const RoundMode rnd =
2420             tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
2421          src0 = fetchSrc(0, c);
2422          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
2423       }
2424       break;
2425    case TGSI_OPCODE_UARL:
2426       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2427          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2428       break;
2429    case TGSI_OPCODE_POW:
2430       val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
2431       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2432          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2433       break;
2434    case TGSI_OPCODE_EX2:
2435    case TGSI_OPCODE_LG2:
2436       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2437       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2438          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2439       break;
2440    case TGSI_OPCODE_COS:
2441    case TGSI_OPCODE_SIN:
2442       val0 = getScratch();
2443       if (mask & 7) {
2444          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2445          mkOp1(op, TYPE_F32, val0, val0);
2446          for (c = 0; c < 3; ++c)
2447             if (dst0[c])
2448                mkMov(dst0[c], val0);
2449       }
2450       if (dst0[3]) {
2451          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2452          mkOp1(op, TYPE_F32, dst0[3], val0);
2453       }
2454       break;
2455    case TGSI_OPCODE_SCS:
2456       if (mask & 3) {
2457          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2458          if (dst0[0])
2459             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2460          if (dst0[1])
2461             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2462       }
2463       if (dst0[2])
2464          loadImm(dst0[2], 0.0f);
2465       if (dst0[3])
2466          loadImm(dst0[3], 1.0f);
2467       break;
2468    case TGSI_OPCODE_EXP:
2469       src0 = fetchSrc(0, 0);
2470       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2471       if (dst0[1])
2472          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2473       if (dst0[0])
2474          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2475       if (dst0[2])
2476          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2477       if (dst0[3])
2478          loadImm(dst0[3], 1.0f);
2479       break;
2480    case TGSI_OPCODE_LOG:
2481       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2482       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2483       if (dst0[0] || dst0[1])
2484          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2485       if (dst0[1]) {
2486          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2487          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2488          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2489       }
2490       if (dst0[3])
2491          loadImm(dst0[3], 1.0f);
2492       break;
2493    case TGSI_OPCODE_DP2:
2494       val0 = buildDot(2);
2495       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2496          mkMov(dst0[c], val0);
2497       break;
2498    case TGSI_OPCODE_DP3:
2499       val0 = buildDot(3);
2500       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2501          mkMov(dst0[c], val0);
2502       break;
2503    case TGSI_OPCODE_DP4:
2504       val0 = buildDot(4);
2505       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2506          mkMov(dst0[c], val0);
2507       break;
2508    case TGSI_OPCODE_DPH:
2509       val0 = buildDot(3);
2510       src1 = fetchSrc(1, 3);
2511       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2512       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2513          mkMov(dst0[c], val0);
2514       break;
2515    case TGSI_OPCODE_DST:
2516       if (dst0[0])
2517          loadImm(dst0[0], 1.0f);
2518       if (dst0[1]) {
2519          src0 = fetchSrc(0, 1);
2520          src1 = fetchSrc(1, 1);
2521          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2522       }
2523       if (dst0[2])
2524          mkMov(dst0[2], fetchSrc(0, 2));
2525       if (dst0[3])
2526          mkMov(dst0[3], fetchSrc(1, 3));
2527       break;
2528    case TGSI_OPCODE_LRP:
2529       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2530          src0 = fetchSrc(0, c);
2531          src1 = fetchSrc(1, c);
2532          src2 = fetchSrc(2, c);
2533          mkOp3(OP_MAD, TYPE_F32, dst0[c],
2534                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2535       }
2536       break;
2537    case TGSI_OPCODE_LIT:
2538       handleLIT(dst0);
2539       break;
2540    case TGSI_OPCODE_XPD:
2541       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2542          if (c < 3) {
2543             val0 = getSSA();
2544             src0 = fetchSrc(1, (c + 1) % 3);
2545             src1 = fetchSrc(0, (c + 2) % 3);
2546             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2547             mkOp1(OP_NEG, TYPE_F32, val0, val0);
2548
2549             src0 = fetchSrc(0, (c + 1) % 3);
2550             src1 = fetchSrc(1, (c + 2) % 3);
2551             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2552          } else {
2553             loadImm(dst0[c], 1.0f);
2554          }
2555       }
2556       break;
2557    case TGSI_OPCODE_ISSG:
2558    case TGSI_OPCODE_SSG:
2559       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2560          src0 = fetchSrc(0, c);
2561          val0 = getScratch();
2562          val1 = getScratch();
2563          mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2564          mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2565          if (srcTy == TYPE_F32)
2566             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2567          else
2568             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2569       }
2570       break;
2571    case TGSI_OPCODE_UCMP:
2572       srcTy = TYPE_U32;
2573       /* fallthrough */
2574    case TGSI_OPCODE_CMP:
2575       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2576          src0 = fetchSrc(0, c);
2577          src1 = fetchSrc(1, c);
2578          src2 = fetchSrc(2, c);
2579          if (src1 == src2)
2580             mkMov(dst0[c], src1);
2581          else
2582             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2583                   srcTy, dst0[c], srcTy, src1, src2, src0);
2584       }
2585       break;
2586    case TGSI_OPCODE_FRC:
2587       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2588          src0 = fetchSrc(0, c);
2589          val0 = getScratch();
2590          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2591          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2592       }
2593       break;
2594    case TGSI_OPCODE_ROUND:
2595       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2596          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2597          ->rnd = ROUND_NI;
2598       break;
2599    case TGSI_OPCODE_CLAMP:
2600       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2601          src0 = fetchSrc(0, c);
2602          src1 = fetchSrc(1, c);
2603          src2 = fetchSrc(2, c);
2604          val0 = getScratch();
2605          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2606          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2607       }
2608       break;
2609    case TGSI_OPCODE_SLT:
2610    case TGSI_OPCODE_SGE:
2611    case TGSI_OPCODE_SEQ:
2612    case TGSI_OPCODE_SGT:
2613    case TGSI_OPCODE_SLE:
2614    case TGSI_OPCODE_SNE:
2615    case TGSI_OPCODE_FSEQ:
2616    case TGSI_OPCODE_FSGE:
2617    case TGSI_OPCODE_FSLT:
2618    case TGSI_OPCODE_FSNE:
2619    case TGSI_OPCODE_ISGE:
2620    case TGSI_OPCODE_ISLT:
2621    case TGSI_OPCODE_USEQ:
2622    case TGSI_OPCODE_USGE:
2623    case TGSI_OPCODE_USLT:
2624    case TGSI_OPCODE_USNE:
2625       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2626          src0 = fetchSrc(0, c);
2627          src1 = fetchSrc(1, c);
2628          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2629       }
2630       break;
2631    case TGSI_OPCODE_KILL_IF:
2632       val0 = new_LValue(func, FILE_PREDICATE);
2633       mask = 0;
2634       for (c = 0; c < 4; ++c) {
2635          const int s = tgsi.getSrc(0).getSwizzle(c);
2636          if (mask & (1 << s))
2637             continue;
2638          mask |= 1 << s;
2639          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2640          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2641       }
2642       break;
2643    case TGSI_OPCODE_KILL:
2644       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2645       break;
2646    case TGSI_OPCODE_TEX:
2647    case TGSI_OPCODE_TXB:
2648    case TGSI_OPCODE_TXL:
2649    case TGSI_OPCODE_TXP:
2650    case TGSI_OPCODE_LODQ:
2651       //              R  S     L     C    Dx    Dy
2652       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2653       break;
2654    case TGSI_OPCODE_TXD:
2655       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2656       break;
2657    case TGSI_OPCODE_TG4:
2658       handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
2659       break;
2660    case TGSI_OPCODE_TEX2:
2661       handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2662       break;
2663    case TGSI_OPCODE_TXB2:
2664    case TGSI_OPCODE_TXL2:
2665       handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
2666       break;
2667    case TGSI_OPCODE_SAMPLE:
2668    case TGSI_OPCODE_SAMPLE_B:
2669    case TGSI_OPCODE_SAMPLE_D:
2670    case TGSI_OPCODE_SAMPLE_L:
2671    case TGSI_OPCODE_SAMPLE_C:
2672    case TGSI_OPCODE_SAMPLE_C_LZ:
2673       handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2674       break;
2675    case TGSI_OPCODE_TXF:
2676       handleTXF(dst0, 1, 0x03);
2677       break;
2678    case TGSI_OPCODE_SAMPLE_I:
2679       handleTXF(dst0, 1, 0x03);
2680       break;
2681    case TGSI_OPCODE_SAMPLE_I_MS:
2682       handleTXF(dst0, 1, 0x20);
2683       break;
2684    case TGSI_OPCODE_TXQ:
2685    case TGSI_OPCODE_SVIEWINFO:
2686       handleTXQ(dst0, TXQ_DIMS);
2687       break;
2688    case TGSI_OPCODE_F2I:
2689    case TGSI_OPCODE_F2U:
2690       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2691          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2692       break;
2693    case TGSI_OPCODE_I2F:
2694    case TGSI_OPCODE_U2F:
2695       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2696          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2697       break;
2698    case TGSI_OPCODE_EMIT:
2699       /* export the saved viewport index */
2700       if (viewport != NULL) {
2701          Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
2702                                   info->out[info->io.viewportId].slot[0] * 4);
2703          mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
2704       }
2705       /* fallthrough */
2706    case TGSI_OPCODE_ENDPRIM:
2707    {
2708       // get vertex stream (must be immediate)
2709       unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
2710       if (stream && op == OP_RESTART)
2711          break;
2712       src0 = mkImm(stream);
2713       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2714       break;
2715    }
2716    case TGSI_OPCODE_IF:
2717    case TGSI_OPCODE_UIF:
2718    {
2719       BasicBlock *ifBB = new BasicBlock(func);
2720
2721       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2722       condBBs.push(bb);
2723       joinBBs.push(bb);
2724
2725       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2726
2727       setPosition(ifBB, true);
2728    }
2729       break;
2730    case TGSI_OPCODE_ELSE:
2731    {
2732       BasicBlock *elseBB = new BasicBlock(func);
2733       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2734
2735       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2736       condBBs.push(bb);
2737
2738       forkBB->getExit()->asFlow()->target.bb = elseBB;
2739       if (!bb->isTerminated())
2740          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2741
2742       setPosition(elseBB, true);
2743    }
2744       break;
2745    case TGSI_OPCODE_ENDIF:
2746    {
2747       BasicBlock *convBB = new BasicBlock(func);
2748       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2749       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2750
2751       if (!bb->isTerminated()) {
2752          // we only want join if none of the clauses ended with CONT/BREAK/RET
2753          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2754             insertConvergenceOps(convBB, forkBB);
2755          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2756          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2757       }
2758
2759       if (prevBB->getExit()->op == OP_BRA) {
2760          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2761          prevBB->getExit()->asFlow()->target.bb = convBB;
2762       }
2763       setPosition(convBB, true);
2764    }
2765       break;
2766    case TGSI_OPCODE_BGNLOOP:
2767    {
2768       BasicBlock *lbgnBB = new BasicBlock(func);
2769       BasicBlock *lbrkBB = new BasicBlock(func);
2770
2771       loopBBs.push(lbgnBB);
2772       breakBBs.push(lbrkBB);
2773       if (loopBBs.getSize() > func->loopNestingBound)
2774          func->loopNestingBound++;
2775
2776       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2777
2778       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2779       setPosition(lbgnBB, true);
2780       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2781    }
2782       break;
2783    case TGSI_OPCODE_ENDLOOP:
2784    {
2785       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2786
2787       if (!bb->isTerminated()) {
2788          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2789          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2790       }
2791       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2792    }
2793       break;
2794    case TGSI_OPCODE_BRK:
2795    {
2796       if (bb->isTerminated())
2797          break;
2798       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2799       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2800       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2801    }
2802       break;
2803    case TGSI_OPCODE_CONT:
2804    {
2805       if (bb->isTerminated())
2806          break;
2807       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2808       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2809       contBB->explicitCont = true;
2810       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2811    }
2812       break;
2813    case TGSI_OPCODE_BGNSUB:
2814    {
2815       Subroutine *s = getSubroutine(ip);
2816       BasicBlock *entry = new BasicBlock(s->f);
2817       BasicBlock *leave = new BasicBlock(s->f);
2818
2819       // multiple entrypoints possible, keep the graph connected
2820       if (prog->getType() == Program::TYPE_COMPUTE)
2821          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2822
2823       sub.cur = s;
2824       s->f->setEntry(entry);
2825       s->f->setExit(leave);
2826       setPosition(entry, true);
2827       return true;
2828    }
2829    case TGSI_OPCODE_ENDSUB:
2830    {
2831       sub.cur = getSubroutine(prog->main);
2832       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2833       return true;
2834    }
2835    case TGSI_OPCODE_CAL:
2836    {
2837       Subroutine *s = getSubroutine(tgsi.getLabel());
2838       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2839       func->call.attach(&s->f->call, Graph::Edge::TREE);
2840       return true;
2841    }
2842    case TGSI_OPCODE_RET:
2843    {
2844       if (bb->isTerminated())
2845          return true;
2846       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2847
2848       if (!isEndOfSubroutine(ip + 1)) {
2849          // insert a PRERET at the entry if this is an early return
2850          // (only needed for sharing code in the epilogue)
2851          BasicBlock *pos = getBB();
2852          setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2853          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2854          setPosition(pos, true);
2855       }
2856       mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2857       bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2858    }
2859       break;
2860    case TGSI_OPCODE_END:
2861    {
2862       // attach and generate epilogue code
2863       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2864       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2865       setPosition(epilogue, true);
2866       if (prog->getType() == Program::TYPE_FRAGMENT)
2867          exportOutputs();
2868       if (info->io.genUserClip > 0)
2869          handleUserClipPlanes();
2870       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2871    }
2872       break;
2873    case TGSI_OPCODE_SWITCH:
2874    case TGSI_OPCODE_CASE:
2875       ERROR("switch/case opcode encountered, should have been lowered\n");
2876       abort();
2877       break;
2878    case TGSI_OPCODE_LOAD:
2879       handleLOAD(dst0);
2880       break;
2881    case TGSI_OPCODE_STORE:
2882       handleSTORE();
2883       break;
2884    case TGSI_OPCODE_BARRIER:
2885       geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2886       geni->fixed = 1;
2887       geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2888       break;
2889    case TGSI_OPCODE_MFENCE:
2890    case TGSI_OPCODE_LFENCE:
2891    case TGSI_OPCODE_SFENCE:
2892       geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2893       geni->fixed = 1;
2894       geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2895       break;
2896    case TGSI_OPCODE_ATOMUADD:
2897    case TGSI_OPCODE_ATOMXCHG:
2898    case TGSI_OPCODE_ATOMCAS:
2899    case TGSI_OPCODE_ATOMAND:
2900    case TGSI_OPCODE_ATOMOR:
2901    case TGSI_OPCODE_ATOMXOR:
2902    case TGSI_OPCODE_ATOMUMIN:
2903    case TGSI_OPCODE_ATOMIMIN:
2904    case TGSI_OPCODE_ATOMUMAX:
2905    case TGSI_OPCODE_ATOMIMAX:
2906       handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2907       break;
2908    case TGSI_OPCODE_IBFE:
2909    case TGSI_OPCODE_UBFE:
2910       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2911          src0 = fetchSrc(0, c);
2912          src1 = fetchSrc(1, c);
2913          src2 = fetchSrc(2, c);
2914          mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
2915          mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
2916       }
2917       break;
2918    case TGSI_OPCODE_BFI:
2919       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2920          src0 = fetchSrc(0, c);
2921          src1 = fetchSrc(1, c);
2922          src2 = fetchSrc(2, c);
2923          src3 = fetchSrc(3, c);
2924          mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
2925          mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
2926       }
2927       break;
2928    case TGSI_OPCODE_LSB:
2929       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2930          src0 = fetchSrc(0, c);
2931          geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
2932          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2933          geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
2934          geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2935       }
2936       break;
2937    case TGSI_OPCODE_IMSB:
2938    case TGSI_OPCODE_UMSB:
2939       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2940          src0 = fetchSrc(0, c);
2941          mkOp1(OP_BFIND, srcTy, dst0[c], src0);
2942       }
2943       break;
2944    case TGSI_OPCODE_BREV:
2945       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2946          src0 = fetchSrc(0, c);
2947          geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
2948          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2949       }
2950       break;
2951    case TGSI_OPCODE_POPC:
2952       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2953          src0 = fetchSrc(0, c);
2954          mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
2955       }
2956       break;
2957    case TGSI_OPCODE_INTERP_CENTROID:
2958    case TGSI_OPCODE_INTERP_SAMPLE:
2959    case TGSI_OPCODE_INTERP_OFFSET:
2960       handleINTERP(dst0);
2961       break;
2962    case TGSI_OPCODE_D2I:
2963    case TGSI_OPCODE_D2U:
2964    case TGSI_OPCODE_D2F: {
2965       int pos = 0;
2966       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2967          Value *dreg = getSSA(8);
2968          src0 = fetchSrc(0, pos);
2969          src1 = fetchSrc(0, pos + 1);
2970          mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
2971          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
2972          pos += 2;
2973       }
2974       break;
2975    }
2976    case TGSI_OPCODE_I2D:
2977    case TGSI_OPCODE_U2D:
2978    case TGSI_OPCODE_F2D:
2979       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2980          Value *dreg = getSSA(8);
2981          mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
2982          mkSplit(&dst0[c], 4, dreg);
2983          c++;
2984       }
2985       break;
2986    case TGSI_OPCODE_DABS:
2987    case TGSI_OPCODE_DNEG:
2988    case TGSI_OPCODE_DRCP:
2989    case TGSI_OPCODE_DSQRT:
2990    case TGSI_OPCODE_DRSQ:
2991    case TGSI_OPCODE_DTRUNC:
2992    case TGSI_OPCODE_DCEIL:
2993    case TGSI_OPCODE_DFLR:
2994       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2995          src0 = getSSA(8);
2996          Value *dst = getSSA(8), *tmp[2];
2997          tmp[0] = fetchSrc(0, c);
2998          tmp[1] = fetchSrc(0, c + 1);
2999          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3000          mkOp1(op, dstTy, dst, src0);
3001          mkSplit(&dst0[c], 4, dst);
3002          c++;
3003       }
3004       break;
3005    case TGSI_OPCODE_DFRAC:
3006       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3007          src0 = getSSA(8);
3008          Value *dst = getSSA(8), *tmp[2];
3009          tmp[0] = fetchSrc(0, c);
3010          tmp[1] = fetchSrc(0, c + 1);
3011          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3012          mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3013          mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3014          mkSplit(&dst0[c], 4, dst);
3015          c++;
3016       }
3017       break;
3018    case TGSI_OPCODE_DSLT:
3019    case TGSI_OPCODE_DSGE:
3020    case TGSI_OPCODE_DSEQ:
3021    case TGSI_OPCODE_DSNE: {
3022       int pos = 0;
3023       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3024          Value *tmp[2];
3025
3026          src0 = getSSA(8);
3027          src1 = getSSA(8);
3028          tmp[0] = fetchSrc(0, pos);
3029          tmp[1] = fetchSrc(0, pos + 1);
3030          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3031          tmp[0] = fetchSrc(1, pos);
3032          tmp[1] = fetchSrc(1, pos + 1);
3033          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3034          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3035          pos += 2;
3036       }
3037       break;
3038    }
3039    case TGSI_OPCODE_DADD:
3040    case TGSI_OPCODE_DMUL:
3041    case TGSI_OPCODE_DMAX:
3042    case TGSI_OPCODE_DMIN:
3043       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3044          src0 = getSSA(8);
3045          src1 = getSSA(8);
3046          Value *dst = getSSA(8), *tmp[2];
3047          tmp[0] = fetchSrc(0, c);
3048          tmp[1] = fetchSrc(0, c + 1);
3049          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3050          tmp[0] = fetchSrc(1, c);
3051          tmp[1] = fetchSrc(1, c + 1);
3052          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3053          mkOp2(op, dstTy, dst, src0, src1);
3054          mkSplit(&dst0[c], 4, dst);
3055          c++;
3056       }
3057       break;
3058    case TGSI_OPCODE_DMAD:
3059       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3060          src0 = getSSA(8);
3061          src1 = getSSA(8);
3062          src2 = getSSA(8);
3063          Value *dst = getSSA(8), *tmp[2];
3064          tmp[0] = fetchSrc(0, c);
3065          tmp[1] = fetchSrc(0, c + 1);
3066          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3067          tmp[0] = fetchSrc(1, c);
3068          tmp[1] = fetchSrc(1, c + 1);
3069          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3070          tmp[0] = fetchSrc(2, c);
3071          tmp[1] = fetchSrc(2, c + 1);
3072          mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3073          mkOp3(op, dstTy, dst, src0, src1, src2);
3074          mkSplit(&dst0[c], 4, dst);
3075          c++;
3076       }
3077       break;
3078    case TGSI_OPCODE_DROUND:
3079       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3080          src0 = getSSA(8);
3081          Value *dst = getSSA(8), *tmp[2];
3082          tmp[0] = fetchSrc(0, c);
3083          tmp[1] = fetchSrc(0, c + 1);
3084          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3085          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3086          ->rnd = ROUND_NI;
3087          mkSplit(&dst0[c], 4, dst);
3088          c++;
3089       }
3090       break;
3091    case TGSI_OPCODE_DSSG:
3092       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3093          src0 = getSSA(8);
3094          Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3095          tmp[0] = fetchSrc(0, c);
3096          tmp[1] = fetchSrc(0, c + 1);
3097          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3098
3099          val0 = getScratch();
3100          val1 = getScratch();
3101          // The zero is wrong here since it's only 32-bit, but it works out in
3102          // the end since it gets replaced with $r63.
3103          mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3104          mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3105          mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3106          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3107          mkSplit(&dst0[c], 4, dst);
3108          c++;
3109       }
3110       break;
3111    default:
3112       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3113       assert(0);
3114       break;
3115    }
3116
3117    if (tgsi.dstCount()) {
3118       for (c = 0; c < 4; ++c) {
3119          if (!dst0[c])
3120             continue;
3121          if (dst0[c] != rDst0[c])
3122             mkMov(rDst0[c], dst0[c]);
3123          storeDst(0, c, rDst0[c]);
3124       }
3125    }
3126    vtxBaseValid = 0;
3127
3128    return true;
3129 }
3130
3131 void
3132 Converter::handleUserClipPlanes()
3133 {
3134    Value *res[8];
3135    int n, i, c;
3136
3137    for (c = 0; c < 4; ++c) {
3138       for (i = 0; i < info->io.genUserClip; ++i) {
3139          Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
3140                                 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3141          Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3142          if (c == 0)
3143             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3144          else
3145             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3146       }
3147    }
3148
3149    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3150
3151    for (i = 0; i < info->io.genUserClip; ++i) {
3152       n = i / 4 + first;
3153       c = i % 4;
3154       Symbol *sym =
3155          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3156       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3157    }
3158 }
3159
3160 void
3161 Converter::exportOutputs()
3162 {
3163    for (unsigned int i = 0; i < info->numOutputs; ++i) {
3164       for (unsigned int c = 0; c < 4; ++c) {
3165          if (!oData.exists(sub.cur->values, i, c))
3166             continue;
3167          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3168                                 info->out[i].slot[c] * 4);
3169          Value *val = oData.load(sub.cur->values, i, c, NULL);
3170          if (val)
3171             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3172       }
3173    }
3174 }
3175
3176 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3177      code(code),
3178      tgsi(NULL),
3179      tData(this), aData(this), pData(this), oData(this)
3180 {
3181    info = code->info;
3182
3183    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
3184
3185    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3186    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3187    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3188    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3189
3190    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
3191    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3192    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3193    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3194
3195    zero = mkImm((uint32_t)0);
3196
3197    vtxBaseValid = 0;
3198 }
3199
3200 Converter::~Converter()
3201 {
3202 }
3203
3204 inline const Converter::Location *
3205 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3206 {
3207    ValueMap::l_iterator it = s->values.l.find(v);
3208    return it == s->values.l.end() ? NULL : &it->second;
3209 }
3210
3211 template<typename T> inline void
3212 Converter::BindArgumentsPass::updateCallArgs(
3213    Instruction *i, void (Instruction::*setArg)(int, Value *),
3214    T (Function::*proto))
3215 {
3216    Function *g = i->asFlow()->target.fn;
3217    Subroutine *subg = conv.getSubroutine(g);
3218
3219    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3220       Value *v = (g->*proto)[a].get();
3221       const Converter::Location &l = *getValueLocation(subg, v);
3222       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3223
3224       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3225    }
3226 }
3227
3228 template<typename T> inline void
3229 Converter::BindArgumentsPass::updatePrototype(
3230    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3231 {
3232    (func->*updateSet)();
3233
3234    for (unsigned i = 0; i < set->getSize(); ++i) {
3235       Value *v = func->getLValue(i);
3236       const Converter::Location *l = getValueLocation(sub, v);
3237
3238       // only include values with a matching TGSI register
3239       if (set->test(i) && l && !conv.code->locals.count(*l))
3240          (func->*proto).push_back(v);
3241    }
3242 }
3243
3244 bool
3245 Converter::BindArgumentsPass::visit(Function *f)
3246 {
3247    sub = conv.getSubroutine(f);
3248
3249    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3250         !bi.end(); bi.next()) {
3251       for (Instruction *i = BasicBlock::get(bi)->getFirst();
3252            i; i = i->next) {
3253          if (i->op == OP_CALL && !i->asFlow()->builtin) {
3254             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3255             updateCallArgs(i, &Instruction::setDef, &Function::outs);
3256          }
3257       }
3258    }
3259
3260    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3261       return true;
3262    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3263                    &Function::buildLiveSets, &Function::ins);
3264    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3265                    &Function::buildDefSets, &Function::outs);
3266
3267    return true;
3268 }
3269
3270 bool
3271 Converter::run()
3272 {
3273    BasicBlock *entry = new BasicBlock(prog->main);
3274    BasicBlock *leave = new BasicBlock(prog->main);
3275
3276    prog->main->setEntry(entry);
3277    prog->main->setExit(leave);
3278
3279    setPosition(entry, true);
3280    sub.cur = getSubroutine(prog->main);
3281
3282    if (info->io.genUserClip > 0) {
3283       for (int c = 0; c < 4; ++c)
3284          clipVtx[c] = getScratch();
3285    }
3286
3287    if (prog->getType() == Program::TYPE_FRAGMENT) {
3288       Symbol *sv = mkSysVal(SV_POSITION, 3);
3289       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
3290       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
3291    }
3292
3293    if (info->io.viewportId >= 0)
3294       viewport = getScratch();
3295    else
3296       viewport = NULL;
3297
3298    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
3299       if (!handleInstruction(&code->insns[ip]))
3300          return false;
3301    }
3302
3303    if (!BindArgumentsPass(*this).run(prog))
3304       return false;
3305
3306    return true;
3307 }
3308
3309 } // unnamed namespace
3310
3311 namespace nv50_ir {
3312
3313 bool
3314 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
3315 {
3316    tgsi::Source src(info);
3317    if (!src.scanSource())
3318       return false;
3319    tlsSize = info->bin.tlsSpace;
3320
3321    Converter builder(this, &src);
3322    return builder.run();
3323 }
3324
3325 } // namespace nv50_ir