src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 extern "C" {
  24 #include "tgsi/tgsi_dump.h"
  25 #include "tgsi/tgsi_scan.h"
  26 #include "tgsi/tgsi_util.h"
  27 }
  28
  29 #include <set>
  30
  31 #include "codegen/nv50_ir.h"
  32 #include "codegen/nv50_ir_util.h"
  33 #include "codegen/nv50_ir_build_util.h"
  34
  35 namespace tgsi {
  36
  37 class Source;
  38
  39 static nv50_ir::operation translateOpcode(uint opcode);
  40 static nv50_ir::DataFile translateFile(uint file);
  41 static nv50_ir::TexTarget translateTexture(uint texTarg);
  42 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  43
  44 class Instruction
  45 {
  46 public:
  47    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  48
  49    class SrcRegister
  50    {
  51    public:
  52       SrcRegister(const struct tgsi_full_src_register *src)
  53          : reg(src->Register),
  54            fsr(src)
  55       { }
  56
  57       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  58
  59       SrcRegister(const struct tgsi_ind_register& ind)
  60          : reg(tgsi_util_get_src_from_ind(&ind)),
  61            fsr(NULL)
  62       { }
  63
  64       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  65       {
  66          struct tgsi_src_register reg;
  67          memset(&reg, 0, sizeof(reg));
  68          reg.Index = off.Index;
  69          reg.File = off.File;
  70          reg.SwizzleX = off.SwizzleX;
  71          reg.SwizzleY = off.SwizzleY;
  72          reg.SwizzleZ = off.SwizzleZ;
  73          return reg;
  74       }
  75
  76       SrcRegister(const struct tgsi_texture_offset& off) :
  77          reg(offsetToSrc(off)),
  78          fsr(NULL)
  79       { }
  80
  81       uint getFile() const { return reg.File; }
  82
  83       bool is2D() const { return reg.Dimension; }
  84
  85       bool isIndirect(int dim) const
  86       {
  87          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  88       }
  89
  90       int getIndex(int dim) const
  91       {
  92          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  93       }
  94
  95       int getSwizzle(int chan) const
  96       {
  97          return tgsi_util_get_src_register_swizzle(&reg, chan);
  98       }
  99
 100       nv50_ir::Modifier getMod(int chan) const;
 101
 102       SrcRegister getIndirect(int dim) const
 103       {
 104          assert(fsr && isIndirect(dim));
 105          if (dim)
 106             return SrcRegister(fsr->DimIndirect);
 107          return SrcRegister(fsr->Indirect);
 108       }
 109
 110       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 111       {
 112          assert(reg.File == TGSI_FILE_IMMEDIATE);
 113          assert(!reg.Absolute);
 114          assert(!reg.Negate);
 115          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 116       }
 117
 118    private:
 119       const struct tgsi_src_register reg;
 120       const struct tgsi_full_src_register *fsr;
 121    };
 122
 123    class DstRegister
 124    {
 125    public:
 126       DstRegister(const struct tgsi_full_dst_register *dst)
 127          : reg(dst->Register),
 128            fdr(dst)
 129       { }
 130
 131       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 132
 133       uint getFile() const { return reg.File; }
 134
 135       bool is2D() const { return reg.Dimension; }
 136
 137       bool isIndirect(int dim) const
 138       {
 139          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 140       }
 141
 142       int getIndex(int dim) const
 143       {
 144          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 145       }
 146
 147       unsigned int getMask() const { return reg.WriteMask; }
 148
 149       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 150
 151       SrcRegister getIndirect(int dim) const
 152       {
 153          assert(fdr && isIndirect(dim));
 154          if (dim)
 155             return SrcRegister(fdr->DimIndirect);
 156          return SrcRegister(fdr->Indirect);
 157       }
 158
 159    private:
 160       const struct tgsi_dst_register reg;
 161       const struct tgsi_full_dst_register *fdr;
 162    };
 163
 164    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 165
 166    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 167    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 168
 169    // mask of used components of source s
 170    unsigned int srcMask(unsigned int s) const;
 171
 172    SrcRegister getSrc(unsigned int s) const
 173    {
 174       assert(s < srcCount());
 175       return SrcRegister(&insn->Src[s]);
 176    }
 177
 178    DstRegister getDst(unsigned int d) const
 179    {
 180       assert(d < dstCount());
 181       return DstRegister(&insn->Dst[d]);
 182    }
 183
 184    SrcRegister getTexOffset(unsigned int i) const
 185    {
 186       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 187       return SrcRegister(insn->TexOffsets[i]);
 188    }
 189
 190    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 191
 192    bool checkDstSrcAliasing() const;
 193
 194    inline nv50_ir::operation getOP() const {
 195       return translateOpcode(getOpcode()); }
 196
 197    nv50_ir::DataType inferSrcType() const;
 198    nv50_ir::DataType inferDstType() const;
 199
 200    nv50_ir::CondCode getSetCond() const;
 201
 202    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 203
 204    inline uint getLabel() { return insn->Label.Label; }
 205
 206    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 207
 208    void print() const
 209    {
 210       tgsi_dump_instruction(insn, 1);
 211    }
 212
 213 private:
 214    const struct tgsi_full_instruction *insn;
 215 };
 216
 217 unsigned int Instruction::srcMask(unsigned int s) const
 218 {
 219    unsigned int mask = insn->Dst[0].Register.WriteMask;
 220
 221    switch (insn->Instruction.Opcode) {
 222    case TGSI_OPCODE_COS:
 223    case TGSI_OPCODE_SIN:
 224       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 225    case TGSI_OPCODE_DP2:
 226       return 0x3;
 227    case TGSI_OPCODE_DP3:
 228       return 0x7;
 229    case TGSI_OPCODE_DP4:
 230    case TGSI_OPCODE_DPH:
 231    case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
 232       return 0xf;
 233    case TGSI_OPCODE_DST:
 234       return mask & (s ? 0xa : 0x6);
 235    case TGSI_OPCODE_EX2:
 236    case TGSI_OPCODE_EXP:
 237    case TGSI_OPCODE_LG2:
 238    case TGSI_OPCODE_LOG:
 239    case TGSI_OPCODE_POW:
 240    case TGSI_OPCODE_RCP:
 241    case TGSI_OPCODE_RSQ:
 242    case TGSI_OPCODE_SCS:
 243       return 0x1;
 244    case TGSI_OPCODE_IF:
 245    case TGSI_OPCODE_UIF:
 246       return 0x1;
 247    case TGSI_OPCODE_LIT:
 248       return 0xb;
 249    case TGSI_OPCODE_TEX2:
 250    case TGSI_OPCODE_TXB2:
 251    case TGSI_OPCODE_TXL2:
 252       return (s == 0) ? 0xf : 0x3;
 253    case TGSI_OPCODE_TEX:
 254    case TGSI_OPCODE_TXB:
 255    case TGSI_OPCODE_TXD:
 256    case TGSI_OPCODE_TXL:
 257    case TGSI_OPCODE_TXP:
 258    case TGSI_OPCODE_LODQ:
 259    {
 260       const struct tgsi_instruction_texture *tex = &insn->Texture;
 261
 262       assert(insn->Instruction.Texture);
 263
 264       mask = 0x7;
 265       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 266           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 267          mask |= 0x8; /* bias, lod or proj */
 268
 269       switch (tex->Texture) {
 270       case TGSI_TEXTURE_1D:
 271          mask &= 0x9;
 272          break;
 273       case TGSI_TEXTURE_SHADOW1D:
 274          mask &= 0xd;
 275          break;
 276       case TGSI_TEXTURE_1D_ARRAY:
 277       case TGSI_TEXTURE_2D:
 278       case TGSI_TEXTURE_RECT:
 279          mask &= 0xb;
 280          break;
 281       case TGSI_TEXTURE_CUBE_ARRAY:
 282       case TGSI_TEXTURE_SHADOW2D_ARRAY:
 283       case TGSI_TEXTURE_SHADOWCUBE:
 284       case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
 285          mask |= 0x8;
 286          break;
 287       default:
 288          break;
 289       }
 290    }
 291       return mask;
 292    case TGSI_OPCODE_XPD:
 293    {
 294       unsigned int x = 0;
 295       if (mask & 1) x |= 0x6;
 296       if (mask & 2) x |= 0x5;
 297       if (mask & 4) x |= 0x3;
 298       return x;
 299    }
 300    default:
 301       break;
 302    }
 303
 304    return mask;
 305 }
 306
 307 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 308 {
 309    nv50_ir::Modifier m(0);
 310
 311    if (reg.Absolute)
 312       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 313    if (reg.Negate)
 314       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 315    return m;
 316 }
 317
 318 static nv50_ir::DataFile translateFile(uint file)
 319 {
 320    switch (file) {
 321    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 322    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 323    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 324    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 325    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 326    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 327    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 328    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 329    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 330    case TGSI_FILE_SAMPLER:
 331    case TGSI_FILE_NULL:
 332    default:
 333       return nv50_ir::FILE_NULL;
 334    }
 335 }
 336
 337 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 338 {
 339    switch (sysval) {
 340    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 341    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 342    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 343    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 344    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 345    case TGSI_SEMANTIC_GRID_SIZE:  return nv50_ir::SV_NCTAID;
 346    case TGSI_SEMANTIC_BLOCK_ID:   return nv50_ir::SV_CTAID;
 347    case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
 348    case TGSI_SEMANTIC_THREAD_ID:  return nv50_ir::SV_TID;
 349    case TGSI_SEMANTIC_SAMPLEID:   return nv50_ir::SV_SAMPLE_INDEX;
 350    case TGSI_SEMANTIC_SAMPLEPOS:  return nv50_ir::SV_SAMPLE_POS;
 351    case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
 352    case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
 353    default:
 354       assert(0);
 355       return nv50_ir::SV_CLOCK;
 356    }
 357 }
 358
 359 #define NV50_IR_TEX_TARG_CASE(a, b) \
 360    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 361
 362 static nv50_ir::TexTarget translateTexture(uint tex)
 363 {
 364    switch (tex) {
 365    NV50_IR_TEX_TARG_CASE(1D, 1D);
 366    NV50_IR_TEX_TARG_CASE(2D, 2D);
 367    NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
 368    NV50_IR_TEX_TARG_CASE(3D, 3D);
 369    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 370    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 371    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 372    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 373    NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
 374    NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
 375    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 376    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 377    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 378    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 379    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 380    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 381    NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
 382    NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
 383
 384    case TGSI_TEXTURE_UNKNOWN:
 385    default:
 386       assert(!"invalid texture target");
 387       return nv50_ir::TEX_TARGET_2D;
 388    }
 389 }
 390
 391 nv50_ir::DataType Instruction::inferSrcType() const
 392 {
 393    switch (getOpcode()) {
 394    case TGSI_OPCODE_UIF:
 395    case TGSI_OPCODE_AND:
 396    case TGSI_OPCODE_OR:
 397    case TGSI_OPCODE_XOR:
 398    case TGSI_OPCODE_NOT:
 399    case TGSI_OPCODE_U2F:
 400    case TGSI_OPCODE_UADD:
 401    case TGSI_OPCODE_UDIV:
 402    case TGSI_OPCODE_UMOD:
 403    case TGSI_OPCODE_UMAD:
 404    case TGSI_OPCODE_UMUL:
 405    case TGSI_OPCODE_UMUL_HI:
 406    case TGSI_OPCODE_UMAX:
 407    case TGSI_OPCODE_UMIN:
 408    case TGSI_OPCODE_USEQ:
 409    case TGSI_OPCODE_USGE:
 410    case TGSI_OPCODE_USLT:
 411    case TGSI_OPCODE_USNE:
 412    case TGSI_OPCODE_USHR:
 413    case TGSI_OPCODE_UCMP:
 414    case TGSI_OPCODE_ATOMUADD:
 415    case TGSI_OPCODE_ATOMXCHG:
 416    case TGSI_OPCODE_ATOMCAS:
 417    case TGSI_OPCODE_ATOMAND:
 418    case TGSI_OPCODE_ATOMOR:
 419    case TGSI_OPCODE_ATOMXOR:
 420    case TGSI_OPCODE_ATOMUMIN:
 421    case TGSI_OPCODE_ATOMUMAX:
 422    case TGSI_OPCODE_UBFE:
 423    case TGSI_OPCODE_UMSB:
 424       return nv50_ir::TYPE_U32;
 425    case TGSI_OPCODE_I2F:
 426    case TGSI_OPCODE_IDIV:
 427    case TGSI_OPCODE_IMUL_HI:
 428    case TGSI_OPCODE_IMAX:
 429    case TGSI_OPCODE_IMIN:
 430    case TGSI_OPCODE_IABS:
 431    case TGSI_OPCODE_INEG:
 432    case TGSI_OPCODE_ISGE:
 433    case TGSI_OPCODE_ISHR:
 434    case TGSI_OPCODE_ISLT:
 435    case TGSI_OPCODE_ISSG:
 436    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 437    case TGSI_OPCODE_MOD:
 438    case TGSI_OPCODE_UARL:
 439    case TGSI_OPCODE_ATOMIMIN:
 440    case TGSI_OPCODE_ATOMIMAX:
 441    case TGSI_OPCODE_IBFE:
 442    case TGSI_OPCODE_IMSB:
 443       return nv50_ir::TYPE_S32;
 444    default:
 445       return nv50_ir::TYPE_F32;
 446    }
 447 }
 448
 449 nv50_ir::DataType Instruction::inferDstType() const
 450 {
 451    switch (getOpcode()) {
 452    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 453    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 454    case TGSI_OPCODE_FSEQ:
 455    case TGSI_OPCODE_FSGE:
 456    case TGSI_OPCODE_FSLT:
 457    case TGSI_OPCODE_FSNE:
 458       return nv50_ir::TYPE_U32;
 459    case TGSI_OPCODE_I2F:
 460    case TGSI_OPCODE_U2F:
 461       return nv50_ir::TYPE_F32;
 462    default:
 463       return inferSrcType();
 464    }
 465 }
 466
 467 nv50_ir::CondCode Instruction::getSetCond() const
 468 {
 469    using namespace nv50_ir;
 470
 471    switch (getOpcode()) {
 472    case TGSI_OPCODE_SLT:
 473    case TGSI_OPCODE_ISLT:
 474    case TGSI_OPCODE_USLT:
 475    case TGSI_OPCODE_FSLT:
 476       return CC_LT;
 477    case TGSI_OPCODE_SLE:
 478       return CC_LE;
 479    case TGSI_OPCODE_SGE:
 480    case TGSI_OPCODE_ISGE:
 481    case TGSI_OPCODE_USGE:
 482    case TGSI_OPCODE_FSGE:
 483       return CC_GE;
 484    case TGSI_OPCODE_SGT:
 485       return CC_GT;
 486    case TGSI_OPCODE_SEQ:
 487    case TGSI_OPCODE_USEQ:
 488    case TGSI_OPCODE_FSEQ:
 489       return CC_EQ;
 490    case TGSI_OPCODE_SNE:
 491    case TGSI_OPCODE_FSNE:
 492       return CC_NEU;
 493    case TGSI_OPCODE_USNE:
 494       return CC_NE;
 495    case TGSI_OPCODE_SFL:
 496       return CC_NEVER;
 497    case TGSI_OPCODE_STR:
 498    default:
 499       return CC_ALWAYS;
 500    }
 501 }
 502
 503 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 504
 505 static nv50_ir::operation translateOpcode(uint opcode)
 506 {
 507    switch (opcode) {
 508    NV50_IR_OPCODE_CASE(ARL, SHL);
 509    NV50_IR_OPCODE_CASE(MOV, MOV);
 510
 511    NV50_IR_OPCODE_CASE(RCP, RCP);
 512    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 513
 514    NV50_IR_OPCODE_CASE(MUL, MUL);
 515    NV50_IR_OPCODE_CASE(ADD, ADD);
 516
 517    NV50_IR_OPCODE_CASE(MIN, MIN);
 518    NV50_IR_OPCODE_CASE(MAX, MAX);
 519    NV50_IR_OPCODE_CASE(SLT, SET);
 520    NV50_IR_OPCODE_CASE(SGE, SET);
 521    NV50_IR_OPCODE_CASE(MAD, MAD);
 522    NV50_IR_OPCODE_CASE(SUB, SUB);
 523
 524    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 525    NV50_IR_OPCODE_CASE(ROUND, CVT);
 526    NV50_IR_OPCODE_CASE(EX2, EX2);
 527    NV50_IR_OPCODE_CASE(LG2, LG2);
 528    NV50_IR_OPCODE_CASE(POW, POW);
 529
 530    NV50_IR_OPCODE_CASE(ABS, ABS);
 531
 532    NV50_IR_OPCODE_CASE(COS, COS);
 533    NV50_IR_OPCODE_CASE(DDX, DFDX);
 534    NV50_IR_OPCODE_CASE(DDY, DFDY);
 535    NV50_IR_OPCODE_CASE(KILL, DISCARD);
 536
 537    NV50_IR_OPCODE_CASE(SEQ, SET);
 538    NV50_IR_OPCODE_CASE(SFL, SET);
 539    NV50_IR_OPCODE_CASE(SGT, SET);
 540    NV50_IR_OPCODE_CASE(SIN, SIN);
 541    NV50_IR_OPCODE_CASE(SLE, SET);
 542    NV50_IR_OPCODE_CASE(SNE, SET);
 543    NV50_IR_OPCODE_CASE(STR, SET);
 544    NV50_IR_OPCODE_CASE(TEX, TEX);
 545    NV50_IR_OPCODE_CASE(TXD, TXD);
 546    NV50_IR_OPCODE_CASE(TXP, TEX);
 547
 548    NV50_IR_OPCODE_CASE(BRA, BRA);
 549    NV50_IR_OPCODE_CASE(CAL, CALL);
 550    NV50_IR_OPCODE_CASE(RET, RET);
 551    NV50_IR_OPCODE_CASE(CMP, SLCT);
 552
 553    NV50_IR_OPCODE_CASE(TXB, TXB);
 554
 555    NV50_IR_OPCODE_CASE(DIV, DIV);
 556
 557    NV50_IR_OPCODE_CASE(TXL, TXL);
 558
 559    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 560    NV50_IR_OPCODE_CASE(I2F, CVT);
 561    NV50_IR_OPCODE_CASE(NOT, NOT);
 562    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 563    NV50_IR_OPCODE_CASE(SHL, SHL);
 564
 565    NV50_IR_OPCODE_CASE(AND, AND);
 566    NV50_IR_OPCODE_CASE(OR, OR);
 567    NV50_IR_OPCODE_CASE(MOD, MOD);
 568    NV50_IR_OPCODE_CASE(XOR, XOR);
 569    NV50_IR_OPCODE_CASE(SAD, SAD);
 570    NV50_IR_OPCODE_CASE(TXF, TXF);
 571    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 572    NV50_IR_OPCODE_CASE(TG4, TXG);
 573    NV50_IR_OPCODE_CASE(LODQ, TXLQ);
 574
 575    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 576    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 577
 578    NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
 579
 580    NV50_IR_OPCODE_CASE(F2I, CVT);
 581    NV50_IR_OPCODE_CASE(FSEQ, SET);
 582    NV50_IR_OPCODE_CASE(FSGE, SET);
 583    NV50_IR_OPCODE_CASE(FSLT, SET);
 584    NV50_IR_OPCODE_CASE(FSNE, SET);
 585    NV50_IR_OPCODE_CASE(IDIV, DIV);
 586    NV50_IR_OPCODE_CASE(IMAX, MAX);
 587    NV50_IR_OPCODE_CASE(IMIN, MIN);
 588    NV50_IR_OPCODE_CASE(IABS, ABS);
 589    NV50_IR_OPCODE_CASE(INEG, NEG);
 590    NV50_IR_OPCODE_CASE(ISGE, SET);
 591    NV50_IR_OPCODE_CASE(ISHR, SHR);
 592    NV50_IR_OPCODE_CASE(ISLT, SET);
 593    NV50_IR_OPCODE_CASE(F2U, CVT);
 594    NV50_IR_OPCODE_CASE(U2F, CVT);
 595    NV50_IR_OPCODE_CASE(UADD, ADD);
 596    NV50_IR_OPCODE_CASE(UDIV, DIV);
 597    NV50_IR_OPCODE_CASE(UMAD, MAD);
 598    NV50_IR_OPCODE_CASE(UMAX, MAX);
 599    NV50_IR_OPCODE_CASE(UMIN, MIN);
 600    NV50_IR_OPCODE_CASE(UMOD, MOD);
 601    NV50_IR_OPCODE_CASE(UMUL, MUL);
 602    NV50_IR_OPCODE_CASE(USEQ, SET);
 603    NV50_IR_OPCODE_CASE(USGE, SET);
 604    NV50_IR_OPCODE_CASE(USHR, SHR);
 605    NV50_IR_OPCODE_CASE(USLT, SET);
 606    NV50_IR_OPCODE_CASE(USNE, SET);
 607
 608    NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
 609    NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
 610
 611    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 612    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 613    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 614    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 615    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 616    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 617    NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
 618    NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
 619    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 620    NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
 621
 622    NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
 623    NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
 624    NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
 625    NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
 626    NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
 627    NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
 628    NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
 629    NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
 630    NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
 631    NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
 632
 633    NV50_IR_OPCODE_CASE(TEX2, TEX);
 634    NV50_IR_OPCODE_CASE(TXB2, TXB);
 635    NV50_IR_OPCODE_CASE(TXL2, TXL);
 636
 637    NV50_IR_OPCODE_CASE(IBFE, EXTBF);
 638    NV50_IR_OPCODE_CASE(UBFE, EXTBF);
 639    NV50_IR_OPCODE_CASE(BFI, INSBF);
 640    NV50_IR_OPCODE_CASE(BREV, EXTBF);
 641    NV50_IR_OPCODE_CASE(POPC, POPCNT);
 642    NV50_IR_OPCODE_CASE(LSB, BFIND);
 643    NV50_IR_OPCODE_CASE(IMSB, BFIND);
 644    NV50_IR_OPCODE_CASE(UMSB, BFIND);
 645
 646    NV50_IR_OPCODE_CASE(END, EXIT);
 647
 648    default:
 649       return nv50_ir::OP_NOP;
 650    }
 651 }
 652
 653 static uint16_t opcodeToSubOp(uint opcode)
 654 {
 655    switch (opcode) {
 656    case TGSI_OPCODE_LFENCE:   return NV50_IR_SUBOP_MEMBAR(L, GL);
 657    case TGSI_OPCODE_SFENCE:   return NV50_IR_SUBOP_MEMBAR(S, GL);
 658    case TGSI_OPCODE_MFENCE:   return NV50_IR_SUBOP_MEMBAR(M, GL);
 659    case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
 660    case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
 661    case TGSI_OPCODE_ATOMCAS:  return NV50_IR_SUBOP_ATOM_CAS;
 662    case TGSI_OPCODE_ATOMAND:  return NV50_IR_SUBOP_ATOM_AND;
 663    case TGSI_OPCODE_ATOMOR:   return NV50_IR_SUBOP_ATOM_OR;
 664    case TGSI_OPCODE_ATOMXOR:  return NV50_IR_SUBOP_ATOM_XOR;
 665    case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
 666    case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
 667    case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
 668    case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
 669    case TGSI_OPCODE_IMUL_HI:
 670    case TGSI_OPCODE_UMUL_HI:
 671       return NV50_IR_SUBOP_MUL_HIGH;
 672    default:
 673       return 0;
 674    }
 675 }
 676
 677 bool Instruction::checkDstSrcAliasing() const
 678 {
 679    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 680       return false;
 681
 682    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 683       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 684          break;
 685       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 686           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 687          return true;
 688    }
 689    return false;
 690 }
 691
 692 class Source
 693 {
 694 public:
 695    Source(struct nv50_ir_prog_info *);
 696    ~Source();
 697
 698 public:
 699    bool scanSource();
 700    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 701
 702 public:
 703    struct tgsi_shader_info scan;
 704    struct tgsi_full_instruction *insns;
 705    const struct tgsi_token *tokens;
 706    struct nv50_ir_prog_info *info;
 707
 708    nv50_ir::DynArray tempArrays;
 709    nv50_ir::DynArray immdArrays;
 710
 711    typedef nv50_ir::BuildUtil::Location Location;
 712    // these registers are per-subroutine, cannot be used for parameter passing
 713    std::set<Location> locals;
 714
 715    bool mainTempsInLMem;
 716
 717    int clipVertexOutput;
 718
 719    struct TextureView {
 720       uint8_t target; // TGSI_TEXTURE_*
 721    };
 722    std::vector<TextureView> textureViews;
 723
 724    struct Resource {
 725       uint8_t target; // TGSI_TEXTURE_*
 726       bool raw;
 727       uint8_t slot; // $surface index
 728    };
 729    std::vector<Resource> resources;
 730
 731 private:
 732    int inferSysValDirection(unsigned sn) const;
 733    bool scanDeclaration(const struct tgsi_full_declaration *);
 734    bool scanInstruction(const struct tgsi_full_instruction *);
 735    void scanProperty(const struct tgsi_full_property *);
 736    void scanImmediate(const struct tgsi_full_immediate *);
 737
 738    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 739 };
 740
 741 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 742 {
 743    tokens = (const struct tgsi_token *)info->bin.source;
 744
 745    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 746       tgsi_dump(tokens, 0);
 747
 748    mainTempsInLMem = FALSE;
 749 }
 750
 751 Source::~Source()
 752 {
 753    if (insns)
 754       FREE(insns);
 755
 756    if (info->immd.data)
 757       FREE(info->immd.data);
 758    if (info->immd.type)
 759       FREE(info->immd.type);
 760 }
 761
 762 bool Source::scanSource()
 763 {
 764    unsigned insnCount = 0;
 765    struct tgsi_parse_context parse;
 766
 767    tgsi_scan_shader(tokens, &scan);
 768
 769    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 770                                                   sizeof(insns[0]));
 771    if (!insns)
 772       return false;
 773
 774    clipVertexOutput = -1;
 775
 776    textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
 777    resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
 778
 779    info->immd.bufSize = 0;
 780
 781    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 782    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 783    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 784
 785    if (info->type == PIPE_SHADER_FRAGMENT) {
 786       info->prop.fp.writesDepth = scan.writes_z;
 787       info->prop.fp.usesDiscard = scan.uses_kill;
 788    } else
 789    if (info->type == PIPE_SHADER_GEOMETRY) {
 790       info->prop.gp.instanceCount = 1; // default value
 791    }
 792
 793    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 794    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 795
 796    tgsi_parse_init(&parse, tokens);
 797    while (!tgsi_parse_end_of_tokens(&parse)) {
 798       tgsi_parse_token(&parse);
 799
 800       switch (parse.FullToken.Token.Type) {
 801       case TGSI_TOKEN_TYPE_IMMEDIATE:
 802          scanImmediate(&parse.FullToken.FullImmediate);
 803          break;
 804       case TGSI_TOKEN_TYPE_DECLARATION:
 805          scanDeclaration(&parse.FullToken.FullDeclaration);
 806          break;
 807       case TGSI_TOKEN_TYPE_INSTRUCTION:
 808          insns[insnCount++] = parse.FullToken.FullInstruction;
 809          scanInstruction(&parse.FullToken.FullInstruction);
 810          break;
 811       case TGSI_TOKEN_TYPE_PROPERTY:
 812          scanProperty(&parse.FullToken.FullProperty);
 813          break;
 814       default:
 815          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 816          break;
 817       }
 818    }
 819    tgsi_parse_free(&parse);
 820
 821    if (mainTempsInLMem)
 822       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 823
 824    if (info->io.genUserClip > 0) {
 825       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 826
 827       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 828
 829       for (unsigned int n = 0; n < nOut; ++n) {
 830          unsigned int i = info->numOutputs++;
 831          info->out[i].id = i;
 832          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 833          info->out[i].si = n;
 834          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 835       }
 836    }
 837
 838    return info->assignSlots(info) == 0;
 839 }
 840
 841 void Source::scanProperty(const struct tgsi_full_property *prop)
 842 {
 843    switch (prop->Property.PropertyName) {
 844    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 845       info->prop.gp.outputPrim = prop->u[0].Data;
 846       break;
 847    case TGSI_PROPERTY_GS_INPUT_PRIM:
 848       info->prop.gp.inputPrim = prop->u[0].Data;
 849       break;
 850    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 851       info->prop.gp.maxVertices = prop->u[0].Data;
 852       break;
 853    case TGSI_PROPERTY_GS_INVOCATIONS:
 854       info->prop.gp.instanceCount = prop->u[0].Data;
 855       break;
 856    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 857       info->prop.fp.separateFragData = TRUE;
 858       break;
 859    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 860    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 861       // we don't care
 862       break;
 863    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 864       info->io.genUserClip = -1;
 865       break;
 866    default:
 867       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 868       break;
 869    }
 870 }
 871
 872 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 873 {
 874    const unsigned n = info->immd.count++;
 875
 876    assert(n < scan.immediate_count);
 877
 878    for (int c = 0; c < 4; ++c)
 879       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 880
 881    info->immd.type[n] = imm->Immediate.DataType;
 882 }
 883
 884 int Source::inferSysValDirection(unsigned sn) const
 885 {
 886    switch (sn) {
 887    case TGSI_SEMANTIC_INSTANCEID:
 888    case TGSI_SEMANTIC_VERTEXID:
 889       return 1;
 890    case TGSI_SEMANTIC_LAYER:
 891 #if 0
 892    case TGSI_SEMANTIC_VIEWPORTINDEX:
 893       return 0;
 894 #endif
 895    case TGSI_SEMANTIC_PRIMID:
 896       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
 897    default:
 898       return 0;
 899    }
 900 }
 901
 902 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
 903 {
 904    unsigned i, c;
 905    unsigned sn = TGSI_SEMANTIC_GENERIC;
 906    unsigned si = 0;
 907    const unsigned first = decl->Range.First, last = decl->Range.Last;
 908
 909    if (decl->Declaration.Semantic) {
 910       sn = decl->Semantic.Name;
 911       si = decl->Semantic.Index;
 912    }
 913
 914    if (decl->Declaration.Local) {
 915       for (i = first; i <= last; ++i) {
 916          for (c = 0; c < 4; ++c) {
 917             locals.insert(
 918                Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
 919          }
 920       }
 921    }
 922
 923    switch (decl->Declaration.File) {
 924    case TGSI_FILE_INPUT:
 925       if (info->type == PIPE_SHADER_VERTEX) {
 926          // all vertex attributes are equal
 927          for (i = first; i <= last; ++i) {
 928             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
 929             info->in[i].si = i;
 930          }
 931       } else {
 932          for (i = first; i <= last; ++i, ++si) {
 933             info->in[i].id = i;
 934             info->in[i].sn = sn;
 935             info->in[i].si = si;
 936             if (info->type == PIPE_SHADER_FRAGMENT) {
 937                // translate interpolation mode
 938                switch (decl->Interp.Interpolate) {
 939                case TGSI_INTERPOLATE_CONSTANT:
 940                   info->in[i].flat = 1;
 941                   break;
 942                case TGSI_INTERPOLATE_COLOR:
 943                   info->in[i].sc = 1;
 944                   break;
 945                case TGSI_INTERPOLATE_LINEAR:
 946                   info->in[i].linear = 1;
 947                   break;
 948                default:
 949                   break;
 950                }
 951                if (decl->Interp.Centroid || info->io.sampleInterp)
 952                   info->in[i].centroid = 1;
 953             }
 954          }
 955       }
 956       break;
 957    case TGSI_FILE_OUTPUT:
 958       for (i = first; i <= last; ++i, ++si) {
 959          switch (sn) {
 960          case TGSI_SEMANTIC_POSITION:
 961             if (info->type == PIPE_SHADER_FRAGMENT)
 962                info->io.fragDepth = i;
 963             else
 964             if (clipVertexOutput < 0)
 965                clipVertexOutput = i;
 966             break;
 967          case TGSI_SEMANTIC_COLOR:
 968             if (info->type == PIPE_SHADER_FRAGMENT)
 969                info->prop.fp.numColourResults++;
 970             break;
 971          case TGSI_SEMANTIC_EDGEFLAG:
 972             info->io.edgeFlagOut = i;
 973             break;
 974          case TGSI_SEMANTIC_CLIPVERTEX:
 975             clipVertexOutput = i;
 976             break;
 977          case TGSI_SEMANTIC_CLIPDIST:
 978             info->io.clipDistanceMask |=
 979                decl->Declaration.UsageMask << (si * 4);
 980             info->io.genUserClip = -1;
 981             break;
 982          case TGSI_SEMANTIC_SAMPLEMASK:
 983             info->io.sampleMask = i;
 984             break;
 985          default:
 986             break;
 987          }
 988          info->out[i].id = i;
 989          info->out[i].sn = sn;
 990          info->out[i].si = si;
 991       }
 992       break;
 993    case TGSI_FILE_SYSTEM_VALUE:
 994       switch (sn) {
 995       case TGSI_SEMANTIC_INSTANCEID:
 996          info->io.instanceId = first;
 997          break;
 998       case TGSI_SEMANTIC_VERTEXID:
 999          info->io.vertexId = first;
1000          break;
1001       default:
1002          break;
1003       }
1004       for (i = first; i <= last; ++i, ++si) {
1005          info->sv[i].sn = sn;
1006          info->sv[i].si = si;
1007          info->sv[i].input = inferSysValDirection(sn);
1008       }
1009       break;
1010    case TGSI_FILE_RESOURCE:
1011       for (i = first; i <= last; ++i) {
1012          resources[i].target = decl->Resource.Resource;
1013          resources[i].raw = decl->Resource.Raw;
1014          resources[i].slot = i;
1015       }
1016       break;
1017    case TGSI_FILE_SAMPLER_VIEW:
1018       for (i = first; i <= last; ++i)
1019          textureViews[i].target = decl->SamplerView.Resource;
1020       break;
1021    case TGSI_FILE_NULL:
1022    case TGSI_FILE_TEMPORARY:
1023    case TGSI_FILE_ADDRESS:
1024    case TGSI_FILE_CONSTANT:
1025    case TGSI_FILE_IMMEDIATE:
1026    case TGSI_FILE_PREDICATE:
1027    case TGSI_FILE_SAMPLER:
1028       break;
1029    default:
1030       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1031       return false;
1032    }
1033    return true;
1034 }
1035
1036 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1037 {
1038    return insn.getOpcode() == TGSI_OPCODE_MOV &&
1039       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1040       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1041 }
1042
1043 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1044 {
1045    Instruction insn(inst);
1046
1047    if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1048       info->numBarriers = 1;
1049
1050    if (insn.dstCount()) {
1051       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1052          Instruction::DstRegister dst = insn.getDst(0);
1053
1054          if (dst.isIndirect(0))
1055             for (unsigned i = 0; i < info->numOutputs; ++i)
1056                info->out[i].mask = 0xf;
1057          else
1058             info->out[dst.getIndex(0)].mask |= dst.getMask();
1059
1060          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1061              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1062              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1063              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1064              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1065             info->out[dst.getIndex(0)].mask &= 1;
1066
1067          if (isEdgeFlagPassthrough(insn))
1068             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1069       } else
1070       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1071          if (insn.getDst(0).isIndirect(0))
1072             mainTempsInLMem = TRUE;
1073       }
1074    }
1075
1076    for (unsigned s = 0; s < insn.srcCount(); ++s) {
1077       Instruction::SrcRegister src = insn.getSrc(s);
1078       if (src.getFile() == TGSI_FILE_TEMPORARY) {
1079          if (src.isIndirect(0))
1080             mainTempsInLMem = TRUE;
1081       } else
1082       if (src.getFile() == TGSI_FILE_RESOURCE) {
1083          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1084             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1085                0x1 : 0x2;
1086       }
1087       if (src.getFile() != TGSI_FILE_INPUT)
1088          continue;
1089       unsigned mask = insn.srcMask(s);
1090
1091       if (src.isIndirect(0)) {
1092          for (unsigned i = 0; i < info->numInputs; ++i)
1093             info->in[i].mask = 0xf;
1094       } else {
1095          const int i = src.getIndex(0);
1096          for (unsigned c = 0; c < 4; ++c) {
1097             if (!(mask & (1 << c)))
1098                continue;
1099             int k = src.getSwizzle(c);
1100             if (k <= TGSI_SWIZZLE_W)
1101                info->in[i].mask |= 1 << k;
1102          }
1103          switch (info->in[i].sn) {
1104          case TGSI_SEMANTIC_PSIZE:
1105          case TGSI_SEMANTIC_PRIMID:
1106          case TGSI_SEMANTIC_FOG:
1107             info->in[i].mask &= 0x1;
1108             break;
1109          case TGSI_SEMANTIC_PCOORD:
1110             info->in[i].mask &= 0x3;
1111             break;
1112          default:
1113             break;
1114          }
1115       }
1116    }
1117    return true;
1118 }
1119
1120 nv50_ir::TexInstruction::Target
1121 Instruction::getTexture(const tgsi::Source *code, int s) const
1122 {
1123    // XXX: indirect access
1124    unsigned int r;
1125
1126    switch (getSrc(s).getFile()) {
1127    case TGSI_FILE_RESOURCE:
1128       r = getSrc(s).getIndex(0);
1129       return translateTexture(code->resources.at(r).target);
1130    case TGSI_FILE_SAMPLER_VIEW:
1131       r = getSrc(s).getIndex(0);
1132       return translateTexture(code->textureViews.at(r).target);
1133    default:
1134       return translateTexture(insn->Texture.Texture);
1135    }
1136 }
1137
1138 } // namespace tgsi
1139
1140 namespace {
1141
1142 using namespace nv50_ir;
1143
1144 class Converter : public BuildUtil
1145 {
1146 public:
1147    Converter(Program *, const tgsi::Source *);
1148    ~Converter();
1149
1150    bool run();
1151
1152 private:
1153    struct Subroutine
1154    {
1155       Subroutine(Function *f) : f(f) { }
1156       Function *f;
1157       ValueMap values;
1158    };
1159
1160    Value *shiftAddress(Value *);
1161    Value *getVertexBase(int s);
1162    DataArray *getArrayForFile(unsigned file, int idx);
1163    Value *fetchSrc(int s, int c);
1164    Value *acquireDst(int d, int c);
1165    void storeDst(int d, int c, Value *);
1166
1167    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1168    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1169                  Value *val, Value *ptr);
1170
1171    Value *applySrcMod(Value *, int s, int c);
1172
1173    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1174    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1175    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1176
1177    bool handleInstruction(const struct tgsi_full_instruction *);
1178    void exportOutputs();
1179    inline Subroutine *getSubroutine(unsigned ip);
1180    inline Subroutine *getSubroutine(Function *);
1181    inline bool isEndOfSubroutine(uint ip);
1182
1183    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1184
1185    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1186    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1187    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1188    void handleTXF(Value *dst0[4], int R, int L_M);
1189    void handleTXQ(Value *dst0[4], enum TexQuery);
1190    void handleLIT(Value *dst0[4]);
1191    void handleUserClipPlanes();
1192
1193    Symbol *getResourceBase(int r);
1194    void getResourceCoords(std::vector<Value *>&, int r, int s);
1195
1196    void handleLOAD(Value *dst0[4]);
1197    void handleSTORE();
1198    void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1199
1200    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1201
1202    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1203
1204    Value *buildDot(int dim);
1205
1206    class BindArgumentsPass : public Pass {
1207    public:
1208       BindArgumentsPass(Converter &conv) : conv(conv) { }
1209
1210    private:
1211       Converter &conv;
1212       Subroutine *sub;
1213
1214       inline const Location *getValueLocation(Subroutine *, Value *);
1215
1216       template<typename T> inline void
1217       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1218                      T (Function::*proto));
1219
1220       template<typename T> inline void
1221       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1222                       T (Function::*proto));
1223
1224    protected:
1225       bool visit(Function *);
1226       bool visit(BasicBlock *bb) { return false; }
1227    };
1228
1229 private:
1230    const struct tgsi::Source *code;
1231    const struct nv50_ir_prog_info *info;
1232
1233    struct {
1234       std::map<unsigned, Subroutine> map;
1235       Subroutine *cur;
1236    } sub;
1237
1238    uint ip; // instruction pointer
1239
1240    tgsi::Instruction tgsi;
1241
1242    DataType dstTy;
1243    DataType srcTy;
1244
1245    DataArray tData; // TGSI_FILE_TEMPORARY
1246    DataArray aData; // TGSI_FILE_ADDRESS
1247    DataArray pData; // TGSI_FILE_PREDICATE
1248    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1249
1250    Value *zero;
1251    Value *fragCoord[4];
1252    Value *clipVtx[4];
1253
1254    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1255    uint8_t vtxBaseValid;
1256
1257    Stack condBBs;  // fork BB, then else clause BB
1258    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1259    Stack loopBBs;  // loop headers
1260    Stack breakBBs; // end of / after loop
1261 };
1262
1263 Symbol *
1264 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1265 {
1266    const int swz = src.getSwizzle(c);
1267
1268    return makeSym(src.getFile(),
1269                   src.is2D() ? src.getIndex(1) : 0,
1270                   src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1271                   src.getIndex(0) * 16 + swz * 4);
1272 }
1273
1274 Symbol *
1275 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1276 {
1277    return makeSym(dst.getFile(),
1278                   dst.is2D() ? dst.getIndex(1) : 0,
1279                   dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1280                   dst.getIndex(0) * 16 + c * 4);
1281 }
1282
1283 Symbol *
1284 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1285 {
1286    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1287
1288    sym->reg.fileIndex = fileIdx;
1289
1290    if (idx >= 0) {
1291       if (sym->reg.file == FILE_SHADER_INPUT)
1292          sym->setOffset(info->in[idx].slot[c] * 4);
1293       else
1294       if (sym->reg.file == FILE_SHADER_OUTPUT)
1295          sym->setOffset(info->out[idx].slot[c] * 4);
1296       else
1297       if (sym->reg.file == FILE_SYSTEM_VALUE)
1298          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1299       else
1300          sym->setOffset(address);
1301    } else {
1302       sym->setOffset(address);
1303    }
1304    return sym;
1305 }
1306
1307 static inline uint8_t
1308 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1309 {
1310    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1311
1312    if (var->flat)
1313       mode = NV50_IR_INTERP_FLAT;
1314    else
1315    if (var->linear)
1316       mode = NV50_IR_INTERP_LINEAR;
1317    else
1318    if (var->sc)
1319       mode = NV50_IR_INTERP_SC;
1320
1321    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1322       ? OP_PINTERP : OP_LINTERP;
1323
1324    if (var->centroid)
1325       mode |= NV50_IR_INTERP_CENTROID;
1326
1327    return mode;
1328 }
1329
1330 Value *
1331 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1332 {
1333    operation op;
1334
1335    // XXX: no way to know interpolation mode if we don't know what's accessed
1336    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1337                                                       src.getIndex(0)], op);
1338
1339    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1340
1341    insn->setDef(0, getScratch());
1342    insn->setSrc(0, srcToSym(src, c));
1343    if (op == OP_PINTERP)
1344       insn->setSrc(1, fragCoord[3]);
1345    if (ptr)
1346       insn->setIndirect(0, 0, ptr);
1347
1348    insn->setInterpolate(mode);
1349
1350    bb->insertTail(insn);
1351    return insn->getDef(0);
1352 }
1353
1354 Value *
1355 Converter::applySrcMod(Value *val, int s, int c)
1356 {
1357    Modifier m = tgsi.getSrc(s).getMod(c);
1358    DataType ty = tgsi.inferSrcType();
1359
1360    if (m & Modifier(NV50_IR_MOD_ABS))
1361       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1362
1363    if (m & Modifier(NV50_IR_MOD_NEG))
1364       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1365
1366    return val;
1367 }
1368
1369 Value *
1370 Converter::getVertexBase(int s)
1371 {
1372    assert(s < 5);
1373    if (!(vtxBaseValid & (1 << s))) {
1374       const int index = tgsi.getSrc(s).getIndex(1);
1375       Value *rel = NULL;
1376       if (tgsi.getSrc(s).isIndirect(1))
1377          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1378       vtxBaseValid |= 1 << s;
1379       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1380                           mkImm(index), rel);
1381    }
1382    return vtxBase[s];
1383 }
1384
1385 Value *
1386 Converter::fetchSrc(int s, int c)
1387 {
1388    Value *res;
1389    Value *ptr = NULL, *dimRel = NULL;
1390
1391    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1392
1393    if (src.isIndirect(0))
1394       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1395
1396    if (src.is2D()) {
1397       switch (src.getFile()) {
1398       case TGSI_FILE_INPUT:
1399          dimRel = getVertexBase(s);
1400          break;
1401       case TGSI_FILE_CONSTANT:
1402          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1403          if (src.isIndirect(1))
1404             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1405          break;
1406       default:
1407          break;
1408       }
1409    }
1410
1411    res = fetchSrc(src, c, ptr);
1412
1413    if (dimRel)
1414       res->getInsn()->setIndirect(0, 1, dimRel);
1415
1416    return applySrcMod(res, s, c);
1417 }
1418
1419 Converter::DataArray *
1420 Converter::getArrayForFile(unsigned file, int idx)
1421 {
1422    switch (file) {
1423    case TGSI_FILE_TEMPORARY:
1424       return &tData;
1425    case TGSI_FILE_PREDICATE:
1426       return &pData;
1427    case TGSI_FILE_ADDRESS:
1428       return &aData;
1429    case TGSI_FILE_OUTPUT:
1430       assert(prog->getType() == Program::TYPE_FRAGMENT);
1431       return &oData;
1432    default:
1433       assert(!"invalid/unhandled TGSI source file");
1434       return NULL;
1435    }
1436 }
1437
1438 Value *
1439 Converter::shiftAddress(Value *index)
1440 {
1441    if (!index)
1442       return NULL;
1443    return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1444 }
1445
1446 Value *
1447 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1448 {
1449    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1450    const int idx = src.getIndex(0);
1451    const int swz = src.getSwizzle(c);
1452
1453    switch (src.getFile()) {
1454    case TGSI_FILE_IMMEDIATE:
1455       assert(!ptr);
1456       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1457    case TGSI_FILE_CONSTANT:
1458       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1459    case TGSI_FILE_INPUT:
1460       if (prog->getType() == Program::TYPE_FRAGMENT) {
1461          // don't load masked inputs, won't be assigned a slot
1462          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1463             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1464          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1465             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1466          return interpolate(src, c, shiftAddress(ptr));
1467       } else
1468       if (prog->getType() == Program::TYPE_GEOMETRY) {
1469          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1470             return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1471          // XXX: This is going to be a problem with scalar arrays, i.e. when
1472          // we cannot assume that the address is given in units of vec4.
1473          //
1474          // nv50 and nvc0 need different things here, so let the lowering
1475          // passes decide what to do with the address
1476          if (ptr)
1477             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1478       }
1479       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1480    case TGSI_FILE_OUTPUT:
1481       assert(!"load from output file");
1482       return NULL;
1483    case TGSI_FILE_SYSTEM_VALUE:
1484       assert(!ptr);
1485       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1486    default:
1487       return getArrayForFile(src.getFile(), idx2d)->load(
1488          sub.cur->values, idx, swz, shiftAddress(ptr));
1489    }
1490 }
1491
1492 Value *
1493 Converter::acquireDst(int d, int c)
1494 {
1495    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1496    const unsigned f = dst.getFile();
1497    const int idx = dst.getIndex(0);
1498    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1499
1500    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1501       return NULL;
1502
1503    if (dst.isIndirect(0) ||
1504        f == TGSI_FILE_SYSTEM_VALUE ||
1505        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1506       return getScratch();
1507
1508    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1509 }
1510
1511 void
1512 Converter::storeDst(int d, int c, Value *val)
1513 {
1514    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1515
1516    switch (tgsi.getSaturate()) {
1517    case TGSI_SAT_NONE:
1518       break;
1519    case TGSI_SAT_ZERO_ONE:
1520       mkOp1(OP_SAT, dstTy, val, val);
1521       break;
1522    case TGSI_SAT_MINUS_PLUS_ONE:
1523       mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1524       mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1525       break;
1526    default:
1527       assert(!"invalid saturation mode");
1528       break;
1529    }
1530
1531    Value *ptr = NULL;
1532    if (dst.isIndirect(0))
1533       ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1534
1535    if (info->io.genUserClip > 0 &&
1536        dst.getFile() == TGSI_FILE_OUTPUT &&
1537        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1538       mkMov(clipVtx[c], val);
1539       val = clipVtx[c];
1540    }
1541
1542    storeDst(dst, c, val, ptr);
1543 }
1544
1545 void
1546 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1547                     Value *val, Value *ptr)
1548 {
1549    const unsigned f = dst.getFile();
1550    const int idx = dst.getIndex(0);
1551    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1552
1553    if (f == TGSI_FILE_SYSTEM_VALUE) {
1554       assert(!ptr);
1555       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1556    } else
1557    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1558       if (ptr || (info->out[idx].mask & (1 << c)))
1559          mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1560    } else
1561    if (f == TGSI_FILE_TEMPORARY ||
1562        f == TGSI_FILE_PREDICATE ||
1563        f == TGSI_FILE_ADDRESS ||
1564        f == TGSI_FILE_OUTPUT) {
1565       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1566    } else {
1567       assert(!"invalid dst file");
1568    }
1569 }
1570
1571 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1572    for (chan = 0; chan < 4; ++chan)                 \
1573       if (!inst.getDst(d).isMasked(chan))
1574
1575 Value *
1576 Converter::buildDot(int dim)
1577 {
1578    assert(dim > 0);
1579
1580    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1581    Value *dotp = getScratch();
1582
1583    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1584
1585    for (int c = 1; c < dim; ++c) {
1586       src0 = fetchSrc(0, c);
1587       src1 = fetchSrc(1, c);
1588       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1589    }
1590    return dotp;
1591 }
1592
1593 void
1594 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1595 {
1596    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1597    join->fixed = 1;
1598    conv->insertHead(join);
1599
1600    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1601    fork->insertBefore(fork->getExit(), fork->joinAt);
1602 }
1603
1604 void
1605 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1606 {
1607    unsigned rIdx = 0, sIdx = 0;
1608
1609    if (R >= 0)
1610       rIdx = tgsi.getSrc(R).getIndex(0);
1611    if (S >= 0)
1612       sIdx = tgsi.getSrc(S).getIndex(0);
1613
1614    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1615
1616    if (tgsi.getSrc(R).isIndirect(0)) {
1617       tex->tex.rIndirectSrc = s;
1618       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1619    }
1620    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1621       tex->tex.sIndirectSrc = s;
1622       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1623    }
1624 }
1625
1626 void
1627 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1628 {
1629    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1630    tex->tex.query = query;
1631    unsigned int c, d;
1632
1633    for (d = 0, c = 0; c < 4; ++c) {
1634       if (!dst0[c])
1635          continue;
1636       tex->tex.mask |= 1 << c;
1637       tex->setDef(d++, dst0[c]);
1638    }
1639    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1640
1641    setTexRS(tex, c, 1, -1);
1642
1643    bb->insertTail(tex);
1644 }
1645
1646 void
1647 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1648 {
1649    Value *proj = fetchSrc(0, 3);
1650    Instruction *insn = proj->getUniqueInsn();
1651    int c;
1652
1653    if (insn->op == OP_PINTERP) {
1654       bb->insertTail(insn = cloneForward(func, insn));
1655       insn->op = OP_LINTERP;
1656       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1657       insn->setSrc(1, NULL);
1658       proj = insn->getDef(0);
1659    }
1660    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1661
1662    for (c = 0; c < 4; ++c) {
1663       if (!(mask & (1 << c)))
1664          continue;
1665       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1666          continue;
1667       mask &= ~(1 << c);
1668
1669       bb->insertTail(insn = cloneForward(func, insn));
1670       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1671       insn->setSrc(1, proj);
1672       dst[c] = insn->getDef(0);
1673    }
1674    if (!mask)
1675       return;
1676
1677    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1678
1679    for (c = 0; c < 4; ++c)
1680       if (mask & (1 << c))
1681          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1682 }
1683
1684 // order of nv50 ir sources: x y z layer lod/bias shadow
1685 // order of TGSI TEX sources: x y z layer shadow lod/bias
1686 //  lowering will finally set the hw specific order (like array first on nvc0)
1687 void
1688 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1689 {
1690    Value *val;
1691    Value *arg[4], *src[8];
1692    Value *lod = NULL, *shd = NULL;
1693    unsigned int s, c, d;
1694    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1695
1696    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1697
1698    for (s = 0; s < tgt.getArgCount(); ++s)
1699       arg[s] = src[s] = fetchSrc(0, s);
1700
1701    if (texi->op == OP_TXL || texi->op == OP_TXB)
1702       lod = fetchSrc(L >> 4, L & 3);
1703
1704    if (C == 0x0f)
1705       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1706
1707    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
1708        tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
1709       shd = fetchSrc(1, 0);
1710    else if (tgt.isShadow())
1711       shd = fetchSrc(C >> 4, C & 3);
1712
1713    if (texi->op == OP_TXD) {
1714       for (c = 0; c < tgt.getDim(); ++c) {
1715          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1716          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1717       }
1718    }
1719
1720    // cube textures don't care about projection value, it's divided out
1721    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1722       unsigned int n = tgt.getDim();
1723       if (shd) {
1724          arg[n] = shd;
1725          ++n;
1726          assert(tgt.getDim() == tgt.getArgCount());
1727       }
1728       loadProjTexCoords(src, arg, (1 << n) - 1);
1729       if (shd)
1730          shd = src[n - 1];
1731    }
1732
1733    if (tgt.isCube()) {
1734       for (c = 0; c < 3; ++c)
1735          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1736       val = getScratch();
1737       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1738       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1739       mkOp1(OP_RCP, TYPE_F32, val, val);
1740       for (c = 0; c < 3; ++c)
1741          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1742    }
1743
1744    for (c = 0, d = 0; c < 4; ++c) {
1745       if (dst[c]) {
1746          texi->setDef(d++, dst[c]);
1747          texi->tex.mask |= 1 << c;
1748       } else {
1749          // NOTE: maybe hook up def too, for CSE
1750       }
1751    }
1752    for (s = 0; s < tgt.getArgCount(); ++s)
1753       texi->setSrc(s, src[s]);
1754    if (lod)
1755       texi->setSrc(s++, lod);
1756    if (shd)
1757       texi->setSrc(s++, shd);
1758
1759    setTexRS(texi, s, R, S);
1760
1761    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1762       texi->tex.levelZero = true;
1763    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
1764       texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
1765
1766    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1767    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1768       for (c = 0; c < 3; ++c) {
1769          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1770          texi->offset[s][c].setInsn(texi);
1771       }
1772    }
1773
1774    bb->insertTail(texi);
1775 }
1776
1777 // 1st source: xyz = coordinates, w = lod/sample
1778 // 2nd source: offset
1779 void
1780 Converter::handleTXF(Value *dst[4], int R, int L_M)
1781 {
1782    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1783    int ms;
1784    unsigned int c, d, s;
1785
1786    texi->tex.target = tgsi.getTexture(code, R);
1787
1788    ms = texi->tex.target.isMS() ? 1 : 0;
1789    texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1790
1791    for (c = 0, d = 0; c < 4; ++c) {
1792       if (dst[c]) {
1793          texi->setDef(d++, dst[c]);
1794          texi->tex.mask |= 1 << c;
1795       }
1796    }
1797    for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1798       texi->setSrc(c, fetchSrc(0, c));
1799    texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1800
1801    setTexRS(texi, c, R, -1);
1802
1803    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1804    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1805       for (c = 0; c < 3; ++c) {
1806          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1807          texi->offset[s][c].setInsn(texi);
1808       }
1809    }
1810
1811    bb->insertTail(texi);
1812 }
1813
1814 void
1815 Converter::handleLIT(Value *dst0[4])
1816 {
1817    Value *val0 = NULL;
1818    unsigned int mask = tgsi.getDst(0).getMask();
1819
1820    if (mask & (1 << 0))
1821       loadImm(dst0[0], 1.0f);
1822
1823    if (mask & (1 << 3))
1824       loadImm(dst0[3], 1.0f);
1825
1826    if (mask & (3 << 1)) {
1827       val0 = getScratch();
1828       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1829       if (mask & (1 << 1))
1830          mkMov(dst0[1], val0);
1831    }
1832
1833    if (mask & (1 << 2)) {
1834       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1835       Value *val1 = getScratch(), *val3 = getScratch();
1836
1837       Value *pos128 = loadImm(NULL, +127.999999f);
1838       Value *neg128 = loadImm(NULL, -127.999999f);
1839
1840       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1841       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1842       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1843       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1844
1845       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
1846    }
1847 }
1848
1849 static inline bool
1850 isResourceSpecial(const int r)
1851 {
1852    return (r == TGSI_RESOURCE_GLOBAL ||
1853            r == TGSI_RESOURCE_LOCAL ||
1854            r == TGSI_RESOURCE_PRIVATE ||
1855            r == TGSI_RESOURCE_INPUT);
1856 }
1857
1858 static inline bool
1859 isResourceRaw(const struct tgsi::Source *code, const int r)
1860 {
1861    return isResourceSpecial(r) || code->resources[r].raw;
1862 }
1863
1864 static inline nv50_ir::TexTarget
1865 getResourceTarget(const struct tgsi::Source *code, int r)
1866 {
1867    if (isResourceSpecial(r))
1868       return nv50_ir::TEX_TARGET_BUFFER;
1869    return tgsi::translateTexture(code->resources.at(r).target);
1870 }
1871
1872 Symbol *
1873 Converter::getResourceBase(const int r)
1874 {
1875    Symbol *sym = NULL;
1876
1877    switch (r) {
1878    case TGSI_RESOURCE_GLOBAL:
1879       sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1880       break;
1881    case TGSI_RESOURCE_LOCAL:
1882       assert(prog->getType() == Program::TYPE_COMPUTE);
1883       sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1884                      info->prop.cp.sharedOffset);
1885       break;
1886    case TGSI_RESOURCE_PRIVATE:
1887       sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1888                      info->bin.tlsSpace);
1889       break;
1890    case TGSI_RESOURCE_INPUT:
1891       assert(prog->getType() == Program::TYPE_COMPUTE);
1892       sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1893                      info->prop.cp.inputOffset);
1894       break;
1895    default:
1896       sym = new_Symbol(prog,
1897                        nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1898       break;
1899    }
1900    return sym;
1901 }
1902
1903 void
1904 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
1905 {
1906    const int arg =
1907       TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
1908
1909    for (int c = 0; c < arg; ++c)
1910       coords.push_back(fetchSrc(s, c));
1911
1912    // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
1913    if (r == TGSI_RESOURCE_LOCAL ||
1914        r == TGSI_RESOURCE_PRIVATE ||
1915        r == TGSI_RESOURCE_INPUT)
1916       coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
1917                          coords[0]);
1918 }
1919
1920 static inline int
1921 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
1922 {
1923    int n = 0;
1924
1925    while (mask) {
1926       if (mask & 1) {
1927          size[n]++;
1928       } else {
1929          if (size[n])
1930             comp[n = 1] = size[0] + 1;
1931          else
1932             comp[n]++;
1933       }
1934       mask >>= 1;
1935    }
1936    if (size[0] == 3) {
1937       n = 1;
1938       size[0] = (comp[0] == 1) ? 1 : 2;
1939       size[1] = 3 - size[0];
1940       comp[1] = comp[0] + size[0];
1941    }
1942    return n + 1;
1943 }
1944
1945 // For raw loads, granularity is 4 byte.
1946 // Usage of the texture read mask on OP_SULDP is not allowed.
1947 void
1948 Converter::handleLOAD(Value *dst0[4])
1949 {
1950    const int r = tgsi.getSrc(0).getIndex(0);
1951    int c;
1952    std::vector<Value *> off, src, ldv, def;
1953
1954    getResourceCoords(off, r, 1);
1955
1956    if (isResourceRaw(code, r)) {
1957       uint8_t mask = 0;
1958       uint8_t comp[2] = { 0, 0 };
1959       uint8_t size[2] = { 0, 0 };
1960
1961       Symbol *base = getResourceBase(r);
1962
1963       // determine the base and size of the at most 2 load ops
1964       for (c = 0; c < 4; ++c)
1965          if (!tgsi.getDst(0).isMasked(c))
1966             mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
1967
1968       int n = partitionLoadStore(comp, size, mask);
1969
1970       src = off;
1971
1972       def.resize(4); // index by component, the ones we need will be non-NULL
1973       for (c = 0; c < 4; ++c) {
1974          if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
1975             def[c] = dst0[c];
1976          else
1977          if (mask & (1 << c))
1978             def[c] = getScratch();
1979       }
1980
1981       const bool useLd = isResourceSpecial(r) ||
1982          (info->io.nv50styleSurfaces &&
1983           code->resources[r].target == TGSI_TEXTURE_BUFFER);
1984
1985       for (int i = 0; i < n; ++i) {
1986          ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
1987
1988          if (comp[i]) // adjust x component of source address if necessary
1989             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
1990                             off[0], mkImm(comp[i] * 4));
1991          else
1992             src[0] = off[0];
1993
1994          if (useLd) {
1995             Instruction *ld =
1996                mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
1997             for (size_t c = 1; c < ldv.size(); ++c)
1998                ld->setDef(c, ldv[c]);
1999          } else {
2000             mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2001                   0, ldv, src)->dType = typeOfSize(size[i] * 4);
2002          }
2003       }
2004    } else {
2005       def.resize(4);
2006       for (c = 0; c < 4; ++c) {
2007          if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2008             def[c] = getScratch();
2009          else
2010             def[c] = dst0[c];
2011       }
2012
2013       mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2014             def, off);
2015    }
2016    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2017       if (dst0[c] != def[c])
2018          mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2019 }
2020
2021 // For formatted stores, the write mask on OP_SUSTP can be used.
2022 // Raw stores have to be split.
2023 void
2024 Converter::handleSTORE()
2025 {
2026    const int r = tgsi.getDst(0).getIndex(0);
2027    int c;
2028    std::vector<Value *> off, src, dummy;
2029
2030    getResourceCoords(off, r, 0);
2031    src = off;
2032    const int s = src.size();
2033
2034    if (isResourceRaw(code, r)) {
2035       uint8_t comp[2] = { 0, 0 };
2036       uint8_t size[2] = { 0, 0 };
2037
2038       int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2039
2040       Symbol *base = getResourceBase(r);
2041
2042       const bool useSt = isResourceSpecial(r) ||
2043          (info->io.nv50styleSurfaces &&
2044           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2045
2046       for (int i = 0; i < n; ++i) {
2047          if (comp[i]) // adjust x component of source address if necessary
2048             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2049                             off[0], mkImm(comp[i] * 4));
2050          else
2051             src[0] = off[0];
2052
2053          const DataType stTy = typeOfSize(size[i] * 4);
2054
2055          if (useSt) {
2056             Instruction *st =
2057                mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2058             for (c = 1; c < size[i]; ++c)
2059                st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2060             st->setIndirect(0, 0, src[0]);
2061          } else {
2062             // attach values to be stored
2063             src.resize(s + size[i]);
2064             for (c = 0; c < size[i]; ++c)
2065                src[s + c] = fetchSrc(1, comp[i] + c);
2066             mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2067                   0, dummy, src)->setType(stTy);
2068          }
2069       }
2070    } else {
2071       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2072          src.push_back(fetchSrc(1, c));
2073
2074       mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2075             dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2076    }
2077 }
2078
2079 // XXX: These only work on resources with the single-component u32/s32 formats.
2080 // Therefore the result is replicated. This might not be intended by TGSI, but
2081 // operating on more than 1 component would produce undefined results because
2082 // they do not exist.
2083 void
2084 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2085 {
2086    const int r = tgsi.getSrc(0).getIndex(0);
2087    std::vector<Value *> srcv;
2088    std::vector<Value *> defv;
2089    LValue *dst = getScratch();
2090
2091    getResourceCoords(srcv, r, 1);
2092
2093    if (isResourceSpecial(r)) {
2094       assert(r != TGSI_RESOURCE_INPUT);
2095       Instruction *insn;
2096       insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2097       insn->subOp = subOp;
2098       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2099          insn->setSrc(2, fetchSrc(3, 0));
2100       insn->setIndirect(0, 0, srcv.at(0));
2101    } else {
2102       operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2103       TexTarget targ = getResourceTarget(code, r);
2104       int idx = code->resources[r].slot;
2105       defv.push_back(dst);
2106       srcv.push_back(fetchSrc(2, 0));
2107       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2108          srcv.push_back(fetchSrc(3, 0));
2109       TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2110       tex->subOp = subOp;
2111       tex->tex.mask = 1;
2112       tex->setType(ty);
2113    }
2114
2115    for (int c = 0; c < 4; ++c)
2116       if (dst0[c])
2117          dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2118 }
2119
2120 Converter::Subroutine *
2121 Converter::getSubroutine(unsigned ip)
2122 {
2123    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2124
2125    if (it == sub.map.end())
2126       it = sub.map.insert(std::make_pair(
2127               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2128
2129    return &it->second;
2130 }
2131
2132 Converter::Subroutine *
2133 Converter::getSubroutine(Function *f)
2134 {
2135    unsigned ip = f->getLabel();
2136    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2137
2138    if (it == sub.map.end())
2139       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2140
2141    return &it->second;
2142 }
2143
2144 bool
2145 Converter::isEndOfSubroutine(uint ip)
2146 {
2147    assert(ip < code->scan.num_instructions);
2148    tgsi::Instruction insn(&code->insns[ip]);
2149    return (insn.getOpcode() == TGSI_OPCODE_END ||
2150            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2151            // does END occur at end of main or the very end ?
2152            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2153 }
2154
2155 bool
2156 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2157 {
2158    Instruction *geni;
2159
2160    Value *dst0[4], *rDst0[4];
2161    Value *src0, *src1, *src2, *src3;
2162    Value *val0, *val1;
2163    int c;
2164
2165    tgsi = tgsi::Instruction(insn);
2166
2167    bool useScratchDst = tgsi.checkDstSrcAliasing();
2168
2169    operation op = tgsi.getOP();
2170    dstTy = tgsi.inferDstType();
2171    srcTy = tgsi.inferSrcType();
2172
2173    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2174
2175    if (tgsi.dstCount()) {
2176       for (c = 0; c < 4; ++c) {
2177          rDst0[c] = acquireDst(0, c);
2178          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2179       }
2180    }
2181
2182    switch (tgsi.getOpcode()) {
2183    case TGSI_OPCODE_ADD:
2184    case TGSI_OPCODE_UADD:
2185    case TGSI_OPCODE_AND:
2186    case TGSI_OPCODE_DIV:
2187    case TGSI_OPCODE_IDIV:
2188    case TGSI_OPCODE_UDIV:
2189    case TGSI_OPCODE_MAX:
2190    case TGSI_OPCODE_MIN:
2191    case TGSI_OPCODE_IMAX:
2192    case TGSI_OPCODE_IMIN:
2193    case TGSI_OPCODE_UMAX:
2194    case TGSI_OPCODE_UMIN:
2195    case TGSI_OPCODE_MOD:
2196    case TGSI_OPCODE_UMOD:
2197    case TGSI_OPCODE_MUL:
2198    case TGSI_OPCODE_UMUL:
2199    case TGSI_OPCODE_IMUL_HI:
2200    case TGSI_OPCODE_UMUL_HI:
2201    case TGSI_OPCODE_OR:
2202    case TGSI_OPCODE_SHL:
2203    case TGSI_OPCODE_ISHR:
2204    case TGSI_OPCODE_USHR:
2205    case TGSI_OPCODE_SUB:
2206    case TGSI_OPCODE_XOR:
2207       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2208          src0 = fetchSrc(0, c);
2209          src1 = fetchSrc(1, c);
2210          geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2211          geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2212       }
2213       break;
2214    case TGSI_OPCODE_MAD:
2215    case TGSI_OPCODE_UMAD:
2216    case TGSI_OPCODE_SAD:
2217       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2218          src0 = fetchSrc(0, c);
2219          src1 = fetchSrc(1, c);
2220          src2 = fetchSrc(2, c);
2221          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2222       }
2223       break;
2224    case TGSI_OPCODE_MOV:
2225    case TGSI_OPCODE_ABS:
2226    case TGSI_OPCODE_CEIL:
2227    case TGSI_OPCODE_FLR:
2228    case TGSI_OPCODE_TRUNC:
2229    case TGSI_OPCODE_RCP:
2230    case TGSI_OPCODE_IABS:
2231    case TGSI_OPCODE_INEG:
2232    case TGSI_OPCODE_NOT:
2233    case TGSI_OPCODE_DDX:
2234    case TGSI_OPCODE_DDY:
2235       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2236          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2237       break;
2238    case TGSI_OPCODE_RSQ:
2239       src0 = fetchSrc(0, 0);
2240       val0 = getScratch();
2241       mkOp1(OP_ABS, TYPE_F32, val0, src0);
2242       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2243       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2244          mkMov(dst0[c], val0);
2245       break;
2246    case TGSI_OPCODE_ARL:
2247       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2248          src0 = fetchSrc(0, c);
2249          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
2250       }
2251       break;
2252    case TGSI_OPCODE_UARL:
2253       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2254          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2255       break;
2256    case TGSI_OPCODE_POW:
2257       val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
2258       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2259          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2260       break;
2261    case TGSI_OPCODE_EX2:
2262    case TGSI_OPCODE_LG2:
2263       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2264       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2265          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2266       break;
2267    case TGSI_OPCODE_COS:
2268    case TGSI_OPCODE_SIN:
2269       val0 = getScratch();
2270       if (mask & 7) {
2271          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2272          mkOp1(op, TYPE_F32, val0, val0);
2273          for (c = 0; c < 3; ++c)
2274             if (dst0[c])
2275                mkMov(dst0[c], val0);
2276       }
2277       if (dst0[3]) {
2278          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2279          mkOp1(op, TYPE_F32, dst0[3], val0);
2280       }
2281       break;
2282    case TGSI_OPCODE_SCS:
2283       if (mask & 3) {
2284          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2285          if (dst0[0])
2286             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2287          if (dst0[1])
2288             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2289       }
2290       if (dst0[2])
2291          loadImm(dst0[2], 0.0f);
2292       if (dst0[3])
2293          loadImm(dst0[3], 1.0f);
2294       break;
2295    case TGSI_OPCODE_EXP:
2296       src0 = fetchSrc(0, 0);
2297       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2298       if (dst0[1])
2299          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2300       if (dst0[0])
2301          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2302       if (dst0[2])
2303          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2304       if (dst0[3])
2305          loadImm(dst0[3], 1.0f);
2306       break;
2307    case TGSI_OPCODE_LOG:
2308       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2309       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2310       if (dst0[0] || dst0[1])
2311          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2312       if (dst0[1]) {
2313          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2314          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2315          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2316       }
2317       if (dst0[3])
2318          loadImm(dst0[3], 1.0f);
2319       break;
2320    case TGSI_OPCODE_DP2:
2321       val0 = buildDot(2);
2322       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2323          mkMov(dst0[c], val0);
2324       break;
2325    case TGSI_OPCODE_DP3:
2326       val0 = buildDot(3);
2327       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2328          mkMov(dst0[c], val0);
2329       break;
2330    case TGSI_OPCODE_DP4:
2331       val0 = buildDot(4);
2332       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2333          mkMov(dst0[c], val0);
2334       break;
2335    case TGSI_OPCODE_DPH:
2336       val0 = buildDot(3);
2337       src1 = fetchSrc(1, 3);
2338       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2339       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2340          mkMov(dst0[c], val0);
2341       break;
2342    case TGSI_OPCODE_DST:
2343       if (dst0[0])
2344          loadImm(dst0[0], 1.0f);
2345       if (dst0[1]) {
2346          src0 = fetchSrc(0, 1);
2347          src1 = fetchSrc(1, 1);
2348          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2349       }
2350       if (dst0[2])
2351          mkMov(dst0[2], fetchSrc(0, 2));
2352       if (dst0[3])
2353          mkMov(dst0[3], fetchSrc(1, 3));
2354       break;
2355    case TGSI_OPCODE_LRP:
2356       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2357          src0 = fetchSrc(0, c);
2358          src1 = fetchSrc(1, c);
2359          src2 = fetchSrc(2, c);
2360          mkOp3(OP_MAD, TYPE_F32, dst0[c],
2361                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2362       }
2363       break;
2364    case TGSI_OPCODE_LIT:
2365       handleLIT(dst0);
2366       break;
2367    case TGSI_OPCODE_XPD:
2368       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2369          if (c < 3) {
2370             val0 = getSSA();
2371             src0 = fetchSrc(1, (c + 1) % 3);
2372             src1 = fetchSrc(0, (c + 2) % 3);
2373             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2374             mkOp1(OP_NEG, TYPE_F32, val0, val0);
2375
2376             src0 = fetchSrc(0, (c + 1) % 3);
2377             src1 = fetchSrc(1, (c + 2) % 3);
2378             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2379          } else {
2380             loadImm(dst0[c], 1.0f);
2381          }
2382       }
2383       break;
2384    case TGSI_OPCODE_ISSG:
2385    case TGSI_OPCODE_SSG:
2386       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2387          src0 = fetchSrc(0, c);
2388          val0 = getScratch();
2389          val1 = getScratch();
2390          mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2391          mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2392          if (srcTy == TYPE_F32)
2393             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2394          else
2395             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2396       }
2397       break;
2398    case TGSI_OPCODE_UCMP:
2399    case TGSI_OPCODE_CMP:
2400       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2401          src0 = fetchSrc(0, c);
2402          src1 = fetchSrc(1, c);
2403          src2 = fetchSrc(2, c);
2404          if (src1 == src2)
2405             mkMov(dst0[c], src1);
2406          else
2407             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2408                   srcTy, dst0[c], srcTy, src1, src2, src0);
2409       }
2410       break;
2411    case TGSI_OPCODE_FRC:
2412       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2413          src0 = fetchSrc(0, c);
2414          val0 = getScratch();
2415          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2416          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2417       }
2418       break;
2419    case TGSI_OPCODE_ROUND:
2420       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2421          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2422          ->rnd = ROUND_NI;
2423       break;
2424    case TGSI_OPCODE_CLAMP:
2425       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2426          src0 = fetchSrc(0, c);
2427          src1 = fetchSrc(1, c);
2428          src2 = fetchSrc(2, c);
2429          val0 = getScratch();
2430          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2431          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2432       }
2433       break;
2434    case TGSI_OPCODE_SLT:
2435    case TGSI_OPCODE_SGE:
2436    case TGSI_OPCODE_SEQ:
2437    case TGSI_OPCODE_SFL:
2438    case TGSI_OPCODE_SGT:
2439    case TGSI_OPCODE_SLE:
2440    case TGSI_OPCODE_SNE:
2441    case TGSI_OPCODE_STR:
2442    case TGSI_OPCODE_FSEQ:
2443    case TGSI_OPCODE_FSGE:
2444    case TGSI_OPCODE_FSLT:
2445    case TGSI_OPCODE_FSNE:
2446    case TGSI_OPCODE_ISGE:
2447    case TGSI_OPCODE_ISLT:
2448    case TGSI_OPCODE_USEQ:
2449    case TGSI_OPCODE_USGE:
2450    case TGSI_OPCODE_USLT:
2451    case TGSI_OPCODE_USNE:
2452       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2453          src0 = fetchSrc(0, c);
2454          src1 = fetchSrc(1, c);
2455          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2456       }
2457       break;
2458    case TGSI_OPCODE_KILL_IF:
2459       val0 = new_LValue(func, FILE_PREDICATE);
2460       for (c = 0; c < 4; ++c) {
2461          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2462          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2463       }
2464       break;
2465    case TGSI_OPCODE_KILL:
2466       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2467       break;
2468    case TGSI_OPCODE_TEX:
2469    case TGSI_OPCODE_TXB:
2470    case TGSI_OPCODE_TXL:
2471    case TGSI_OPCODE_TXP:
2472    case TGSI_OPCODE_LODQ:
2473       //              R  S     L     C    Dx    Dy
2474       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2475       break;
2476    case TGSI_OPCODE_TXD:
2477       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2478       break;
2479    case TGSI_OPCODE_TG4:
2480       handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
2481       break;
2482    case TGSI_OPCODE_TEX2:
2483       handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2484       break;
2485    case TGSI_OPCODE_TXB2:
2486    case TGSI_OPCODE_TXL2:
2487       handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
2488       break;
2489    case TGSI_OPCODE_SAMPLE:
2490    case TGSI_OPCODE_SAMPLE_B:
2491    case TGSI_OPCODE_SAMPLE_D:
2492    case TGSI_OPCODE_SAMPLE_L:
2493    case TGSI_OPCODE_SAMPLE_C:
2494    case TGSI_OPCODE_SAMPLE_C_LZ:
2495       handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2496       break;
2497    case TGSI_OPCODE_TXF:
2498       handleTXF(dst0, 1, 0x03);
2499       break;
2500    case TGSI_OPCODE_SAMPLE_I:
2501       handleTXF(dst0, 1, 0x03);
2502       break;
2503    case TGSI_OPCODE_SAMPLE_I_MS:
2504       handleTXF(dst0, 1, 0x20);
2505       break;
2506    case TGSI_OPCODE_TXQ:
2507    case TGSI_OPCODE_SVIEWINFO:
2508       handleTXQ(dst0, TXQ_DIMS);
2509       break;
2510    case TGSI_OPCODE_F2I:
2511    case TGSI_OPCODE_F2U:
2512       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2513          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2514       break;
2515    case TGSI_OPCODE_I2F:
2516    case TGSI_OPCODE_U2F:
2517       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2518          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2519       break;
2520    case TGSI_OPCODE_EMIT:
2521    case TGSI_OPCODE_ENDPRIM:
2522       // get vertex stream if specified (must be immediate)
2523       src0 = tgsi.srcCount() ?
2524          mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2525       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2526       break;
2527    case TGSI_OPCODE_IF:
2528    case TGSI_OPCODE_UIF:
2529    {
2530       BasicBlock *ifBB = new BasicBlock(func);
2531
2532       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2533       condBBs.push(bb);
2534       joinBBs.push(bb);
2535
2536       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2537
2538       setPosition(ifBB, true);
2539    }
2540       break;
2541    case TGSI_OPCODE_ELSE:
2542    {
2543       BasicBlock *elseBB = new BasicBlock(func);
2544       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2545
2546       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2547       condBBs.push(bb);
2548
2549       forkBB->getExit()->asFlow()->target.bb = elseBB;
2550       if (!bb->isTerminated())
2551          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2552
2553       setPosition(elseBB, true);
2554    }
2555       break;
2556    case TGSI_OPCODE_ENDIF:
2557    {
2558       BasicBlock *convBB = new BasicBlock(func);
2559       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2560       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2561
2562       if (!bb->isTerminated()) {
2563          // we only want join if none of the clauses ended with CONT/BREAK/RET
2564          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2565             insertConvergenceOps(convBB, forkBB);
2566          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2567          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2568       }
2569
2570       if (prevBB->getExit()->op == OP_BRA) {
2571          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2572          prevBB->getExit()->asFlow()->target.bb = convBB;
2573       }
2574       setPosition(convBB, true);
2575    }
2576       break;
2577    case TGSI_OPCODE_BGNLOOP:
2578    {
2579       BasicBlock *lbgnBB = new BasicBlock(func);
2580       BasicBlock *lbrkBB = new BasicBlock(func);
2581
2582       loopBBs.push(lbgnBB);
2583       breakBBs.push(lbrkBB);
2584       if (loopBBs.getSize() > func->loopNestingBound)
2585          func->loopNestingBound++;
2586
2587       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2588
2589       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2590       setPosition(lbgnBB, true);
2591       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2592    }
2593       break;
2594    case TGSI_OPCODE_ENDLOOP:
2595    {
2596       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2597
2598       if (!bb->isTerminated()) {
2599          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2600          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2601       }
2602       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2603    }
2604       break;
2605    case TGSI_OPCODE_BRK:
2606    {
2607       if (bb->isTerminated())
2608          break;
2609       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2610       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2611       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2612    }
2613       break;
2614    case TGSI_OPCODE_CONT:
2615    {
2616       if (bb->isTerminated())
2617          break;
2618       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2619       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2620       contBB->explicitCont = true;
2621       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2622    }
2623       break;
2624    case TGSI_OPCODE_BGNSUB:
2625    {
2626       Subroutine *s = getSubroutine(ip);
2627       BasicBlock *entry = new BasicBlock(s->f);
2628       BasicBlock *leave = new BasicBlock(s->f);
2629
2630       // multiple entrypoints possible, keep the graph connected
2631       if (prog->getType() == Program::TYPE_COMPUTE)
2632          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2633
2634       sub.cur = s;
2635       s->f->setEntry(entry);
2636       s->f->setExit(leave);
2637       setPosition(entry, true);
2638       return true;
2639    }
2640    case TGSI_OPCODE_ENDSUB:
2641    {
2642       sub.cur = getSubroutine(prog->main);
2643       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2644       return true;
2645    }
2646    case TGSI_OPCODE_CAL:
2647    {
2648       Subroutine *s = getSubroutine(tgsi.getLabel());
2649       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2650       func->call.attach(&s->f->call, Graph::Edge::TREE);
2651       return true;
2652    }
2653    case TGSI_OPCODE_RET:
2654    {
2655       if (bb->isTerminated())
2656          return true;
2657       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2658
2659       if (!isEndOfSubroutine(ip + 1)) {
2660          // insert a PRERET at the entry if this is an early return
2661          // (only needed for sharing code in the epilogue)
2662          BasicBlock *pos = getBB();
2663          setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2664          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2665          setPosition(pos, true);
2666       }
2667       mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2668       bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2669    }
2670       break;
2671    case TGSI_OPCODE_END:
2672    {
2673       // attach and generate epilogue code
2674       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2675       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2676       setPosition(epilogue, true);
2677       if (prog->getType() == Program::TYPE_FRAGMENT)
2678          exportOutputs();
2679       if (info->io.genUserClip > 0)
2680          handleUserClipPlanes();
2681       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2682    }
2683       break;
2684    case TGSI_OPCODE_SWITCH:
2685    case TGSI_OPCODE_CASE:
2686       ERROR("switch/case opcode encountered, should have been lowered\n");
2687       abort();
2688       break;
2689    case TGSI_OPCODE_LOAD:
2690       handleLOAD(dst0);
2691       break;
2692    case TGSI_OPCODE_STORE:
2693       handleSTORE();
2694       break;
2695    case TGSI_OPCODE_BARRIER:
2696       geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2697       geni->fixed = 1;
2698       geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2699       break;
2700    case TGSI_OPCODE_MFENCE:
2701    case TGSI_OPCODE_LFENCE:
2702    case TGSI_OPCODE_SFENCE:
2703       geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2704       geni->fixed = 1;
2705       geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2706       break;
2707    case TGSI_OPCODE_ATOMUADD:
2708    case TGSI_OPCODE_ATOMXCHG:
2709    case TGSI_OPCODE_ATOMCAS:
2710    case TGSI_OPCODE_ATOMAND:
2711    case TGSI_OPCODE_ATOMOR:
2712    case TGSI_OPCODE_ATOMXOR:
2713    case TGSI_OPCODE_ATOMUMIN:
2714    case TGSI_OPCODE_ATOMIMIN:
2715    case TGSI_OPCODE_ATOMUMAX:
2716    case TGSI_OPCODE_ATOMIMAX:
2717       handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2718       break;
2719    case TGSI_OPCODE_IBFE:
2720    case TGSI_OPCODE_UBFE:
2721       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2722          src0 = fetchSrc(0, c);
2723          src1 = fetchSrc(1, c);
2724          src2 = fetchSrc(2, c);
2725          mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
2726          mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
2727       }
2728       break;
2729    case TGSI_OPCODE_BFI:
2730       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2731          src0 = fetchSrc(0, c);
2732          src1 = fetchSrc(1, c);
2733          src2 = fetchSrc(2, c);
2734          src3 = fetchSrc(3, c);
2735          mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
2736          mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
2737       }
2738       break;
2739    case TGSI_OPCODE_LSB:
2740       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2741          src0 = fetchSrc(0, c);
2742          geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
2743          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2744          geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
2745          geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2746       }
2747       break;
2748    case TGSI_OPCODE_IMSB:
2749    case TGSI_OPCODE_UMSB:
2750       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2751          src0 = fetchSrc(0, c);
2752          mkOp1(OP_BFIND, srcTy, dst0[c], src0);
2753       }
2754       break;
2755    case TGSI_OPCODE_BREV:
2756       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2757          src0 = fetchSrc(0, c);
2758          geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
2759          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2760       }
2761       break;
2762    case TGSI_OPCODE_POPC:
2763       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2764          src0 = fetchSrc(0, c);
2765          mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
2766       }
2767       break;
2768    default:
2769       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2770       assert(0);
2771       break;
2772    }
2773
2774    if (tgsi.dstCount()) {
2775       for (c = 0; c < 4; ++c) {
2776          if (!dst0[c])
2777             continue;
2778          if (dst0[c] != rDst0[c])
2779             mkMov(rDst0[c], dst0[c]);
2780          storeDst(0, c, rDst0[c]);
2781       }
2782    }
2783    vtxBaseValid = 0;
2784
2785    return true;
2786 }
2787
2788 void
2789 Converter::handleUserClipPlanes()
2790 {
2791    Value *res[8];
2792    int n, i, c;
2793
2794    for (c = 0; c < 4; ++c) {
2795       for (i = 0; i < info->io.genUserClip; ++i) {
2796          Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
2797                                 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
2798          Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
2799          if (c == 0)
2800             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2801          else
2802             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2803       }
2804    }
2805
2806    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2807
2808    for (i = 0; i < info->io.genUserClip; ++i) {
2809       n = i / 4 + first;
2810       c = i % 4;
2811       Symbol *sym =
2812          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2813       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2814    }
2815 }
2816
2817 void
2818 Converter::exportOutputs()
2819 {
2820    for (unsigned int i = 0; i < info->numOutputs; ++i) {
2821       for (unsigned int c = 0; c < 4; ++c) {
2822          if (!oData.exists(sub.cur->values, i, c))
2823             continue;
2824          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2825                                 info->out[i].slot[c] * 4);
2826          Value *val = oData.load(sub.cur->values, i, c, NULL);
2827          if (val)
2828             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2829       }
2830    }
2831 }
2832
2833 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2834      code(code),
2835      tgsi(NULL),
2836      tData(this), aData(this), pData(this), oData(this)
2837 {
2838    info = code->info;
2839
2840    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2841
2842    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2843    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2844    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2845    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2846
2847    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2848    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2849    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
2850    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2851
2852    zero = mkImm((uint32_t)0);
2853
2854    vtxBaseValid = 0;
2855 }
2856
2857 Converter::~Converter()
2858 {
2859 }
2860
2861 inline const Converter::Location *
2862 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
2863 {
2864    ValueMap::l_iterator it = s->values.l.find(v);
2865    return it == s->values.l.end() ? NULL : &it->second;
2866 }
2867
2868 template<typename T> inline void
2869 Converter::BindArgumentsPass::updateCallArgs(
2870    Instruction *i, void (Instruction::*setArg)(int, Value *),
2871    T (Function::*proto))
2872 {
2873    Function *g = i->asFlow()->target.fn;
2874    Subroutine *subg = conv.getSubroutine(g);
2875
2876    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2877       Value *v = (g->*proto)[a].get();
2878       const Converter::Location &l = *getValueLocation(subg, v);
2879       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2880
2881       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2882    }
2883 }
2884
2885 template<typename T> inline void
2886 Converter::BindArgumentsPass::updatePrototype(
2887    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2888 {
2889    (func->*updateSet)();
2890
2891    for (unsigned i = 0; i < set->getSize(); ++i) {
2892       Value *v = func->getLValue(i);
2893       const Converter::Location *l = getValueLocation(sub, v);
2894
2895       // only include values with a matching TGSI register
2896       if (set->test(i) && l && !conv.code->locals.count(*l))
2897          (func->*proto).push_back(v);
2898    }
2899 }
2900
2901 bool
2902 Converter::BindArgumentsPass::visit(Function *f)
2903 {
2904    sub = conv.getSubroutine(f);
2905
2906    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2907         !bi.end(); bi.next()) {
2908       for (Instruction *i = BasicBlock::get(bi)->getFirst();
2909            i; i = i->next) {
2910          if (i->op == OP_CALL && !i->asFlow()->builtin) {
2911             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2912             updateCallArgs(i, &Instruction::setDef, &Function::outs);
2913          }
2914       }
2915    }
2916
2917    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2918       return true;
2919    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2920                    &Function::buildLiveSets, &Function::ins);
2921    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2922                    &Function::buildDefSets, &Function::outs);
2923
2924    return true;
2925 }
2926
2927 bool
2928 Converter::run()
2929 {
2930    BasicBlock *entry = new BasicBlock(prog->main);
2931    BasicBlock *leave = new BasicBlock(prog->main);
2932
2933    prog->main->setEntry(entry);
2934    prog->main->setExit(leave);
2935
2936    setPosition(entry, true);
2937    sub.cur = getSubroutine(prog->main);
2938
2939    if (info->io.genUserClip > 0) {
2940       for (int c = 0; c < 4; ++c)
2941          clipVtx[c] = getScratch();
2942    }
2943
2944    if (prog->getType() == Program::TYPE_FRAGMENT) {
2945       Symbol *sv = mkSysVal(SV_POSITION, 3);
2946       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2947       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2948    }
2949
2950    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2951       if (!handleInstruction(&code->insns[ip]))
2952          return false;
2953    }
2954
2955    if (!BindArgumentsPass(*this).run(prog))
2956       return false;
2957
2958    return true;
2959 }
2960
2961 } // unnamed namespace
2962
2963 namespace nv50_ir {
2964
2965 bool
2966 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2967 {
2968    tgsi::Source src(info);
2969    if (!src.scanSource())
2970       return false;
2971    tlsSize = info->bin.tlsSpace;
2972
2973    Converter builder(this, &src);
2974    return builder.run();
2975 }
2976
2977 } // namespace nv50_ir