src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 extern "C" {
  24 #include "tgsi/tgsi_dump.h"
  25 #include "tgsi/tgsi_scan.h"
  26 #include "tgsi/tgsi_util.h"
  27 }
  28
  29 #include <set>
  30
  31 #include "codegen/nv50_ir.h"
  32 #include "codegen/nv50_ir_util.h"
  33 #include "codegen/nv50_ir_build_util.h"
  34
  35 namespace tgsi {
  36
  37 class Source;
  38
  39 static nv50_ir::operation translateOpcode(uint opcode);
  40 static nv50_ir::DataFile translateFile(uint file);
  41 static nv50_ir::TexTarget translateTexture(uint texTarg);
  42 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  43
  44 class Instruction
  45 {
  46 public:
  47    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  48
  49    class SrcRegister
  50    {
  51    public:
  52       SrcRegister(const struct tgsi_full_src_register *src)
  53          : reg(src->Register),
  54            fsr(src)
  55       { }
  56
  57       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  58
  59       SrcRegister(const struct tgsi_ind_register& ind)
  60          : reg(tgsi_util_get_src_from_ind(&ind)),
  61            fsr(NULL)
  62       { }
  63
  64       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  65       {
  66          struct tgsi_src_register reg;
  67          memset(&reg, 0, sizeof(reg));
  68          reg.Index = off.Index;
  69          reg.File = off.File;
  70          reg.SwizzleX = off.SwizzleX;
  71          reg.SwizzleY = off.SwizzleY;
  72          reg.SwizzleZ = off.SwizzleZ;
  73          return reg;
  74       }
  75
  76       SrcRegister(const struct tgsi_texture_offset& off) :
  77          reg(offsetToSrc(off)),
  78          fsr(NULL)
  79       { }
  80
  81       uint getFile() const { return reg.File; }
  82
  83       bool is2D() const { return reg.Dimension; }
  84
  85       bool isIndirect(int dim) const
  86       {
  87          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  88       }
  89
  90       int getIndex(int dim) const
  91       {
  92          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  93       }
  94
  95       int getSwizzle(int chan) const
  96       {
  97          return tgsi_util_get_src_register_swizzle(&reg, chan);
  98       }
  99
 100       nv50_ir::Modifier getMod(int chan) const;
 101
 102       SrcRegister getIndirect(int dim) const
 103       {
 104          assert(fsr && isIndirect(dim));
 105          if (dim)
 106             return SrcRegister(fsr->DimIndirect);
 107          return SrcRegister(fsr->Indirect);
 108       }
 109
 110       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 111       {
 112          assert(reg.File == TGSI_FILE_IMMEDIATE);
 113          assert(!reg.Absolute);
 114          assert(!reg.Negate);
 115          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 116       }
 117
 118    private:
 119       const struct tgsi_src_register reg;
 120       const struct tgsi_full_src_register *fsr;
 121    };
 122
 123    class DstRegister
 124    {
 125    public:
 126       DstRegister(const struct tgsi_full_dst_register *dst)
 127          : reg(dst->Register),
 128            fdr(dst)
 129       { }
 130
 131       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 132
 133       uint getFile() const { return reg.File; }
 134
 135       bool is2D() const { return reg.Dimension; }
 136
 137       bool isIndirect(int dim) const
 138       {
 139          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 140       }
 141
 142       int getIndex(int dim) const
 143       {
 144          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 145       }
 146
 147       unsigned int getMask() const { return reg.WriteMask; }
 148
 149       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 150
 151       SrcRegister getIndirect(int dim) const
 152       {
 153          assert(fdr && isIndirect(dim));
 154          if (dim)
 155             return SrcRegister(fdr->DimIndirect);
 156          return SrcRegister(fdr->Indirect);
 157       }
 158
 159    private:
 160       const struct tgsi_dst_register reg;
 161       const struct tgsi_full_dst_register *fdr;
 162    };
 163
 164    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 165
 166    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 167    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 168
 169    // mask of used components of source s
 170    unsigned int srcMask(unsigned int s) const;
 171
 172    SrcRegister getSrc(unsigned int s) const
 173    {
 174       assert(s < srcCount());
 175       return SrcRegister(&insn->Src[s]);
 176    }
 177
 178    DstRegister getDst(unsigned int d) const
 179    {
 180       assert(d < dstCount());
 181       return DstRegister(&insn->Dst[d]);
 182    }
 183
 184    SrcRegister getTexOffset(unsigned int i) const
 185    {
 186       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 187       return SrcRegister(insn->TexOffsets[i]);
 188    }
 189
 190    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 191
 192    bool checkDstSrcAliasing() const;
 193
 194    inline nv50_ir::operation getOP() const {
 195       return translateOpcode(getOpcode()); }
 196
 197    nv50_ir::DataType inferSrcType() const;
 198    nv50_ir::DataType inferDstType() const;
 199
 200    nv50_ir::CondCode getSetCond() const;
 201
 202    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 203
 204    inline uint getLabel() { return insn->Label.Label; }
 205
 206    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 207
 208    void print() const
 209    {
 210       tgsi_dump_instruction(insn, 1);
 211    }
 212
 213 private:
 214    const struct tgsi_full_instruction *insn;
 215 };
 216
 217 unsigned int Instruction::srcMask(unsigned int s) const
 218 {
 219    unsigned int mask = insn->Dst[0].Register.WriteMask;
 220
 221    switch (insn->Instruction.Opcode) {
 222    case TGSI_OPCODE_COS:
 223    case TGSI_OPCODE_SIN:
 224       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 225    case TGSI_OPCODE_DP2:
 226       return 0x3;
 227    case TGSI_OPCODE_DP3:
 228       return 0x7;
 229    case TGSI_OPCODE_DP4:
 230    case TGSI_OPCODE_DPH:
 231    case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
 232       return 0xf;
 233    case TGSI_OPCODE_DST:
 234       return mask & (s ? 0xa : 0x6);
 235    case TGSI_OPCODE_EX2:
 236    case TGSI_OPCODE_EXP:
 237    case TGSI_OPCODE_LG2:
 238    case TGSI_OPCODE_LOG:
 239    case TGSI_OPCODE_POW:
 240    case TGSI_OPCODE_RCP:
 241    case TGSI_OPCODE_RSQ:
 242    case TGSI_OPCODE_SCS:
 243       return 0x1;
 244    case TGSI_OPCODE_IF:
 245    case TGSI_OPCODE_UIF:
 246       return 0x1;
 247    case TGSI_OPCODE_LIT:
 248       return 0xb;
 249    case TGSI_OPCODE_TEX2:
 250    case TGSI_OPCODE_TXB2:
 251    case TGSI_OPCODE_TXL2:
 252       return (s == 0) ? 0xf : 0x3;
 253    case TGSI_OPCODE_TEX:
 254    case TGSI_OPCODE_TXB:
 255    case TGSI_OPCODE_TXD:
 256    case TGSI_OPCODE_TXL:
 257    case TGSI_OPCODE_TXP:
 258    {
 259       const struct tgsi_instruction_texture *tex = &insn->Texture;
 260
 261       assert(insn->Instruction.Texture);
 262
 263       mask = 0x7;
 264       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 265           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 266          mask |= 0x8; /* bias, lod or proj */
 267
 268       switch (tex->Texture) {
 269       case TGSI_TEXTURE_1D:
 270          mask &= 0x9;
 271          break;
 272       case TGSI_TEXTURE_SHADOW1D:
 273          mask &= 0xd;
 274          break;
 275       case TGSI_TEXTURE_1D_ARRAY:
 276       case TGSI_TEXTURE_2D:
 277       case TGSI_TEXTURE_RECT:
 278          mask &= 0xb;
 279          break;
 280       case TGSI_TEXTURE_CUBE_ARRAY:
 281       case TGSI_TEXTURE_SHADOW2D_ARRAY:
 282       case TGSI_TEXTURE_SHADOWCUBE:
 283       case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
 284          mask |= 0x8;
 285          break;
 286       default:
 287          break;
 288       }
 289    }
 290       return mask;
 291    case TGSI_OPCODE_XPD:
 292    {
 293       unsigned int x = 0;
 294       if (mask & 1) x |= 0x6;
 295       if (mask & 2) x |= 0x5;
 296       if (mask & 4) x |= 0x3;
 297       return x;
 298    }
 299    default:
 300       break;
 301    }
 302
 303    return mask;
 304 }
 305
 306 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 307 {
 308    nv50_ir::Modifier m(0);
 309
 310    if (reg.Absolute)
 311       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 312    if (reg.Negate)
 313       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 314    return m;
 315 }
 316
 317 static nv50_ir::DataFile translateFile(uint file)
 318 {
 319    switch (file) {
 320    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 321    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 322    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 323    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 324    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 325    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 326    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 327    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 328    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 329    case TGSI_FILE_SAMPLER:
 330    case TGSI_FILE_NULL:
 331    default:
 332       return nv50_ir::FILE_NULL;
 333    }
 334 }
 335
 336 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 337 {
 338    switch (sysval) {
 339    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 340    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 341    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 342    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 343    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 344    case TGSI_SEMANTIC_GRID_SIZE:  return nv50_ir::SV_NCTAID;
 345    case TGSI_SEMANTIC_BLOCK_ID:   return nv50_ir::SV_CTAID;
 346    case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
 347    case TGSI_SEMANTIC_THREAD_ID:  return nv50_ir::SV_TID;
 348    default:
 349       assert(0);
 350       return nv50_ir::SV_CLOCK;
 351    }
 352 }
 353
 354 #define NV50_IR_TEX_TARG_CASE(a, b) \
 355    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 356
 357 static nv50_ir::TexTarget translateTexture(uint tex)
 358 {
 359    switch (tex) {
 360    NV50_IR_TEX_TARG_CASE(1D, 1D);
 361    NV50_IR_TEX_TARG_CASE(2D, 2D);
 362    NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
 363    NV50_IR_TEX_TARG_CASE(3D, 3D);
 364    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 365    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 366    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 367    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 368    NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
 369    NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
 370    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 371    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 372    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 373    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 374    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 375    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 376    NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
 377    NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
 378
 379    case TGSI_TEXTURE_UNKNOWN:
 380    default:
 381       assert(!"invalid texture target");
 382       return nv50_ir::TEX_TARGET_2D;
 383    }
 384 }
 385
 386 nv50_ir::DataType Instruction::inferSrcType() const
 387 {
 388    switch (getOpcode()) {
 389    case TGSI_OPCODE_UIF:
 390    case TGSI_OPCODE_AND:
 391    case TGSI_OPCODE_OR:
 392    case TGSI_OPCODE_XOR:
 393    case TGSI_OPCODE_NOT:
 394    case TGSI_OPCODE_U2F:
 395    case TGSI_OPCODE_UADD:
 396    case TGSI_OPCODE_UDIV:
 397    case TGSI_OPCODE_UMOD:
 398    case TGSI_OPCODE_UMAD:
 399    case TGSI_OPCODE_UMUL:
 400    case TGSI_OPCODE_UMAX:
 401    case TGSI_OPCODE_UMIN:
 402    case TGSI_OPCODE_USEQ:
 403    case TGSI_OPCODE_USGE:
 404    case TGSI_OPCODE_USLT:
 405    case TGSI_OPCODE_USNE:
 406    case TGSI_OPCODE_USHR:
 407    case TGSI_OPCODE_UCMP:
 408    case TGSI_OPCODE_ATOMUADD:
 409    case TGSI_OPCODE_ATOMXCHG:
 410    case TGSI_OPCODE_ATOMCAS:
 411    case TGSI_OPCODE_ATOMAND:
 412    case TGSI_OPCODE_ATOMOR:
 413    case TGSI_OPCODE_ATOMXOR:
 414    case TGSI_OPCODE_ATOMUMIN:
 415    case TGSI_OPCODE_ATOMUMAX:
 416       return nv50_ir::TYPE_U32;
 417    case TGSI_OPCODE_I2F:
 418    case TGSI_OPCODE_IDIV:
 419    case TGSI_OPCODE_IMAX:
 420    case TGSI_OPCODE_IMIN:
 421    case TGSI_OPCODE_IABS:
 422    case TGSI_OPCODE_INEG:
 423    case TGSI_OPCODE_ISGE:
 424    case TGSI_OPCODE_ISHR:
 425    case TGSI_OPCODE_ISLT:
 426    case TGSI_OPCODE_ISSG:
 427    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 428    case TGSI_OPCODE_MOD:
 429    case TGSI_OPCODE_UARL:
 430    case TGSI_OPCODE_ATOMIMIN:
 431    case TGSI_OPCODE_ATOMIMAX:
 432       return nv50_ir::TYPE_S32;
 433    default:
 434       return nv50_ir::TYPE_F32;
 435    }
 436 }
 437
 438 nv50_ir::DataType Instruction::inferDstType() const
 439 {
 440    switch (getOpcode()) {
 441    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 442    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 443    case TGSI_OPCODE_FSEQ:
 444    case TGSI_OPCODE_FSGE:
 445    case TGSI_OPCODE_FSLT:
 446    case TGSI_OPCODE_FSNE:
 447       return nv50_ir::TYPE_U32;
 448    case TGSI_OPCODE_I2F:
 449    case TGSI_OPCODE_U2F:
 450       return nv50_ir::TYPE_F32;
 451    default:
 452       return inferSrcType();
 453    }
 454 }
 455
 456 nv50_ir::CondCode Instruction::getSetCond() const
 457 {
 458    using namespace nv50_ir;
 459
 460    switch (getOpcode()) {
 461    case TGSI_OPCODE_SLT:
 462    case TGSI_OPCODE_ISLT:
 463    case TGSI_OPCODE_USLT:
 464    case TGSI_OPCODE_FSLT:
 465       return CC_LT;
 466    case TGSI_OPCODE_SLE:
 467       return CC_LE;
 468    case TGSI_OPCODE_SGE:
 469    case TGSI_OPCODE_ISGE:
 470    case TGSI_OPCODE_USGE:
 471    case TGSI_OPCODE_FSGE:
 472       return CC_GE;
 473    case TGSI_OPCODE_SGT:
 474       return CC_GT;
 475    case TGSI_OPCODE_SEQ:
 476    case TGSI_OPCODE_USEQ:
 477    case TGSI_OPCODE_FSEQ:
 478       return CC_EQ;
 479    case TGSI_OPCODE_SNE:
 480    case TGSI_OPCODE_FSNE:
 481       return CC_NEU;
 482    case TGSI_OPCODE_USNE:
 483       return CC_NE;
 484    case TGSI_OPCODE_SFL:
 485       return CC_NEVER;
 486    case TGSI_OPCODE_STR:
 487    default:
 488       return CC_ALWAYS;
 489    }
 490 }
 491
 492 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 493
 494 static nv50_ir::operation translateOpcode(uint opcode)
 495 {
 496    switch (opcode) {
 497    NV50_IR_OPCODE_CASE(ARL, SHL);
 498    NV50_IR_OPCODE_CASE(MOV, MOV);
 499
 500    NV50_IR_OPCODE_CASE(RCP, RCP);
 501    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 502
 503    NV50_IR_OPCODE_CASE(MUL, MUL);
 504    NV50_IR_OPCODE_CASE(ADD, ADD);
 505
 506    NV50_IR_OPCODE_CASE(MIN, MIN);
 507    NV50_IR_OPCODE_CASE(MAX, MAX);
 508    NV50_IR_OPCODE_CASE(SLT, SET);
 509    NV50_IR_OPCODE_CASE(SGE, SET);
 510    NV50_IR_OPCODE_CASE(MAD, MAD);
 511    NV50_IR_OPCODE_CASE(SUB, SUB);
 512
 513    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 514    NV50_IR_OPCODE_CASE(ROUND, CVT);
 515    NV50_IR_OPCODE_CASE(EX2, EX2);
 516    NV50_IR_OPCODE_CASE(LG2, LG2);
 517    NV50_IR_OPCODE_CASE(POW, POW);
 518
 519    NV50_IR_OPCODE_CASE(ABS, ABS);
 520
 521    NV50_IR_OPCODE_CASE(COS, COS);
 522    NV50_IR_OPCODE_CASE(DDX, DFDX);
 523    NV50_IR_OPCODE_CASE(DDY, DFDY);
 524    NV50_IR_OPCODE_CASE(KILL, DISCARD);
 525
 526    NV50_IR_OPCODE_CASE(SEQ, SET);
 527    NV50_IR_OPCODE_CASE(SFL, SET);
 528    NV50_IR_OPCODE_CASE(SGT, SET);
 529    NV50_IR_OPCODE_CASE(SIN, SIN);
 530    NV50_IR_OPCODE_CASE(SLE, SET);
 531    NV50_IR_OPCODE_CASE(SNE, SET);
 532    NV50_IR_OPCODE_CASE(STR, SET);
 533    NV50_IR_OPCODE_CASE(TEX, TEX);
 534    NV50_IR_OPCODE_CASE(TXD, TXD);
 535    NV50_IR_OPCODE_CASE(TXP, TEX);
 536
 537    NV50_IR_OPCODE_CASE(BRA, BRA);
 538    NV50_IR_OPCODE_CASE(CAL, CALL);
 539    NV50_IR_OPCODE_CASE(RET, RET);
 540    NV50_IR_OPCODE_CASE(CMP, SLCT);
 541
 542    NV50_IR_OPCODE_CASE(TXB, TXB);
 543
 544    NV50_IR_OPCODE_CASE(DIV, DIV);
 545
 546    NV50_IR_OPCODE_CASE(TXL, TXL);
 547
 548    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 549    NV50_IR_OPCODE_CASE(I2F, CVT);
 550    NV50_IR_OPCODE_CASE(NOT, NOT);
 551    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 552    NV50_IR_OPCODE_CASE(SHL, SHL);
 553
 554    NV50_IR_OPCODE_CASE(AND, AND);
 555    NV50_IR_OPCODE_CASE(OR, OR);
 556    NV50_IR_OPCODE_CASE(MOD, MOD);
 557    NV50_IR_OPCODE_CASE(XOR, XOR);
 558    NV50_IR_OPCODE_CASE(SAD, SAD);
 559    NV50_IR_OPCODE_CASE(TXF, TXF);
 560    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 561
 562    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 563    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 564
 565    NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
 566
 567    NV50_IR_OPCODE_CASE(F2I, CVT);
 568    NV50_IR_OPCODE_CASE(FSEQ, SET);
 569    NV50_IR_OPCODE_CASE(FSGE, SET);
 570    NV50_IR_OPCODE_CASE(FSLT, SET);
 571    NV50_IR_OPCODE_CASE(FSNE, SET);
 572    NV50_IR_OPCODE_CASE(IDIV, DIV);
 573    NV50_IR_OPCODE_CASE(IMAX, MAX);
 574    NV50_IR_OPCODE_CASE(IMIN, MIN);
 575    NV50_IR_OPCODE_CASE(IABS, ABS);
 576    NV50_IR_OPCODE_CASE(INEG, NEG);
 577    NV50_IR_OPCODE_CASE(ISGE, SET);
 578    NV50_IR_OPCODE_CASE(ISHR, SHR);
 579    NV50_IR_OPCODE_CASE(ISLT, SET);
 580    NV50_IR_OPCODE_CASE(F2U, CVT);
 581    NV50_IR_OPCODE_CASE(U2F, CVT);
 582    NV50_IR_OPCODE_CASE(UADD, ADD);
 583    NV50_IR_OPCODE_CASE(UDIV, DIV);
 584    NV50_IR_OPCODE_CASE(UMAD, MAD);
 585    NV50_IR_OPCODE_CASE(UMAX, MAX);
 586    NV50_IR_OPCODE_CASE(UMIN, MIN);
 587    NV50_IR_OPCODE_CASE(UMOD, MOD);
 588    NV50_IR_OPCODE_CASE(UMUL, MUL);
 589    NV50_IR_OPCODE_CASE(USEQ, SET);
 590    NV50_IR_OPCODE_CASE(USGE, SET);
 591    NV50_IR_OPCODE_CASE(USHR, SHR);
 592    NV50_IR_OPCODE_CASE(USLT, SET);
 593    NV50_IR_OPCODE_CASE(USNE, SET);
 594
 595    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 596    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 597    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 598    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 599    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 600    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 601    NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
 602    NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
 603    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 604    NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
 605
 606    NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
 607    NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
 608    NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
 609    NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
 610    NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
 611    NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
 612    NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
 613    NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
 614    NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
 615    NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
 616
 617    NV50_IR_OPCODE_CASE(TEX2, TEX);
 618    NV50_IR_OPCODE_CASE(TXB2, TXB);
 619    NV50_IR_OPCODE_CASE(TXL2, TXL);
 620
 621    NV50_IR_OPCODE_CASE(END, EXIT);
 622
 623    default:
 624       return nv50_ir::OP_NOP;
 625    }
 626 }
 627
 628 static uint16_t opcodeToSubOp(uint opcode)
 629 {
 630    switch (opcode) {
 631    case TGSI_OPCODE_LFENCE:   return NV50_IR_SUBOP_MEMBAR(L, GL);
 632    case TGSI_OPCODE_SFENCE:   return NV50_IR_SUBOP_MEMBAR(S, GL);
 633    case TGSI_OPCODE_MFENCE:   return NV50_IR_SUBOP_MEMBAR(M, GL);
 634    case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
 635    case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
 636    case TGSI_OPCODE_ATOMCAS:  return NV50_IR_SUBOP_ATOM_CAS;
 637    case TGSI_OPCODE_ATOMAND:  return NV50_IR_SUBOP_ATOM_AND;
 638    case TGSI_OPCODE_ATOMOR:   return NV50_IR_SUBOP_ATOM_OR;
 639    case TGSI_OPCODE_ATOMXOR:  return NV50_IR_SUBOP_ATOM_XOR;
 640    case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
 641    case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
 642    case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
 643    case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
 644    default:
 645       return 0;
 646    }
 647 }
 648
 649 bool Instruction::checkDstSrcAliasing() const
 650 {
 651    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 652       return false;
 653
 654    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 655       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 656          break;
 657       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 658           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 659          return true;
 660    }
 661    return false;
 662 }
 663
 664 class Source
 665 {
 666 public:
 667    Source(struct nv50_ir_prog_info *);
 668    ~Source();
 669
 670 public:
 671    bool scanSource();
 672    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 673
 674 public:
 675    struct tgsi_shader_info scan;
 676    struct tgsi_full_instruction *insns;
 677    const struct tgsi_token *tokens;
 678    struct nv50_ir_prog_info *info;
 679
 680    nv50_ir::DynArray tempArrays;
 681    nv50_ir::DynArray immdArrays;
 682
 683    typedef nv50_ir::BuildUtil::Location Location;
 684    // these registers are per-subroutine, cannot be used for parameter passing
 685    std::set<Location> locals;
 686
 687    bool mainTempsInLMem;
 688
 689    int clipVertexOutput;
 690
 691    struct TextureView {
 692       uint8_t target; // TGSI_TEXTURE_*
 693    };
 694    std::vector<TextureView> textureViews;
 695
 696    struct Resource {
 697       uint8_t target; // TGSI_TEXTURE_*
 698       bool raw;
 699       uint8_t slot; // $surface index
 700    };
 701    std::vector<Resource> resources;
 702
 703 private:
 704    int inferSysValDirection(unsigned sn) const;
 705    bool scanDeclaration(const struct tgsi_full_declaration *);
 706    bool scanInstruction(const struct tgsi_full_instruction *);
 707    void scanProperty(const struct tgsi_full_property *);
 708    void scanImmediate(const struct tgsi_full_immediate *);
 709
 710    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 711 };
 712
 713 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 714 {
 715    tokens = (const struct tgsi_token *)info->bin.source;
 716
 717    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 718       tgsi_dump(tokens, 0);
 719
 720    mainTempsInLMem = FALSE;
 721 }
 722
 723 Source::~Source()
 724 {
 725    if (insns)
 726       FREE(insns);
 727
 728    if (info->immd.data)
 729       FREE(info->immd.data);
 730    if (info->immd.type)
 731       FREE(info->immd.type);
 732 }
 733
 734 bool Source::scanSource()
 735 {
 736    unsigned insnCount = 0;
 737    struct tgsi_parse_context parse;
 738
 739    tgsi_scan_shader(tokens, &scan);
 740
 741    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 742                                                   sizeof(insns[0]));
 743    if (!insns)
 744       return false;
 745
 746    clipVertexOutput = -1;
 747
 748    textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
 749    resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
 750
 751    info->immd.bufSize = 0;
 752
 753    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 754    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 755    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 756
 757    if (info->type == PIPE_SHADER_FRAGMENT) {
 758       info->prop.fp.writesDepth = scan.writes_z;
 759       info->prop.fp.usesDiscard = scan.uses_kill;
 760    } else
 761    if (info->type == PIPE_SHADER_GEOMETRY) {
 762       info->prop.gp.instanceCount = 1; // default value
 763    }
 764
 765    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 766    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 767
 768    tgsi_parse_init(&parse, tokens);
 769    while (!tgsi_parse_end_of_tokens(&parse)) {
 770       tgsi_parse_token(&parse);
 771
 772       switch (parse.FullToken.Token.Type) {
 773       case TGSI_TOKEN_TYPE_IMMEDIATE:
 774          scanImmediate(&parse.FullToken.FullImmediate);
 775          break;
 776       case TGSI_TOKEN_TYPE_DECLARATION:
 777          scanDeclaration(&parse.FullToken.FullDeclaration);
 778          break;
 779       case TGSI_TOKEN_TYPE_INSTRUCTION:
 780          insns[insnCount++] = parse.FullToken.FullInstruction;
 781          scanInstruction(&parse.FullToken.FullInstruction);
 782          break;
 783       case TGSI_TOKEN_TYPE_PROPERTY:
 784          scanProperty(&parse.FullToken.FullProperty);
 785          break;
 786       default:
 787          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 788          break;
 789       }
 790    }
 791    tgsi_parse_free(&parse);
 792
 793    if (mainTempsInLMem)
 794       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 795
 796    if (info->io.genUserClip > 0) {
 797       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 798
 799       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 800
 801       for (unsigned int n = 0; n < nOut; ++n) {
 802          unsigned int i = info->numOutputs++;
 803          info->out[i].id = i;
 804          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 805          info->out[i].si = n;
 806          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 807       }
 808    }
 809
 810    return info->assignSlots(info) == 0;
 811 }
 812
 813 void Source::scanProperty(const struct tgsi_full_property *prop)
 814 {
 815    switch (prop->Property.PropertyName) {
 816    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 817       info->prop.gp.outputPrim = prop->u[0].Data;
 818       break;
 819    case TGSI_PROPERTY_GS_INPUT_PRIM:
 820       info->prop.gp.inputPrim = prop->u[0].Data;
 821       break;
 822    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 823       info->prop.gp.maxVertices = prop->u[0].Data;
 824       break;
 825 #if 0
 826    case TGSI_PROPERTY_GS_INSTANCE_COUNT:
 827       info->prop.gp.instanceCount = prop->u[0].Data;
 828       break;
 829 #endif
 830    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 831       info->prop.fp.separateFragData = TRUE;
 832       break;
 833    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 834    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 835       // we don't care
 836       break;
 837    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 838       info->io.genUserClip = -1;
 839       break;
 840    default:
 841       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 842       break;
 843    }
 844 }
 845
 846 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 847 {
 848    const unsigned n = info->immd.count++;
 849
 850    assert(n < scan.immediate_count);
 851
 852    for (int c = 0; c < 4; ++c)
 853       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 854
 855    info->immd.type[n] = imm->Immediate.DataType;
 856 }
 857
 858 int Source::inferSysValDirection(unsigned sn) const
 859 {
 860    switch (sn) {
 861    case TGSI_SEMANTIC_INSTANCEID:
 862    case TGSI_SEMANTIC_VERTEXID:
 863       return 1;
 864    case TGSI_SEMANTIC_LAYER:
 865 #if 0
 866    case TGSI_SEMANTIC_VIEWPORTINDEX:
 867       return 0;
 868 #endif
 869    case TGSI_SEMANTIC_PRIMID:
 870       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
 871    default:
 872       return 0;
 873    }
 874 }
 875
 876 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
 877 {
 878    unsigned i, c;
 879    unsigned sn = TGSI_SEMANTIC_GENERIC;
 880    unsigned si = 0;
 881    const unsigned first = decl->Range.First, last = decl->Range.Last;
 882
 883    if (decl->Declaration.Semantic) {
 884       sn = decl->Semantic.Name;
 885       si = decl->Semantic.Index;
 886    }
 887
 888    if (decl->Declaration.Local) {
 889       for (i = first; i <= last; ++i) {
 890          for (c = 0; c < 4; ++c) {
 891             locals.insert(
 892                Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
 893          }
 894       }
 895    }
 896
 897    switch (decl->Declaration.File) {
 898    case TGSI_FILE_INPUT:
 899       if (info->type == PIPE_SHADER_VERTEX) {
 900          // all vertex attributes are equal
 901          for (i = first; i <= last; ++i) {
 902             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
 903             info->in[i].si = i;
 904          }
 905       } else {
 906          for (i = first; i <= last; ++i, ++si) {
 907             info->in[i].id = i;
 908             info->in[i].sn = sn;
 909             info->in[i].si = si;
 910             if (info->type == PIPE_SHADER_FRAGMENT) {
 911                // translate interpolation mode
 912                switch (decl->Interp.Interpolate) {
 913                case TGSI_INTERPOLATE_CONSTANT:
 914                   info->in[i].flat = 1;
 915                   break;
 916                case TGSI_INTERPOLATE_COLOR:
 917                   info->in[i].sc = 1;
 918                   break;
 919                case TGSI_INTERPOLATE_LINEAR:
 920                   info->in[i].linear = 1;
 921                   break;
 922                default:
 923                   break;
 924                }
 925                if (decl->Interp.Centroid)
 926                   info->in[i].centroid = 1;
 927             }
 928          }
 929       }
 930       break;
 931    case TGSI_FILE_OUTPUT:
 932       for (i = first; i <= last; ++i, ++si) {
 933          switch (sn) {
 934          case TGSI_SEMANTIC_POSITION:
 935             if (info->type == PIPE_SHADER_FRAGMENT)
 936                info->io.fragDepth = i;
 937             else
 938             if (clipVertexOutput < 0)
 939                clipVertexOutput = i;
 940             break;
 941          case TGSI_SEMANTIC_COLOR:
 942             if (info->type == PIPE_SHADER_FRAGMENT)
 943                info->prop.fp.numColourResults++;
 944             break;
 945          case TGSI_SEMANTIC_EDGEFLAG:
 946             info->io.edgeFlagOut = i;
 947             break;
 948          case TGSI_SEMANTIC_CLIPVERTEX:
 949             clipVertexOutput = i;
 950             break;
 951          case TGSI_SEMANTIC_CLIPDIST:
 952             info->io.clipDistanceMask |=
 953                decl->Declaration.UsageMask << (si * 4);
 954             info->io.genUserClip = -1;
 955             break;
 956          default:
 957             break;
 958          }
 959          info->out[i].id = i;
 960          info->out[i].sn = sn;
 961          info->out[i].si = si;
 962       }
 963       break;
 964    case TGSI_FILE_SYSTEM_VALUE:
 965       switch (sn) {
 966       case TGSI_SEMANTIC_INSTANCEID:
 967          info->io.instanceId = first;
 968          break;
 969       case TGSI_SEMANTIC_VERTEXID:
 970          info->io.vertexId = first;
 971          break;
 972       default:
 973          break;
 974       }
 975       for (i = first; i <= last; ++i, ++si) {
 976          info->sv[i].sn = sn;
 977          info->sv[i].si = si;
 978          info->sv[i].input = inferSysValDirection(sn);
 979       }
 980       break;
 981    case TGSI_FILE_RESOURCE:
 982       for (i = first; i <= last; ++i) {
 983          resources[i].target = decl->Resource.Resource;
 984          resources[i].raw = decl->Resource.Raw;
 985          resources[i].slot = i;
 986       }
 987       break;
 988    case TGSI_FILE_SAMPLER_VIEW:
 989       for (i = first; i <= last; ++i)
 990          textureViews[i].target = decl->SamplerView.Resource;
 991       break;
 992    case TGSI_FILE_NULL:
 993    case TGSI_FILE_TEMPORARY:
 994    case TGSI_FILE_ADDRESS:
 995    case TGSI_FILE_CONSTANT:
 996    case TGSI_FILE_IMMEDIATE:
 997    case TGSI_FILE_PREDICATE:
 998    case TGSI_FILE_SAMPLER:
 999       break;
1000    default:
1001       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1002       return false;
1003    }
1004    return true;
1005 }
1006
1007 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1008 {
1009    return insn.getOpcode() == TGSI_OPCODE_MOV &&
1010       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1011       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1012 }
1013
1014 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1015 {
1016    Instruction insn(inst);
1017
1018    if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1019       info->numBarriers = 1;
1020
1021    if (insn.dstCount()) {
1022       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1023          Instruction::DstRegister dst = insn.getDst(0);
1024
1025          if (dst.isIndirect(0))
1026             for (unsigned i = 0; i < info->numOutputs; ++i)
1027                info->out[i].mask = 0xf;
1028          else
1029             info->out[dst.getIndex(0)].mask |= dst.getMask();
1030
1031          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1032              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1033              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1034              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1035              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1036             info->out[dst.getIndex(0)].mask &= 1;
1037
1038          if (isEdgeFlagPassthrough(insn))
1039             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1040       } else
1041       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1042          if (insn.getDst(0).isIndirect(0))
1043             mainTempsInLMem = TRUE;
1044       }
1045    }
1046
1047    for (unsigned s = 0; s < insn.srcCount(); ++s) {
1048       Instruction::SrcRegister src = insn.getSrc(s);
1049       if (src.getFile() == TGSI_FILE_TEMPORARY) {
1050          if (src.isIndirect(0))
1051             mainTempsInLMem = TRUE;
1052       } else
1053       if (src.getFile() == TGSI_FILE_RESOURCE) {
1054          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1055             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1056                0x1 : 0x2;
1057       }
1058       if (src.getFile() != TGSI_FILE_INPUT)
1059          continue;
1060       unsigned mask = insn.srcMask(s);
1061
1062       if (src.isIndirect(0)) {
1063          for (unsigned i = 0; i < info->numInputs; ++i)
1064             info->in[i].mask = 0xf;
1065       } else {
1066          const int i = src.getIndex(0);
1067          for (unsigned c = 0; c < 4; ++c) {
1068             if (!(mask & (1 << c)))
1069                continue;
1070             int k = src.getSwizzle(c);
1071             if (k <= TGSI_SWIZZLE_W)
1072                info->in[i].mask |= 1 << k;
1073          }
1074          switch (info->in[i].sn) {
1075          case TGSI_SEMANTIC_PSIZE:
1076          case TGSI_SEMANTIC_PRIMID:
1077          case TGSI_SEMANTIC_FOG:
1078             info->in[i].mask &= 0x1;
1079             break;
1080          case TGSI_SEMANTIC_PCOORD:
1081             info->in[i].mask &= 0x3;
1082             break;
1083          default:
1084             break;
1085          }
1086       }
1087    }
1088    return true;
1089 }
1090
1091 nv50_ir::TexInstruction::Target
1092 Instruction::getTexture(const tgsi::Source *code, int s) const
1093 {
1094    // XXX: indirect access
1095    unsigned int r;
1096
1097    switch (getSrc(s).getFile()) {
1098    case TGSI_FILE_RESOURCE:
1099       r = getSrc(s).getIndex(0);
1100       return translateTexture(code->resources.at(r).target);
1101    case TGSI_FILE_SAMPLER_VIEW:
1102       r = getSrc(s).getIndex(0);
1103       return translateTexture(code->textureViews.at(r).target);
1104    default:
1105       return translateTexture(insn->Texture.Texture);
1106    }
1107 }
1108
1109 } // namespace tgsi
1110
1111 namespace {
1112
1113 using namespace nv50_ir;
1114
1115 class Converter : public BuildUtil
1116 {
1117 public:
1118    Converter(Program *, const tgsi::Source *);
1119    ~Converter();
1120
1121    bool run();
1122
1123 private:
1124    struct Subroutine
1125    {
1126       Subroutine(Function *f) : f(f) { }
1127       Function *f;
1128       ValueMap values;
1129    };
1130
1131    Value *shiftAddress(Value *);
1132    Value *getVertexBase(int s);
1133    DataArray *getArrayForFile(unsigned file, int idx);
1134    Value *fetchSrc(int s, int c);
1135    Value *acquireDst(int d, int c);
1136    void storeDst(int d, int c, Value *);
1137
1138    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1139    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1140                  Value *val, Value *ptr);
1141
1142    Value *applySrcMod(Value *, int s, int c);
1143
1144    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1145    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1146    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1147
1148    bool handleInstruction(const struct tgsi_full_instruction *);
1149    void exportOutputs();
1150    inline Subroutine *getSubroutine(unsigned ip);
1151    inline Subroutine *getSubroutine(Function *);
1152    inline bool isEndOfSubroutine(uint ip);
1153
1154    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1155
1156    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1157    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1158    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1159    void handleTXF(Value *dst0[4], int R, int L_M);
1160    void handleTXQ(Value *dst0[4], enum TexQuery);
1161    void handleLIT(Value *dst0[4]);
1162    void handleUserClipPlanes();
1163
1164    Symbol *getResourceBase(int r);
1165    void getResourceCoords(std::vector<Value *>&, int r, int s);
1166
1167    void handleLOAD(Value *dst0[4]);
1168    void handleSTORE();
1169    void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1170
1171    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1172
1173    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1174
1175    Value *buildDot(int dim);
1176
1177    class BindArgumentsPass : public Pass {
1178    public:
1179       BindArgumentsPass(Converter &conv) : conv(conv) { }
1180
1181    private:
1182       Converter &conv;
1183       Subroutine *sub;
1184
1185       inline const Location *getValueLocation(Subroutine *, Value *);
1186
1187       template<typename T> inline void
1188       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1189                      T (Function::*proto));
1190
1191       template<typename T> inline void
1192       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1193                       T (Function::*proto));
1194
1195    protected:
1196       bool visit(Function *);
1197       bool visit(BasicBlock *bb) { return false; }
1198    };
1199
1200 private:
1201    const struct tgsi::Source *code;
1202    const struct nv50_ir_prog_info *info;
1203
1204    struct {
1205       std::map<unsigned, Subroutine> map;
1206       Subroutine *cur;
1207    } sub;
1208
1209    uint ip; // instruction pointer
1210
1211    tgsi::Instruction tgsi;
1212
1213    DataType dstTy;
1214    DataType srcTy;
1215
1216    DataArray tData; // TGSI_FILE_TEMPORARY
1217    DataArray aData; // TGSI_FILE_ADDRESS
1218    DataArray pData; // TGSI_FILE_PREDICATE
1219    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1220
1221    Value *zero;
1222    Value *fragCoord[4];
1223    Value *clipVtx[4];
1224
1225    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1226    uint8_t vtxBaseValid;
1227
1228    Stack condBBs;  // fork BB, then else clause BB
1229    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1230    Stack loopBBs;  // loop headers
1231    Stack breakBBs; // end of / after loop
1232 };
1233
1234 Symbol *
1235 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1236 {
1237    const int swz = src.getSwizzle(c);
1238
1239    return makeSym(src.getFile(),
1240                   src.is2D() ? src.getIndex(1) : 0,
1241                   src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1242                   src.getIndex(0) * 16 + swz * 4);
1243 }
1244
1245 Symbol *
1246 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1247 {
1248    return makeSym(dst.getFile(),
1249                   dst.is2D() ? dst.getIndex(1) : 0,
1250                   dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1251                   dst.getIndex(0) * 16 + c * 4);
1252 }
1253
1254 Symbol *
1255 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1256 {
1257    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1258
1259    sym->reg.fileIndex = fileIdx;
1260
1261    if (idx >= 0) {
1262       if (sym->reg.file == FILE_SHADER_INPUT)
1263          sym->setOffset(info->in[idx].slot[c] * 4);
1264       else
1265       if (sym->reg.file == FILE_SHADER_OUTPUT)
1266          sym->setOffset(info->out[idx].slot[c] * 4);
1267       else
1268       if (sym->reg.file == FILE_SYSTEM_VALUE)
1269          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1270       else
1271          sym->setOffset(address);
1272    } else {
1273       sym->setOffset(address);
1274    }
1275    return sym;
1276 }
1277
1278 static inline uint8_t
1279 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1280 {
1281    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1282
1283    if (var->flat)
1284       mode = NV50_IR_INTERP_FLAT;
1285    else
1286    if (var->linear)
1287       mode = NV50_IR_INTERP_LINEAR;
1288    else
1289    if (var->sc)
1290       mode = NV50_IR_INTERP_SC;
1291
1292    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1293       ? OP_PINTERP : OP_LINTERP;
1294
1295    if (var->centroid)
1296       mode |= NV50_IR_INTERP_CENTROID;
1297
1298    return mode;
1299 }
1300
1301 Value *
1302 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1303 {
1304    operation op;
1305
1306    // XXX: no way to know interpolation mode if we don't know what's accessed
1307    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1308                                                       src.getIndex(0)], op);
1309
1310    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1311
1312    insn->setDef(0, getScratch());
1313    insn->setSrc(0, srcToSym(src, c));
1314    if (op == OP_PINTERP)
1315       insn->setSrc(1, fragCoord[3]);
1316    if (ptr)
1317       insn->setIndirect(0, 0, ptr);
1318
1319    insn->setInterpolate(mode);
1320
1321    bb->insertTail(insn);
1322    return insn->getDef(0);
1323 }
1324
1325 Value *
1326 Converter::applySrcMod(Value *val, int s, int c)
1327 {
1328    Modifier m = tgsi.getSrc(s).getMod(c);
1329    DataType ty = tgsi.inferSrcType();
1330
1331    if (m & Modifier(NV50_IR_MOD_ABS))
1332       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1333
1334    if (m & Modifier(NV50_IR_MOD_NEG))
1335       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1336
1337    return val;
1338 }
1339
1340 Value *
1341 Converter::getVertexBase(int s)
1342 {
1343    assert(s < 5);
1344    if (!(vtxBaseValid & (1 << s))) {
1345       const int index = tgsi.getSrc(s).getIndex(1);
1346       Value *rel = NULL;
1347       if (tgsi.getSrc(s).isIndirect(1))
1348          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1349       vtxBaseValid |= 1 << s;
1350       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1351                           mkImm(index), rel);
1352    }
1353    return vtxBase[s];
1354 }
1355
1356 Value *
1357 Converter::fetchSrc(int s, int c)
1358 {
1359    Value *res;
1360    Value *ptr = NULL, *dimRel = NULL;
1361
1362    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1363
1364    if (src.isIndirect(0))
1365       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1366
1367    if (src.is2D()) {
1368       switch (src.getFile()) {
1369       case TGSI_FILE_INPUT:
1370          dimRel = getVertexBase(s);
1371          break;
1372       case TGSI_FILE_CONSTANT:
1373          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1374          if (src.isIndirect(1))
1375             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1376          break;
1377       default:
1378          break;
1379       }
1380    }
1381
1382    res = fetchSrc(src, c, ptr);
1383
1384    if (dimRel)
1385       res->getInsn()->setIndirect(0, 1, dimRel);
1386
1387    return applySrcMod(res, s, c);
1388 }
1389
1390 Converter::DataArray *
1391 Converter::getArrayForFile(unsigned file, int idx)
1392 {
1393    switch (file) {
1394    case TGSI_FILE_TEMPORARY:
1395       return &tData;
1396    case TGSI_FILE_PREDICATE:
1397       return &pData;
1398    case TGSI_FILE_ADDRESS:
1399       return &aData;
1400    case TGSI_FILE_OUTPUT:
1401       assert(prog->getType() == Program::TYPE_FRAGMENT);
1402       return &oData;
1403    default:
1404       assert(!"invalid/unhandled TGSI source file");
1405       return NULL;
1406    }
1407 }
1408
1409 Value *
1410 Converter::shiftAddress(Value *index)
1411 {
1412    if (!index)
1413       return NULL;
1414    return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1415 }
1416
1417 Value *
1418 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1419 {
1420    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1421    const int idx = src.getIndex(0);
1422    const int swz = src.getSwizzle(c);
1423
1424    switch (src.getFile()) {
1425    case TGSI_FILE_IMMEDIATE:
1426       assert(!ptr);
1427       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1428    case TGSI_FILE_CONSTANT:
1429       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1430    case TGSI_FILE_INPUT:
1431       if (prog->getType() == Program::TYPE_FRAGMENT) {
1432          // don't load masked inputs, won't be assigned a slot
1433          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1434             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1435          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1436             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1437          return interpolate(src, c, shiftAddress(ptr));
1438       } else
1439       if (prog->getType() == Program::TYPE_GEOMETRY) {
1440          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1441             return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1442          // XXX: This is going to be a problem with scalar arrays, i.e. when
1443          // we cannot assume that the address is given in units of vec4.
1444          //
1445          // nv50 and nvc0 need different things here, so let the lowering
1446          // passes decide what to do with the address
1447          if (ptr)
1448             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1449       }
1450       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1451    case TGSI_FILE_OUTPUT:
1452       assert(!"load from output file");
1453       return NULL;
1454    case TGSI_FILE_SYSTEM_VALUE:
1455       assert(!ptr);
1456       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1457    default:
1458       return getArrayForFile(src.getFile(), idx2d)->load(
1459          sub.cur->values, idx, swz, shiftAddress(ptr));
1460    }
1461 }
1462
1463 Value *
1464 Converter::acquireDst(int d, int c)
1465 {
1466    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1467    const unsigned f = dst.getFile();
1468    const int idx = dst.getIndex(0);
1469    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1470
1471    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1472       return NULL;
1473
1474    if (dst.isIndirect(0) ||
1475        f == TGSI_FILE_SYSTEM_VALUE ||
1476        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1477       return getScratch();
1478
1479    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1480 }
1481
1482 void
1483 Converter::storeDst(int d, int c, Value *val)
1484 {
1485    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1486
1487    switch (tgsi.getSaturate()) {
1488    case TGSI_SAT_NONE:
1489       break;
1490    case TGSI_SAT_ZERO_ONE:
1491       mkOp1(OP_SAT, dstTy, val, val);
1492       break;
1493    case TGSI_SAT_MINUS_PLUS_ONE:
1494       mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1495       mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1496       break;
1497    default:
1498       assert(!"invalid saturation mode");
1499       break;
1500    }
1501
1502    Value *ptr = NULL;
1503    if (dst.isIndirect(0))
1504       ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1505
1506    if (info->io.genUserClip > 0 &&
1507        dst.getFile() == TGSI_FILE_OUTPUT &&
1508        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1509       mkMov(clipVtx[c], val);
1510       val = clipVtx[c];
1511    }
1512
1513    storeDst(dst, c, val, ptr);
1514 }
1515
1516 void
1517 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1518                     Value *val, Value *ptr)
1519 {
1520    const unsigned f = dst.getFile();
1521    const int idx = dst.getIndex(0);
1522    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1523
1524    if (f == TGSI_FILE_SYSTEM_VALUE) {
1525       assert(!ptr);
1526       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1527    } else
1528    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1529       if (ptr || (info->out[idx].mask & (1 << c)))
1530          mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1531    } else
1532    if (f == TGSI_FILE_TEMPORARY ||
1533        f == TGSI_FILE_PREDICATE ||
1534        f == TGSI_FILE_ADDRESS ||
1535        f == TGSI_FILE_OUTPUT) {
1536       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1537    } else {
1538       assert(!"invalid dst file");
1539    }
1540 }
1541
1542 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1543    for (chan = 0; chan < 4; ++chan)                 \
1544       if (!inst.getDst(d).isMasked(chan))
1545
1546 Value *
1547 Converter::buildDot(int dim)
1548 {
1549    assert(dim > 0);
1550
1551    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1552    Value *dotp = getScratch();
1553
1554    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1555
1556    for (int c = 1; c < dim; ++c) {
1557       src0 = fetchSrc(0, c);
1558       src1 = fetchSrc(1, c);
1559       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1560    }
1561    return dotp;
1562 }
1563
1564 void
1565 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1566 {
1567    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1568    join->fixed = 1;
1569    conv->insertHead(join);
1570
1571    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1572    fork->insertBefore(fork->getExit(), fork->joinAt);
1573 }
1574
1575 void
1576 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1577 {
1578    unsigned rIdx = 0, sIdx = 0;
1579
1580    if (R >= 0)
1581       rIdx = tgsi.getSrc(R).getIndex(0);
1582    if (S >= 0)
1583       sIdx = tgsi.getSrc(S).getIndex(0);
1584
1585    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1586
1587    if (tgsi.getSrc(R).isIndirect(0)) {
1588       tex->tex.rIndirectSrc = s;
1589       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1590    }
1591    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1592       tex->tex.sIndirectSrc = s;
1593       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1594    }
1595 }
1596
1597 void
1598 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1599 {
1600    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1601    tex->tex.query = query;
1602    unsigned int c, d;
1603
1604    for (d = 0, c = 0; c < 4; ++c) {
1605       if (!dst0[c])
1606          continue;
1607       tex->tex.mask |= 1 << c;
1608       tex->setDef(d++, dst0[c]);
1609    }
1610    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1611
1612    setTexRS(tex, c, 1, -1);
1613
1614    bb->insertTail(tex);
1615 }
1616
1617 void
1618 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1619 {
1620    Value *proj = fetchSrc(0, 3);
1621    Instruction *insn = proj->getUniqueInsn();
1622    int c;
1623
1624    if (insn->op == OP_PINTERP) {
1625       bb->insertTail(insn = cloneForward(func, insn));
1626       insn->op = OP_LINTERP;
1627       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1628       insn->setSrc(1, NULL);
1629       proj = insn->getDef(0);
1630    }
1631    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1632
1633    for (c = 0; c < 4; ++c) {
1634       if (!(mask & (1 << c)))
1635          continue;
1636       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1637          continue;
1638       mask &= ~(1 << c);
1639
1640       bb->insertTail(insn = cloneForward(func, insn));
1641       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1642       insn->setSrc(1, proj);
1643       dst[c] = insn->getDef(0);
1644    }
1645    if (!mask)
1646       return;
1647
1648    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1649
1650    for (c = 0; c < 4; ++c)
1651       if (mask & (1 << c))
1652          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1653 }
1654
1655 // order of nv50 ir sources: x y z layer lod/bias shadow
1656 // order of TGSI TEX sources: x y z layer shadow lod/bias
1657 //  lowering will finally set the hw specific order (like array first on nvc0)
1658 void
1659 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1660 {
1661    Value *val;
1662    Value *arg[4], *src[8];
1663    Value *lod = NULL, *shd = NULL;
1664    unsigned int s, c, d;
1665    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1666
1667    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1668
1669    for (s = 0; s < tgt.getArgCount(); ++s)
1670       arg[s] = src[s] = fetchSrc(0, s);
1671
1672    if (texi->op == OP_TXL || texi->op == OP_TXB)
1673       lod = fetchSrc(L >> 4, L & 3);
1674
1675    if (C == 0x0f)
1676       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1677
1678    if (tgt.isShadow())
1679       shd = fetchSrc(C >> 4, C & 3);
1680
1681    if (texi->op == OP_TXD) {
1682       for (c = 0; c < tgt.getDim(); ++c) {
1683          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1684          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1685       }
1686    }
1687
1688    // cube textures don't care about projection value, it's divided out
1689    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1690       unsigned int n = tgt.getDim();
1691       if (shd) {
1692          arg[n] = shd;
1693          ++n;
1694          assert(tgt.getDim() == tgt.getArgCount());
1695       }
1696       loadProjTexCoords(src, arg, (1 << n) - 1);
1697       if (shd)
1698          shd = src[n - 1];
1699    }
1700
1701    if (tgt.isCube()) {
1702       for (c = 0; c < 3; ++c)
1703          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1704       val = getScratch();
1705       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1706       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1707       mkOp1(OP_RCP, TYPE_F32, val, val);
1708       for (c = 0; c < 3; ++c)
1709          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1710    }
1711
1712    for (c = 0, d = 0; c < 4; ++c) {
1713       if (dst[c]) {
1714          texi->setDef(d++, dst[c]);
1715          texi->tex.mask |= 1 << c;
1716       } else {
1717          // NOTE: maybe hook up def too, for CSE
1718       }
1719    }
1720    for (s = 0; s < tgt.getArgCount(); ++s)
1721       texi->setSrc(s, src[s]);
1722    if (lod)
1723       texi->setSrc(s++, lod);
1724    if (shd)
1725       texi->setSrc(s++, shd);
1726
1727    setTexRS(texi, s, R, S);
1728
1729    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1730       texi->tex.levelZero = true;
1731
1732    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1733       for (c = 0; c < 3; ++c) {
1734          texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1735          if (texi->tex.offset[s][c])
1736             texi->tex.useOffsets = s + 1;
1737       }
1738    }
1739
1740    bb->insertTail(texi);
1741 }
1742
1743 // 1st source: xyz = coordinates, w = lod/sample
1744 // 2nd source: offset
1745 void
1746 Converter::handleTXF(Value *dst[4], int R, int L_M)
1747 {
1748    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1749    int ms;
1750    unsigned int c, d, s;
1751
1752    texi->tex.target = tgsi.getTexture(code, R);
1753
1754    ms = texi->tex.target.isMS() ? 1 : 0;
1755    texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1756
1757    for (c = 0, d = 0; c < 4; ++c) {
1758       if (dst[c]) {
1759          texi->setDef(d++, dst[c]);
1760          texi->tex.mask |= 1 << c;
1761       }
1762    }
1763    for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1764       texi->setSrc(c, fetchSrc(0, c));
1765    texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1766
1767    setTexRS(texi, c, R, -1);
1768
1769    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1770       for (c = 0; c < 3; ++c) {
1771          texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1772          if (texi->tex.offset[s][c])
1773             texi->tex.useOffsets = s + 1;
1774       }
1775    }
1776
1777    bb->insertTail(texi);
1778 }
1779
1780 void
1781 Converter::handleLIT(Value *dst0[4])
1782 {
1783    Value *val0 = NULL;
1784    unsigned int mask = tgsi.getDst(0).getMask();
1785
1786    if (mask & (1 << 0))
1787       loadImm(dst0[0], 1.0f);
1788
1789    if (mask & (1 << 3))
1790       loadImm(dst0[3], 1.0f);
1791
1792    if (mask & (3 << 1)) {
1793       val0 = getScratch();
1794       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1795       if (mask & (1 << 1))
1796          mkMov(dst0[1], val0);
1797    }
1798
1799    if (mask & (1 << 2)) {
1800       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1801       Value *val1 = getScratch(), *val3 = getScratch();
1802
1803       Value *pos128 = loadImm(NULL, +127.999999f);
1804       Value *neg128 = loadImm(NULL, -127.999999f);
1805
1806       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1807       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1808       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1809       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1810
1811       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
1812    }
1813 }
1814
1815 static inline bool
1816 isResourceSpecial(const int r)
1817 {
1818    return (r == TGSI_RESOURCE_GLOBAL ||
1819            r == TGSI_RESOURCE_LOCAL ||
1820            r == TGSI_RESOURCE_PRIVATE ||
1821            r == TGSI_RESOURCE_INPUT);
1822 }
1823
1824 static inline bool
1825 isResourceRaw(const struct tgsi::Source *code, const int r)
1826 {
1827    return isResourceSpecial(r) || code->resources[r].raw;
1828 }
1829
1830 static inline nv50_ir::TexTarget
1831 getResourceTarget(const struct tgsi::Source *code, int r)
1832 {
1833    if (isResourceSpecial(r))
1834       return nv50_ir::TEX_TARGET_BUFFER;
1835    return tgsi::translateTexture(code->resources.at(r).target);
1836 }
1837
1838 Symbol *
1839 Converter::getResourceBase(const int r)
1840 {
1841    Symbol *sym = NULL;
1842
1843    switch (r) {
1844    case TGSI_RESOURCE_GLOBAL:
1845       sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1846       break;
1847    case TGSI_RESOURCE_LOCAL:
1848       assert(prog->getType() == Program::TYPE_COMPUTE);
1849       sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1850                      info->prop.cp.sharedOffset);
1851       break;
1852    case TGSI_RESOURCE_PRIVATE:
1853       sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1854                      info->bin.tlsSpace);
1855       break;
1856    case TGSI_RESOURCE_INPUT:
1857       assert(prog->getType() == Program::TYPE_COMPUTE);
1858       sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1859                      info->prop.cp.inputOffset);
1860       break;
1861    default:
1862       sym = new_Symbol(prog,
1863                        nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1864       break;
1865    }
1866    return sym;
1867 }
1868
1869 void
1870 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
1871 {
1872    const int arg =
1873       TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
1874
1875    for (int c = 0; c < arg; ++c)
1876       coords.push_back(fetchSrc(s, c));
1877
1878    // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
1879    if (r == TGSI_RESOURCE_LOCAL ||
1880        r == TGSI_RESOURCE_PRIVATE ||
1881        r == TGSI_RESOURCE_INPUT)
1882       coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
1883                          coords[0]);
1884 }
1885
1886 static inline int
1887 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
1888 {
1889    int n = 0;
1890
1891    while (mask) {
1892       if (mask & 1) {
1893          size[n]++;
1894       } else {
1895          if (size[n])
1896             comp[n = 1] = size[0] + 1;
1897          else
1898             comp[n]++;
1899       }
1900       mask >>= 1;
1901    }
1902    if (size[0] == 3) {
1903       n = 1;
1904       size[0] = (comp[0] == 1) ? 1 : 2;
1905       size[1] = 3 - size[0];
1906       comp[1] = comp[0] + size[0];
1907    }
1908    return n + 1;
1909 }
1910
1911 // For raw loads, granularity is 4 byte.
1912 // Usage of the texture read mask on OP_SULDP is not allowed.
1913 void
1914 Converter::handleLOAD(Value *dst0[4])
1915 {
1916    const int r = tgsi.getSrc(0).getIndex(0);
1917    int c;
1918    std::vector<Value *> off, src, ldv, def;
1919
1920    getResourceCoords(off, r, 1);
1921
1922    if (isResourceRaw(code, r)) {
1923       uint8_t mask = 0;
1924       uint8_t comp[2] = { 0, 0 };
1925       uint8_t size[2] = { 0, 0 };
1926
1927       Symbol *base = getResourceBase(r);
1928
1929       // determine the base and size of the at most 2 load ops
1930       for (c = 0; c < 4; ++c)
1931          if (!tgsi.getDst(0).isMasked(c))
1932             mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
1933
1934       int n = partitionLoadStore(comp, size, mask);
1935
1936       src = off;
1937
1938       def.resize(4); // index by component, the ones we need will be non-NULL
1939       for (c = 0; c < 4; ++c) {
1940          if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
1941             def[c] = dst0[c];
1942          else
1943          if (mask & (1 << c))
1944             def[c] = getScratch();
1945       }
1946
1947       const bool useLd = isResourceSpecial(r) ||
1948          (info->io.nv50styleSurfaces &&
1949           code->resources[r].target == TGSI_TEXTURE_BUFFER);
1950
1951       for (int i = 0; i < n; ++i) {
1952          ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
1953
1954          if (comp[i]) // adjust x component of source address if necessary
1955             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
1956                             off[0], mkImm(comp[i] * 4));
1957          else
1958             src[0] = off[0];
1959
1960          if (useLd) {
1961             Instruction *ld =
1962                mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
1963             for (size_t c = 1; c < ldv.size(); ++c)
1964                ld->setDef(c, ldv[c]);
1965          } else {
1966             mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
1967                   0, ldv, src)->dType = typeOfSize(size[i] * 4);
1968          }
1969       }
1970    } else {
1971       def.resize(4);
1972       for (c = 0; c < 4; ++c) {
1973          if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
1974             def[c] = getScratch();
1975          else
1976             def[c] = dst0[c];
1977       }
1978
1979       mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
1980             def, off);
1981    }
1982    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1983       if (dst0[c] != def[c])
1984          mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
1985 }
1986
1987 // For formatted stores, the write mask on OP_SUSTP can be used.
1988 // Raw stores have to be split.
1989 void
1990 Converter::handleSTORE()
1991 {
1992    const int r = tgsi.getDst(0).getIndex(0);
1993    int c;
1994    std::vector<Value *> off, src, dummy;
1995
1996    getResourceCoords(off, r, 0);
1997    src = off;
1998    const int s = src.size();
1999
2000    if (isResourceRaw(code, r)) {
2001       uint8_t comp[2] = { 0, 0 };
2002       uint8_t size[2] = { 0, 0 };
2003
2004       int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2005
2006       Symbol *base = getResourceBase(r);
2007
2008       const bool useSt = isResourceSpecial(r) ||
2009          (info->io.nv50styleSurfaces &&
2010           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2011
2012       for (int i = 0; i < n; ++i) {
2013          if (comp[i]) // adjust x component of source address if necessary
2014             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2015                             off[0], mkImm(comp[i] * 4));
2016          else
2017             src[0] = off[0];
2018
2019          const DataType stTy = typeOfSize(size[i] * 4);
2020
2021          if (useSt) {
2022             Instruction *st =
2023                mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2024             for (c = 1; c < size[i]; ++c)
2025                st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2026             st->setIndirect(0, 0, src[0]);
2027          } else {
2028             // attach values to be stored
2029             src.resize(s + size[i]);
2030             for (c = 0; c < size[i]; ++c)
2031                src[s + c] = fetchSrc(1, comp[i] + c);
2032             mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2033                   0, dummy, src)->setType(stTy);
2034          }
2035       }
2036    } else {
2037       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2038          src.push_back(fetchSrc(1, c));
2039
2040       mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2041             dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2042    }
2043 }
2044
2045 // XXX: These only work on resources with the single-component u32/s32 formats.
2046 // Therefore the result is replicated. This might not be intended by TGSI, but
2047 // operating on more than 1 component would produce undefined results because
2048 // they do not exist.
2049 void
2050 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2051 {
2052    const int r = tgsi.getSrc(0).getIndex(0);
2053    std::vector<Value *> srcv;
2054    std::vector<Value *> defv;
2055    LValue *dst = getScratch();
2056
2057    getResourceCoords(srcv, r, 1);
2058
2059    if (isResourceSpecial(r)) {
2060       assert(r != TGSI_RESOURCE_INPUT);
2061       Instruction *insn;
2062       insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2063       insn->subOp = subOp;
2064       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2065          insn->setSrc(2, fetchSrc(3, 0));
2066       insn->setIndirect(0, 0, srcv.at(0));
2067    } else {
2068       operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2069       TexTarget targ = getResourceTarget(code, r);
2070       int idx = code->resources[r].slot;
2071       defv.push_back(dst);
2072       srcv.push_back(fetchSrc(2, 0));
2073       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2074          srcv.push_back(fetchSrc(3, 0));
2075       TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2076       tex->subOp = subOp;
2077       tex->tex.mask = 1;
2078       tex->setType(ty);
2079    }
2080
2081    for (int c = 0; c < 4; ++c)
2082       if (dst0[c])
2083          dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2084 }
2085
2086 Converter::Subroutine *
2087 Converter::getSubroutine(unsigned ip)
2088 {
2089    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2090
2091    if (it == sub.map.end())
2092       it = sub.map.insert(std::make_pair(
2093               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2094
2095    return &it->second;
2096 }
2097
2098 Converter::Subroutine *
2099 Converter::getSubroutine(Function *f)
2100 {
2101    unsigned ip = f->getLabel();
2102    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2103
2104    if (it == sub.map.end())
2105       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2106
2107    return &it->second;
2108 }
2109
2110 bool
2111 Converter::isEndOfSubroutine(uint ip)
2112 {
2113    assert(ip < code->scan.num_instructions);
2114    tgsi::Instruction insn(&code->insns[ip]);
2115    return (insn.getOpcode() == TGSI_OPCODE_END ||
2116            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2117            // does END occur at end of main or the very end ?
2118            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2119 }
2120
2121 bool
2122 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2123 {
2124    Instruction *geni;
2125
2126    Value *dst0[4], *rDst0[4];
2127    Value *src0, *src1, *src2;
2128    Value *val0, *val1;
2129    int c;
2130
2131    tgsi = tgsi::Instruction(insn);
2132
2133    bool useScratchDst = tgsi.checkDstSrcAliasing();
2134
2135    operation op = tgsi.getOP();
2136    dstTy = tgsi.inferDstType();
2137    srcTy = tgsi.inferSrcType();
2138
2139    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2140
2141    if (tgsi.dstCount()) {
2142       for (c = 0; c < 4; ++c) {
2143          rDst0[c] = acquireDst(0, c);
2144          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2145       }
2146    }
2147
2148    switch (tgsi.getOpcode()) {
2149    case TGSI_OPCODE_ADD:
2150    case TGSI_OPCODE_UADD:
2151    case TGSI_OPCODE_AND:
2152    case TGSI_OPCODE_DIV:
2153    case TGSI_OPCODE_IDIV:
2154    case TGSI_OPCODE_UDIV:
2155    case TGSI_OPCODE_MAX:
2156    case TGSI_OPCODE_MIN:
2157    case TGSI_OPCODE_IMAX:
2158    case TGSI_OPCODE_IMIN:
2159    case TGSI_OPCODE_UMAX:
2160    case TGSI_OPCODE_UMIN:
2161    case TGSI_OPCODE_MOD:
2162    case TGSI_OPCODE_UMOD:
2163    case TGSI_OPCODE_MUL:
2164    case TGSI_OPCODE_UMUL:
2165    case TGSI_OPCODE_OR:
2166    case TGSI_OPCODE_POW:
2167    case TGSI_OPCODE_SHL:
2168    case TGSI_OPCODE_ISHR:
2169    case TGSI_OPCODE_USHR:
2170    case TGSI_OPCODE_SUB:
2171    case TGSI_OPCODE_XOR:
2172       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2173          src0 = fetchSrc(0, c);
2174          src1 = fetchSrc(1, c);
2175          mkOp2(op, dstTy, dst0[c], src0, src1);
2176       }
2177       break;
2178    case TGSI_OPCODE_MAD:
2179    case TGSI_OPCODE_UMAD:
2180    case TGSI_OPCODE_SAD:
2181       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2182          src0 = fetchSrc(0, c);
2183          src1 = fetchSrc(1, c);
2184          src2 = fetchSrc(2, c);
2185          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2186       }
2187       break;
2188    case TGSI_OPCODE_MOV:
2189    case TGSI_OPCODE_ABS:
2190    case TGSI_OPCODE_CEIL:
2191    case TGSI_OPCODE_FLR:
2192    case TGSI_OPCODE_TRUNC:
2193    case TGSI_OPCODE_RCP:
2194    case TGSI_OPCODE_IABS:
2195    case TGSI_OPCODE_INEG:
2196    case TGSI_OPCODE_NOT:
2197    case TGSI_OPCODE_DDX:
2198    case TGSI_OPCODE_DDY:
2199       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2200          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2201       break;
2202    case TGSI_OPCODE_RSQ:
2203       src0 = fetchSrc(0, 0);
2204       val0 = getScratch();
2205       mkOp1(OP_ABS, TYPE_F32, val0, src0);
2206       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2207       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2208          mkMov(dst0[c], val0);
2209       break;
2210    case TGSI_OPCODE_ARL:
2211       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2212          src0 = fetchSrc(0, c);
2213          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
2214       }
2215       break;
2216    case TGSI_OPCODE_UARL:
2217       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2218          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2219       break;
2220    case TGSI_OPCODE_EX2:
2221    case TGSI_OPCODE_LG2:
2222       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2223       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2224          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2225       break;
2226    case TGSI_OPCODE_COS:
2227    case TGSI_OPCODE_SIN:
2228       val0 = getScratch();
2229       if (mask & 7) {
2230          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2231          mkOp1(op, TYPE_F32, val0, val0);
2232          for (c = 0; c < 3; ++c)
2233             if (dst0[c])
2234                mkMov(dst0[c], val0);
2235       }
2236       if (dst0[3]) {
2237          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2238          mkOp1(op, TYPE_F32, dst0[3], val0);
2239       }
2240       break;
2241    case TGSI_OPCODE_SCS:
2242       if (mask & 3) {
2243          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2244          if (dst0[0])
2245             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2246          if (dst0[1])
2247             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2248       }
2249       if (dst0[2])
2250          loadImm(dst0[2], 0.0f);
2251       if (dst0[3])
2252          loadImm(dst0[3], 1.0f);
2253       break;
2254    case TGSI_OPCODE_EXP:
2255       src0 = fetchSrc(0, 0);
2256       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2257       if (dst0[1])
2258          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2259       if (dst0[0])
2260          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2261       if (dst0[2])
2262          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2263       if (dst0[3])
2264          loadImm(dst0[3], 1.0f);
2265       break;
2266    case TGSI_OPCODE_LOG:
2267       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2268       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2269       if (dst0[0] || dst0[1])
2270          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2271       if (dst0[1]) {
2272          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2273          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2274          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2275       }
2276       if (dst0[3])
2277          loadImm(dst0[3], 1.0f);
2278       break;
2279    case TGSI_OPCODE_DP2:
2280       val0 = buildDot(2);
2281       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2282          mkMov(dst0[c], val0);
2283       break;
2284    case TGSI_OPCODE_DP3:
2285       val0 = buildDot(3);
2286       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2287          mkMov(dst0[c], val0);
2288       break;
2289    case TGSI_OPCODE_DP4:
2290       val0 = buildDot(4);
2291       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2292          mkMov(dst0[c], val0);
2293       break;
2294    case TGSI_OPCODE_DPH:
2295       val0 = buildDot(3);
2296       src1 = fetchSrc(1, 3);
2297       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2298       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2299          mkMov(dst0[c], val0);
2300       break;
2301    case TGSI_OPCODE_DST:
2302       if (dst0[0])
2303          loadImm(dst0[0], 1.0f);
2304       if (dst0[1]) {
2305          src0 = fetchSrc(0, 1);
2306          src1 = fetchSrc(1, 1);
2307          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2308       }
2309       if (dst0[2])
2310          mkMov(dst0[2], fetchSrc(0, 2));
2311       if (dst0[3])
2312          mkMov(dst0[3], fetchSrc(1, 3));
2313       break;
2314    case TGSI_OPCODE_LRP:
2315       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2316          src0 = fetchSrc(0, c);
2317          src1 = fetchSrc(1, c);
2318          src2 = fetchSrc(2, c);
2319          mkOp3(OP_MAD, TYPE_F32, dst0[c],
2320                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2321       }
2322       break;
2323    case TGSI_OPCODE_LIT:
2324       handleLIT(dst0);
2325       break;
2326    case TGSI_OPCODE_XPD:
2327       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2328          if (c < 3) {
2329             val0 = getSSA();
2330             src0 = fetchSrc(1, (c + 1) % 3);
2331             src1 = fetchSrc(0, (c + 2) % 3);
2332             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2333             mkOp1(OP_NEG, TYPE_F32, val0, val0);
2334
2335             src0 = fetchSrc(0, (c + 1) % 3);
2336             src1 = fetchSrc(1, (c + 2) % 3);
2337             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2338          } else {
2339             loadImm(dst0[c], 1.0f);
2340          }
2341       }
2342       break;
2343    case TGSI_OPCODE_ISSG:
2344    case TGSI_OPCODE_SSG:
2345       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2346          src0 = fetchSrc(0, c);
2347          val0 = getScratch();
2348          val1 = getScratch();
2349          mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2350          mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2351          if (srcTy == TYPE_F32)
2352             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2353          else
2354             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2355       }
2356       break;
2357    case TGSI_OPCODE_UCMP:
2358    case TGSI_OPCODE_CMP:
2359       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2360          src0 = fetchSrc(0, c);
2361          src1 = fetchSrc(1, c);
2362          src2 = fetchSrc(2, c);
2363          if (src1 == src2)
2364             mkMov(dst0[c], src1);
2365          else
2366             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2367                   srcTy, dst0[c], srcTy, src1, src2, src0);
2368       }
2369       break;
2370    case TGSI_OPCODE_FRC:
2371       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2372          src0 = fetchSrc(0, c);
2373          val0 = getScratch();
2374          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2375          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2376       }
2377       break;
2378    case TGSI_OPCODE_ROUND:
2379       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2380          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2381          ->rnd = ROUND_NI;
2382       break;
2383    case TGSI_OPCODE_CLAMP:
2384       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2385          src0 = fetchSrc(0, c);
2386          src1 = fetchSrc(1, c);
2387          src2 = fetchSrc(2, c);
2388          val0 = getScratch();
2389          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2390          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2391       }
2392       break;
2393    case TGSI_OPCODE_SLT:
2394    case TGSI_OPCODE_SGE:
2395    case TGSI_OPCODE_SEQ:
2396    case TGSI_OPCODE_SFL:
2397    case TGSI_OPCODE_SGT:
2398    case TGSI_OPCODE_SLE:
2399    case TGSI_OPCODE_SNE:
2400    case TGSI_OPCODE_STR:
2401    case TGSI_OPCODE_FSEQ:
2402    case TGSI_OPCODE_FSGE:
2403    case TGSI_OPCODE_FSLT:
2404    case TGSI_OPCODE_FSNE:
2405    case TGSI_OPCODE_ISGE:
2406    case TGSI_OPCODE_ISLT:
2407    case TGSI_OPCODE_USEQ:
2408    case TGSI_OPCODE_USGE:
2409    case TGSI_OPCODE_USLT:
2410    case TGSI_OPCODE_USNE:
2411       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2412          src0 = fetchSrc(0, c);
2413          src1 = fetchSrc(1, c);
2414          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2415       }
2416       break;
2417    case TGSI_OPCODE_KILL_IF:
2418       val0 = new_LValue(func, FILE_PREDICATE);
2419       for (c = 0; c < 4; ++c) {
2420          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2421          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2422       }
2423       break;
2424    case TGSI_OPCODE_KILL:
2425       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2426       break;
2427    case TGSI_OPCODE_TEX:
2428    case TGSI_OPCODE_TXB:
2429    case TGSI_OPCODE_TXL:
2430    case TGSI_OPCODE_TXP:
2431       //              R  S     L     C    Dx    Dy
2432       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2433       break;
2434    case TGSI_OPCODE_TXD:
2435       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2436       break;
2437    case TGSI_OPCODE_TEX2:
2438       handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2439       break;
2440    case TGSI_OPCODE_TXB2:
2441    case TGSI_OPCODE_TXL2:
2442       handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
2443       break;
2444    case TGSI_OPCODE_SAMPLE:
2445    case TGSI_OPCODE_SAMPLE_B:
2446    case TGSI_OPCODE_SAMPLE_D:
2447    case TGSI_OPCODE_SAMPLE_L:
2448    case TGSI_OPCODE_SAMPLE_C:
2449    case TGSI_OPCODE_SAMPLE_C_LZ:
2450       handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2451       break;
2452    case TGSI_OPCODE_TXF:
2453       handleTXF(dst0, 1, 0x03);
2454       break;
2455    case TGSI_OPCODE_SAMPLE_I:
2456       handleTXF(dst0, 1, 0x03);
2457       break;
2458    case TGSI_OPCODE_SAMPLE_I_MS:
2459       handleTXF(dst0, 1, 0x20);
2460       break;
2461    case TGSI_OPCODE_TXQ:
2462    case TGSI_OPCODE_SVIEWINFO:
2463       handleTXQ(dst0, TXQ_DIMS);
2464       break;
2465    case TGSI_OPCODE_F2I:
2466    case TGSI_OPCODE_F2U:
2467       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2468          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2469       break;
2470    case TGSI_OPCODE_I2F:
2471    case TGSI_OPCODE_U2F:
2472       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2473          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2474       break;
2475    case TGSI_OPCODE_EMIT:
2476    case TGSI_OPCODE_ENDPRIM:
2477       // get vertex stream if specified (must be immediate)
2478       src0 = tgsi.srcCount() ?
2479          mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2480       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2481       break;
2482    case TGSI_OPCODE_IF:
2483    case TGSI_OPCODE_UIF:
2484    {
2485       BasicBlock *ifBB = new BasicBlock(func);
2486
2487       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2488       condBBs.push(bb);
2489       joinBBs.push(bb);
2490
2491       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2492
2493       setPosition(ifBB, true);
2494    }
2495       break;
2496    case TGSI_OPCODE_ELSE:
2497    {
2498       BasicBlock *elseBB = new BasicBlock(func);
2499       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2500
2501       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2502       condBBs.push(bb);
2503
2504       forkBB->getExit()->asFlow()->target.bb = elseBB;
2505       if (!bb->isTerminated())
2506          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2507
2508       setPosition(elseBB, true);
2509    }
2510       break;
2511    case TGSI_OPCODE_ENDIF:
2512    {
2513       BasicBlock *convBB = new BasicBlock(func);
2514       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2515       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2516
2517       if (!bb->isTerminated()) {
2518          // we only want join if none of the clauses ended with CONT/BREAK/RET
2519          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2520             insertConvergenceOps(convBB, forkBB);
2521          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2522          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2523       }
2524
2525       if (prevBB->getExit()->op == OP_BRA) {
2526          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2527          prevBB->getExit()->asFlow()->target.bb = convBB;
2528       }
2529       setPosition(convBB, true);
2530    }
2531       break;
2532    case TGSI_OPCODE_BGNLOOP:
2533    {
2534       BasicBlock *lbgnBB = new BasicBlock(func);
2535       BasicBlock *lbrkBB = new BasicBlock(func);
2536
2537       loopBBs.push(lbgnBB);
2538       breakBBs.push(lbrkBB);
2539       if (loopBBs.getSize() > func->loopNestingBound)
2540          func->loopNestingBound++;
2541
2542       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2543
2544       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2545       setPosition(lbgnBB, true);
2546       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2547    }
2548       break;
2549    case TGSI_OPCODE_ENDLOOP:
2550    {
2551       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2552
2553       if (!bb->isTerminated()) {
2554          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2555          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2556       }
2557       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2558    }
2559       break;
2560    case TGSI_OPCODE_BRK:
2561    {
2562       if (bb->isTerminated())
2563          break;
2564       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2565       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2566       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2567    }
2568       break;
2569    case TGSI_OPCODE_CONT:
2570    {
2571       if (bb->isTerminated())
2572          break;
2573       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2574       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2575       contBB->explicitCont = true;
2576       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2577    }
2578       break;
2579    case TGSI_OPCODE_BGNSUB:
2580    {
2581       Subroutine *s = getSubroutine(ip);
2582       BasicBlock *entry = new BasicBlock(s->f);
2583       BasicBlock *leave = new BasicBlock(s->f);
2584
2585       // multiple entrypoints possible, keep the graph connected
2586       if (prog->getType() == Program::TYPE_COMPUTE)
2587          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2588
2589       sub.cur = s;
2590       s->f->setEntry(entry);
2591       s->f->setExit(leave);
2592       setPosition(entry, true);
2593       return true;
2594    }
2595    case TGSI_OPCODE_ENDSUB:
2596    {
2597       sub.cur = getSubroutine(prog->main);
2598       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2599       return true;
2600    }
2601    case TGSI_OPCODE_CAL:
2602    {
2603       Subroutine *s = getSubroutine(tgsi.getLabel());
2604       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2605       func->call.attach(&s->f->call, Graph::Edge::TREE);
2606       return true;
2607    }
2608    case TGSI_OPCODE_RET:
2609    {
2610       if (bb->isTerminated())
2611          return true;
2612       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2613
2614       if (!isEndOfSubroutine(ip + 1)) {
2615          // insert a PRERET at the entry if this is an early return
2616          // (only needed for sharing code in the epilogue)
2617          BasicBlock *pos = getBB();
2618          setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2619          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2620          setPosition(pos, true);
2621       }
2622       mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2623       bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2624    }
2625       break;
2626    case TGSI_OPCODE_END:
2627    {
2628       // attach and generate epilogue code
2629       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2630       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2631       setPosition(epilogue, true);
2632       if (prog->getType() == Program::TYPE_FRAGMENT)
2633          exportOutputs();
2634       if (info->io.genUserClip > 0)
2635          handleUserClipPlanes();
2636       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2637    }
2638       break;
2639    case TGSI_OPCODE_SWITCH:
2640    case TGSI_OPCODE_CASE:
2641       ERROR("switch/case opcode encountered, should have been lowered\n");
2642       abort();
2643       break;
2644    case TGSI_OPCODE_LOAD:
2645       handleLOAD(dst0);
2646       break;
2647    case TGSI_OPCODE_STORE:
2648       handleSTORE();
2649       break;
2650    case TGSI_OPCODE_BARRIER:
2651       geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2652       geni->fixed = 1;
2653       geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2654       break;
2655    case TGSI_OPCODE_MFENCE:
2656    case TGSI_OPCODE_LFENCE:
2657    case TGSI_OPCODE_SFENCE:
2658       geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2659       geni->fixed = 1;
2660       geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2661       break;
2662    case TGSI_OPCODE_ATOMUADD:
2663    case TGSI_OPCODE_ATOMXCHG:
2664    case TGSI_OPCODE_ATOMCAS:
2665    case TGSI_OPCODE_ATOMAND:
2666    case TGSI_OPCODE_ATOMOR:
2667    case TGSI_OPCODE_ATOMXOR:
2668    case TGSI_OPCODE_ATOMUMIN:
2669    case TGSI_OPCODE_ATOMIMIN:
2670    case TGSI_OPCODE_ATOMUMAX:
2671    case TGSI_OPCODE_ATOMIMAX:
2672       handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2673       break;
2674    default:
2675       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2676       assert(0);
2677       break;
2678    }
2679
2680    if (tgsi.dstCount()) {
2681       for (c = 0; c < 4; ++c) {
2682          if (!dst0[c])
2683             continue;
2684          if (dst0[c] != rDst0[c])
2685             mkMov(rDst0[c], dst0[c]);
2686          storeDst(0, c, rDst0[c]);
2687       }
2688    }
2689    vtxBaseValid = 0;
2690
2691    return true;
2692 }
2693
2694 void
2695 Converter::handleUserClipPlanes()
2696 {
2697    Value *res[8];
2698    int n, i, c;
2699
2700    for (c = 0; c < 4; ++c) {
2701       for (i = 0; i < info->io.genUserClip; ++i) {
2702          Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
2703                                 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
2704          Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
2705          if (c == 0)
2706             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2707          else
2708             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2709       }
2710    }
2711
2712    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2713
2714    for (i = 0; i < info->io.genUserClip; ++i) {
2715       n = i / 4 + first;
2716       c = i % 4;
2717       Symbol *sym =
2718          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2719       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2720    }
2721 }
2722
2723 void
2724 Converter::exportOutputs()
2725 {
2726    for (unsigned int i = 0; i < info->numOutputs; ++i) {
2727       for (unsigned int c = 0; c < 4; ++c) {
2728          if (!oData.exists(sub.cur->values, i, c))
2729             continue;
2730          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2731                                 info->out[i].slot[c] * 4);
2732          Value *val = oData.load(sub.cur->values, i, c, NULL);
2733          if (val)
2734             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2735       }
2736    }
2737 }
2738
2739 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2740      code(code),
2741      tgsi(NULL),
2742      tData(this), aData(this), pData(this), oData(this)
2743 {
2744    info = code->info;
2745
2746    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2747
2748    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2749    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2750    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2751    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2752
2753    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2754    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2755    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
2756    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2757
2758    zero = mkImm((uint32_t)0);
2759
2760    vtxBaseValid = 0;
2761 }
2762
2763 Converter::~Converter()
2764 {
2765 }
2766
2767 inline const Converter::Location *
2768 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
2769 {
2770    ValueMap::l_iterator it = s->values.l.find(v);
2771    return it == s->values.l.end() ? NULL : &it->second;
2772 }
2773
2774 template<typename T> inline void
2775 Converter::BindArgumentsPass::updateCallArgs(
2776    Instruction *i, void (Instruction::*setArg)(int, Value *),
2777    T (Function::*proto))
2778 {
2779    Function *g = i->asFlow()->target.fn;
2780    Subroutine *subg = conv.getSubroutine(g);
2781
2782    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2783       Value *v = (g->*proto)[a].get();
2784       const Converter::Location &l = *getValueLocation(subg, v);
2785       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2786
2787       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2788    }
2789 }
2790
2791 template<typename T> inline void
2792 Converter::BindArgumentsPass::updatePrototype(
2793    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2794 {
2795    (func->*updateSet)();
2796
2797    for (unsigned i = 0; i < set->getSize(); ++i) {
2798       Value *v = func->getLValue(i);
2799       const Converter::Location *l = getValueLocation(sub, v);
2800
2801       // only include values with a matching TGSI register
2802       if (set->test(i) && l && !conv.code->locals.count(*l))
2803          (func->*proto).push_back(v);
2804    }
2805 }
2806
2807 bool
2808 Converter::BindArgumentsPass::visit(Function *f)
2809 {
2810    sub = conv.getSubroutine(f);
2811
2812    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2813         !bi.end(); bi.next()) {
2814       for (Instruction *i = BasicBlock::get(bi)->getFirst();
2815            i; i = i->next) {
2816          if (i->op == OP_CALL && !i->asFlow()->builtin) {
2817             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2818             updateCallArgs(i, &Instruction::setDef, &Function::outs);
2819          }
2820       }
2821    }
2822
2823    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2824       return true;
2825    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2826                    &Function::buildLiveSets, &Function::ins);
2827    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2828                    &Function::buildDefSets, &Function::outs);
2829
2830    return true;
2831 }
2832
2833 bool
2834 Converter::run()
2835 {
2836    BasicBlock *entry = new BasicBlock(prog->main);
2837    BasicBlock *leave = new BasicBlock(prog->main);
2838
2839    prog->main->setEntry(entry);
2840    prog->main->setExit(leave);
2841
2842    setPosition(entry, true);
2843    sub.cur = getSubroutine(prog->main);
2844
2845    if (info->io.genUserClip > 0) {
2846       for (int c = 0; c < 4; ++c)
2847          clipVtx[c] = getScratch();
2848    }
2849
2850    if (prog->getType() == Program::TYPE_FRAGMENT) {
2851       Symbol *sv = mkSysVal(SV_POSITION, 3);
2852       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2853       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2854    }
2855
2856    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2857       if (!handleInstruction(&code->insns[ip]))
2858          return false;
2859    }
2860
2861    if (!BindArgumentsPass(*this).run(prog))
2862       return false;
2863
2864    return true;
2865 }
2866
2867 } // unnamed namespace
2868
2869 namespace nv50_ir {
2870
2871 bool
2872 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2873 {
2874    tgsi::Source src(info);
2875    if (!src.scanSource())
2876       return false;
2877    tlsSize = info->bin.tlsSpace;
2878
2879    Converter builder(this, &src);
2880    return builder.run();
2881 }
2882
2883 } // namespace nv50_ir