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nvc0/ir: add support for INVOCATIONID system value
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_util.h"
27 }
28
29 #include <set>
30
31 #include "codegen/nv50_ir.h"
32 #include "codegen/nv50_ir_util.h"
33 #include "codegen/nv50_ir_build_util.h"
34
35 namespace tgsi {
36
37 class Source;
38
39 static nv50_ir::operation translateOpcode(uint opcode);
40 static nv50_ir::DataFile translateFile(uint file);
41 static nv50_ir::TexTarget translateTexture(uint texTarg);
42 static nv50_ir::SVSemantic translateSysVal(uint sysval);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 nv50_ir::Modifier getMod(int chan) const;
101
102 SrcRegister getIndirect(int dim) const
103 {
104 assert(fsr && isIndirect(dim));
105 if (dim)
106 return SrcRegister(fsr->DimIndirect);
107 return SrcRegister(fsr->Indirect);
108 }
109
110 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
111 {
112 assert(reg.File == TGSI_FILE_IMMEDIATE);
113 assert(!reg.Absolute);
114 assert(!reg.Negate);
115 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
116 }
117
118 private:
119 const struct tgsi_src_register reg;
120 const struct tgsi_full_src_register *fsr;
121 };
122
123 class DstRegister
124 {
125 public:
126 DstRegister(const struct tgsi_full_dst_register *dst)
127 : reg(dst->Register),
128 fdr(dst)
129 { }
130
131 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
132
133 uint getFile() const { return reg.File; }
134
135 bool is2D() const { return reg.Dimension; }
136
137 bool isIndirect(int dim) const
138 {
139 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
140 }
141
142 int getIndex(int dim) const
143 {
144 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
145 }
146
147 unsigned int getMask() const { return reg.WriteMask; }
148
149 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
150
151 SrcRegister getIndirect(int dim) const
152 {
153 assert(fdr && isIndirect(dim));
154 if (dim)
155 return SrcRegister(fdr->DimIndirect);
156 return SrcRegister(fdr->Indirect);
157 }
158
159 private:
160 const struct tgsi_dst_register reg;
161 const struct tgsi_full_dst_register *fdr;
162 };
163
164 inline uint getOpcode() const { return insn->Instruction.Opcode; }
165
166 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
167 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
168
169 // mask of used components of source s
170 unsigned int srcMask(unsigned int s) const;
171
172 SrcRegister getSrc(unsigned int s) const
173 {
174 assert(s < srcCount());
175 return SrcRegister(&insn->Src[s]);
176 }
177
178 DstRegister getDst(unsigned int d) const
179 {
180 assert(d < dstCount());
181 return DstRegister(&insn->Dst[d]);
182 }
183
184 SrcRegister getTexOffset(unsigned int i) const
185 {
186 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
187 return SrcRegister(insn->TexOffsets[i]);
188 }
189
190 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
191
192 bool checkDstSrcAliasing() const;
193
194 inline nv50_ir::operation getOP() const {
195 return translateOpcode(getOpcode()); }
196
197 nv50_ir::DataType inferSrcType() const;
198 nv50_ir::DataType inferDstType() const;
199
200 nv50_ir::CondCode getSetCond() const;
201
202 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
203
204 inline uint getLabel() { return insn->Label.Label; }
205
206 unsigned getSaturate() const { return insn->Instruction.Saturate; }
207
208 void print() const
209 {
210 tgsi_dump_instruction(insn, 1);
211 }
212
213 private:
214 const struct tgsi_full_instruction *insn;
215 };
216
217 unsigned int Instruction::srcMask(unsigned int s) const
218 {
219 unsigned int mask = insn->Dst[0].Register.WriteMask;
220
221 switch (insn->Instruction.Opcode) {
222 case TGSI_OPCODE_COS:
223 case TGSI_OPCODE_SIN:
224 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
225 case TGSI_OPCODE_DP2:
226 return 0x3;
227 case TGSI_OPCODE_DP3:
228 return 0x7;
229 case TGSI_OPCODE_DP4:
230 case TGSI_OPCODE_DPH:
231 case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
232 return 0xf;
233 case TGSI_OPCODE_DST:
234 return mask & (s ? 0xa : 0x6);
235 case TGSI_OPCODE_EX2:
236 case TGSI_OPCODE_EXP:
237 case TGSI_OPCODE_LG2:
238 case TGSI_OPCODE_LOG:
239 case TGSI_OPCODE_POW:
240 case TGSI_OPCODE_RCP:
241 case TGSI_OPCODE_RSQ:
242 case TGSI_OPCODE_SCS:
243 return 0x1;
244 case TGSI_OPCODE_IF:
245 case TGSI_OPCODE_UIF:
246 return 0x1;
247 case TGSI_OPCODE_LIT:
248 return 0xb;
249 case TGSI_OPCODE_TEX2:
250 case TGSI_OPCODE_TXB2:
251 case TGSI_OPCODE_TXL2:
252 return (s == 0) ? 0xf : 0x3;
253 case TGSI_OPCODE_TEX:
254 case TGSI_OPCODE_TXB:
255 case TGSI_OPCODE_TXD:
256 case TGSI_OPCODE_TXL:
257 case TGSI_OPCODE_TXP:
258 case TGSI_OPCODE_LODQ:
259 {
260 const struct tgsi_instruction_texture *tex = &insn->Texture;
261
262 assert(insn->Instruction.Texture);
263
264 mask = 0x7;
265 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
266 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
267 mask |= 0x8; /* bias, lod or proj */
268
269 switch (tex->Texture) {
270 case TGSI_TEXTURE_1D:
271 mask &= 0x9;
272 break;
273 case TGSI_TEXTURE_SHADOW1D:
274 mask &= 0xd;
275 break;
276 case TGSI_TEXTURE_1D_ARRAY:
277 case TGSI_TEXTURE_2D:
278 case TGSI_TEXTURE_RECT:
279 mask &= 0xb;
280 break;
281 case TGSI_TEXTURE_CUBE_ARRAY:
282 case TGSI_TEXTURE_SHADOW2D_ARRAY:
283 case TGSI_TEXTURE_SHADOWCUBE:
284 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
285 mask |= 0x8;
286 break;
287 default:
288 break;
289 }
290 }
291 return mask;
292 case TGSI_OPCODE_XPD:
293 {
294 unsigned int x = 0;
295 if (mask & 1) x |= 0x6;
296 if (mask & 2) x |= 0x5;
297 if (mask & 4) x |= 0x3;
298 return x;
299 }
300 default:
301 break;
302 }
303
304 return mask;
305 }
306
307 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
308 {
309 nv50_ir::Modifier m(0);
310
311 if (reg.Absolute)
312 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
313 if (reg.Negate)
314 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
315 return m;
316 }
317
318 static nv50_ir::DataFile translateFile(uint file)
319 {
320 switch (file) {
321 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
322 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
323 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
324 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
325 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
326 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
327 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
328 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
329 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
330 case TGSI_FILE_SAMPLER:
331 case TGSI_FILE_NULL:
332 default:
333 return nv50_ir::FILE_NULL;
334 }
335 }
336
337 static nv50_ir::SVSemantic translateSysVal(uint sysval)
338 {
339 switch (sysval) {
340 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
341 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
342 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
343 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
344 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
345 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
346 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
347 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
348 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
349 case TGSI_SEMANTIC_SAMPLEID: return nv50_ir::SV_SAMPLE_INDEX;
350 case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
351 case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
352 case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
353 default:
354 assert(0);
355 return nv50_ir::SV_CLOCK;
356 }
357 }
358
359 #define NV50_IR_TEX_TARG_CASE(a, b) \
360 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
361
362 static nv50_ir::TexTarget translateTexture(uint tex)
363 {
364 switch (tex) {
365 NV50_IR_TEX_TARG_CASE(1D, 1D);
366 NV50_IR_TEX_TARG_CASE(2D, 2D);
367 NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
368 NV50_IR_TEX_TARG_CASE(3D, 3D);
369 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
370 NV50_IR_TEX_TARG_CASE(RECT, RECT);
371 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
372 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
373 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
374 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
375 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
376 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
377 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
378 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
379 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
380 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
381 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
382 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
383
384 case TGSI_TEXTURE_UNKNOWN:
385 default:
386 assert(!"invalid texture target");
387 return nv50_ir::TEX_TARGET_2D;
388 }
389 }
390
391 nv50_ir::DataType Instruction::inferSrcType() const
392 {
393 switch (getOpcode()) {
394 case TGSI_OPCODE_UIF:
395 case TGSI_OPCODE_AND:
396 case TGSI_OPCODE_OR:
397 case TGSI_OPCODE_XOR:
398 case TGSI_OPCODE_NOT:
399 case TGSI_OPCODE_U2F:
400 case TGSI_OPCODE_UADD:
401 case TGSI_OPCODE_UDIV:
402 case TGSI_OPCODE_UMOD:
403 case TGSI_OPCODE_UMAD:
404 case TGSI_OPCODE_UMUL:
405 case TGSI_OPCODE_UMAX:
406 case TGSI_OPCODE_UMIN:
407 case TGSI_OPCODE_USEQ:
408 case TGSI_OPCODE_USGE:
409 case TGSI_OPCODE_USLT:
410 case TGSI_OPCODE_USNE:
411 case TGSI_OPCODE_USHR:
412 case TGSI_OPCODE_UCMP:
413 case TGSI_OPCODE_ATOMUADD:
414 case TGSI_OPCODE_ATOMXCHG:
415 case TGSI_OPCODE_ATOMCAS:
416 case TGSI_OPCODE_ATOMAND:
417 case TGSI_OPCODE_ATOMOR:
418 case TGSI_OPCODE_ATOMXOR:
419 case TGSI_OPCODE_ATOMUMIN:
420 case TGSI_OPCODE_ATOMUMAX:
421 return nv50_ir::TYPE_U32;
422 case TGSI_OPCODE_I2F:
423 case TGSI_OPCODE_IDIV:
424 case TGSI_OPCODE_IMAX:
425 case TGSI_OPCODE_IMIN:
426 case TGSI_OPCODE_IABS:
427 case TGSI_OPCODE_INEG:
428 case TGSI_OPCODE_ISGE:
429 case TGSI_OPCODE_ISHR:
430 case TGSI_OPCODE_ISLT:
431 case TGSI_OPCODE_ISSG:
432 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
433 case TGSI_OPCODE_MOD:
434 case TGSI_OPCODE_UARL:
435 case TGSI_OPCODE_ATOMIMIN:
436 case TGSI_OPCODE_ATOMIMAX:
437 return nv50_ir::TYPE_S32;
438 default:
439 return nv50_ir::TYPE_F32;
440 }
441 }
442
443 nv50_ir::DataType Instruction::inferDstType() const
444 {
445 switch (getOpcode()) {
446 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
447 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
448 case TGSI_OPCODE_FSEQ:
449 case TGSI_OPCODE_FSGE:
450 case TGSI_OPCODE_FSLT:
451 case TGSI_OPCODE_FSNE:
452 return nv50_ir::TYPE_U32;
453 case TGSI_OPCODE_I2F:
454 case TGSI_OPCODE_U2F:
455 return nv50_ir::TYPE_F32;
456 default:
457 return inferSrcType();
458 }
459 }
460
461 nv50_ir::CondCode Instruction::getSetCond() const
462 {
463 using namespace nv50_ir;
464
465 switch (getOpcode()) {
466 case TGSI_OPCODE_SLT:
467 case TGSI_OPCODE_ISLT:
468 case TGSI_OPCODE_USLT:
469 case TGSI_OPCODE_FSLT:
470 return CC_LT;
471 case TGSI_OPCODE_SLE:
472 return CC_LE;
473 case TGSI_OPCODE_SGE:
474 case TGSI_OPCODE_ISGE:
475 case TGSI_OPCODE_USGE:
476 case TGSI_OPCODE_FSGE:
477 return CC_GE;
478 case TGSI_OPCODE_SGT:
479 return CC_GT;
480 case TGSI_OPCODE_SEQ:
481 case TGSI_OPCODE_USEQ:
482 case TGSI_OPCODE_FSEQ:
483 return CC_EQ;
484 case TGSI_OPCODE_SNE:
485 case TGSI_OPCODE_FSNE:
486 return CC_NEU;
487 case TGSI_OPCODE_USNE:
488 return CC_NE;
489 case TGSI_OPCODE_SFL:
490 return CC_NEVER;
491 case TGSI_OPCODE_STR:
492 default:
493 return CC_ALWAYS;
494 }
495 }
496
497 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
498
499 static nv50_ir::operation translateOpcode(uint opcode)
500 {
501 switch (opcode) {
502 NV50_IR_OPCODE_CASE(ARL, SHL);
503 NV50_IR_OPCODE_CASE(MOV, MOV);
504
505 NV50_IR_OPCODE_CASE(RCP, RCP);
506 NV50_IR_OPCODE_CASE(RSQ, RSQ);
507
508 NV50_IR_OPCODE_CASE(MUL, MUL);
509 NV50_IR_OPCODE_CASE(ADD, ADD);
510
511 NV50_IR_OPCODE_CASE(MIN, MIN);
512 NV50_IR_OPCODE_CASE(MAX, MAX);
513 NV50_IR_OPCODE_CASE(SLT, SET);
514 NV50_IR_OPCODE_CASE(SGE, SET);
515 NV50_IR_OPCODE_CASE(MAD, MAD);
516 NV50_IR_OPCODE_CASE(SUB, SUB);
517
518 NV50_IR_OPCODE_CASE(FLR, FLOOR);
519 NV50_IR_OPCODE_CASE(ROUND, CVT);
520 NV50_IR_OPCODE_CASE(EX2, EX2);
521 NV50_IR_OPCODE_CASE(LG2, LG2);
522 NV50_IR_OPCODE_CASE(POW, POW);
523
524 NV50_IR_OPCODE_CASE(ABS, ABS);
525
526 NV50_IR_OPCODE_CASE(COS, COS);
527 NV50_IR_OPCODE_CASE(DDX, DFDX);
528 NV50_IR_OPCODE_CASE(DDY, DFDY);
529 NV50_IR_OPCODE_CASE(KILL, DISCARD);
530
531 NV50_IR_OPCODE_CASE(SEQ, SET);
532 NV50_IR_OPCODE_CASE(SFL, SET);
533 NV50_IR_OPCODE_CASE(SGT, SET);
534 NV50_IR_OPCODE_CASE(SIN, SIN);
535 NV50_IR_OPCODE_CASE(SLE, SET);
536 NV50_IR_OPCODE_CASE(SNE, SET);
537 NV50_IR_OPCODE_CASE(STR, SET);
538 NV50_IR_OPCODE_CASE(TEX, TEX);
539 NV50_IR_OPCODE_CASE(TXD, TXD);
540 NV50_IR_OPCODE_CASE(TXP, TEX);
541
542 NV50_IR_OPCODE_CASE(BRA, BRA);
543 NV50_IR_OPCODE_CASE(CAL, CALL);
544 NV50_IR_OPCODE_CASE(RET, RET);
545 NV50_IR_OPCODE_CASE(CMP, SLCT);
546
547 NV50_IR_OPCODE_CASE(TXB, TXB);
548
549 NV50_IR_OPCODE_CASE(DIV, DIV);
550
551 NV50_IR_OPCODE_CASE(TXL, TXL);
552
553 NV50_IR_OPCODE_CASE(CEIL, CEIL);
554 NV50_IR_OPCODE_CASE(I2F, CVT);
555 NV50_IR_OPCODE_CASE(NOT, NOT);
556 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
557 NV50_IR_OPCODE_CASE(SHL, SHL);
558
559 NV50_IR_OPCODE_CASE(AND, AND);
560 NV50_IR_OPCODE_CASE(OR, OR);
561 NV50_IR_OPCODE_CASE(MOD, MOD);
562 NV50_IR_OPCODE_CASE(XOR, XOR);
563 NV50_IR_OPCODE_CASE(SAD, SAD);
564 NV50_IR_OPCODE_CASE(TXF, TXF);
565 NV50_IR_OPCODE_CASE(TXQ, TXQ);
566 NV50_IR_OPCODE_CASE(TG4, TXG);
567 NV50_IR_OPCODE_CASE(LODQ, TXLQ);
568
569 NV50_IR_OPCODE_CASE(EMIT, EMIT);
570 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
571
572 NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
573
574 NV50_IR_OPCODE_CASE(F2I, CVT);
575 NV50_IR_OPCODE_CASE(FSEQ, SET);
576 NV50_IR_OPCODE_CASE(FSGE, SET);
577 NV50_IR_OPCODE_CASE(FSLT, SET);
578 NV50_IR_OPCODE_CASE(FSNE, SET);
579 NV50_IR_OPCODE_CASE(IDIV, DIV);
580 NV50_IR_OPCODE_CASE(IMAX, MAX);
581 NV50_IR_OPCODE_CASE(IMIN, MIN);
582 NV50_IR_OPCODE_CASE(IABS, ABS);
583 NV50_IR_OPCODE_CASE(INEG, NEG);
584 NV50_IR_OPCODE_CASE(ISGE, SET);
585 NV50_IR_OPCODE_CASE(ISHR, SHR);
586 NV50_IR_OPCODE_CASE(ISLT, SET);
587 NV50_IR_OPCODE_CASE(F2U, CVT);
588 NV50_IR_OPCODE_CASE(U2F, CVT);
589 NV50_IR_OPCODE_CASE(UADD, ADD);
590 NV50_IR_OPCODE_CASE(UDIV, DIV);
591 NV50_IR_OPCODE_CASE(UMAD, MAD);
592 NV50_IR_OPCODE_CASE(UMAX, MAX);
593 NV50_IR_OPCODE_CASE(UMIN, MIN);
594 NV50_IR_OPCODE_CASE(UMOD, MOD);
595 NV50_IR_OPCODE_CASE(UMUL, MUL);
596 NV50_IR_OPCODE_CASE(USEQ, SET);
597 NV50_IR_OPCODE_CASE(USGE, SET);
598 NV50_IR_OPCODE_CASE(USHR, SHR);
599 NV50_IR_OPCODE_CASE(USLT, SET);
600 NV50_IR_OPCODE_CASE(USNE, SET);
601
602 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
603 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
604 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
605 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
606 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
607 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
608 NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
609 NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
610 NV50_IR_OPCODE_CASE(GATHER4, TXG);
611 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
612
613 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
614 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
615 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
616 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
617 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
618 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
619 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
620 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
621 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
622 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
623
624 NV50_IR_OPCODE_CASE(TEX2, TEX);
625 NV50_IR_OPCODE_CASE(TXB2, TXB);
626 NV50_IR_OPCODE_CASE(TXL2, TXL);
627
628 NV50_IR_OPCODE_CASE(END, EXIT);
629
630 default:
631 return nv50_ir::OP_NOP;
632 }
633 }
634
635 static uint16_t opcodeToSubOp(uint opcode)
636 {
637 switch (opcode) {
638 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
639 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
640 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
641 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
642 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
643 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
644 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
645 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
646 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
647 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
648 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
649 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
650 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
651 default:
652 return 0;
653 }
654 }
655
656 bool Instruction::checkDstSrcAliasing() const
657 {
658 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
659 return false;
660
661 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
662 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
663 break;
664 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
665 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
666 return true;
667 }
668 return false;
669 }
670
671 class Source
672 {
673 public:
674 Source(struct nv50_ir_prog_info *);
675 ~Source();
676
677 public:
678 bool scanSource();
679 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
680
681 public:
682 struct tgsi_shader_info scan;
683 struct tgsi_full_instruction *insns;
684 const struct tgsi_token *tokens;
685 struct nv50_ir_prog_info *info;
686
687 nv50_ir::DynArray tempArrays;
688 nv50_ir::DynArray immdArrays;
689
690 typedef nv50_ir::BuildUtil::Location Location;
691 // these registers are per-subroutine, cannot be used for parameter passing
692 std::set<Location> locals;
693
694 bool mainTempsInLMem;
695
696 int clipVertexOutput;
697
698 struct TextureView {
699 uint8_t target; // TGSI_TEXTURE_*
700 };
701 std::vector<TextureView> textureViews;
702
703 struct Resource {
704 uint8_t target; // TGSI_TEXTURE_*
705 bool raw;
706 uint8_t slot; // $surface index
707 };
708 std::vector<Resource> resources;
709
710 private:
711 int inferSysValDirection(unsigned sn) const;
712 bool scanDeclaration(const struct tgsi_full_declaration *);
713 bool scanInstruction(const struct tgsi_full_instruction *);
714 void scanProperty(const struct tgsi_full_property *);
715 void scanImmediate(const struct tgsi_full_immediate *);
716
717 inline bool isEdgeFlagPassthrough(const Instruction&) const;
718 };
719
720 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
721 {
722 tokens = (const struct tgsi_token *)info->bin.source;
723
724 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
725 tgsi_dump(tokens, 0);
726
727 mainTempsInLMem = FALSE;
728 }
729
730 Source::~Source()
731 {
732 if (insns)
733 FREE(insns);
734
735 if (info->immd.data)
736 FREE(info->immd.data);
737 if (info->immd.type)
738 FREE(info->immd.type);
739 }
740
741 bool Source::scanSource()
742 {
743 unsigned insnCount = 0;
744 struct tgsi_parse_context parse;
745
746 tgsi_scan_shader(tokens, &scan);
747
748 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
749 sizeof(insns[0]));
750 if (!insns)
751 return false;
752
753 clipVertexOutput = -1;
754
755 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
756 resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
757
758 info->immd.bufSize = 0;
759
760 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
761 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
762 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
763
764 if (info->type == PIPE_SHADER_FRAGMENT) {
765 info->prop.fp.writesDepth = scan.writes_z;
766 info->prop.fp.usesDiscard = scan.uses_kill;
767 } else
768 if (info->type == PIPE_SHADER_GEOMETRY) {
769 info->prop.gp.instanceCount = 1; // default value
770 }
771
772 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
773 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
774
775 tgsi_parse_init(&parse, tokens);
776 while (!tgsi_parse_end_of_tokens(&parse)) {
777 tgsi_parse_token(&parse);
778
779 switch (parse.FullToken.Token.Type) {
780 case TGSI_TOKEN_TYPE_IMMEDIATE:
781 scanImmediate(&parse.FullToken.FullImmediate);
782 break;
783 case TGSI_TOKEN_TYPE_DECLARATION:
784 scanDeclaration(&parse.FullToken.FullDeclaration);
785 break;
786 case TGSI_TOKEN_TYPE_INSTRUCTION:
787 insns[insnCount++] = parse.FullToken.FullInstruction;
788 scanInstruction(&parse.FullToken.FullInstruction);
789 break;
790 case TGSI_TOKEN_TYPE_PROPERTY:
791 scanProperty(&parse.FullToken.FullProperty);
792 break;
793 default:
794 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
795 break;
796 }
797 }
798 tgsi_parse_free(&parse);
799
800 if (mainTempsInLMem)
801 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
802
803 if (info->io.genUserClip > 0) {
804 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
805
806 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
807
808 for (unsigned int n = 0; n < nOut; ++n) {
809 unsigned int i = info->numOutputs++;
810 info->out[i].id = i;
811 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
812 info->out[i].si = n;
813 info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
814 }
815 }
816
817 return info->assignSlots(info) == 0;
818 }
819
820 void Source::scanProperty(const struct tgsi_full_property *prop)
821 {
822 switch (prop->Property.PropertyName) {
823 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
824 info->prop.gp.outputPrim = prop->u[0].Data;
825 break;
826 case TGSI_PROPERTY_GS_INPUT_PRIM:
827 info->prop.gp.inputPrim = prop->u[0].Data;
828 break;
829 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
830 info->prop.gp.maxVertices = prop->u[0].Data;
831 break;
832 #if 0
833 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
834 info->prop.gp.instanceCount = prop->u[0].Data;
835 break;
836 #endif
837 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
838 info->prop.fp.separateFragData = TRUE;
839 break;
840 case TGSI_PROPERTY_FS_COORD_ORIGIN:
841 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
842 // we don't care
843 break;
844 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
845 info->io.genUserClip = -1;
846 break;
847 default:
848 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
849 break;
850 }
851 }
852
853 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
854 {
855 const unsigned n = info->immd.count++;
856
857 assert(n < scan.immediate_count);
858
859 for (int c = 0; c < 4; ++c)
860 info->immd.data[n * 4 + c] = imm->u[c].Uint;
861
862 info->immd.type[n] = imm->Immediate.DataType;
863 }
864
865 int Source::inferSysValDirection(unsigned sn) const
866 {
867 switch (sn) {
868 case TGSI_SEMANTIC_INSTANCEID:
869 case TGSI_SEMANTIC_VERTEXID:
870 return 1;
871 case TGSI_SEMANTIC_LAYER:
872 #if 0
873 case TGSI_SEMANTIC_VIEWPORTINDEX:
874 return 0;
875 #endif
876 case TGSI_SEMANTIC_PRIMID:
877 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
878 default:
879 return 0;
880 }
881 }
882
883 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
884 {
885 unsigned i, c;
886 unsigned sn = TGSI_SEMANTIC_GENERIC;
887 unsigned si = 0;
888 const unsigned first = decl->Range.First, last = decl->Range.Last;
889
890 if (decl->Declaration.Semantic) {
891 sn = decl->Semantic.Name;
892 si = decl->Semantic.Index;
893 }
894
895 if (decl->Declaration.Local) {
896 for (i = first; i <= last; ++i) {
897 for (c = 0; c < 4; ++c) {
898 locals.insert(
899 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
900 }
901 }
902 }
903
904 switch (decl->Declaration.File) {
905 case TGSI_FILE_INPUT:
906 if (info->type == PIPE_SHADER_VERTEX) {
907 // all vertex attributes are equal
908 for (i = first; i <= last; ++i) {
909 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
910 info->in[i].si = i;
911 }
912 } else {
913 for (i = first; i <= last; ++i, ++si) {
914 info->in[i].id = i;
915 info->in[i].sn = sn;
916 info->in[i].si = si;
917 if (info->type == PIPE_SHADER_FRAGMENT) {
918 // translate interpolation mode
919 switch (decl->Interp.Interpolate) {
920 case TGSI_INTERPOLATE_CONSTANT:
921 info->in[i].flat = 1;
922 break;
923 case TGSI_INTERPOLATE_COLOR:
924 info->in[i].sc = 1;
925 break;
926 case TGSI_INTERPOLATE_LINEAR:
927 info->in[i].linear = 1;
928 break;
929 default:
930 break;
931 }
932 if (decl->Interp.Centroid || info->io.sampleInterp)
933 info->in[i].centroid = 1;
934 }
935 }
936 }
937 break;
938 case TGSI_FILE_OUTPUT:
939 for (i = first; i <= last; ++i, ++si) {
940 switch (sn) {
941 case TGSI_SEMANTIC_POSITION:
942 if (info->type == PIPE_SHADER_FRAGMENT)
943 info->io.fragDepth = i;
944 else
945 if (clipVertexOutput < 0)
946 clipVertexOutput = i;
947 break;
948 case TGSI_SEMANTIC_COLOR:
949 if (info->type == PIPE_SHADER_FRAGMENT)
950 info->prop.fp.numColourResults++;
951 break;
952 case TGSI_SEMANTIC_EDGEFLAG:
953 info->io.edgeFlagOut = i;
954 break;
955 case TGSI_SEMANTIC_CLIPVERTEX:
956 clipVertexOutput = i;
957 break;
958 case TGSI_SEMANTIC_CLIPDIST:
959 info->io.clipDistanceMask |=
960 decl->Declaration.UsageMask << (si * 4);
961 info->io.genUserClip = -1;
962 break;
963 case TGSI_SEMANTIC_SAMPLEMASK:
964 info->io.sampleMask = i;
965 break;
966 default:
967 break;
968 }
969 info->out[i].id = i;
970 info->out[i].sn = sn;
971 info->out[i].si = si;
972 }
973 break;
974 case TGSI_FILE_SYSTEM_VALUE:
975 switch (sn) {
976 case TGSI_SEMANTIC_INSTANCEID:
977 info->io.instanceId = first;
978 break;
979 case TGSI_SEMANTIC_VERTEXID:
980 info->io.vertexId = first;
981 break;
982 default:
983 break;
984 }
985 for (i = first; i <= last; ++i, ++si) {
986 info->sv[i].sn = sn;
987 info->sv[i].si = si;
988 info->sv[i].input = inferSysValDirection(sn);
989 }
990 break;
991 case TGSI_FILE_RESOURCE:
992 for (i = first; i <= last; ++i) {
993 resources[i].target = decl->Resource.Resource;
994 resources[i].raw = decl->Resource.Raw;
995 resources[i].slot = i;
996 }
997 break;
998 case TGSI_FILE_SAMPLER_VIEW:
999 for (i = first; i <= last; ++i)
1000 textureViews[i].target = decl->SamplerView.Resource;
1001 break;
1002 case TGSI_FILE_NULL:
1003 case TGSI_FILE_TEMPORARY:
1004 case TGSI_FILE_ADDRESS:
1005 case TGSI_FILE_CONSTANT:
1006 case TGSI_FILE_IMMEDIATE:
1007 case TGSI_FILE_PREDICATE:
1008 case TGSI_FILE_SAMPLER:
1009 break;
1010 default:
1011 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1012 return false;
1013 }
1014 return true;
1015 }
1016
1017 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1018 {
1019 return insn.getOpcode() == TGSI_OPCODE_MOV &&
1020 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1021 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1022 }
1023
1024 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1025 {
1026 Instruction insn(inst);
1027
1028 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1029 info->numBarriers = 1;
1030
1031 if (insn.dstCount()) {
1032 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1033 Instruction::DstRegister dst = insn.getDst(0);
1034
1035 if (dst.isIndirect(0))
1036 for (unsigned i = 0; i < info->numOutputs; ++i)
1037 info->out[i].mask = 0xf;
1038 else
1039 info->out[dst.getIndex(0)].mask |= dst.getMask();
1040
1041 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1042 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1043 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1044 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1045 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1046 info->out[dst.getIndex(0)].mask &= 1;
1047
1048 if (isEdgeFlagPassthrough(insn))
1049 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1050 } else
1051 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1052 if (insn.getDst(0).isIndirect(0))
1053 mainTempsInLMem = TRUE;
1054 }
1055 }
1056
1057 for (unsigned s = 0; s < insn.srcCount(); ++s) {
1058 Instruction::SrcRegister src = insn.getSrc(s);
1059 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1060 if (src.isIndirect(0))
1061 mainTempsInLMem = TRUE;
1062 } else
1063 if (src.getFile() == TGSI_FILE_RESOURCE) {
1064 if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1065 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1066 0x1 : 0x2;
1067 }
1068 if (src.getFile() != TGSI_FILE_INPUT)
1069 continue;
1070 unsigned mask = insn.srcMask(s);
1071
1072 if (src.isIndirect(0)) {
1073 for (unsigned i = 0; i < info->numInputs; ++i)
1074 info->in[i].mask = 0xf;
1075 } else {
1076 const int i = src.getIndex(0);
1077 for (unsigned c = 0; c < 4; ++c) {
1078 if (!(mask & (1 << c)))
1079 continue;
1080 int k = src.getSwizzle(c);
1081 if (k <= TGSI_SWIZZLE_W)
1082 info->in[i].mask |= 1 << k;
1083 }
1084 switch (info->in[i].sn) {
1085 case TGSI_SEMANTIC_PSIZE:
1086 case TGSI_SEMANTIC_PRIMID:
1087 case TGSI_SEMANTIC_FOG:
1088 info->in[i].mask &= 0x1;
1089 break;
1090 case TGSI_SEMANTIC_PCOORD:
1091 info->in[i].mask &= 0x3;
1092 break;
1093 default:
1094 break;
1095 }
1096 }
1097 }
1098 return true;
1099 }
1100
1101 nv50_ir::TexInstruction::Target
1102 Instruction::getTexture(const tgsi::Source *code, int s) const
1103 {
1104 // XXX: indirect access
1105 unsigned int r;
1106
1107 switch (getSrc(s).getFile()) {
1108 case TGSI_FILE_RESOURCE:
1109 r = getSrc(s).getIndex(0);
1110 return translateTexture(code->resources.at(r).target);
1111 case TGSI_FILE_SAMPLER_VIEW:
1112 r = getSrc(s).getIndex(0);
1113 return translateTexture(code->textureViews.at(r).target);
1114 default:
1115 return translateTexture(insn->Texture.Texture);
1116 }
1117 }
1118
1119 } // namespace tgsi
1120
1121 namespace {
1122
1123 using namespace nv50_ir;
1124
1125 class Converter : public BuildUtil
1126 {
1127 public:
1128 Converter(Program *, const tgsi::Source *);
1129 ~Converter();
1130
1131 bool run();
1132
1133 private:
1134 struct Subroutine
1135 {
1136 Subroutine(Function *f) : f(f) { }
1137 Function *f;
1138 ValueMap values;
1139 };
1140
1141 Value *shiftAddress(Value *);
1142 Value *getVertexBase(int s);
1143 DataArray *getArrayForFile(unsigned file, int idx);
1144 Value *fetchSrc(int s, int c);
1145 Value *acquireDst(int d, int c);
1146 void storeDst(int d, int c, Value *);
1147
1148 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1149 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1150 Value *val, Value *ptr);
1151
1152 Value *applySrcMod(Value *, int s, int c);
1153
1154 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1155 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1156 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1157
1158 bool handleInstruction(const struct tgsi_full_instruction *);
1159 void exportOutputs();
1160 inline Subroutine *getSubroutine(unsigned ip);
1161 inline Subroutine *getSubroutine(Function *);
1162 inline bool isEndOfSubroutine(uint ip);
1163
1164 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1165
1166 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1167 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1168 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1169 void handleTXF(Value *dst0[4], int R, int L_M);
1170 void handleTXQ(Value *dst0[4], enum TexQuery);
1171 void handleLIT(Value *dst0[4]);
1172 void handleUserClipPlanes();
1173
1174 Symbol *getResourceBase(int r);
1175 void getResourceCoords(std::vector<Value *>&, int r, int s);
1176
1177 void handleLOAD(Value *dst0[4]);
1178 void handleSTORE();
1179 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1180
1181 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1182
1183 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1184
1185 Value *buildDot(int dim);
1186
1187 class BindArgumentsPass : public Pass {
1188 public:
1189 BindArgumentsPass(Converter &conv) : conv(conv) { }
1190
1191 private:
1192 Converter &conv;
1193 Subroutine *sub;
1194
1195 inline const Location *getValueLocation(Subroutine *, Value *);
1196
1197 template<typename T> inline void
1198 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1199 T (Function::*proto));
1200
1201 template<typename T> inline void
1202 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1203 T (Function::*proto));
1204
1205 protected:
1206 bool visit(Function *);
1207 bool visit(BasicBlock *bb) { return false; }
1208 };
1209
1210 private:
1211 const struct tgsi::Source *code;
1212 const struct nv50_ir_prog_info *info;
1213
1214 struct {
1215 std::map<unsigned, Subroutine> map;
1216 Subroutine *cur;
1217 } sub;
1218
1219 uint ip; // instruction pointer
1220
1221 tgsi::Instruction tgsi;
1222
1223 DataType dstTy;
1224 DataType srcTy;
1225
1226 DataArray tData; // TGSI_FILE_TEMPORARY
1227 DataArray aData; // TGSI_FILE_ADDRESS
1228 DataArray pData; // TGSI_FILE_PREDICATE
1229 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1230
1231 Value *zero;
1232 Value *fragCoord[4];
1233 Value *clipVtx[4];
1234
1235 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1236 uint8_t vtxBaseValid;
1237
1238 Stack condBBs; // fork BB, then else clause BB
1239 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1240 Stack loopBBs; // loop headers
1241 Stack breakBBs; // end of / after loop
1242 };
1243
1244 Symbol *
1245 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1246 {
1247 const int swz = src.getSwizzle(c);
1248
1249 return makeSym(src.getFile(),
1250 src.is2D() ? src.getIndex(1) : 0,
1251 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1252 src.getIndex(0) * 16 + swz * 4);
1253 }
1254
1255 Symbol *
1256 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1257 {
1258 return makeSym(dst.getFile(),
1259 dst.is2D() ? dst.getIndex(1) : 0,
1260 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1261 dst.getIndex(0) * 16 + c * 4);
1262 }
1263
1264 Symbol *
1265 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1266 {
1267 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1268
1269 sym->reg.fileIndex = fileIdx;
1270
1271 if (idx >= 0) {
1272 if (sym->reg.file == FILE_SHADER_INPUT)
1273 sym->setOffset(info->in[idx].slot[c] * 4);
1274 else
1275 if (sym->reg.file == FILE_SHADER_OUTPUT)
1276 sym->setOffset(info->out[idx].slot[c] * 4);
1277 else
1278 if (sym->reg.file == FILE_SYSTEM_VALUE)
1279 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1280 else
1281 sym->setOffset(address);
1282 } else {
1283 sym->setOffset(address);
1284 }
1285 return sym;
1286 }
1287
1288 static inline uint8_t
1289 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1290 {
1291 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1292
1293 if (var->flat)
1294 mode = NV50_IR_INTERP_FLAT;
1295 else
1296 if (var->linear)
1297 mode = NV50_IR_INTERP_LINEAR;
1298 else
1299 if (var->sc)
1300 mode = NV50_IR_INTERP_SC;
1301
1302 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1303 ? OP_PINTERP : OP_LINTERP;
1304
1305 if (var->centroid)
1306 mode |= NV50_IR_INTERP_CENTROID;
1307
1308 return mode;
1309 }
1310
1311 Value *
1312 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1313 {
1314 operation op;
1315
1316 // XXX: no way to know interpolation mode if we don't know what's accessed
1317 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1318 src.getIndex(0)], op);
1319
1320 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1321
1322 insn->setDef(0, getScratch());
1323 insn->setSrc(0, srcToSym(src, c));
1324 if (op == OP_PINTERP)
1325 insn->setSrc(1, fragCoord[3]);
1326 if (ptr)
1327 insn->setIndirect(0, 0, ptr);
1328
1329 insn->setInterpolate(mode);
1330
1331 bb->insertTail(insn);
1332 return insn->getDef(0);
1333 }
1334
1335 Value *
1336 Converter::applySrcMod(Value *val, int s, int c)
1337 {
1338 Modifier m = tgsi.getSrc(s).getMod(c);
1339 DataType ty = tgsi.inferSrcType();
1340
1341 if (m & Modifier(NV50_IR_MOD_ABS))
1342 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1343
1344 if (m & Modifier(NV50_IR_MOD_NEG))
1345 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1346
1347 return val;
1348 }
1349
1350 Value *
1351 Converter::getVertexBase(int s)
1352 {
1353 assert(s < 5);
1354 if (!(vtxBaseValid & (1 << s))) {
1355 const int index = tgsi.getSrc(s).getIndex(1);
1356 Value *rel = NULL;
1357 if (tgsi.getSrc(s).isIndirect(1))
1358 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1359 vtxBaseValid |= 1 << s;
1360 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1361 mkImm(index), rel);
1362 }
1363 return vtxBase[s];
1364 }
1365
1366 Value *
1367 Converter::fetchSrc(int s, int c)
1368 {
1369 Value *res;
1370 Value *ptr = NULL, *dimRel = NULL;
1371
1372 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1373
1374 if (src.isIndirect(0))
1375 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1376
1377 if (src.is2D()) {
1378 switch (src.getFile()) {
1379 case TGSI_FILE_INPUT:
1380 dimRel = getVertexBase(s);
1381 break;
1382 case TGSI_FILE_CONSTANT:
1383 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1384 if (src.isIndirect(1))
1385 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1386 break;
1387 default:
1388 break;
1389 }
1390 }
1391
1392 res = fetchSrc(src, c, ptr);
1393
1394 if (dimRel)
1395 res->getInsn()->setIndirect(0, 1, dimRel);
1396
1397 return applySrcMod(res, s, c);
1398 }
1399
1400 Converter::DataArray *
1401 Converter::getArrayForFile(unsigned file, int idx)
1402 {
1403 switch (file) {
1404 case TGSI_FILE_TEMPORARY:
1405 return &tData;
1406 case TGSI_FILE_PREDICATE:
1407 return &pData;
1408 case TGSI_FILE_ADDRESS:
1409 return &aData;
1410 case TGSI_FILE_OUTPUT:
1411 assert(prog->getType() == Program::TYPE_FRAGMENT);
1412 return &oData;
1413 default:
1414 assert(!"invalid/unhandled TGSI source file");
1415 return NULL;
1416 }
1417 }
1418
1419 Value *
1420 Converter::shiftAddress(Value *index)
1421 {
1422 if (!index)
1423 return NULL;
1424 return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1425 }
1426
1427 Value *
1428 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1429 {
1430 const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1431 const int idx = src.getIndex(0);
1432 const int swz = src.getSwizzle(c);
1433
1434 switch (src.getFile()) {
1435 case TGSI_FILE_IMMEDIATE:
1436 assert(!ptr);
1437 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1438 case TGSI_FILE_CONSTANT:
1439 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1440 case TGSI_FILE_INPUT:
1441 if (prog->getType() == Program::TYPE_FRAGMENT) {
1442 // don't load masked inputs, won't be assigned a slot
1443 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1444 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1445 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1446 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1447 return interpolate(src, c, shiftAddress(ptr));
1448 } else
1449 if (prog->getType() == Program::TYPE_GEOMETRY) {
1450 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1451 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1452 // XXX: This is going to be a problem with scalar arrays, i.e. when
1453 // we cannot assume that the address is given in units of vec4.
1454 //
1455 // nv50 and nvc0 need different things here, so let the lowering
1456 // passes decide what to do with the address
1457 if (ptr)
1458 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1459 }
1460 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1461 case TGSI_FILE_OUTPUT:
1462 assert(!"load from output file");
1463 return NULL;
1464 case TGSI_FILE_SYSTEM_VALUE:
1465 assert(!ptr);
1466 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1467 default:
1468 return getArrayForFile(src.getFile(), idx2d)->load(
1469 sub.cur->values, idx, swz, shiftAddress(ptr));
1470 }
1471 }
1472
1473 Value *
1474 Converter::acquireDst(int d, int c)
1475 {
1476 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1477 const unsigned f = dst.getFile();
1478 const int idx = dst.getIndex(0);
1479 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1480
1481 if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1482 return NULL;
1483
1484 if (dst.isIndirect(0) ||
1485 f == TGSI_FILE_SYSTEM_VALUE ||
1486 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1487 return getScratch();
1488
1489 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1490 }
1491
1492 void
1493 Converter::storeDst(int d, int c, Value *val)
1494 {
1495 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1496
1497 switch (tgsi.getSaturate()) {
1498 case TGSI_SAT_NONE:
1499 break;
1500 case TGSI_SAT_ZERO_ONE:
1501 mkOp1(OP_SAT, dstTy, val, val);
1502 break;
1503 case TGSI_SAT_MINUS_PLUS_ONE:
1504 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1505 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1506 break;
1507 default:
1508 assert(!"invalid saturation mode");
1509 break;
1510 }
1511
1512 Value *ptr = NULL;
1513 if (dst.isIndirect(0))
1514 ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1515
1516 if (info->io.genUserClip > 0 &&
1517 dst.getFile() == TGSI_FILE_OUTPUT &&
1518 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1519 mkMov(clipVtx[c], val);
1520 val = clipVtx[c];
1521 }
1522
1523 storeDst(dst, c, val, ptr);
1524 }
1525
1526 void
1527 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1528 Value *val, Value *ptr)
1529 {
1530 const unsigned f = dst.getFile();
1531 const int idx = dst.getIndex(0);
1532 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1533
1534 if (f == TGSI_FILE_SYSTEM_VALUE) {
1535 assert(!ptr);
1536 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1537 } else
1538 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1539 if (ptr || (info->out[idx].mask & (1 << c)))
1540 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1541 } else
1542 if (f == TGSI_FILE_TEMPORARY ||
1543 f == TGSI_FILE_PREDICATE ||
1544 f == TGSI_FILE_ADDRESS ||
1545 f == TGSI_FILE_OUTPUT) {
1546 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1547 } else {
1548 assert(!"invalid dst file");
1549 }
1550 }
1551
1552 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1553 for (chan = 0; chan < 4; ++chan) \
1554 if (!inst.getDst(d).isMasked(chan))
1555
1556 Value *
1557 Converter::buildDot(int dim)
1558 {
1559 assert(dim > 0);
1560
1561 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1562 Value *dotp = getScratch();
1563
1564 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1565
1566 for (int c = 1; c < dim; ++c) {
1567 src0 = fetchSrc(0, c);
1568 src1 = fetchSrc(1, c);
1569 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1570 }
1571 return dotp;
1572 }
1573
1574 void
1575 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1576 {
1577 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1578 join->fixed = 1;
1579 conv->insertHead(join);
1580
1581 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1582 fork->insertBefore(fork->getExit(), fork->joinAt);
1583 }
1584
1585 void
1586 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1587 {
1588 unsigned rIdx = 0, sIdx = 0;
1589
1590 if (R >= 0)
1591 rIdx = tgsi.getSrc(R).getIndex(0);
1592 if (S >= 0)
1593 sIdx = tgsi.getSrc(S).getIndex(0);
1594
1595 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1596
1597 if (tgsi.getSrc(R).isIndirect(0)) {
1598 tex->tex.rIndirectSrc = s;
1599 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1600 }
1601 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1602 tex->tex.sIndirectSrc = s;
1603 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1604 }
1605 }
1606
1607 void
1608 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1609 {
1610 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1611 tex->tex.query = query;
1612 unsigned int c, d;
1613
1614 for (d = 0, c = 0; c < 4; ++c) {
1615 if (!dst0[c])
1616 continue;
1617 tex->tex.mask |= 1 << c;
1618 tex->setDef(d++, dst0[c]);
1619 }
1620 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1621
1622 setTexRS(tex, c, 1, -1);
1623
1624 bb->insertTail(tex);
1625 }
1626
1627 void
1628 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1629 {
1630 Value *proj = fetchSrc(0, 3);
1631 Instruction *insn = proj->getUniqueInsn();
1632 int c;
1633
1634 if (insn->op == OP_PINTERP) {
1635 bb->insertTail(insn = cloneForward(func, insn));
1636 insn->op = OP_LINTERP;
1637 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1638 insn->setSrc(1, NULL);
1639 proj = insn->getDef(0);
1640 }
1641 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1642
1643 for (c = 0; c < 4; ++c) {
1644 if (!(mask & (1 << c)))
1645 continue;
1646 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1647 continue;
1648 mask &= ~(1 << c);
1649
1650 bb->insertTail(insn = cloneForward(func, insn));
1651 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1652 insn->setSrc(1, proj);
1653 dst[c] = insn->getDef(0);
1654 }
1655 if (!mask)
1656 return;
1657
1658 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1659
1660 for (c = 0; c < 4; ++c)
1661 if (mask & (1 << c))
1662 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1663 }
1664
1665 // order of nv50 ir sources: x y z layer lod/bias shadow
1666 // order of TGSI TEX sources: x y z layer shadow lod/bias
1667 // lowering will finally set the hw specific order (like array first on nvc0)
1668 void
1669 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1670 {
1671 Value *val;
1672 Value *arg[4], *src[8];
1673 Value *lod = NULL, *shd = NULL;
1674 unsigned int s, c, d;
1675 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1676
1677 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1678
1679 for (s = 0; s < tgt.getArgCount(); ++s)
1680 arg[s] = src[s] = fetchSrc(0, s);
1681
1682 if (texi->op == OP_TXL || texi->op == OP_TXB)
1683 lod = fetchSrc(L >> 4, L & 3);
1684
1685 if (C == 0x0f)
1686 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1687
1688 if (tgt.isShadow())
1689 shd = fetchSrc(C >> 4, C & 3);
1690
1691 if (texi->op == OP_TXD) {
1692 for (c = 0; c < tgt.getDim(); ++c) {
1693 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1694 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1695 }
1696 }
1697
1698 // cube textures don't care about projection value, it's divided out
1699 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1700 unsigned int n = tgt.getDim();
1701 if (shd) {
1702 arg[n] = shd;
1703 ++n;
1704 assert(tgt.getDim() == tgt.getArgCount());
1705 }
1706 loadProjTexCoords(src, arg, (1 << n) - 1);
1707 if (shd)
1708 shd = src[n - 1];
1709 }
1710
1711 if (tgt.isCube()) {
1712 for (c = 0; c < 3; ++c)
1713 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1714 val = getScratch();
1715 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1716 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1717 mkOp1(OP_RCP, TYPE_F32, val, val);
1718 for (c = 0; c < 3; ++c)
1719 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1720 }
1721
1722 for (c = 0, d = 0; c < 4; ++c) {
1723 if (dst[c]) {
1724 texi->setDef(d++, dst[c]);
1725 texi->tex.mask |= 1 << c;
1726 } else {
1727 // NOTE: maybe hook up def too, for CSE
1728 }
1729 }
1730 for (s = 0; s < tgt.getArgCount(); ++s)
1731 texi->setSrc(s, src[s]);
1732 if (lod)
1733 texi->setSrc(s++, lod);
1734 if (shd)
1735 texi->setSrc(s++, shd);
1736
1737 setTexRS(texi, s, R, S);
1738
1739 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1740 texi->tex.levelZero = true;
1741
1742 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1743 for (c = 0; c < 3; ++c) {
1744 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1745 if (texi->tex.offset[s][c])
1746 texi->tex.useOffsets = s + 1;
1747 }
1748 }
1749
1750 bb->insertTail(texi);
1751 }
1752
1753 // 1st source: xyz = coordinates, w = lod/sample
1754 // 2nd source: offset
1755 void
1756 Converter::handleTXF(Value *dst[4], int R, int L_M)
1757 {
1758 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1759 int ms;
1760 unsigned int c, d, s;
1761
1762 texi->tex.target = tgsi.getTexture(code, R);
1763
1764 ms = texi->tex.target.isMS() ? 1 : 0;
1765 texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1766
1767 for (c = 0, d = 0; c < 4; ++c) {
1768 if (dst[c]) {
1769 texi->setDef(d++, dst[c]);
1770 texi->tex.mask |= 1 << c;
1771 }
1772 }
1773 for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1774 texi->setSrc(c, fetchSrc(0, c));
1775 texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1776
1777 setTexRS(texi, c, R, -1);
1778
1779 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1780 for (c = 0; c < 3; ++c) {
1781 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1782 if (texi->tex.offset[s][c])
1783 texi->tex.useOffsets = s + 1;
1784 }
1785 }
1786
1787 bb->insertTail(texi);
1788 }
1789
1790 void
1791 Converter::handleLIT(Value *dst0[4])
1792 {
1793 Value *val0 = NULL;
1794 unsigned int mask = tgsi.getDst(0).getMask();
1795
1796 if (mask & (1 << 0))
1797 loadImm(dst0[0], 1.0f);
1798
1799 if (mask & (1 << 3))
1800 loadImm(dst0[3], 1.0f);
1801
1802 if (mask & (3 << 1)) {
1803 val0 = getScratch();
1804 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1805 if (mask & (1 << 1))
1806 mkMov(dst0[1], val0);
1807 }
1808
1809 if (mask & (1 << 2)) {
1810 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1811 Value *val1 = getScratch(), *val3 = getScratch();
1812
1813 Value *pos128 = loadImm(NULL, +127.999999f);
1814 Value *neg128 = loadImm(NULL, -127.999999f);
1815
1816 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1817 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1818 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1819 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1820
1821 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
1822 }
1823 }
1824
1825 static inline bool
1826 isResourceSpecial(const int r)
1827 {
1828 return (r == TGSI_RESOURCE_GLOBAL ||
1829 r == TGSI_RESOURCE_LOCAL ||
1830 r == TGSI_RESOURCE_PRIVATE ||
1831 r == TGSI_RESOURCE_INPUT);
1832 }
1833
1834 static inline bool
1835 isResourceRaw(const struct tgsi::Source *code, const int r)
1836 {
1837 return isResourceSpecial(r) || code->resources[r].raw;
1838 }
1839
1840 static inline nv50_ir::TexTarget
1841 getResourceTarget(const struct tgsi::Source *code, int r)
1842 {
1843 if (isResourceSpecial(r))
1844 return nv50_ir::TEX_TARGET_BUFFER;
1845 return tgsi::translateTexture(code->resources.at(r).target);
1846 }
1847
1848 Symbol *
1849 Converter::getResourceBase(const int r)
1850 {
1851 Symbol *sym = NULL;
1852
1853 switch (r) {
1854 case TGSI_RESOURCE_GLOBAL:
1855 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1856 break;
1857 case TGSI_RESOURCE_LOCAL:
1858 assert(prog->getType() == Program::TYPE_COMPUTE);
1859 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1860 info->prop.cp.sharedOffset);
1861 break;
1862 case TGSI_RESOURCE_PRIVATE:
1863 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1864 info->bin.tlsSpace);
1865 break;
1866 case TGSI_RESOURCE_INPUT:
1867 assert(prog->getType() == Program::TYPE_COMPUTE);
1868 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1869 info->prop.cp.inputOffset);
1870 break;
1871 default:
1872 sym = new_Symbol(prog,
1873 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1874 break;
1875 }
1876 return sym;
1877 }
1878
1879 void
1880 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
1881 {
1882 const int arg =
1883 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
1884
1885 for (int c = 0; c < arg; ++c)
1886 coords.push_back(fetchSrc(s, c));
1887
1888 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
1889 if (r == TGSI_RESOURCE_LOCAL ||
1890 r == TGSI_RESOURCE_PRIVATE ||
1891 r == TGSI_RESOURCE_INPUT)
1892 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
1893 coords[0]);
1894 }
1895
1896 static inline int
1897 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
1898 {
1899 int n = 0;
1900
1901 while (mask) {
1902 if (mask & 1) {
1903 size[n]++;
1904 } else {
1905 if (size[n])
1906 comp[n = 1] = size[0] + 1;
1907 else
1908 comp[n]++;
1909 }
1910 mask >>= 1;
1911 }
1912 if (size[0] == 3) {
1913 n = 1;
1914 size[0] = (comp[0] == 1) ? 1 : 2;
1915 size[1] = 3 - size[0];
1916 comp[1] = comp[0] + size[0];
1917 }
1918 return n + 1;
1919 }
1920
1921 // For raw loads, granularity is 4 byte.
1922 // Usage of the texture read mask on OP_SULDP is not allowed.
1923 void
1924 Converter::handleLOAD(Value *dst0[4])
1925 {
1926 const int r = tgsi.getSrc(0).getIndex(0);
1927 int c;
1928 std::vector<Value *> off, src, ldv, def;
1929
1930 getResourceCoords(off, r, 1);
1931
1932 if (isResourceRaw(code, r)) {
1933 uint8_t mask = 0;
1934 uint8_t comp[2] = { 0, 0 };
1935 uint8_t size[2] = { 0, 0 };
1936
1937 Symbol *base = getResourceBase(r);
1938
1939 // determine the base and size of the at most 2 load ops
1940 for (c = 0; c < 4; ++c)
1941 if (!tgsi.getDst(0).isMasked(c))
1942 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
1943
1944 int n = partitionLoadStore(comp, size, mask);
1945
1946 src = off;
1947
1948 def.resize(4); // index by component, the ones we need will be non-NULL
1949 for (c = 0; c < 4; ++c) {
1950 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
1951 def[c] = dst0[c];
1952 else
1953 if (mask & (1 << c))
1954 def[c] = getScratch();
1955 }
1956
1957 const bool useLd = isResourceSpecial(r) ||
1958 (info->io.nv50styleSurfaces &&
1959 code->resources[r].target == TGSI_TEXTURE_BUFFER);
1960
1961 for (int i = 0; i < n; ++i) {
1962 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
1963
1964 if (comp[i]) // adjust x component of source address if necessary
1965 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
1966 off[0], mkImm(comp[i] * 4));
1967 else
1968 src[0] = off[0];
1969
1970 if (useLd) {
1971 Instruction *ld =
1972 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
1973 for (size_t c = 1; c < ldv.size(); ++c)
1974 ld->setDef(c, ldv[c]);
1975 } else {
1976 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
1977 0, ldv, src)->dType = typeOfSize(size[i] * 4);
1978 }
1979 }
1980 } else {
1981 def.resize(4);
1982 for (c = 0; c < 4; ++c) {
1983 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
1984 def[c] = getScratch();
1985 else
1986 def[c] = dst0[c];
1987 }
1988
1989 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
1990 def, off);
1991 }
1992 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1993 if (dst0[c] != def[c])
1994 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
1995 }
1996
1997 // For formatted stores, the write mask on OP_SUSTP can be used.
1998 // Raw stores have to be split.
1999 void
2000 Converter::handleSTORE()
2001 {
2002 const int r = tgsi.getDst(0).getIndex(0);
2003 int c;
2004 std::vector<Value *> off, src, dummy;
2005
2006 getResourceCoords(off, r, 0);
2007 src = off;
2008 const int s = src.size();
2009
2010 if (isResourceRaw(code, r)) {
2011 uint8_t comp[2] = { 0, 0 };
2012 uint8_t size[2] = { 0, 0 };
2013
2014 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2015
2016 Symbol *base = getResourceBase(r);
2017
2018 const bool useSt = isResourceSpecial(r) ||
2019 (info->io.nv50styleSurfaces &&
2020 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2021
2022 for (int i = 0; i < n; ++i) {
2023 if (comp[i]) // adjust x component of source address if necessary
2024 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2025 off[0], mkImm(comp[i] * 4));
2026 else
2027 src[0] = off[0];
2028
2029 const DataType stTy = typeOfSize(size[i] * 4);
2030
2031 if (useSt) {
2032 Instruction *st =
2033 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2034 for (c = 1; c < size[i]; ++c)
2035 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2036 st->setIndirect(0, 0, src[0]);
2037 } else {
2038 // attach values to be stored
2039 src.resize(s + size[i]);
2040 for (c = 0; c < size[i]; ++c)
2041 src[s + c] = fetchSrc(1, comp[i] + c);
2042 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2043 0, dummy, src)->setType(stTy);
2044 }
2045 }
2046 } else {
2047 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2048 src.push_back(fetchSrc(1, c));
2049
2050 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2051 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2052 }
2053 }
2054
2055 // XXX: These only work on resources with the single-component u32/s32 formats.
2056 // Therefore the result is replicated. This might not be intended by TGSI, but
2057 // operating on more than 1 component would produce undefined results because
2058 // they do not exist.
2059 void
2060 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2061 {
2062 const int r = tgsi.getSrc(0).getIndex(0);
2063 std::vector<Value *> srcv;
2064 std::vector<Value *> defv;
2065 LValue *dst = getScratch();
2066
2067 getResourceCoords(srcv, r, 1);
2068
2069 if (isResourceSpecial(r)) {
2070 assert(r != TGSI_RESOURCE_INPUT);
2071 Instruction *insn;
2072 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2073 insn->subOp = subOp;
2074 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2075 insn->setSrc(2, fetchSrc(3, 0));
2076 insn->setIndirect(0, 0, srcv.at(0));
2077 } else {
2078 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2079 TexTarget targ = getResourceTarget(code, r);
2080 int idx = code->resources[r].slot;
2081 defv.push_back(dst);
2082 srcv.push_back(fetchSrc(2, 0));
2083 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2084 srcv.push_back(fetchSrc(3, 0));
2085 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2086 tex->subOp = subOp;
2087 tex->tex.mask = 1;
2088 tex->setType(ty);
2089 }
2090
2091 for (int c = 0; c < 4; ++c)
2092 if (dst0[c])
2093 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2094 }
2095
2096 Converter::Subroutine *
2097 Converter::getSubroutine(unsigned ip)
2098 {
2099 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2100
2101 if (it == sub.map.end())
2102 it = sub.map.insert(std::make_pair(
2103 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2104
2105 return &it->second;
2106 }
2107
2108 Converter::Subroutine *
2109 Converter::getSubroutine(Function *f)
2110 {
2111 unsigned ip = f->getLabel();
2112 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2113
2114 if (it == sub.map.end())
2115 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2116
2117 return &it->second;
2118 }
2119
2120 bool
2121 Converter::isEndOfSubroutine(uint ip)
2122 {
2123 assert(ip < code->scan.num_instructions);
2124 tgsi::Instruction insn(&code->insns[ip]);
2125 return (insn.getOpcode() == TGSI_OPCODE_END ||
2126 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2127 // does END occur at end of main or the very end ?
2128 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2129 }
2130
2131 bool
2132 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2133 {
2134 Instruction *geni;
2135
2136 Value *dst0[4], *rDst0[4];
2137 Value *src0, *src1, *src2;
2138 Value *val0, *val1;
2139 int c;
2140
2141 tgsi = tgsi::Instruction(insn);
2142
2143 bool useScratchDst = tgsi.checkDstSrcAliasing();
2144
2145 operation op = tgsi.getOP();
2146 dstTy = tgsi.inferDstType();
2147 srcTy = tgsi.inferSrcType();
2148
2149 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2150
2151 if (tgsi.dstCount()) {
2152 for (c = 0; c < 4; ++c) {
2153 rDst0[c] = acquireDst(0, c);
2154 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2155 }
2156 }
2157
2158 switch (tgsi.getOpcode()) {
2159 case TGSI_OPCODE_ADD:
2160 case TGSI_OPCODE_UADD:
2161 case TGSI_OPCODE_AND:
2162 case TGSI_OPCODE_DIV:
2163 case TGSI_OPCODE_IDIV:
2164 case TGSI_OPCODE_UDIV:
2165 case TGSI_OPCODE_MAX:
2166 case TGSI_OPCODE_MIN:
2167 case TGSI_OPCODE_IMAX:
2168 case TGSI_OPCODE_IMIN:
2169 case TGSI_OPCODE_UMAX:
2170 case TGSI_OPCODE_UMIN:
2171 case TGSI_OPCODE_MOD:
2172 case TGSI_OPCODE_UMOD:
2173 case TGSI_OPCODE_MUL:
2174 case TGSI_OPCODE_UMUL:
2175 case TGSI_OPCODE_OR:
2176 case TGSI_OPCODE_POW:
2177 case TGSI_OPCODE_SHL:
2178 case TGSI_OPCODE_ISHR:
2179 case TGSI_OPCODE_USHR:
2180 case TGSI_OPCODE_SUB:
2181 case TGSI_OPCODE_XOR:
2182 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2183 src0 = fetchSrc(0, c);
2184 src1 = fetchSrc(1, c);
2185 mkOp2(op, dstTy, dst0[c], src0, src1);
2186 }
2187 break;
2188 case TGSI_OPCODE_MAD:
2189 case TGSI_OPCODE_UMAD:
2190 case TGSI_OPCODE_SAD:
2191 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2192 src0 = fetchSrc(0, c);
2193 src1 = fetchSrc(1, c);
2194 src2 = fetchSrc(2, c);
2195 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2196 }
2197 break;
2198 case TGSI_OPCODE_MOV:
2199 case TGSI_OPCODE_ABS:
2200 case TGSI_OPCODE_CEIL:
2201 case TGSI_OPCODE_FLR:
2202 case TGSI_OPCODE_TRUNC:
2203 case TGSI_OPCODE_RCP:
2204 case TGSI_OPCODE_IABS:
2205 case TGSI_OPCODE_INEG:
2206 case TGSI_OPCODE_NOT:
2207 case TGSI_OPCODE_DDX:
2208 case TGSI_OPCODE_DDY:
2209 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2210 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2211 break;
2212 case TGSI_OPCODE_RSQ:
2213 src0 = fetchSrc(0, 0);
2214 val0 = getScratch();
2215 mkOp1(OP_ABS, TYPE_F32, val0, src0);
2216 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2217 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2218 mkMov(dst0[c], val0);
2219 break;
2220 case TGSI_OPCODE_ARL:
2221 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2222 src0 = fetchSrc(0, c);
2223 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
2224 }
2225 break;
2226 case TGSI_OPCODE_UARL:
2227 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2228 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2229 break;
2230 case TGSI_OPCODE_EX2:
2231 case TGSI_OPCODE_LG2:
2232 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2233 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2234 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2235 break;
2236 case TGSI_OPCODE_COS:
2237 case TGSI_OPCODE_SIN:
2238 val0 = getScratch();
2239 if (mask & 7) {
2240 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2241 mkOp1(op, TYPE_F32, val0, val0);
2242 for (c = 0; c < 3; ++c)
2243 if (dst0[c])
2244 mkMov(dst0[c], val0);
2245 }
2246 if (dst0[3]) {
2247 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2248 mkOp1(op, TYPE_F32, dst0[3], val0);
2249 }
2250 break;
2251 case TGSI_OPCODE_SCS:
2252 if (mask & 3) {
2253 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2254 if (dst0[0])
2255 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2256 if (dst0[1])
2257 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2258 }
2259 if (dst0[2])
2260 loadImm(dst0[2], 0.0f);
2261 if (dst0[3])
2262 loadImm(dst0[3], 1.0f);
2263 break;
2264 case TGSI_OPCODE_EXP:
2265 src0 = fetchSrc(0, 0);
2266 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2267 if (dst0[1])
2268 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2269 if (dst0[0])
2270 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2271 if (dst0[2])
2272 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2273 if (dst0[3])
2274 loadImm(dst0[3], 1.0f);
2275 break;
2276 case TGSI_OPCODE_LOG:
2277 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2278 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2279 if (dst0[0] || dst0[1])
2280 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2281 if (dst0[1]) {
2282 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2283 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2284 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2285 }
2286 if (dst0[3])
2287 loadImm(dst0[3], 1.0f);
2288 break;
2289 case TGSI_OPCODE_DP2:
2290 val0 = buildDot(2);
2291 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2292 mkMov(dst0[c], val0);
2293 break;
2294 case TGSI_OPCODE_DP3:
2295 val0 = buildDot(3);
2296 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2297 mkMov(dst0[c], val0);
2298 break;
2299 case TGSI_OPCODE_DP4:
2300 val0 = buildDot(4);
2301 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2302 mkMov(dst0[c], val0);
2303 break;
2304 case TGSI_OPCODE_DPH:
2305 val0 = buildDot(3);
2306 src1 = fetchSrc(1, 3);
2307 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2308 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2309 mkMov(dst0[c], val0);
2310 break;
2311 case TGSI_OPCODE_DST:
2312 if (dst0[0])
2313 loadImm(dst0[0], 1.0f);
2314 if (dst0[1]) {
2315 src0 = fetchSrc(0, 1);
2316 src1 = fetchSrc(1, 1);
2317 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2318 }
2319 if (dst0[2])
2320 mkMov(dst0[2], fetchSrc(0, 2));
2321 if (dst0[3])
2322 mkMov(dst0[3], fetchSrc(1, 3));
2323 break;
2324 case TGSI_OPCODE_LRP:
2325 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2326 src0 = fetchSrc(0, c);
2327 src1 = fetchSrc(1, c);
2328 src2 = fetchSrc(2, c);
2329 mkOp3(OP_MAD, TYPE_F32, dst0[c],
2330 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2331 }
2332 break;
2333 case TGSI_OPCODE_LIT:
2334 handleLIT(dst0);
2335 break;
2336 case TGSI_OPCODE_XPD:
2337 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2338 if (c < 3) {
2339 val0 = getSSA();
2340 src0 = fetchSrc(1, (c + 1) % 3);
2341 src1 = fetchSrc(0, (c + 2) % 3);
2342 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2343 mkOp1(OP_NEG, TYPE_F32, val0, val0);
2344
2345 src0 = fetchSrc(0, (c + 1) % 3);
2346 src1 = fetchSrc(1, (c + 2) % 3);
2347 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2348 } else {
2349 loadImm(dst0[c], 1.0f);
2350 }
2351 }
2352 break;
2353 case TGSI_OPCODE_ISSG:
2354 case TGSI_OPCODE_SSG:
2355 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2356 src0 = fetchSrc(0, c);
2357 val0 = getScratch();
2358 val1 = getScratch();
2359 mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2360 mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2361 if (srcTy == TYPE_F32)
2362 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2363 else
2364 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2365 }
2366 break;
2367 case TGSI_OPCODE_UCMP:
2368 case TGSI_OPCODE_CMP:
2369 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2370 src0 = fetchSrc(0, c);
2371 src1 = fetchSrc(1, c);
2372 src2 = fetchSrc(2, c);
2373 if (src1 == src2)
2374 mkMov(dst0[c], src1);
2375 else
2376 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2377 srcTy, dst0[c], srcTy, src1, src2, src0);
2378 }
2379 break;
2380 case TGSI_OPCODE_FRC:
2381 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2382 src0 = fetchSrc(0, c);
2383 val0 = getScratch();
2384 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2385 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2386 }
2387 break;
2388 case TGSI_OPCODE_ROUND:
2389 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2390 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2391 ->rnd = ROUND_NI;
2392 break;
2393 case TGSI_OPCODE_CLAMP:
2394 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2395 src0 = fetchSrc(0, c);
2396 src1 = fetchSrc(1, c);
2397 src2 = fetchSrc(2, c);
2398 val0 = getScratch();
2399 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2400 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2401 }
2402 break;
2403 case TGSI_OPCODE_SLT:
2404 case TGSI_OPCODE_SGE:
2405 case TGSI_OPCODE_SEQ:
2406 case TGSI_OPCODE_SFL:
2407 case TGSI_OPCODE_SGT:
2408 case TGSI_OPCODE_SLE:
2409 case TGSI_OPCODE_SNE:
2410 case TGSI_OPCODE_STR:
2411 case TGSI_OPCODE_FSEQ:
2412 case TGSI_OPCODE_FSGE:
2413 case TGSI_OPCODE_FSLT:
2414 case TGSI_OPCODE_FSNE:
2415 case TGSI_OPCODE_ISGE:
2416 case TGSI_OPCODE_ISLT:
2417 case TGSI_OPCODE_USEQ:
2418 case TGSI_OPCODE_USGE:
2419 case TGSI_OPCODE_USLT:
2420 case TGSI_OPCODE_USNE:
2421 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2422 src0 = fetchSrc(0, c);
2423 src1 = fetchSrc(1, c);
2424 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2425 }
2426 break;
2427 case TGSI_OPCODE_KILL_IF:
2428 val0 = new_LValue(func, FILE_PREDICATE);
2429 for (c = 0; c < 4; ++c) {
2430 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2431 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2432 }
2433 break;
2434 case TGSI_OPCODE_KILL:
2435 mkOp(OP_DISCARD, TYPE_NONE, NULL);
2436 break;
2437 case TGSI_OPCODE_TEX:
2438 case TGSI_OPCODE_TXB:
2439 case TGSI_OPCODE_TXL:
2440 case TGSI_OPCODE_TXP:
2441 case TGSI_OPCODE_LODQ:
2442 // R S L C Dx Dy
2443 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2444 break;
2445 case TGSI_OPCODE_TXD:
2446 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2447 break;
2448 case TGSI_OPCODE_TG4:
2449 handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
2450 break;
2451 case TGSI_OPCODE_TEX2:
2452 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2453 break;
2454 case TGSI_OPCODE_TXB2:
2455 case TGSI_OPCODE_TXL2:
2456 handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
2457 break;
2458 case TGSI_OPCODE_SAMPLE:
2459 case TGSI_OPCODE_SAMPLE_B:
2460 case TGSI_OPCODE_SAMPLE_D:
2461 case TGSI_OPCODE_SAMPLE_L:
2462 case TGSI_OPCODE_SAMPLE_C:
2463 case TGSI_OPCODE_SAMPLE_C_LZ:
2464 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2465 break;
2466 case TGSI_OPCODE_TXF:
2467 handleTXF(dst0, 1, 0x03);
2468 break;
2469 case TGSI_OPCODE_SAMPLE_I:
2470 handleTXF(dst0, 1, 0x03);
2471 break;
2472 case TGSI_OPCODE_SAMPLE_I_MS:
2473 handleTXF(dst0, 1, 0x20);
2474 break;
2475 case TGSI_OPCODE_TXQ:
2476 case TGSI_OPCODE_SVIEWINFO:
2477 handleTXQ(dst0, TXQ_DIMS);
2478 break;
2479 case TGSI_OPCODE_F2I:
2480 case TGSI_OPCODE_F2U:
2481 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2482 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2483 break;
2484 case TGSI_OPCODE_I2F:
2485 case TGSI_OPCODE_U2F:
2486 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2487 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2488 break;
2489 case TGSI_OPCODE_EMIT:
2490 case TGSI_OPCODE_ENDPRIM:
2491 // get vertex stream if specified (must be immediate)
2492 src0 = tgsi.srcCount() ?
2493 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2494 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2495 break;
2496 case TGSI_OPCODE_IF:
2497 case TGSI_OPCODE_UIF:
2498 {
2499 BasicBlock *ifBB = new BasicBlock(func);
2500
2501 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2502 condBBs.push(bb);
2503 joinBBs.push(bb);
2504
2505 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2506
2507 setPosition(ifBB, true);
2508 }
2509 break;
2510 case TGSI_OPCODE_ELSE:
2511 {
2512 BasicBlock *elseBB = new BasicBlock(func);
2513 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2514
2515 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2516 condBBs.push(bb);
2517
2518 forkBB->getExit()->asFlow()->target.bb = elseBB;
2519 if (!bb->isTerminated())
2520 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2521
2522 setPosition(elseBB, true);
2523 }
2524 break;
2525 case TGSI_OPCODE_ENDIF:
2526 {
2527 BasicBlock *convBB = new BasicBlock(func);
2528 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2529 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2530
2531 if (!bb->isTerminated()) {
2532 // we only want join if none of the clauses ended with CONT/BREAK/RET
2533 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2534 insertConvergenceOps(convBB, forkBB);
2535 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2536 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2537 }
2538
2539 if (prevBB->getExit()->op == OP_BRA) {
2540 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2541 prevBB->getExit()->asFlow()->target.bb = convBB;
2542 }
2543 setPosition(convBB, true);
2544 }
2545 break;
2546 case TGSI_OPCODE_BGNLOOP:
2547 {
2548 BasicBlock *lbgnBB = new BasicBlock(func);
2549 BasicBlock *lbrkBB = new BasicBlock(func);
2550
2551 loopBBs.push(lbgnBB);
2552 breakBBs.push(lbrkBB);
2553 if (loopBBs.getSize() > func->loopNestingBound)
2554 func->loopNestingBound++;
2555
2556 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2557
2558 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2559 setPosition(lbgnBB, true);
2560 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2561 }
2562 break;
2563 case TGSI_OPCODE_ENDLOOP:
2564 {
2565 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2566
2567 if (!bb->isTerminated()) {
2568 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2569 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2570 }
2571 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2572 }
2573 break;
2574 case TGSI_OPCODE_BRK:
2575 {
2576 if (bb->isTerminated())
2577 break;
2578 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2579 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2580 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2581 }
2582 break;
2583 case TGSI_OPCODE_CONT:
2584 {
2585 if (bb->isTerminated())
2586 break;
2587 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2588 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2589 contBB->explicitCont = true;
2590 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2591 }
2592 break;
2593 case TGSI_OPCODE_BGNSUB:
2594 {
2595 Subroutine *s = getSubroutine(ip);
2596 BasicBlock *entry = new BasicBlock(s->f);
2597 BasicBlock *leave = new BasicBlock(s->f);
2598
2599 // multiple entrypoints possible, keep the graph connected
2600 if (prog->getType() == Program::TYPE_COMPUTE)
2601 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2602
2603 sub.cur = s;
2604 s->f->setEntry(entry);
2605 s->f->setExit(leave);
2606 setPosition(entry, true);
2607 return true;
2608 }
2609 case TGSI_OPCODE_ENDSUB:
2610 {
2611 sub.cur = getSubroutine(prog->main);
2612 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2613 return true;
2614 }
2615 case TGSI_OPCODE_CAL:
2616 {
2617 Subroutine *s = getSubroutine(tgsi.getLabel());
2618 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2619 func->call.attach(&s->f->call, Graph::Edge::TREE);
2620 return true;
2621 }
2622 case TGSI_OPCODE_RET:
2623 {
2624 if (bb->isTerminated())
2625 return true;
2626 BasicBlock *leave = BasicBlock::get(func->cfgExit);
2627
2628 if (!isEndOfSubroutine(ip + 1)) {
2629 // insert a PRERET at the entry if this is an early return
2630 // (only needed for sharing code in the epilogue)
2631 BasicBlock *pos = getBB();
2632 setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2633 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2634 setPosition(pos, true);
2635 }
2636 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2637 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2638 }
2639 break;
2640 case TGSI_OPCODE_END:
2641 {
2642 // attach and generate epilogue code
2643 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2644 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2645 setPosition(epilogue, true);
2646 if (prog->getType() == Program::TYPE_FRAGMENT)
2647 exportOutputs();
2648 if (info->io.genUserClip > 0)
2649 handleUserClipPlanes();
2650 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2651 }
2652 break;
2653 case TGSI_OPCODE_SWITCH:
2654 case TGSI_OPCODE_CASE:
2655 ERROR("switch/case opcode encountered, should have been lowered\n");
2656 abort();
2657 break;
2658 case TGSI_OPCODE_LOAD:
2659 handleLOAD(dst0);
2660 break;
2661 case TGSI_OPCODE_STORE:
2662 handleSTORE();
2663 break;
2664 case TGSI_OPCODE_BARRIER:
2665 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2666 geni->fixed = 1;
2667 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2668 break;
2669 case TGSI_OPCODE_MFENCE:
2670 case TGSI_OPCODE_LFENCE:
2671 case TGSI_OPCODE_SFENCE:
2672 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2673 geni->fixed = 1;
2674 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2675 break;
2676 case TGSI_OPCODE_ATOMUADD:
2677 case TGSI_OPCODE_ATOMXCHG:
2678 case TGSI_OPCODE_ATOMCAS:
2679 case TGSI_OPCODE_ATOMAND:
2680 case TGSI_OPCODE_ATOMOR:
2681 case TGSI_OPCODE_ATOMXOR:
2682 case TGSI_OPCODE_ATOMUMIN:
2683 case TGSI_OPCODE_ATOMIMIN:
2684 case TGSI_OPCODE_ATOMUMAX:
2685 case TGSI_OPCODE_ATOMIMAX:
2686 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2687 break;
2688 default:
2689 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2690 assert(0);
2691 break;
2692 }
2693
2694 if (tgsi.dstCount()) {
2695 for (c = 0; c < 4; ++c) {
2696 if (!dst0[c])
2697 continue;
2698 if (dst0[c] != rDst0[c])
2699 mkMov(rDst0[c], dst0[c]);
2700 storeDst(0, c, rDst0[c]);
2701 }
2702 }
2703 vtxBaseValid = 0;
2704
2705 return true;
2706 }
2707
2708 void
2709 Converter::handleUserClipPlanes()
2710 {
2711 Value *res[8];
2712 int n, i, c;
2713
2714 for (c = 0; c < 4; ++c) {
2715 for (i = 0; i < info->io.genUserClip; ++i) {
2716 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
2717 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
2718 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
2719 if (c == 0)
2720 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2721 else
2722 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2723 }
2724 }
2725
2726 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2727
2728 for (i = 0; i < info->io.genUserClip; ++i) {
2729 n = i / 4 + first;
2730 c = i % 4;
2731 Symbol *sym =
2732 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2733 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2734 }
2735 }
2736
2737 void
2738 Converter::exportOutputs()
2739 {
2740 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2741 for (unsigned int c = 0; c < 4; ++c) {
2742 if (!oData.exists(sub.cur->values, i, c))
2743 continue;
2744 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2745 info->out[i].slot[c] * 4);
2746 Value *val = oData.load(sub.cur->values, i, c, NULL);
2747 if (val)
2748 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2749 }
2750 }
2751 }
2752
2753 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2754 code(code),
2755 tgsi(NULL),
2756 tData(this), aData(this), pData(this), oData(this)
2757 {
2758 info = code->info;
2759
2760 const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2761
2762 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2763 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2764 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2765 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2766
2767 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2768 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2769 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
2770 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2771
2772 zero = mkImm((uint32_t)0);
2773
2774 vtxBaseValid = 0;
2775 }
2776
2777 Converter::~Converter()
2778 {
2779 }
2780
2781 inline const Converter::Location *
2782 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
2783 {
2784 ValueMap::l_iterator it = s->values.l.find(v);
2785 return it == s->values.l.end() ? NULL : &it->second;
2786 }
2787
2788 template<typename T> inline void
2789 Converter::BindArgumentsPass::updateCallArgs(
2790 Instruction *i, void (Instruction::*setArg)(int, Value *),
2791 T (Function::*proto))
2792 {
2793 Function *g = i->asFlow()->target.fn;
2794 Subroutine *subg = conv.getSubroutine(g);
2795
2796 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2797 Value *v = (g->*proto)[a].get();
2798 const Converter::Location &l = *getValueLocation(subg, v);
2799 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2800
2801 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2802 }
2803 }
2804
2805 template<typename T> inline void
2806 Converter::BindArgumentsPass::updatePrototype(
2807 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2808 {
2809 (func->*updateSet)();
2810
2811 for (unsigned i = 0; i < set->getSize(); ++i) {
2812 Value *v = func->getLValue(i);
2813 const Converter::Location *l = getValueLocation(sub, v);
2814
2815 // only include values with a matching TGSI register
2816 if (set->test(i) && l && !conv.code->locals.count(*l))
2817 (func->*proto).push_back(v);
2818 }
2819 }
2820
2821 bool
2822 Converter::BindArgumentsPass::visit(Function *f)
2823 {
2824 sub = conv.getSubroutine(f);
2825
2826 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2827 !bi.end(); bi.next()) {
2828 for (Instruction *i = BasicBlock::get(bi)->getFirst();
2829 i; i = i->next) {
2830 if (i->op == OP_CALL && !i->asFlow()->builtin) {
2831 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2832 updateCallArgs(i, &Instruction::setDef, &Function::outs);
2833 }
2834 }
2835 }
2836
2837 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2838 return true;
2839 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2840 &Function::buildLiveSets, &Function::ins);
2841 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2842 &Function::buildDefSets, &Function::outs);
2843
2844 return true;
2845 }
2846
2847 bool
2848 Converter::run()
2849 {
2850 BasicBlock *entry = new BasicBlock(prog->main);
2851 BasicBlock *leave = new BasicBlock(prog->main);
2852
2853 prog->main->setEntry(entry);
2854 prog->main->setExit(leave);
2855
2856 setPosition(entry, true);
2857 sub.cur = getSubroutine(prog->main);
2858
2859 if (info->io.genUserClip > 0) {
2860 for (int c = 0; c < 4; ++c)
2861 clipVtx[c] = getScratch();
2862 }
2863
2864 if (prog->getType() == Program::TYPE_FRAGMENT) {
2865 Symbol *sv = mkSysVal(SV_POSITION, 3);
2866 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2867 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2868 }
2869
2870 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2871 if (!handleInstruction(&code->insns[ip]))
2872 return false;
2873 }
2874
2875 if (!BindArgumentsPass(*this).run(prog))
2876 return false;
2877
2878 return true;
2879 }
2880
2881 } // unnamed namespace
2882
2883 namespace nv50_ir {
2884
2885 bool
2886 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2887 {
2888 tgsi::Source src(info);
2889 if (!src.scanSource())
2890 return false;
2891 tlsSize = info->bin.tlsSpace;
2892
2893 Converter builder(this, &src);
2894 return builder.run();
2895 }
2896
2897 } // namespace nv50_ir