src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "tgsi/tgsi_dump.h"
  24 #include "tgsi/tgsi_scan.h"
  25 #include "tgsi/tgsi_util.h"
  26
  27 #include <set>
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_util.h"
  31 #include "codegen/nv50_ir_build_util.h"
  32
  33 namespace tgsi {
  34
  35 class Source;
  36
  37 static nv50_ir::operation translateOpcode(uint opcode);
  38 static nv50_ir::DataFile translateFile(uint file);
  39 static nv50_ir::TexTarget translateTexture(uint texTarg);
  40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  41
  42 class Instruction
  43 {
  44 public:
  45    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  46
  47    class SrcRegister
  48    {
  49    public:
  50       SrcRegister(const struct tgsi_full_src_register *src)
  51          : reg(src->Register),
  52            fsr(src)
  53       { }
  54
  55       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  56
  57       SrcRegister(const struct tgsi_ind_register& ind)
  58          : reg(tgsi_util_get_src_from_ind(&ind)),
  59            fsr(NULL)
  60       { }
  61
  62       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  63       {
  64          struct tgsi_src_register reg;
  65          memset(&reg, 0, sizeof(reg));
  66          reg.Index = off.Index;
  67          reg.File = off.File;
  68          reg.SwizzleX = off.SwizzleX;
  69          reg.SwizzleY = off.SwizzleY;
  70          reg.SwizzleZ = off.SwizzleZ;
  71          return reg;
  72       }
  73
  74       SrcRegister(const struct tgsi_texture_offset& off) :
  75          reg(offsetToSrc(off)),
  76          fsr(NULL)
  77       { }
  78
  79       uint getFile() const { return reg.File; }
  80
  81       bool is2D() const { return reg.Dimension; }
  82
  83       bool isIndirect(int dim) const
  84       {
  85          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  86       }
  87
  88       int getIndex(int dim) const
  89       {
  90          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  91       }
  92
  93       int getSwizzle(int chan) const
  94       {
  95          return tgsi_util_get_src_register_swizzle(&reg, chan);
  96       }
  97
  98       nv50_ir::Modifier getMod(int chan) const;
  99
 100       SrcRegister getIndirect(int dim) const
 101       {
 102          assert(fsr && isIndirect(dim));
 103          if (dim)
 104             return SrcRegister(fsr->DimIndirect);
 105          return SrcRegister(fsr->Indirect);
 106       }
 107
 108       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 109       {
 110          assert(reg.File == TGSI_FILE_IMMEDIATE);
 111          assert(!reg.Absolute);
 112          assert(!reg.Negate);
 113          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 114       }
 115
 116    private:
 117       const struct tgsi_src_register reg;
 118       const struct tgsi_full_src_register *fsr;
 119    };
 120
 121    class DstRegister
 122    {
 123    public:
 124       DstRegister(const struct tgsi_full_dst_register *dst)
 125          : reg(dst->Register),
 126            fdr(dst)
 127       { }
 128
 129       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 130
 131       uint getFile() const { return reg.File; }
 132
 133       bool is2D() const { return reg.Dimension; }
 134
 135       bool isIndirect(int dim) const
 136       {
 137          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 138       }
 139
 140       int getIndex(int dim) const
 141       {
 142          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 143       }
 144
 145       unsigned int getMask() const { return reg.WriteMask; }
 146
 147       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 148
 149       SrcRegister getIndirect(int dim) const
 150       {
 151          assert(fdr && isIndirect(dim));
 152          if (dim)
 153             return SrcRegister(fdr->DimIndirect);
 154          return SrcRegister(fdr->Indirect);
 155       }
 156
 157    private:
 158       const struct tgsi_dst_register reg;
 159       const struct tgsi_full_dst_register *fdr;
 160    };
 161
 162    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 163
 164    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 165    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 166
 167    // mask of used components of source s
 168    unsigned int srcMask(unsigned int s) const;
 169
 170    SrcRegister getSrc(unsigned int s) const
 171    {
 172       assert(s < srcCount());
 173       return SrcRegister(&insn->Src[s]);
 174    }
 175
 176    DstRegister getDst(unsigned int d) const
 177    {
 178       assert(d < dstCount());
 179       return DstRegister(&insn->Dst[d]);
 180    }
 181
 182    SrcRegister getTexOffset(unsigned int i) const
 183    {
 184       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 185       return SrcRegister(insn->TexOffsets[i]);
 186    }
 187
 188    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 189
 190    bool checkDstSrcAliasing() const;
 191
 192    inline nv50_ir::operation getOP() const {
 193       return translateOpcode(getOpcode()); }
 194
 195    nv50_ir::DataType inferSrcType() const;
 196    nv50_ir::DataType inferDstType() const;
 197
 198    nv50_ir::CondCode getSetCond() const;
 199
 200    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 201
 202    inline uint getLabel() { return insn->Label.Label; }
 203
 204    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 205
 206    void print() const
 207    {
 208       tgsi_dump_instruction(insn, 1);
 209    }
 210
 211 private:
 212    const struct tgsi_full_instruction *insn;
 213 };
 214
 215 unsigned int Instruction::srcMask(unsigned int s) const
 216 {
 217    unsigned int mask = insn->Dst[0].Register.WriteMask;
 218
 219    switch (insn->Instruction.Opcode) {
 220    case TGSI_OPCODE_COS:
 221    case TGSI_OPCODE_SIN:
 222       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 223    case TGSI_OPCODE_DP2:
 224       return 0x3;
 225    case TGSI_OPCODE_DP3:
 226       return 0x7;
 227    case TGSI_OPCODE_DP4:
 228    case TGSI_OPCODE_DPH:
 229    case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
 230       return 0xf;
 231    case TGSI_OPCODE_DST:
 232       return mask & (s ? 0xa : 0x6);
 233    case TGSI_OPCODE_EX2:
 234    case TGSI_OPCODE_EXP:
 235    case TGSI_OPCODE_LG2:
 236    case TGSI_OPCODE_LOG:
 237    case TGSI_OPCODE_POW:
 238    case TGSI_OPCODE_RCP:
 239    case TGSI_OPCODE_RSQ:
 240    case TGSI_OPCODE_SCS:
 241       return 0x1;
 242    case TGSI_OPCODE_IF:
 243    case TGSI_OPCODE_UIF:
 244       return 0x1;
 245    case TGSI_OPCODE_LIT:
 246       return 0xb;
 247    case TGSI_OPCODE_TEX2:
 248    case TGSI_OPCODE_TXB2:
 249    case TGSI_OPCODE_TXL2:
 250       return (s == 0) ? 0xf : 0x3;
 251    case TGSI_OPCODE_TEX:
 252    case TGSI_OPCODE_TXB:
 253    case TGSI_OPCODE_TXD:
 254    case TGSI_OPCODE_TXL:
 255    case TGSI_OPCODE_TXP:
 256    case TGSI_OPCODE_LODQ:
 257    {
 258       const struct tgsi_instruction_texture *tex = &insn->Texture;
 259
 260       assert(insn->Instruction.Texture);
 261
 262       mask = 0x7;
 263       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 264           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 265          mask |= 0x8; /* bias, lod or proj */
 266
 267       switch (tex->Texture) {
 268       case TGSI_TEXTURE_1D:
 269          mask &= 0x9;
 270          break;
 271       case TGSI_TEXTURE_SHADOW1D:
 272          mask &= 0xd;
 273          break;
 274       case TGSI_TEXTURE_1D_ARRAY:
 275       case TGSI_TEXTURE_2D:
 276       case TGSI_TEXTURE_RECT:
 277          mask &= 0xb;
 278          break;
 279       case TGSI_TEXTURE_CUBE_ARRAY:
 280       case TGSI_TEXTURE_SHADOW2D_ARRAY:
 281       case TGSI_TEXTURE_SHADOWCUBE:
 282       case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
 283          mask |= 0x8;
 284          break;
 285       default:
 286          break;
 287       }
 288    }
 289       return mask;
 290    case TGSI_OPCODE_XPD:
 291    {
 292       unsigned int x = 0;
 293       if (mask & 1) x |= 0x6;
 294       if (mask & 2) x |= 0x5;
 295       if (mask & 4) x |= 0x3;
 296       return x;
 297    }
 298    case TGSI_OPCODE_D2I:
 299    case TGSI_OPCODE_D2U:
 300    case TGSI_OPCODE_D2F:
 301    case TGSI_OPCODE_DSLT:
 302    case TGSI_OPCODE_DSGE:
 303    case TGSI_OPCODE_DSEQ:
 304    case TGSI_OPCODE_DSNE:
 305       switch (util_bitcount(mask)) {
 306       case 1: return 0x3;
 307       case 2: return 0xf;
 308       default:
 309          assert(!"unexpected mask");
 310          return 0xf;
 311       }
 312    case TGSI_OPCODE_I2D:
 313    case TGSI_OPCODE_U2D:
 314    case TGSI_OPCODE_F2D: {
 315       unsigned int x = 0;
 316       if ((mask & 0x3) == 0x3)
 317          x |= 1;
 318       if ((mask & 0xc) == 0xc)
 319          x |= 2;
 320       return x;
 321    }
 322    default:
 323       break;
 324    }
 325
 326    return mask;
 327 }
 328
 329 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 330 {
 331    nv50_ir::Modifier m(0);
 332
 333    if (reg.Absolute)
 334       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 335    if (reg.Negate)
 336       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 337    return m;
 338 }
 339
 340 static nv50_ir::DataFile translateFile(uint file)
 341 {
 342    switch (file) {
 343    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 344    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 345    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 346    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 347    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 348    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 349    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 350    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 351    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 352    case TGSI_FILE_SAMPLER:
 353    case TGSI_FILE_NULL:
 354    default:
 355       return nv50_ir::FILE_NULL;
 356    }
 357 }
 358
 359 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 360 {
 361    switch (sysval) {
 362    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 363    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 364    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 365    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 366    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 367    case TGSI_SEMANTIC_GRID_SIZE:  return nv50_ir::SV_NCTAID;
 368    case TGSI_SEMANTIC_BLOCK_ID:   return nv50_ir::SV_CTAID;
 369    case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
 370    case TGSI_SEMANTIC_THREAD_ID:  return nv50_ir::SV_TID;
 371    case TGSI_SEMANTIC_SAMPLEID:   return nv50_ir::SV_SAMPLE_INDEX;
 372    case TGSI_SEMANTIC_SAMPLEPOS:  return nv50_ir::SV_SAMPLE_POS;
 373    case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
 374    case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
 375    case TGSI_SEMANTIC_TESSCOORD:  return nv50_ir::SV_TESS_COORD;
 376    case TGSI_SEMANTIC_TESSOUTER:  return nv50_ir::SV_TESS_OUTER;
 377    case TGSI_SEMANTIC_TESSINNER:  return nv50_ir::SV_TESS_INNER;
 378    case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
 379    default:
 380       assert(0);
 381       return nv50_ir::SV_CLOCK;
 382    }
 383 }
 384
 385 #define NV50_IR_TEX_TARG_CASE(a, b) \
 386    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 387
 388 static nv50_ir::TexTarget translateTexture(uint tex)
 389 {
 390    switch (tex) {
 391    NV50_IR_TEX_TARG_CASE(1D, 1D);
 392    NV50_IR_TEX_TARG_CASE(2D, 2D);
 393    NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
 394    NV50_IR_TEX_TARG_CASE(3D, 3D);
 395    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 396    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 397    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 398    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 399    NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
 400    NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
 401    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 402    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 403    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 404    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 405    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 406    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 407    NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
 408    NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
 409
 410    case TGSI_TEXTURE_UNKNOWN:
 411    default:
 412       assert(!"invalid texture target");
 413       return nv50_ir::TEX_TARGET_2D;
 414    }
 415 }
 416
 417 nv50_ir::DataType Instruction::inferSrcType() const
 418 {
 419    switch (getOpcode()) {
 420    case TGSI_OPCODE_UIF:
 421    case TGSI_OPCODE_AND:
 422    case TGSI_OPCODE_OR:
 423    case TGSI_OPCODE_XOR:
 424    case TGSI_OPCODE_NOT:
 425    case TGSI_OPCODE_SHL:
 426    case TGSI_OPCODE_U2F:
 427    case TGSI_OPCODE_U2D:
 428    case TGSI_OPCODE_UADD:
 429    case TGSI_OPCODE_UDIV:
 430    case TGSI_OPCODE_UMOD:
 431    case TGSI_OPCODE_UMAD:
 432    case TGSI_OPCODE_UMUL:
 433    case TGSI_OPCODE_UMUL_HI:
 434    case TGSI_OPCODE_UMAX:
 435    case TGSI_OPCODE_UMIN:
 436    case TGSI_OPCODE_USEQ:
 437    case TGSI_OPCODE_USGE:
 438    case TGSI_OPCODE_USLT:
 439    case TGSI_OPCODE_USNE:
 440    case TGSI_OPCODE_USHR:
 441    case TGSI_OPCODE_ATOMUADD:
 442    case TGSI_OPCODE_ATOMXCHG:
 443    case TGSI_OPCODE_ATOMCAS:
 444    case TGSI_OPCODE_ATOMAND:
 445    case TGSI_OPCODE_ATOMOR:
 446    case TGSI_OPCODE_ATOMXOR:
 447    case TGSI_OPCODE_ATOMUMIN:
 448    case TGSI_OPCODE_ATOMUMAX:
 449    case TGSI_OPCODE_UBFE:
 450    case TGSI_OPCODE_UMSB:
 451       return nv50_ir::TYPE_U32;
 452    case TGSI_OPCODE_I2F:
 453    case TGSI_OPCODE_I2D:
 454    case TGSI_OPCODE_IDIV:
 455    case TGSI_OPCODE_IMUL_HI:
 456    case TGSI_OPCODE_IMAX:
 457    case TGSI_OPCODE_IMIN:
 458    case TGSI_OPCODE_IABS:
 459    case TGSI_OPCODE_INEG:
 460    case TGSI_OPCODE_ISGE:
 461    case TGSI_OPCODE_ISHR:
 462    case TGSI_OPCODE_ISLT:
 463    case TGSI_OPCODE_ISSG:
 464    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 465    case TGSI_OPCODE_MOD:
 466    case TGSI_OPCODE_UARL:
 467    case TGSI_OPCODE_ATOMIMIN:
 468    case TGSI_OPCODE_ATOMIMAX:
 469    case TGSI_OPCODE_IBFE:
 470    case TGSI_OPCODE_IMSB:
 471       return nv50_ir::TYPE_S32;
 472    case TGSI_OPCODE_D2F:
 473    case TGSI_OPCODE_D2I:
 474    case TGSI_OPCODE_D2U:
 475    case TGSI_OPCODE_DABS:
 476    case TGSI_OPCODE_DNEG:
 477    case TGSI_OPCODE_DADD:
 478    case TGSI_OPCODE_DMUL:
 479    case TGSI_OPCODE_DMAX:
 480    case TGSI_OPCODE_DMIN:
 481    case TGSI_OPCODE_DSLT:
 482    case TGSI_OPCODE_DSGE:
 483    case TGSI_OPCODE_DSEQ:
 484    case TGSI_OPCODE_DSNE:
 485    case TGSI_OPCODE_DRCP:
 486    case TGSI_OPCODE_DSQRT:
 487    case TGSI_OPCODE_DMAD:
 488    case TGSI_OPCODE_DFRAC:
 489    case TGSI_OPCODE_DRSQ:
 490    case TGSI_OPCODE_DTRUNC:
 491    case TGSI_OPCODE_DCEIL:
 492    case TGSI_OPCODE_DFLR:
 493    case TGSI_OPCODE_DROUND:
 494       return nv50_ir::TYPE_F64;
 495    default:
 496       return nv50_ir::TYPE_F32;
 497    }
 498 }
 499
 500 nv50_ir::DataType Instruction::inferDstType() const
 501 {
 502    switch (getOpcode()) {
 503    case TGSI_OPCODE_D2U:
 504    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 505    case TGSI_OPCODE_D2I:
 506    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 507    case TGSI_OPCODE_FSEQ:
 508    case TGSI_OPCODE_FSGE:
 509    case TGSI_OPCODE_FSLT:
 510    case TGSI_OPCODE_FSNE:
 511    case TGSI_OPCODE_DSEQ:
 512    case TGSI_OPCODE_DSGE:
 513    case TGSI_OPCODE_DSLT:
 514    case TGSI_OPCODE_DSNE:
 515       return nv50_ir::TYPE_U32;
 516    case TGSI_OPCODE_I2F:
 517    case TGSI_OPCODE_U2F:
 518    case TGSI_OPCODE_D2F:
 519       return nv50_ir::TYPE_F32;
 520    case TGSI_OPCODE_I2D:
 521    case TGSI_OPCODE_U2D:
 522    case TGSI_OPCODE_F2D:
 523       return nv50_ir::TYPE_F64;
 524    default:
 525       return inferSrcType();
 526    }
 527 }
 528
 529 nv50_ir::CondCode Instruction::getSetCond() const
 530 {
 531    using namespace nv50_ir;
 532
 533    switch (getOpcode()) {
 534    case TGSI_OPCODE_SLT:
 535    case TGSI_OPCODE_ISLT:
 536    case TGSI_OPCODE_USLT:
 537    case TGSI_OPCODE_FSLT:
 538    case TGSI_OPCODE_DSLT:
 539       return CC_LT;
 540    case TGSI_OPCODE_SLE:
 541       return CC_LE;
 542    case TGSI_OPCODE_SGE:
 543    case TGSI_OPCODE_ISGE:
 544    case TGSI_OPCODE_USGE:
 545    case TGSI_OPCODE_FSGE:
 546    case TGSI_OPCODE_DSGE:
 547       return CC_GE;
 548    case TGSI_OPCODE_SGT:
 549       return CC_GT;
 550    case TGSI_OPCODE_SEQ:
 551    case TGSI_OPCODE_USEQ:
 552    case TGSI_OPCODE_FSEQ:
 553    case TGSI_OPCODE_DSEQ:
 554       return CC_EQ;
 555    case TGSI_OPCODE_SNE:
 556    case TGSI_OPCODE_FSNE:
 557    case TGSI_OPCODE_DSNE:
 558       return CC_NEU;
 559    case TGSI_OPCODE_USNE:
 560       return CC_NE;
 561    default:
 562       return CC_ALWAYS;
 563    }
 564 }
 565
 566 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 567
 568 static nv50_ir::operation translateOpcode(uint opcode)
 569 {
 570    switch (opcode) {
 571    NV50_IR_OPCODE_CASE(ARL, SHL);
 572    NV50_IR_OPCODE_CASE(MOV, MOV);
 573
 574    NV50_IR_OPCODE_CASE(RCP, RCP);
 575    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 576
 577    NV50_IR_OPCODE_CASE(MUL, MUL);
 578    NV50_IR_OPCODE_CASE(ADD, ADD);
 579
 580    NV50_IR_OPCODE_CASE(MIN, MIN);
 581    NV50_IR_OPCODE_CASE(MAX, MAX);
 582    NV50_IR_OPCODE_CASE(SLT, SET);
 583    NV50_IR_OPCODE_CASE(SGE, SET);
 584    NV50_IR_OPCODE_CASE(MAD, MAD);
 585    NV50_IR_OPCODE_CASE(SUB, SUB);
 586
 587    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 588    NV50_IR_OPCODE_CASE(ROUND, CVT);
 589    NV50_IR_OPCODE_CASE(EX2, EX2);
 590    NV50_IR_OPCODE_CASE(LG2, LG2);
 591    NV50_IR_OPCODE_CASE(POW, POW);
 592
 593    NV50_IR_OPCODE_CASE(ABS, ABS);
 594
 595    NV50_IR_OPCODE_CASE(COS, COS);
 596    NV50_IR_OPCODE_CASE(DDX, DFDX);
 597    NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
 598    NV50_IR_OPCODE_CASE(DDY, DFDY);
 599    NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
 600    NV50_IR_OPCODE_CASE(KILL, DISCARD);
 601
 602    NV50_IR_OPCODE_CASE(SEQ, SET);
 603    NV50_IR_OPCODE_CASE(SGT, SET);
 604    NV50_IR_OPCODE_CASE(SIN, SIN);
 605    NV50_IR_OPCODE_CASE(SLE, SET);
 606    NV50_IR_OPCODE_CASE(SNE, SET);
 607    NV50_IR_OPCODE_CASE(TEX, TEX);
 608    NV50_IR_OPCODE_CASE(TXD, TXD);
 609    NV50_IR_OPCODE_CASE(TXP, TEX);
 610
 611    NV50_IR_OPCODE_CASE(CAL, CALL);
 612    NV50_IR_OPCODE_CASE(RET, RET);
 613    NV50_IR_OPCODE_CASE(CMP, SLCT);
 614
 615    NV50_IR_OPCODE_CASE(TXB, TXB);
 616
 617    NV50_IR_OPCODE_CASE(DIV, DIV);
 618
 619    NV50_IR_OPCODE_CASE(TXL, TXL);
 620
 621    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 622    NV50_IR_OPCODE_CASE(I2F, CVT);
 623    NV50_IR_OPCODE_CASE(NOT, NOT);
 624    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 625    NV50_IR_OPCODE_CASE(SHL, SHL);
 626
 627    NV50_IR_OPCODE_CASE(AND, AND);
 628    NV50_IR_OPCODE_CASE(OR, OR);
 629    NV50_IR_OPCODE_CASE(MOD, MOD);
 630    NV50_IR_OPCODE_CASE(XOR, XOR);
 631    NV50_IR_OPCODE_CASE(SAD, SAD);
 632    NV50_IR_OPCODE_CASE(TXF, TXF);
 633    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 634    NV50_IR_OPCODE_CASE(TG4, TXG);
 635    NV50_IR_OPCODE_CASE(LODQ, TXLQ);
 636
 637    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 638    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 639
 640    NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
 641
 642    NV50_IR_OPCODE_CASE(F2I, CVT);
 643    NV50_IR_OPCODE_CASE(FSEQ, SET);
 644    NV50_IR_OPCODE_CASE(FSGE, SET);
 645    NV50_IR_OPCODE_CASE(FSLT, SET);
 646    NV50_IR_OPCODE_CASE(FSNE, SET);
 647    NV50_IR_OPCODE_CASE(IDIV, DIV);
 648    NV50_IR_OPCODE_CASE(IMAX, MAX);
 649    NV50_IR_OPCODE_CASE(IMIN, MIN);
 650    NV50_IR_OPCODE_CASE(IABS, ABS);
 651    NV50_IR_OPCODE_CASE(INEG, NEG);
 652    NV50_IR_OPCODE_CASE(ISGE, SET);
 653    NV50_IR_OPCODE_CASE(ISHR, SHR);
 654    NV50_IR_OPCODE_CASE(ISLT, SET);
 655    NV50_IR_OPCODE_CASE(F2U, CVT);
 656    NV50_IR_OPCODE_CASE(U2F, CVT);
 657    NV50_IR_OPCODE_CASE(UADD, ADD);
 658    NV50_IR_OPCODE_CASE(UDIV, DIV);
 659    NV50_IR_OPCODE_CASE(UMAD, MAD);
 660    NV50_IR_OPCODE_CASE(UMAX, MAX);
 661    NV50_IR_OPCODE_CASE(UMIN, MIN);
 662    NV50_IR_OPCODE_CASE(UMOD, MOD);
 663    NV50_IR_OPCODE_CASE(UMUL, MUL);
 664    NV50_IR_OPCODE_CASE(USEQ, SET);
 665    NV50_IR_OPCODE_CASE(USGE, SET);
 666    NV50_IR_OPCODE_CASE(USHR, SHR);
 667    NV50_IR_OPCODE_CASE(USLT, SET);
 668    NV50_IR_OPCODE_CASE(USNE, SET);
 669
 670    NV50_IR_OPCODE_CASE(DABS, ABS);
 671    NV50_IR_OPCODE_CASE(DNEG, NEG);
 672    NV50_IR_OPCODE_CASE(DADD, ADD);
 673    NV50_IR_OPCODE_CASE(DMUL, MUL);
 674    NV50_IR_OPCODE_CASE(DMAX, MAX);
 675    NV50_IR_OPCODE_CASE(DMIN, MIN);
 676    NV50_IR_OPCODE_CASE(DSLT, SET);
 677    NV50_IR_OPCODE_CASE(DSGE, SET);
 678    NV50_IR_OPCODE_CASE(DSEQ, SET);
 679    NV50_IR_OPCODE_CASE(DSNE, SET);
 680    NV50_IR_OPCODE_CASE(DRCP, RCP);
 681    NV50_IR_OPCODE_CASE(DSQRT, SQRT);
 682    NV50_IR_OPCODE_CASE(DMAD, MAD);
 683    NV50_IR_OPCODE_CASE(D2I, CVT);
 684    NV50_IR_OPCODE_CASE(D2U, CVT);
 685    NV50_IR_OPCODE_CASE(I2D, CVT);
 686    NV50_IR_OPCODE_CASE(U2D, CVT);
 687    NV50_IR_OPCODE_CASE(DRSQ, RSQ);
 688    NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
 689    NV50_IR_OPCODE_CASE(DCEIL, CEIL);
 690    NV50_IR_OPCODE_CASE(DFLR, FLOOR);
 691    NV50_IR_OPCODE_CASE(DROUND, CVT);
 692
 693    NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
 694    NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
 695
 696    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 697    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 698    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 699    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 700    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 701    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 702    NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
 703    NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
 704    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 705    NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
 706
 707    NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
 708    NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
 709    NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
 710    NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
 711    NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
 712    NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
 713    NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
 714    NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
 715    NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
 716    NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
 717
 718    NV50_IR_OPCODE_CASE(TEX2, TEX);
 719    NV50_IR_OPCODE_CASE(TXB2, TXB);
 720    NV50_IR_OPCODE_CASE(TXL2, TXL);
 721
 722    NV50_IR_OPCODE_CASE(IBFE, EXTBF);
 723    NV50_IR_OPCODE_CASE(UBFE, EXTBF);
 724    NV50_IR_OPCODE_CASE(BFI, INSBF);
 725    NV50_IR_OPCODE_CASE(BREV, EXTBF);
 726    NV50_IR_OPCODE_CASE(POPC, POPCNT);
 727    NV50_IR_OPCODE_CASE(LSB, BFIND);
 728    NV50_IR_OPCODE_CASE(IMSB, BFIND);
 729    NV50_IR_OPCODE_CASE(UMSB, BFIND);
 730
 731    NV50_IR_OPCODE_CASE(END, EXIT);
 732
 733    default:
 734       return nv50_ir::OP_NOP;
 735    }
 736 }
 737
 738 static uint16_t opcodeToSubOp(uint opcode)
 739 {
 740    switch (opcode) {
 741    case TGSI_OPCODE_LFENCE:   return NV50_IR_SUBOP_MEMBAR(L, GL);
 742    case TGSI_OPCODE_SFENCE:   return NV50_IR_SUBOP_MEMBAR(S, GL);
 743    case TGSI_OPCODE_MFENCE:   return NV50_IR_SUBOP_MEMBAR(M, GL);
 744    case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
 745    case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
 746    case TGSI_OPCODE_ATOMCAS:  return NV50_IR_SUBOP_ATOM_CAS;
 747    case TGSI_OPCODE_ATOMAND:  return NV50_IR_SUBOP_ATOM_AND;
 748    case TGSI_OPCODE_ATOMOR:   return NV50_IR_SUBOP_ATOM_OR;
 749    case TGSI_OPCODE_ATOMXOR:  return NV50_IR_SUBOP_ATOM_XOR;
 750    case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
 751    case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
 752    case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
 753    case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
 754    case TGSI_OPCODE_IMUL_HI:
 755    case TGSI_OPCODE_UMUL_HI:
 756       return NV50_IR_SUBOP_MUL_HIGH;
 757    default:
 758       return 0;
 759    }
 760 }
 761
 762 bool Instruction::checkDstSrcAliasing() const
 763 {
 764    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 765       return false;
 766
 767    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 768       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 769          break;
 770       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 771           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 772          return true;
 773    }
 774    return false;
 775 }
 776
 777 class Source
 778 {
 779 public:
 780    Source(struct nv50_ir_prog_info *);
 781    ~Source();
 782
 783 public:
 784    bool scanSource();
 785    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 786
 787 public:
 788    struct tgsi_shader_info scan;
 789    struct tgsi_full_instruction *insns;
 790    const struct tgsi_token *tokens;
 791    struct nv50_ir_prog_info *info;
 792
 793    nv50_ir::DynArray tempArrays;
 794    nv50_ir::DynArray immdArrays;
 795
 796    typedef nv50_ir::BuildUtil::Location Location;
 797    // these registers are per-subroutine, cannot be used for parameter passing
 798    std::set<Location> locals;
 799
 800    bool mainTempsInLMem;
 801
 802    int clipVertexOutput;
 803
 804    struct TextureView {
 805       uint8_t target; // TGSI_TEXTURE_*
 806    };
 807    std::vector<TextureView> textureViews;
 808
 809    struct Resource {
 810       uint8_t target; // TGSI_TEXTURE_*
 811       bool raw;
 812       uint8_t slot; // $surface index
 813    };
 814    std::vector<Resource> resources;
 815
 816 private:
 817    int inferSysValDirection(unsigned sn) const;
 818    bool scanDeclaration(const struct tgsi_full_declaration *);
 819    bool scanInstruction(const struct tgsi_full_instruction *);
 820    void scanProperty(const struct tgsi_full_property *);
 821    void scanImmediate(const struct tgsi_full_immediate *);
 822
 823    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 824 };
 825
 826 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 827 {
 828    tokens = (const struct tgsi_token *)info->bin.source;
 829
 830    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 831       tgsi_dump(tokens, 0);
 832
 833    mainTempsInLMem = false;
 834 }
 835
 836 Source::~Source()
 837 {
 838    if (insns)
 839       FREE(insns);
 840
 841    if (info->immd.data)
 842       FREE(info->immd.data);
 843    if (info->immd.type)
 844       FREE(info->immd.type);
 845 }
 846
 847 bool Source::scanSource()
 848 {
 849    unsigned insnCount = 0;
 850    struct tgsi_parse_context parse;
 851
 852    tgsi_scan_shader(tokens, &scan);
 853
 854    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 855                                                   sizeof(insns[0]));
 856    if (!insns)
 857       return false;
 858
 859    clipVertexOutput = -1;
 860
 861    textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
 862    resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
 863
 864    info->immd.bufSize = 0;
 865
 866    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 867    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 868    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 869
 870    if (info->type == PIPE_SHADER_FRAGMENT) {
 871       info->prop.fp.writesDepth = scan.writes_z;
 872       info->prop.fp.usesDiscard = scan.uses_kill;
 873    } else
 874    if (info->type == PIPE_SHADER_GEOMETRY) {
 875       info->prop.gp.instanceCount = 1; // default value
 876    }
 877
 878    info->io.viewportId = -1;
 879
 880    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 881    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 882
 883    tgsi_parse_init(&parse, tokens);
 884    while (!tgsi_parse_end_of_tokens(&parse)) {
 885       tgsi_parse_token(&parse);
 886
 887       switch (parse.FullToken.Token.Type) {
 888       case TGSI_TOKEN_TYPE_IMMEDIATE:
 889          scanImmediate(&parse.FullToken.FullImmediate);
 890          break;
 891       case TGSI_TOKEN_TYPE_DECLARATION:
 892          scanDeclaration(&parse.FullToken.FullDeclaration);
 893          break;
 894       case TGSI_TOKEN_TYPE_INSTRUCTION:
 895          insns[insnCount++] = parse.FullToken.FullInstruction;
 896          scanInstruction(&parse.FullToken.FullInstruction);
 897          break;
 898       case TGSI_TOKEN_TYPE_PROPERTY:
 899          scanProperty(&parse.FullToken.FullProperty);
 900          break;
 901       default:
 902          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 903          break;
 904       }
 905    }
 906    tgsi_parse_free(&parse);
 907
 908    if (mainTempsInLMem)
 909       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 910
 911    if (info->io.genUserClip > 0) {
 912       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 913
 914       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 915
 916       for (unsigned int n = 0; n < nOut; ++n) {
 917          unsigned int i = info->numOutputs++;
 918          info->out[i].id = i;
 919          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 920          info->out[i].si = n;
 921          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 922       }
 923    }
 924
 925    return info->assignSlots(info) == 0;
 926 }
 927
 928 void Source::scanProperty(const struct tgsi_full_property *prop)
 929 {
 930    switch (prop->Property.PropertyName) {
 931    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 932       info->prop.gp.outputPrim = prop->u[0].Data;
 933       break;
 934    case TGSI_PROPERTY_GS_INPUT_PRIM:
 935       info->prop.gp.inputPrim = prop->u[0].Data;
 936       break;
 937    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 938       info->prop.gp.maxVertices = prop->u[0].Data;
 939       break;
 940    case TGSI_PROPERTY_GS_INVOCATIONS:
 941       info->prop.gp.instanceCount = prop->u[0].Data;
 942       break;
 943    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 944       info->prop.fp.separateFragData = true;
 945       break;
 946    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 947    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 948       // we don't care
 949       break;
 950    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 951       info->io.genUserClip = -1;
 952       break;
 953    case TGSI_PROPERTY_TCS_VERTICES_OUT:
 954       info->prop.tp.outputPatchSize = prop->u[0].Data;
 955       break;
 956    case TGSI_PROPERTY_TES_PRIM_MODE:
 957       info->prop.tp.domain = prop->u[0].Data;
 958       break;
 959    case TGSI_PROPERTY_TES_SPACING:
 960       info->prop.tp.partitioning = prop->u[0].Data;
 961       break;
 962    case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
 963       info->prop.tp.winding = prop->u[0].Data;
 964       break;
 965    case TGSI_PROPERTY_TES_POINT_MODE:
 966       if (prop->u[0].Data)
 967          info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
 968       else
 969          info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
 970       break;
 971    default:
 972       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 973       break;
 974    }
 975 }
 976
 977 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 978 {
 979    const unsigned n = info->immd.count++;
 980
 981    assert(n < scan.immediate_count);
 982
 983    for (int c = 0; c < 4; ++c)
 984       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 985
 986    info->immd.type[n] = imm->Immediate.DataType;
 987 }
 988
 989 int Source::inferSysValDirection(unsigned sn) const
 990 {
 991    switch (sn) {
 992    case TGSI_SEMANTIC_INSTANCEID:
 993    case TGSI_SEMANTIC_VERTEXID:
 994       return 1;
 995    case TGSI_SEMANTIC_LAYER:
 996 #if 0
 997    case TGSI_SEMANTIC_VIEWPORTINDEX:
 998       return 0;
 999 #endif
1000    case TGSI_SEMANTIC_PRIMID:
1001       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
1002    default:
1003       return 0;
1004    }
1005 }
1006
1007 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
1008 {
1009    unsigned i, c;
1010    unsigned sn = TGSI_SEMANTIC_GENERIC;
1011    unsigned si = 0;
1012    const unsigned first = decl->Range.First, last = decl->Range.Last;
1013
1014    if (decl->Declaration.Semantic) {
1015       sn = decl->Semantic.Name;
1016       si = decl->Semantic.Index;
1017    }
1018
1019    if (decl->Declaration.Local) {
1020       for (i = first; i <= last; ++i) {
1021          for (c = 0; c < 4; ++c) {
1022             locals.insert(
1023                Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1024          }
1025       }
1026    }
1027
1028    switch (decl->Declaration.File) {
1029    case TGSI_FILE_INPUT:
1030       if (info->type == PIPE_SHADER_VERTEX) {
1031          // all vertex attributes are equal
1032          for (i = first; i <= last; ++i) {
1033             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1034             info->in[i].si = i;
1035          }
1036       } else {
1037          for (i = first; i <= last; ++i, ++si) {
1038             info->in[i].id = i;
1039             info->in[i].sn = sn;
1040             info->in[i].si = si;
1041             if (info->type == PIPE_SHADER_FRAGMENT) {
1042                // translate interpolation mode
1043                switch (decl->Interp.Interpolate) {
1044                case TGSI_INTERPOLATE_CONSTANT:
1045                   info->in[i].flat = 1;
1046                   break;
1047                case TGSI_INTERPOLATE_COLOR:
1048                   info->in[i].sc = 1;
1049                   break;
1050                case TGSI_INTERPOLATE_LINEAR:
1051                   info->in[i].linear = 1;
1052                   break;
1053                default:
1054                   break;
1055                }
1056                if (decl->Interp.Location || info->io.sampleInterp)
1057                   info->in[i].centroid = 1;
1058             }
1059
1060             if (sn == TGSI_SEMANTIC_PATCH)
1061                info->in[i].patch = 1;
1062             if (sn == TGSI_SEMANTIC_PATCH)
1063                info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1064          }
1065       }
1066       break;
1067    case TGSI_FILE_OUTPUT:
1068       for (i = first; i <= last; ++i, ++si) {
1069          switch (sn) {
1070          case TGSI_SEMANTIC_POSITION:
1071             if (info->type == PIPE_SHADER_FRAGMENT)
1072                info->io.fragDepth = i;
1073             else
1074             if (clipVertexOutput < 0)
1075                clipVertexOutput = i;
1076             break;
1077          case TGSI_SEMANTIC_COLOR:
1078             if (info->type == PIPE_SHADER_FRAGMENT)
1079                info->prop.fp.numColourResults++;
1080             break;
1081          case TGSI_SEMANTIC_EDGEFLAG:
1082             info->io.edgeFlagOut = i;
1083             break;
1084          case TGSI_SEMANTIC_CLIPVERTEX:
1085             clipVertexOutput = i;
1086             break;
1087          case TGSI_SEMANTIC_CLIPDIST:
1088             info->io.clipDistanceMask |=
1089                decl->Declaration.UsageMask << (si * 4);
1090             info->io.genUserClip = -1;
1091             break;
1092          case TGSI_SEMANTIC_SAMPLEMASK:
1093             info->io.sampleMask = i;
1094             break;
1095          case TGSI_SEMANTIC_VIEWPORT_INDEX:
1096             info->io.viewportId = i;
1097             break;
1098          case TGSI_SEMANTIC_PATCH:
1099             info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1100             /* fallthrough */
1101          case TGSI_SEMANTIC_TESSOUTER:
1102          case TGSI_SEMANTIC_TESSINNER:
1103             info->out[i].patch = 1;
1104             break;
1105          default:
1106             break;
1107          }
1108          info->out[i].id = i;
1109          info->out[i].sn = sn;
1110          info->out[i].si = si;
1111       }
1112       break;
1113    case TGSI_FILE_SYSTEM_VALUE:
1114       switch (sn) {
1115       case TGSI_SEMANTIC_INSTANCEID:
1116          info->io.instanceId = first;
1117          break;
1118       case TGSI_SEMANTIC_VERTEXID:
1119          info->io.vertexId = first;
1120          break;
1121       default:
1122          break;
1123       }
1124       for (i = first; i <= last; ++i, ++si) {
1125          info->sv[i].sn = sn;
1126          info->sv[i].si = si;
1127          info->sv[i].input = inferSysValDirection(sn);
1128
1129          switch (sn) {
1130          case TGSI_SEMANTIC_TESSOUTER:
1131          case TGSI_SEMANTIC_TESSINNER:
1132             info->sv[i].patch = 1;
1133             break;
1134          }
1135       }
1136       break;
1137    case TGSI_FILE_RESOURCE:
1138       for (i = first; i <= last; ++i) {
1139          resources[i].target = decl->Resource.Resource;
1140          resources[i].raw = decl->Resource.Raw;
1141          resources[i].slot = i;
1142       }
1143       break;
1144    case TGSI_FILE_SAMPLER_VIEW:
1145       for (i = first; i <= last; ++i)
1146          textureViews[i].target = decl->SamplerView.Resource;
1147       break;
1148    case TGSI_FILE_NULL:
1149    case TGSI_FILE_TEMPORARY:
1150    case TGSI_FILE_ADDRESS:
1151    case TGSI_FILE_CONSTANT:
1152    case TGSI_FILE_IMMEDIATE:
1153    case TGSI_FILE_PREDICATE:
1154    case TGSI_FILE_SAMPLER:
1155       break;
1156    default:
1157       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1158       return false;
1159    }
1160    return true;
1161 }
1162
1163 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1164 {
1165    return insn.getOpcode() == TGSI_OPCODE_MOV &&
1166       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1167       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1168 }
1169
1170 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1171 {
1172    Instruction insn(inst);
1173
1174    if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1175       info->numBarriers = 1;
1176
1177    if (insn.dstCount()) {
1178       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1179          Instruction::DstRegister dst = insn.getDst(0);
1180
1181          if (dst.isIndirect(0))
1182             for (unsigned i = 0; i < info->numOutputs; ++i)
1183                info->out[i].mask = 0xf;
1184          else
1185             info->out[dst.getIndex(0)].mask |= dst.getMask();
1186
1187          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1188              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1189              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1190              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1191              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1192             info->out[dst.getIndex(0)].mask &= 1;
1193
1194          if (isEdgeFlagPassthrough(insn))
1195             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1196       } else
1197       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1198          if (insn.getDst(0).isIndirect(0))
1199             mainTempsInLMem = true;
1200       }
1201    }
1202
1203    for (unsigned s = 0; s < insn.srcCount(); ++s) {
1204       Instruction::SrcRegister src = insn.getSrc(s);
1205       if (src.getFile() == TGSI_FILE_TEMPORARY) {
1206          if (src.isIndirect(0))
1207             mainTempsInLMem = true;
1208       } else
1209       if (src.getFile() == TGSI_FILE_RESOURCE) {
1210          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1211             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1212                0x1 : 0x2;
1213       } else
1214       if (src.getFile() == TGSI_FILE_OUTPUT) {
1215          if (src.isIndirect(0)) {
1216             // We don't know which one is accessed, just mark everything for
1217             // reading. This is an extremely unlikely occurrence.
1218             for (unsigned i = 0; i < info->numOutputs; ++i)
1219                info->out[i].oread = 1;
1220          } else {
1221             info->out[src.getIndex(0)].oread = 1;
1222          }
1223       }
1224       if (src.getFile() != TGSI_FILE_INPUT)
1225          continue;
1226       unsigned mask = insn.srcMask(s);
1227
1228       if (src.isIndirect(0)) {
1229          for (unsigned i = 0; i < info->numInputs; ++i)
1230             info->in[i].mask = 0xf;
1231       } else {
1232          const int i = src.getIndex(0);
1233          for (unsigned c = 0; c < 4; ++c) {
1234             if (!(mask & (1 << c)))
1235                continue;
1236             int k = src.getSwizzle(c);
1237             if (k <= TGSI_SWIZZLE_W)
1238                info->in[i].mask |= 1 << k;
1239          }
1240          switch (info->in[i].sn) {
1241          case TGSI_SEMANTIC_PSIZE:
1242          case TGSI_SEMANTIC_PRIMID:
1243          case TGSI_SEMANTIC_FOG:
1244             info->in[i].mask &= 0x1;
1245             break;
1246          case TGSI_SEMANTIC_PCOORD:
1247             info->in[i].mask &= 0x3;
1248             break;
1249          default:
1250             break;
1251          }
1252       }
1253    }
1254    return true;
1255 }
1256
1257 nv50_ir::TexInstruction::Target
1258 Instruction::getTexture(const tgsi::Source *code, int s) const
1259 {
1260    // XXX: indirect access
1261    unsigned int r;
1262
1263    switch (getSrc(s).getFile()) {
1264    case TGSI_FILE_RESOURCE:
1265       r = getSrc(s).getIndex(0);
1266       return translateTexture(code->resources.at(r).target);
1267    case TGSI_FILE_SAMPLER_VIEW:
1268       r = getSrc(s).getIndex(0);
1269       return translateTexture(code->textureViews.at(r).target);
1270    default:
1271       return translateTexture(insn->Texture.Texture);
1272    }
1273 }
1274
1275 } // namespace tgsi
1276
1277 namespace {
1278
1279 using namespace nv50_ir;
1280
1281 class Converter : public BuildUtil
1282 {
1283 public:
1284    Converter(Program *, const tgsi::Source *);
1285    ~Converter();
1286
1287    bool run();
1288
1289 private:
1290    struct Subroutine
1291    {
1292       Subroutine(Function *f) : f(f) { }
1293       Function *f;
1294       ValueMap values;
1295    };
1296
1297    Value *shiftAddress(Value *);
1298    Value *getVertexBase(int s);
1299    Value *getOutputBase(int s);
1300    DataArray *getArrayForFile(unsigned file, int idx);
1301    Value *fetchSrc(int s, int c);
1302    Value *acquireDst(int d, int c);
1303    void storeDst(int d, int c, Value *);
1304
1305    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1306    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1307                  Value *val, Value *ptr);
1308
1309    Value *applySrcMod(Value *, int s, int c);
1310
1311    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1312    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1313    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1314
1315    bool handleInstruction(const struct tgsi_full_instruction *);
1316    void exportOutputs();
1317    inline Subroutine *getSubroutine(unsigned ip);
1318    inline Subroutine *getSubroutine(Function *);
1319    inline bool isEndOfSubroutine(uint ip);
1320
1321    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1322
1323    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1324    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1325    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1326    void handleTXF(Value *dst0[4], int R, int L_M);
1327    void handleTXQ(Value *dst0[4], enum TexQuery);
1328    void handleLIT(Value *dst0[4]);
1329    void handleUserClipPlanes();
1330
1331    Symbol *getResourceBase(int r);
1332    void getResourceCoords(std::vector<Value *>&, int r, int s);
1333
1334    void handleLOAD(Value *dst0[4]);
1335    void handleSTORE();
1336    void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1337
1338    void handleINTERP(Value *dst0[4]);
1339
1340    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1341
1342    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1343
1344    Value *buildDot(int dim);
1345
1346    class BindArgumentsPass : public Pass {
1347    public:
1348       BindArgumentsPass(Converter &conv) : conv(conv) { }
1349
1350    private:
1351       Converter &conv;
1352       Subroutine *sub;
1353
1354       inline const Location *getValueLocation(Subroutine *, Value *);
1355
1356       template<typename T> inline void
1357       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1358                      T (Function::*proto));
1359
1360       template<typename T> inline void
1361       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1362                       T (Function::*proto));
1363
1364    protected:
1365       bool visit(Function *);
1366       bool visit(BasicBlock *bb) { return false; }
1367    };
1368
1369 private:
1370    const tgsi::Source *code;
1371    const struct nv50_ir_prog_info *info;
1372
1373    struct {
1374       std::map<unsigned, Subroutine> map;
1375       Subroutine *cur;
1376    } sub;
1377
1378    uint ip; // instruction pointer
1379
1380    tgsi::Instruction tgsi;
1381
1382    DataType dstTy;
1383    DataType srcTy;
1384
1385    DataArray tData; // TGSI_FILE_TEMPORARY
1386    DataArray aData; // TGSI_FILE_ADDRESS
1387    DataArray pData; // TGSI_FILE_PREDICATE
1388    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1389
1390    Value *zero;
1391    Value *fragCoord[4];
1392    Value *clipVtx[4];
1393
1394    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1395    uint8_t vtxBaseValid;
1396
1397    Value *outBase; // base address of vertex out patch (for TCP)
1398
1399    Stack condBBs;  // fork BB, then else clause BB
1400    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1401    Stack loopBBs;  // loop headers
1402    Stack breakBBs; // end of / after loop
1403
1404    Value *viewport;
1405 };
1406
1407 Symbol *
1408 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1409 {
1410    const int swz = src.getSwizzle(c);
1411
1412    /* TODO: Use Array ID when it's available for the index */
1413    return makeSym(src.getFile(),
1414                   src.is2D() ? src.getIndex(1) : 0,
1415                   src.getIndex(0), swz,
1416                   src.getIndex(0) * 16 + swz * 4);
1417 }
1418
1419 Symbol *
1420 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1421 {
1422    /* TODO: Use Array ID when it's available for the index */
1423    return makeSym(dst.getFile(),
1424                   dst.is2D() ? dst.getIndex(1) : 0,
1425                   dst.getIndex(0), c,
1426                   dst.getIndex(0) * 16 + c * 4);
1427 }
1428
1429 Symbol *
1430 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1431 {
1432    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1433
1434    sym->reg.fileIndex = fileIdx;
1435
1436    if (idx >= 0) {
1437       if (sym->reg.file == FILE_SHADER_INPUT)
1438          sym->setOffset(info->in[idx].slot[c] * 4);
1439       else
1440       if (sym->reg.file == FILE_SHADER_OUTPUT)
1441          sym->setOffset(info->out[idx].slot[c] * 4);
1442       else
1443       if (sym->reg.file == FILE_SYSTEM_VALUE)
1444          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1445       else
1446          sym->setOffset(address);
1447    } else {
1448       sym->setOffset(address);
1449    }
1450    return sym;
1451 }
1452
1453 static inline uint8_t
1454 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1455 {
1456    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1457
1458    if (var->flat)
1459       mode = NV50_IR_INTERP_FLAT;
1460    else
1461    if (var->linear)
1462       mode = NV50_IR_INTERP_LINEAR;
1463    else
1464    if (var->sc)
1465       mode = NV50_IR_INTERP_SC;
1466
1467    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1468       ? OP_PINTERP : OP_LINTERP;
1469
1470    if (var->centroid)
1471       mode |= NV50_IR_INTERP_CENTROID;
1472
1473    return mode;
1474 }
1475
1476 Value *
1477 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1478 {
1479    operation op;
1480
1481    // XXX: no way to know interpolation mode if we don't know what's accessed
1482    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1483                                                       src.getIndex(0)], op);
1484
1485    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1486
1487    insn->setDef(0, getScratch());
1488    insn->setSrc(0, srcToSym(src, c));
1489    if (op == OP_PINTERP)
1490       insn->setSrc(1, fragCoord[3]);
1491    if (ptr)
1492       insn->setIndirect(0, 0, ptr);
1493
1494    insn->setInterpolate(mode);
1495
1496    bb->insertTail(insn);
1497    return insn->getDef(0);
1498 }
1499
1500 Value *
1501 Converter::applySrcMod(Value *val, int s, int c)
1502 {
1503    Modifier m = tgsi.getSrc(s).getMod(c);
1504    DataType ty = tgsi.inferSrcType();
1505
1506    if (m & Modifier(NV50_IR_MOD_ABS))
1507       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1508
1509    if (m & Modifier(NV50_IR_MOD_NEG))
1510       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1511
1512    return val;
1513 }
1514
1515 Value *
1516 Converter::getVertexBase(int s)
1517 {
1518    assert(s < 5);
1519    if (!(vtxBaseValid & (1 << s))) {
1520       const int index = tgsi.getSrc(s).getIndex(1);
1521       Value *rel = NULL;
1522       if (tgsi.getSrc(s).isIndirect(1))
1523          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1524       vtxBaseValid |= 1 << s;
1525       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1526                           mkImm(index), rel);
1527    }
1528    return vtxBase[s];
1529 }
1530
1531 Value *
1532 Converter::getOutputBase(int s)
1533 {
1534    assert(s < 5);
1535    if (!(vtxBaseValid & (1 << s))) {
1536       Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1));
1537       if (tgsi.getSrc(s).isIndirect(1))
1538          offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(),
1539                          fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL),
1540                          offset);
1541       vtxBaseValid |= 1 << s;
1542       vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset);
1543    }
1544    return vtxBase[s];
1545 }
1546
1547 Value *
1548 Converter::fetchSrc(int s, int c)
1549 {
1550    Value *res;
1551    Value *ptr = NULL, *dimRel = NULL;
1552
1553    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1554
1555    if (src.isIndirect(0))
1556       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1557
1558    if (src.is2D()) {
1559       switch (src.getFile()) {
1560       case TGSI_FILE_OUTPUT:
1561          dimRel = getOutputBase(s);
1562          break;
1563       case TGSI_FILE_INPUT:
1564          dimRel = getVertexBase(s);
1565          break;
1566       case TGSI_FILE_CONSTANT:
1567          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1568          if (src.isIndirect(1))
1569             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1570          break;
1571       default:
1572          break;
1573       }
1574    }
1575
1576    res = fetchSrc(src, c, ptr);
1577
1578    if (dimRel)
1579       res->getInsn()->setIndirect(0, 1, dimRel);
1580
1581    return applySrcMod(res, s, c);
1582 }
1583
1584 Converter::DataArray *
1585 Converter::getArrayForFile(unsigned file, int idx)
1586 {
1587    switch (file) {
1588    case TGSI_FILE_TEMPORARY:
1589       return &tData;
1590    case TGSI_FILE_PREDICATE:
1591       return &pData;
1592    case TGSI_FILE_ADDRESS:
1593       return &aData;
1594    case TGSI_FILE_OUTPUT:
1595       assert(prog->getType() == Program::TYPE_FRAGMENT);
1596       return &oData;
1597    default:
1598       assert(!"invalid/unhandled TGSI source file");
1599       return NULL;
1600    }
1601 }
1602
1603 Value *
1604 Converter::shiftAddress(Value *index)
1605 {
1606    if (!index)
1607       return NULL;
1608    return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1609 }
1610
1611 Value *
1612 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1613 {
1614    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1615    const int idx = src.getIndex(0);
1616    const int swz = src.getSwizzle(c);
1617    Instruction *ld;
1618
1619    switch (src.getFile()) {
1620    case TGSI_FILE_IMMEDIATE:
1621       assert(!ptr);
1622       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1623    case TGSI_FILE_CONSTANT:
1624       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1625    case TGSI_FILE_INPUT:
1626       if (prog->getType() == Program::TYPE_FRAGMENT) {
1627          // don't load masked inputs, won't be assigned a slot
1628          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1629             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1630          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1631             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1632          return interpolate(src, c, shiftAddress(ptr));
1633       } else
1634       if (prog->getType() == Program::TYPE_GEOMETRY) {
1635          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1636             return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1637          // XXX: This is going to be a problem with scalar arrays, i.e. when
1638          // we cannot assume that the address is given in units of vec4.
1639          //
1640          // nv50 and nvc0 need different things here, so let the lowering
1641          // passes decide what to do with the address
1642          if (ptr)
1643             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1644       }
1645       ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1646       ld->perPatch = info->in[idx].patch;
1647       return ld->getDef(0);
1648    case TGSI_FILE_OUTPUT:
1649       assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
1650       ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1651       ld->perPatch = info->out[idx].patch;
1652       return ld->getDef(0);
1653    case TGSI_FILE_SYSTEM_VALUE:
1654       assert(!ptr);
1655       ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1656       ld->perPatch = info->sv[idx].patch;
1657       return ld->getDef(0);
1658    default:
1659       return getArrayForFile(src.getFile(), idx2d)->load(
1660          sub.cur->values, idx, swz, shiftAddress(ptr));
1661    }
1662 }
1663
1664 Value *
1665 Converter::acquireDst(int d, int c)
1666 {
1667    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1668    const unsigned f = dst.getFile();
1669    const int idx = dst.getIndex(0);
1670    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1671
1672    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1673       return NULL;
1674
1675    if (dst.isIndirect(0) ||
1676        f == TGSI_FILE_SYSTEM_VALUE ||
1677        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1678       return getScratch();
1679
1680    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1681 }
1682
1683 void
1684 Converter::storeDst(int d, int c, Value *val)
1685 {
1686    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1687
1688    if (tgsi.getSaturate()) {
1689       mkOp1(OP_SAT, dstTy, val, val);
1690    }
1691
1692    Value *ptr = NULL;
1693    if (dst.isIndirect(0))
1694       ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1695
1696    if (info->io.genUserClip > 0 &&
1697        dst.getFile() == TGSI_FILE_OUTPUT &&
1698        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1699       mkMov(clipVtx[c], val);
1700       val = clipVtx[c];
1701    }
1702
1703    storeDst(dst, c, val, ptr);
1704 }
1705
1706 void
1707 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1708                     Value *val, Value *ptr)
1709 {
1710    const unsigned f = dst.getFile();
1711    const int idx = dst.getIndex(0);
1712    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1713
1714    if (f == TGSI_FILE_SYSTEM_VALUE) {
1715       assert(!ptr);
1716       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1717    } else
1718    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1719
1720       if (ptr || (info->out[idx].mask & (1 << c))) {
1721          /* Save the viewport index into a scratch register so that it can be
1722             exported at EMIT time */
1723          if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
1724              viewport != NULL)
1725             mkOp1(OP_MOV, TYPE_U32, viewport, val);
1726          else
1727             mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
1728                info->out[idx].patch;
1729       }
1730    } else
1731    if (f == TGSI_FILE_TEMPORARY ||
1732        f == TGSI_FILE_PREDICATE ||
1733        f == TGSI_FILE_ADDRESS ||
1734        f == TGSI_FILE_OUTPUT) {
1735       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1736    } else {
1737       assert(!"invalid dst file");
1738    }
1739 }
1740
1741 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1742    for (chan = 0; chan < 4; ++chan)                 \
1743       if (!inst.getDst(d).isMasked(chan))
1744
1745 Value *
1746 Converter::buildDot(int dim)
1747 {
1748    assert(dim > 0);
1749
1750    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1751    Value *dotp = getScratch();
1752
1753    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1754
1755    for (int c = 1; c < dim; ++c) {
1756       src0 = fetchSrc(0, c);
1757       src1 = fetchSrc(1, c);
1758       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1759    }
1760    return dotp;
1761 }
1762
1763 void
1764 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1765 {
1766    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1767    join->fixed = 1;
1768    conv->insertHead(join);
1769
1770    assert(!fork->joinAt);
1771    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1772    fork->insertBefore(fork->getExit(), fork->joinAt);
1773 }
1774
1775 void
1776 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1777 {
1778    unsigned rIdx = 0, sIdx = 0;
1779
1780    if (R >= 0)
1781       rIdx = tgsi.getSrc(R).getIndex(0);
1782    if (S >= 0)
1783       sIdx = tgsi.getSrc(S).getIndex(0);
1784
1785    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1786
1787    if (tgsi.getSrc(R).isIndirect(0)) {
1788       tex->tex.rIndirectSrc = s;
1789       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1790    }
1791    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1792       tex->tex.sIndirectSrc = s;
1793       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1794    }
1795 }
1796
1797 void
1798 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1799 {
1800    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1801    tex->tex.query = query;
1802    unsigned int c, d;
1803
1804    for (d = 0, c = 0; c < 4; ++c) {
1805       if (!dst0[c])
1806          continue;
1807       tex->tex.mask |= 1 << c;
1808       tex->setDef(d++, dst0[c]);
1809    }
1810    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1811
1812    setTexRS(tex, ++c, 1, -1);
1813
1814    bb->insertTail(tex);
1815 }
1816
1817 void
1818 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1819 {
1820    Value *proj = fetchSrc(0, 3);
1821    Instruction *insn = proj->getUniqueInsn();
1822    int c;
1823
1824    if (insn->op == OP_PINTERP) {
1825       bb->insertTail(insn = cloneForward(func, insn));
1826       insn->op = OP_LINTERP;
1827       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1828       insn->setSrc(1, NULL);
1829       proj = insn->getDef(0);
1830    }
1831    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1832
1833    for (c = 0; c < 4; ++c) {
1834       if (!(mask & (1 << c)))
1835          continue;
1836       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1837          continue;
1838       mask &= ~(1 << c);
1839
1840       bb->insertTail(insn = cloneForward(func, insn));
1841       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1842       insn->setSrc(1, proj);
1843       dst[c] = insn->getDef(0);
1844    }
1845    if (!mask)
1846       return;
1847
1848    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1849
1850    for (c = 0; c < 4; ++c)
1851       if (mask & (1 << c))
1852          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1853 }
1854
1855 // order of nv50 ir sources: x y z layer lod/bias shadow
1856 // order of TGSI TEX sources: x y z layer shadow lod/bias
1857 //  lowering will finally set the hw specific order (like array first on nvc0)
1858 void
1859 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1860 {
1861    Value *val;
1862    Value *arg[4], *src[8];
1863    Value *lod = NULL, *shd = NULL;
1864    unsigned int s, c, d;
1865    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1866
1867    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1868
1869    for (s = 0; s < tgt.getArgCount(); ++s)
1870       arg[s] = src[s] = fetchSrc(0, s);
1871
1872    if (texi->op == OP_TXL || texi->op == OP_TXB)
1873       lod = fetchSrc(L >> 4, L & 3);
1874
1875    if (C == 0x0f)
1876       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1877
1878    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
1879        tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
1880       shd = fetchSrc(1, 0);
1881    else if (tgt.isShadow())
1882       shd = fetchSrc(C >> 4, C & 3);
1883
1884    if (texi->op == OP_TXD) {
1885       for (c = 0; c < tgt.getDim(); ++c) {
1886          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1887          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1888       }
1889    }
1890
1891    // cube textures don't care about projection value, it's divided out
1892    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1893       unsigned int n = tgt.getDim();
1894       if (shd) {
1895          arg[n] = shd;
1896          ++n;
1897          assert(tgt.getDim() == tgt.getArgCount());
1898       }
1899       loadProjTexCoords(src, arg, (1 << n) - 1);
1900       if (shd)
1901          shd = src[n - 1];
1902    }
1903
1904    if (tgt.isCube()) {
1905       for (c = 0; c < 3; ++c)
1906          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1907       val = getScratch();
1908       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1909       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1910       mkOp1(OP_RCP, TYPE_F32, val, val);
1911       for (c = 0; c < 3; ++c)
1912          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1913    }
1914
1915    for (c = 0, d = 0; c < 4; ++c) {
1916       if (dst[c]) {
1917          texi->setDef(d++, dst[c]);
1918          texi->tex.mask |= 1 << c;
1919       } else {
1920          // NOTE: maybe hook up def too, for CSE
1921       }
1922    }
1923    for (s = 0; s < tgt.getArgCount(); ++s)
1924       texi->setSrc(s, src[s]);
1925    if (lod)
1926       texi->setSrc(s++, lod);
1927    if (shd)
1928       texi->setSrc(s++, shd);
1929
1930    setTexRS(texi, s, R, S);
1931
1932    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1933       texi->tex.levelZero = true;
1934    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
1935       texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
1936
1937    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1938    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1939       for (c = 0; c < 3; ++c) {
1940          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1941          texi->offset[s][c].setInsn(texi);
1942       }
1943    }
1944
1945    bb->insertTail(texi);
1946 }
1947
1948 // 1st source: xyz = coordinates, w = lod/sample
1949 // 2nd source: offset
1950 void
1951 Converter::handleTXF(Value *dst[4], int R, int L_M)
1952 {
1953    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1954    int ms;
1955    unsigned int c, d, s;
1956
1957    texi->tex.target = tgsi.getTexture(code, R);
1958
1959    ms = texi->tex.target.isMS() ? 1 : 0;
1960    texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1961
1962    for (c = 0, d = 0; c < 4; ++c) {
1963       if (dst[c]) {
1964          texi->setDef(d++, dst[c]);
1965          texi->tex.mask |= 1 << c;
1966       }
1967    }
1968    for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1969       texi->setSrc(c, fetchSrc(0, c));
1970    texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1971
1972    setTexRS(texi, c, R, -1);
1973
1974    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1975    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1976       for (c = 0; c < 3; ++c) {
1977          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1978          texi->offset[s][c].setInsn(texi);
1979       }
1980    }
1981
1982    bb->insertTail(texi);
1983 }
1984
1985 void
1986 Converter::handleLIT(Value *dst0[4])
1987 {
1988    Value *val0 = NULL;
1989    unsigned int mask = tgsi.getDst(0).getMask();
1990
1991    if (mask & (1 << 0))
1992       loadImm(dst0[0], 1.0f);
1993
1994    if (mask & (1 << 3))
1995       loadImm(dst0[3], 1.0f);
1996
1997    if (mask & (3 << 1)) {
1998       val0 = getScratch();
1999       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
2000       if (mask & (1 << 1))
2001          mkMov(dst0[1], val0);
2002    }
2003
2004    if (mask & (1 << 2)) {
2005       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
2006       Value *val1 = getScratch(), *val3 = getScratch();
2007
2008       Value *pos128 = loadImm(NULL, +127.999999f);
2009       Value *neg128 = loadImm(NULL, -127.999999f);
2010
2011       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
2012       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
2013       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
2014       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
2015
2016       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
2017    }
2018 }
2019
2020 static inline bool
2021 isResourceSpecial(const int r)
2022 {
2023    return (r == TGSI_RESOURCE_GLOBAL ||
2024            r == TGSI_RESOURCE_LOCAL ||
2025            r == TGSI_RESOURCE_PRIVATE ||
2026            r == TGSI_RESOURCE_INPUT);
2027 }
2028
2029 static inline bool
2030 isResourceRaw(const tgsi::Source *code, const int r)
2031 {
2032    return isResourceSpecial(r) || code->resources[r].raw;
2033 }
2034
2035 static inline nv50_ir::TexTarget
2036 getResourceTarget(const tgsi::Source *code, int r)
2037 {
2038    if (isResourceSpecial(r))
2039       return nv50_ir::TEX_TARGET_BUFFER;
2040    return tgsi::translateTexture(code->resources.at(r).target);
2041 }
2042
2043 Symbol *
2044 Converter::getResourceBase(const int r)
2045 {
2046    Symbol *sym = NULL;
2047
2048    switch (r) {
2049    case TGSI_RESOURCE_GLOBAL:
2050       sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
2051       break;
2052    case TGSI_RESOURCE_LOCAL:
2053       assert(prog->getType() == Program::TYPE_COMPUTE);
2054       sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2055                      info->prop.cp.sharedOffset);
2056       break;
2057    case TGSI_RESOURCE_PRIVATE:
2058       sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2059                      info->bin.tlsSpace);
2060       break;
2061    case TGSI_RESOURCE_INPUT:
2062       assert(prog->getType() == Program::TYPE_COMPUTE);
2063       sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2064                      info->prop.cp.inputOffset);
2065       break;
2066    default:
2067       sym = new_Symbol(prog,
2068                        nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2069       break;
2070    }
2071    return sym;
2072 }
2073
2074 void
2075 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2076 {
2077    const int arg =
2078       TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2079
2080    for (int c = 0; c < arg; ++c)
2081       coords.push_back(fetchSrc(s, c));
2082
2083    // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2084    if (r == TGSI_RESOURCE_LOCAL ||
2085        r == TGSI_RESOURCE_PRIVATE ||
2086        r == TGSI_RESOURCE_INPUT)
2087       coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2088                          coords[0]);
2089 }
2090
2091 static inline int
2092 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2093 {
2094    int n = 0;
2095
2096    while (mask) {
2097       if (mask & 1) {
2098          size[n]++;
2099       } else {
2100          if (size[n])
2101             comp[n = 1] = size[0] + 1;
2102          else
2103             comp[n]++;
2104       }
2105       mask >>= 1;
2106    }
2107    if (size[0] == 3) {
2108       n = 1;
2109       size[0] = (comp[0] == 1) ? 1 : 2;
2110       size[1] = 3 - size[0];
2111       comp[1] = comp[0] + size[0];
2112    }
2113    return n + 1;
2114 }
2115
2116 // For raw loads, granularity is 4 byte.
2117 // Usage of the texture read mask on OP_SULDP is not allowed.
2118 void
2119 Converter::handleLOAD(Value *dst0[4])
2120 {
2121    const int r = tgsi.getSrc(0).getIndex(0);
2122    int c;
2123    std::vector<Value *> off, src, ldv, def;
2124
2125    getResourceCoords(off, r, 1);
2126
2127    if (isResourceRaw(code, r)) {
2128       uint8_t mask = 0;
2129       uint8_t comp[2] = { 0, 0 };
2130       uint8_t size[2] = { 0, 0 };
2131
2132       Symbol *base = getResourceBase(r);
2133
2134       // determine the base and size of the at most 2 load ops
2135       for (c = 0; c < 4; ++c)
2136          if (!tgsi.getDst(0).isMasked(c))
2137             mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2138
2139       int n = partitionLoadStore(comp, size, mask);
2140
2141       src = off;
2142
2143       def.resize(4); // index by component, the ones we need will be non-NULL
2144       for (c = 0; c < 4; ++c) {
2145          if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2146             def[c] = dst0[c];
2147          else
2148          if (mask & (1 << c))
2149             def[c] = getScratch();
2150       }
2151
2152       const bool useLd = isResourceSpecial(r) ||
2153          (info->io.nv50styleSurfaces &&
2154           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2155
2156       for (int i = 0; i < n; ++i) {
2157          ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2158
2159          if (comp[i]) // adjust x component of source address if necessary
2160             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2161                             off[0], mkImm(comp[i] * 4));
2162          else
2163             src[0] = off[0];
2164
2165          if (useLd) {
2166             Instruction *ld =
2167                mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2168             for (size_t c = 1; c < ldv.size(); ++c)
2169                ld->setDef(c, ldv[c]);
2170          } else {
2171             mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2172                   0, ldv, src)->dType = typeOfSize(size[i] * 4);
2173          }
2174       }
2175    } else {
2176       def.resize(4);
2177       for (c = 0; c < 4; ++c) {
2178          if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2179             def[c] = getScratch();
2180          else
2181             def[c] = dst0[c];
2182       }
2183
2184       mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2185             def, off);
2186    }
2187    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2188       if (dst0[c] != def[c])
2189          mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2190 }
2191
2192 // For formatted stores, the write mask on OP_SUSTP can be used.
2193 // Raw stores have to be split.
2194 void
2195 Converter::handleSTORE()
2196 {
2197    const int r = tgsi.getDst(0).getIndex(0);
2198    int c;
2199    std::vector<Value *> off, src, dummy;
2200
2201    getResourceCoords(off, r, 0);
2202    src = off;
2203    const int s = src.size();
2204
2205    if (isResourceRaw(code, r)) {
2206       uint8_t comp[2] = { 0, 0 };
2207       uint8_t size[2] = { 0, 0 };
2208
2209       int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2210
2211       Symbol *base = getResourceBase(r);
2212
2213       const bool useSt = isResourceSpecial(r) ||
2214          (info->io.nv50styleSurfaces &&
2215           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2216
2217       for (int i = 0; i < n; ++i) {
2218          if (comp[i]) // adjust x component of source address if necessary
2219             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2220                             off[0], mkImm(comp[i] * 4));
2221          else
2222             src[0] = off[0];
2223
2224          const DataType stTy = typeOfSize(size[i] * 4);
2225
2226          if (useSt) {
2227             Instruction *st =
2228                mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2229             for (c = 1; c < size[i]; ++c)
2230                st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2231             st->setIndirect(0, 0, src[0]);
2232          } else {
2233             // attach values to be stored
2234             src.resize(s + size[i]);
2235             for (c = 0; c < size[i]; ++c)
2236                src[s + c] = fetchSrc(1, comp[i] + c);
2237             mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2238                   0, dummy, src)->setType(stTy);
2239          }
2240       }
2241    } else {
2242       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2243          src.push_back(fetchSrc(1, c));
2244
2245       mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2246             dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2247    }
2248 }
2249
2250 // XXX: These only work on resources with the single-component u32/s32 formats.
2251 // Therefore the result is replicated. This might not be intended by TGSI, but
2252 // operating on more than 1 component would produce undefined results because
2253 // they do not exist.
2254 void
2255 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2256 {
2257    const int r = tgsi.getSrc(0).getIndex(0);
2258    std::vector<Value *> srcv;
2259    std::vector<Value *> defv;
2260    LValue *dst = getScratch();
2261
2262    getResourceCoords(srcv, r, 1);
2263
2264    if (isResourceSpecial(r)) {
2265       assert(r != TGSI_RESOURCE_INPUT);
2266       Instruction *insn;
2267       insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2268       insn->subOp = subOp;
2269       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2270          insn->setSrc(2, fetchSrc(3, 0));
2271       insn->setIndirect(0, 0, srcv.at(0));
2272    } else {
2273       operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2274       TexTarget targ = getResourceTarget(code, r);
2275       int idx = code->resources[r].slot;
2276       defv.push_back(dst);
2277       srcv.push_back(fetchSrc(2, 0));
2278       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2279          srcv.push_back(fetchSrc(3, 0));
2280       TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2281       tex->subOp = subOp;
2282       tex->tex.mask = 1;
2283       tex->setType(ty);
2284    }
2285
2286    for (int c = 0; c < 4; ++c)
2287       if (dst0[c])
2288          dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2289 }
2290
2291 void
2292 Converter::handleINTERP(Value *dst[4])
2293 {
2294    // Check whether the input is linear. All other attributes ignored.
2295    Instruction *insn;
2296    Value *offset = NULL, *ptr = NULL, *w = NULL;
2297    bool linear;
2298    operation op;
2299    int c, mode;
2300
2301    tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2302    assert(src.getFile() == TGSI_FILE_INPUT);
2303
2304    if (src.isIndirect(0))
2305       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2306
2307    // XXX: no way to know interp mode if we don't know the index
2308    linear = info->in[ptr ? 0 : src.getIndex(0)].linear;
2309    if (linear) {
2310       op = OP_LINTERP;
2311       mode = NV50_IR_INTERP_LINEAR;
2312    } else {
2313       op = OP_PINTERP;
2314       mode = NV50_IR_INTERP_PERSPECTIVE;
2315    }
2316
2317    switch (tgsi.getOpcode()) {
2318    case TGSI_OPCODE_INTERP_CENTROID:
2319       mode |= NV50_IR_INTERP_CENTROID;
2320       break;
2321    case TGSI_OPCODE_INTERP_SAMPLE:
2322       insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2323       insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2324       mode |= NV50_IR_INTERP_OFFSET;
2325       break;
2326    case TGSI_OPCODE_INTERP_OFFSET: {
2327       // The input in src1.xy is float, but we need a single 32-bit value
2328       // where the upper and lower 16 bits are encoded in S0.12 format. We need
2329       // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2330       // and then convert to s32.
2331       Value *offs[2];
2332       for (c = 0; c < 2; c++) {
2333          offs[c] = fetchSrc(1, c);
2334          mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2335          mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2336          mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2337          mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2338       }
2339       offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2340                       offs[1], mkImm(0x1010), offs[0]);
2341       mode |= NV50_IR_INTERP_OFFSET;
2342       break;
2343    }
2344    }
2345
2346    if (op == OP_PINTERP) {
2347       if (offset) {
2348          w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2349          mkOp1(OP_RCP, TYPE_F32, w, w);
2350       } else {
2351          w = fragCoord[3];
2352       }
2353    }
2354
2355
2356    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2357       insn = mkOp1(op, TYPE_F32, dst[c], srcToSym(src, c));
2358       if (op == OP_PINTERP)
2359          insn->setSrc(1, w);
2360       if (ptr)
2361          insn->setIndirect(0, 0, ptr);
2362       if (offset)
2363          insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2364
2365       insn->setInterpolate(mode);
2366    }
2367 }
2368
2369 Converter::Subroutine *
2370 Converter::getSubroutine(unsigned ip)
2371 {
2372    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2373
2374    if (it == sub.map.end())
2375       it = sub.map.insert(std::make_pair(
2376               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2377
2378    return &it->second;
2379 }
2380
2381 Converter::Subroutine *
2382 Converter::getSubroutine(Function *f)
2383 {
2384    unsigned ip = f->getLabel();
2385    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2386
2387    if (it == sub.map.end())
2388       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2389
2390    return &it->second;
2391 }
2392
2393 bool
2394 Converter::isEndOfSubroutine(uint ip)
2395 {
2396    assert(ip < code->scan.num_instructions);
2397    tgsi::Instruction insn(&code->insns[ip]);
2398    return (insn.getOpcode() == TGSI_OPCODE_END ||
2399            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2400            // does END occur at end of main or the very end ?
2401            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2402 }
2403
2404 bool
2405 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2406 {
2407    Instruction *geni;
2408
2409    Value *dst0[4], *rDst0[4];
2410    Value *src0, *src1, *src2, *src3;
2411    Value *val0, *val1;
2412    int c;
2413
2414    tgsi = tgsi::Instruction(insn);
2415
2416    bool useScratchDst = tgsi.checkDstSrcAliasing();
2417
2418    operation op = tgsi.getOP();
2419    dstTy = tgsi.inferDstType();
2420    srcTy = tgsi.inferSrcType();
2421
2422    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2423
2424    if (tgsi.dstCount()) {
2425       for (c = 0; c < 4; ++c) {
2426          rDst0[c] = acquireDst(0, c);
2427          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2428       }
2429    }
2430
2431    switch (tgsi.getOpcode()) {
2432    case TGSI_OPCODE_ADD:
2433    case TGSI_OPCODE_UADD:
2434    case TGSI_OPCODE_AND:
2435    case TGSI_OPCODE_DIV:
2436    case TGSI_OPCODE_IDIV:
2437    case TGSI_OPCODE_UDIV:
2438    case TGSI_OPCODE_MAX:
2439    case TGSI_OPCODE_MIN:
2440    case TGSI_OPCODE_IMAX:
2441    case TGSI_OPCODE_IMIN:
2442    case TGSI_OPCODE_UMAX:
2443    case TGSI_OPCODE_UMIN:
2444    case TGSI_OPCODE_MOD:
2445    case TGSI_OPCODE_UMOD:
2446    case TGSI_OPCODE_MUL:
2447    case TGSI_OPCODE_UMUL:
2448    case TGSI_OPCODE_IMUL_HI:
2449    case TGSI_OPCODE_UMUL_HI:
2450    case TGSI_OPCODE_OR:
2451    case TGSI_OPCODE_SHL:
2452    case TGSI_OPCODE_ISHR:
2453    case TGSI_OPCODE_USHR:
2454    case TGSI_OPCODE_SUB:
2455    case TGSI_OPCODE_XOR:
2456       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2457          src0 = fetchSrc(0, c);
2458          src1 = fetchSrc(1, c);
2459          geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2460          geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2461       }
2462       break;
2463    case TGSI_OPCODE_MAD:
2464    case TGSI_OPCODE_UMAD:
2465    case TGSI_OPCODE_SAD:
2466       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2467          src0 = fetchSrc(0, c);
2468          src1 = fetchSrc(1, c);
2469          src2 = fetchSrc(2, c);
2470          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2471       }
2472       break;
2473    case TGSI_OPCODE_MOV:
2474    case TGSI_OPCODE_ABS:
2475    case TGSI_OPCODE_CEIL:
2476    case TGSI_OPCODE_FLR:
2477    case TGSI_OPCODE_TRUNC:
2478    case TGSI_OPCODE_RCP:
2479    case TGSI_OPCODE_IABS:
2480    case TGSI_OPCODE_INEG:
2481    case TGSI_OPCODE_NOT:
2482    case TGSI_OPCODE_DDX:
2483    case TGSI_OPCODE_DDY:
2484    case TGSI_OPCODE_DDX_FINE:
2485    case TGSI_OPCODE_DDY_FINE:
2486       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2487          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2488       break;
2489    case TGSI_OPCODE_RSQ:
2490       src0 = fetchSrc(0, 0);
2491       val0 = getScratch();
2492       mkOp1(OP_ABS, TYPE_F32, val0, src0);
2493       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2494       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2495          mkMov(dst0[c], val0);
2496       break;
2497    case TGSI_OPCODE_ARL:
2498    case TGSI_OPCODE_ARR:
2499       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2500          const RoundMode rnd =
2501             tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
2502          src0 = fetchSrc(0, c);
2503          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
2504       }
2505       break;
2506    case TGSI_OPCODE_UARL:
2507       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2508          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2509       break;
2510    case TGSI_OPCODE_POW:
2511       val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
2512       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2513          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2514       break;
2515    case TGSI_OPCODE_EX2:
2516    case TGSI_OPCODE_LG2:
2517       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2518       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2519          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2520       break;
2521    case TGSI_OPCODE_COS:
2522    case TGSI_OPCODE_SIN:
2523       val0 = getScratch();
2524       if (mask & 7) {
2525          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2526          mkOp1(op, TYPE_F32, val0, val0);
2527          for (c = 0; c < 3; ++c)
2528             if (dst0[c])
2529                mkMov(dst0[c], val0);
2530       }
2531       if (dst0[3]) {
2532          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2533          mkOp1(op, TYPE_F32, dst0[3], val0);
2534       }
2535       break;
2536    case TGSI_OPCODE_SCS:
2537       if (mask & 3) {
2538          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2539          if (dst0[0])
2540             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2541          if (dst0[1])
2542             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2543       }
2544       if (dst0[2])
2545          loadImm(dst0[2], 0.0f);
2546       if (dst0[3])
2547          loadImm(dst0[3], 1.0f);
2548       break;
2549    case TGSI_OPCODE_EXP:
2550       src0 = fetchSrc(0, 0);
2551       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2552       if (dst0[1])
2553          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2554       if (dst0[0])
2555          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2556       if (dst0[2])
2557          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2558       if (dst0[3])
2559          loadImm(dst0[3], 1.0f);
2560       break;
2561    case TGSI_OPCODE_LOG:
2562       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2563       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2564       if (dst0[0] || dst0[1])
2565          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2566       if (dst0[1]) {
2567          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2568          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2569          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2570       }
2571       if (dst0[3])
2572          loadImm(dst0[3], 1.0f);
2573       break;
2574    case TGSI_OPCODE_DP2:
2575       val0 = buildDot(2);
2576       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2577          mkMov(dst0[c], val0);
2578       break;
2579    case TGSI_OPCODE_DP3:
2580       val0 = buildDot(3);
2581       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2582          mkMov(dst0[c], val0);
2583       break;
2584    case TGSI_OPCODE_DP4:
2585       val0 = buildDot(4);
2586       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2587          mkMov(dst0[c], val0);
2588       break;
2589    case TGSI_OPCODE_DPH:
2590       val0 = buildDot(3);
2591       src1 = fetchSrc(1, 3);
2592       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2593       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2594          mkMov(dst0[c], val0);
2595       break;
2596    case TGSI_OPCODE_DST:
2597       if (dst0[0])
2598          loadImm(dst0[0], 1.0f);
2599       if (dst0[1]) {
2600          src0 = fetchSrc(0, 1);
2601          src1 = fetchSrc(1, 1);
2602          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2603       }
2604       if (dst0[2])
2605          mkMov(dst0[2], fetchSrc(0, 2));
2606       if (dst0[3])
2607          mkMov(dst0[3], fetchSrc(1, 3));
2608       break;
2609    case TGSI_OPCODE_LRP:
2610       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2611          src0 = fetchSrc(0, c);
2612          src1 = fetchSrc(1, c);
2613          src2 = fetchSrc(2, c);
2614          mkOp3(OP_MAD, TYPE_F32, dst0[c],
2615                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2616       }
2617       break;
2618    case TGSI_OPCODE_LIT:
2619       handleLIT(dst0);
2620       break;
2621    case TGSI_OPCODE_XPD:
2622       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2623          if (c < 3) {
2624             val0 = getSSA();
2625             src0 = fetchSrc(1, (c + 1) % 3);
2626             src1 = fetchSrc(0, (c + 2) % 3);
2627             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2628             mkOp1(OP_NEG, TYPE_F32, val0, val0);
2629
2630             src0 = fetchSrc(0, (c + 1) % 3);
2631             src1 = fetchSrc(1, (c + 2) % 3);
2632             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2633          } else {
2634             loadImm(dst0[c], 1.0f);
2635          }
2636       }
2637       break;
2638    case TGSI_OPCODE_ISSG:
2639    case TGSI_OPCODE_SSG:
2640       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2641          src0 = fetchSrc(0, c);
2642          val0 = getScratch();
2643          val1 = getScratch();
2644          mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2645          mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2646          if (srcTy == TYPE_F32)
2647             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2648          else
2649             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2650       }
2651       break;
2652    case TGSI_OPCODE_UCMP:
2653       srcTy = TYPE_U32;
2654       /* fallthrough */
2655    case TGSI_OPCODE_CMP:
2656       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2657          src0 = fetchSrc(0, c);
2658          src1 = fetchSrc(1, c);
2659          src2 = fetchSrc(2, c);
2660          if (src1 == src2)
2661             mkMov(dst0[c], src1);
2662          else
2663             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2664                   srcTy, dst0[c], srcTy, src1, src2, src0);
2665       }
2666       break;
2667    case TGSI_OPCODE_FRC:
2668       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2669          src0 = fetchSrc(0, c);
2670          val0 = getScratch();
2671          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2672          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2673       }
2674       break;
2675    case TGSI_OPCODE_ROUND:
2676       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2677          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2678          ->rnd = ROUND_NI;
2679       break;
2680    case TGSI_OPCODE_CLAMP:
2681       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2682          src0 = fetchSrc(0, c);
2683          src1 = fetchSrc(1, c);
2684          src2 = fetchSrc(2, c);
2685          val0 = getScratch();
2686          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2687          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2688       }
2689       break;
2690    case TGSI_OPCODE_SLT:
2691    case TGSI_OPCODE_SGE:
2692    case TGSI_OPCODE_SEQ:
2693    case TGSI_OPCODE_SGT:
2694    case TGSI_OPCODE_SLE:
2695    case TGSI_OPCODE_SNE:
2696    case TGSI_OPCODE_FSEQ:
2697    case TGSI_OPCODE_FSGE:
2698    case TGSI_OPCODE_FSLT:
2699    case TGSI_OPCODE_FSNE:
2700    case TGSI_OPCODE_ISGE:
2701    case TGSI_OPCODE_ISLT:
2702    case TGSI_OPCODE_USEQ:
2703    case TGSI_OPCODE_USGE:
2704    case TGSI_OPCODE_USLT:
2705    case TGSI_OPCODE_USNE:
2706       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2707          src0 = fetchSrc(0, c);
2708          src1 = fetchSrc(1, c);
2709          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2710       }
2711       break;
2712    case TGSI_OPCODE_KILL_IF:
2713       val0 = new_LValue(func, FILE_PREDICATE);
2714       mask = 0;
2715       for (c = 0; c < 4; ++c) {
2716          const int s = tgsi.getSrc(0).getSwizzle(c);
2717          if (mask & (1 << s))
2718             continue;
2719          mask |= 1 << s;
2720          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2721          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2722       }
2723       break;
2724    case TGSI_OPCODE_KILL:
2725       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2726       break;
2727    case TGSI_OPCODE_TEX:
2728    case TGSI_OPCODE_TXB:
2729    case TGSI_OPCODE_TXL:
2730    case TGSI_OPCODE_TXP:
2731    case TGSI_OPCODE_LODQ:
2732       //              R  S     L     C    Dx    Dy
2733       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2734       break;
2735    case TGSI_OPCODE_TXD:
2736       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2737       break;
2738    case TGSI_OPCODE_TG4:
2739       handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
2740       break;
2741    case TGSI_OPCODE_TEX2:
2742       handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2743       break;
2744    case TGSI_OPCODE_TXB2:
2745    case TGSI_OPCODE_TXL2:
2746       handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
2747       break;
2748    case TGSI_OPCODE_SAMPLE:
2749    case TGSI_OPCODE_SAMPLE_B:
2750    case TGSI_OPCODE_SAMPLE_D:
2751    case TGSI_OPCODE_SAMPLE_L:
2752    case TGSI_OPCODE_SAMPLE_C:
2753    case TGSI_OPCODE_SAMPLE_C_LZ:
2754       handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2755       break;
2756    case TGSI_OPCODE_TXF:
2757       handleTXF(dst0, 1, 0x03);
2758       break;
2759    case TGSI_OPCODE_SAMPLE_I:
2760       handleTXF(dst0, 1, 0x03);
2761       break;
2762    case TGSI_OPCODE_SAMPLE_I_MS:
2763       handleTXF(dst0, 1, 0x20);
2764       break;
2765    case TGSI_OPCODE_TXQ:
2766    case TGSI_OPCODE_SVIEWINFO:
2767       handleTXQ(dst0, TXQ_DIMS);
2768       break;
2769    case TGSI_OPCODE_F2I:
2770    case TGSI_OPCODE_F2U:
2771       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2772          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2773       break;
2774    case TGSI_OPCODE_I2F:
2775    case TGSI_OPCODE_U2F:
2776       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2777          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2778       break;
2779    case TGSI_OPCODE_EMIT:
2780       /* export the saved viewport index */
2781       if (viewport != NULL) {
2782          Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
2783                                   info->out[info->io.viewportId].slot[0] * 4);
2784          mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
2785       }
2786       /* fallthrough */
2787    case TGSI_OPCODE_ENDPRIM:
2788    {
2789       // get vertex stream (must be immediate)
2790       unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
2791       if (stream && op == OP_RESTART)
2792          break;
2793       src0 = mkImm(stream);
2794       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2795       break;
2796    }
2797    case TGSI_OPCODE_IF:
2798    case TGSI_OPCODE_UIF:
2799    {
2800       BasicBlock *ifBB = new BasicBlock(func);
2801
2802       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2803       condBBs.push(bb);
2804       joinBBs.push(bb);
2805
2806       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2807
2808       setPosition(ifBB, true);
2809    }
2810       break;
2811    case TGSI_OPCODE_ELSE:
2812    {
2813       BasicBlock *elseBB = new BasicBlock(func);
2814       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2815
2816       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2817       condBBs.push(bb);
2818
2819       forkBB->getExit()->asFlow()->target.bb = elseBB;
2820       if (!bb->isTerminated())
2821          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2822
2823       setPosition(elseBB, true);
2824    }
2825       break;
2826    case TGSI_OPCODE_ENDIF:
2827    {
2828       BasicBlock *convBB = new BasicBlock(func);
2829       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2830       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2831
2832       if (!bb->isTerminated()) {
2833          // we only want join if none of the clauses ended with CONT/BREAK/RET
2834          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2835             insertConvergenceOps(convBB, forkBB);
2836          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2837          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2838       }
2839
2840       if (prevBB->getExit()->op == OP_BRA) {
2841          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2842          prevBB->getExit()->asFlow()->target.bb = convBB;
2843       }
2844       setPosition(convBB, true);
2845    }
2846       break;
2847    case TGSI_OPCODE_BGNLOOP:
2848    {
2849       BasicBlock *lbgnBB = new BasicBlock(func);
2850       BasicBlock *lbrkBB = new BasicBlock(func);
2851
2852       loopBBs.push(lbgnBB);
2853       breakBBs.push(lbrkBB);
2854       if (loopBBs.getSize() > func->loopNestingBound)
2855          func->loopNestingBound++;
2856
2857       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2858
2859       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2860       setPosition(lbgnBB, true);
2861       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2862    }
2863       break;
2864    case TGSI_OPCODE_ENDLOOP:
2865    {
2866       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2867
2868       if (!bb->isTerminated()) {
2869          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2870          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2871       }
2872       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2873    }
2874       break;
2875    case TGSI_OPCODE_BRK:
2876    {
2877       if (bb->isTerminated())
2878          break;
2879       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2880       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2881       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2882    }
2883       break;
2884    case TGSI_OPCODE_CONT:
2885    {
2886       if (bb->isTerminated())
2887          break;
2888       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2889       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2890       contBB->explicitCont = true;
2891       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2892    }
2893       break;
2894    case TGSI_OPCODE_BGNSUB:
2895    {
2896       Subroutine *s = getSubroutine(ip);
2897       BasicBlock *entry = new BasicBlock(s->f);
2898       BasicBlock *leave = new BasicBlock(s->f);
2899
2900       // multiple entrypoints possible, keep the graph connected
2901       if (prog->getType() == Program::TYPE_COMPUTE)
2902          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2903
2904       sub.cur = s;
2905       s->f->setEntry(entry);
2906       s->f->setExit(leave);
2907       setPosition(entry, true);
2908       return true;
2909    }
2910    case TGSI_OPCODE_ENDSUB:
2911    {
2912       sub.cur = getSubroutine(prog->main);
2913       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2914       return true;
2915    }
2916    case TGSI_OPCODE_CAL:
2917    {
2918       Subroutine *s = getSubroutine(tgsi.getLabel());
2919       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2920       func->call.attach(&s->f->call, Graph::Edge::TREE);
2921       return true;
2922    }
2923    case TGSI_OPCODE_RET:
2924    {
2925       if (bb->isTerminated())
2926          return true;
2927       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2928
2929       if (!isEndOfSubroutine(ip + 1)) {
2930          // insert a PRERET at the entry if this is an early return
2931          // (only needed for sharing code in the epilogue)
2932          BasicBlock *pos = getBB();
2933          setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2934          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2935          setPosition(pos, true);
2936       }
2937       mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2938       bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2939    }
2940       break;
2941    case TGSI_OPCODE_END:
2942    {
2943       // attach and generate epilogue code
2944       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2945       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2946       setPosition(epilogue, true);
2947       if (prog->getType() == Program::TYPE_FRAGMENT)
2948          exportOutputs();
2949       if (info->io.genUserClip > 0)
2950          handleUserClipPlanes();
2951       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2952    }
2953       break;
2954    case TGSI_OPCODE_SWITCH:
2955    case TGSI_OPCODE_CASE:
2956       ERROR("switch/case opcode encountered, should have been lowered\n");
2957       abort();
2958       break;
2959    case TGSI_OPCODE_LOAD:
2960       handleLOAD(dst0);
2961       break;
2962    case TGSI_OPCODE_STORE:
2963       handleSTORE();
2964       break;
2965    case TGSI_OPCODE_BARRIER:
2966       geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2967       geni->fixed = 1;
2968       geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2969       break;
2970    case TGSI_OPCODE_MFENCE:
2971    case TGSI_OPCODE_LFENCE:
2972    case TGSI_OPCODE_SFENCE:
2973       geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2974       geni->fixed = 1;
2975       geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2976       break;
2977    case TGSI_OPCODE_ATOMUADD:
2978    case TGSI_OPCODE_ATOMXCHG:
2979    case TGSI_OPCODE_ATOMCAS:
2980    case TGSI_OPCODE_ATOMAND:
2981    case TGSI_OPCODE_ATOMOR:
2982    case TGSI_OPCODE_ATOMXOR:
2983    case TGSI_OPCODE_ATOMUMIN:
2984    case TGSI_OPCODE_ATOMIMIN:
2985    case TGSI_OPCODE_ATOMUMAX:
2986    case TGSI_OPCODE_ATOMIMAX:
2987       handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2988       break;
2989    case TGSI_OPCODE_IBFE:
2990    case TGSI_OPCODE_UBFE:
2991       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2992          src0 = fetchSrc(0, c);
2993          if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
2994              tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
2995             src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
2996                            tgsi.getSrc(1).getValueU32(c, info));
2997          } else {
2998             src1 = fetchSrc(1, c);
2999             src2 = fetchSrc(2, c);
3000             mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
3001          }
3002          mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
3003       }
3004       break;
3005    case TGSI_OPCODE_BFI:
3006       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3007          src0 = fetchSrc(0, c);
3008          src1 = fetchSrc(1, c);
3009          src2 = fetchSrc(2, c);
3010          src3 = fetchSrc(3, c);
3011          mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
3012          mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
3013       }
3014       break;
3015    case TGSI_OPCODE_LSB:
3016       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3017          src0 = fetchSrc(0, c);
3018          geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
3019          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3020          geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
3021          geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3022       }
3023       break;
3024    case TGSI_OPCODE_IMSB:
3025    case TGSI_OPCODE_UMSB:
3026       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3027          src0 = fetchSrc(0, c);
3028          mkOp1(OP_BFIND, srcTy, dst0[c], src0);
3029       }
3030       break;
3031    case TGSI_OPCODE_BREV:
3032       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3033          src0 = fetchSrc(0, c);
3034          geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
3035          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3036       }
3037       break;
3038    case TGSI_OPCODE_POPC:
3039       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3040          src0 = fetchSrc(0, c);
3041          mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
3042       }
3043       break;
3044    case TGSI_OPCODE_INTERP_CENTROID:
3045    case TGSI_OPCODE_INTERP_SAMPLE:
3046    case TGSI_OPCODE_INTERP_OFFSET:
3047       handleINTERP(dst0);
3048       break;
3049    case TGSI_OPCODE_D2I:
3050    case TGSI_OPCODE_D2U:
3051    case TGSI_OPCODE_D2F: {
3052       int pos = 0;
3053       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3054          Value *dreg = getSSA(8);
3055          src0 = fetchSrc(0, pos);
3056          src1 = fetchSrc(0, pos + 1);
3057          mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3058          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
3059          pos += 2;
3060       }
3061       break;
3062    }
3063    case TGSI_OPCODE_I2D:
3064    case TGSI_OPCODE_U2D:
3065    case TGSI_OPCODE_F2D:
3066       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3067          Value *dreg = getSSA(8);
3068          mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
3069          mkSplit(&dst0[c], 4, dreg);
3070          c++;
3071       }
3072       break;
3073    case TGSI_OPCODE_DABS:
3074    case TGSI_OPCODE_DNEG:
3075    case TGSI_OPCODE_DRCP:
3076    case TGSI_OPCODE_DSQRT:
3077    case TGSI_OPCODE_DRSQ:
3078    case TGSI_OPCODE_DTRUNC:
3079    case TGSI_OPCODE_DCEIL:
3080    case TGSI_OPCODE_DFLR:
3081       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3082          src0 = getSSA(8);
3083          Value *dst = getSSA(8), *tmp[2];
3084          tmp[0] = fetchSrc(0, c);
3085          tmp[1] = fetchSrc(0, c + 1);
3086          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3087          mkOp1(op, dstTy, dst, src0);
3088          mkSplit(&dst0[c], 4, dst);
3089          c++;
3090       }
3091       break;
3092    case TGSI_OPCODE_DFRAC:
3093       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3094          src0 = getSSA(8);
3095          Value *dst = getSSA(8), *tmp[2];
3096          tmp[0] = fetchSrc(0, c);
3097          tmp[1] = fetchSrc(0, c + 1);
3098          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3099          mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3100          mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3101          mkSplit(&dst0[c], 4, dst);
3102          c++;
3103       }
3104       break;
3105    case TGSI_OPCODE_DSLT:
3106    case TGSI_OPCODE_DSGE:
3107    case TGSI_OPCODE_DSEQ:
3108    case TGSI_OPCODE_DSNE: {
3109       int pos = 0;
3110       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3111          Value *tmp[2];
3112
3113          src0 = getSSA(8);
3114          src1 = getSSA(8);
3115          tmp[0] = fetchSrc(0, pos);
3116          tmp[1] = fetchSrc(0, pos + 1);
3117          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3118          tmp[0] = fetchSrc(1, pos);
3119          tmp[1] = fetchSrc(1, pos + 1);
3120          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3121          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3122          pos += 2;
3123       }
3124       break;
3125    }
3126    case TGSI_OPCODE_DADD:
3127    case TGSI_OPCODE_DMUL:
3128    case TGSI_OPCODE_DMAX:
3129    case TGSI_OPCODE_DMIN:
3130       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3131          src0 = getSSA(8);
3132          src1 = getSSA(8);
3133          Value *dst = getSSA(8), *tmp[2];
3134          tmp[0] = fetchSrc(0, c);
3135          tmp[1] = fetchSrc(0, c + 1);
3136          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3137          tmp[0] = fetchSrc(1, c);
3138          tmp[1] = fetchSrc(1, c + 1);
3139          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3140          mkOp2(op, dstTy, dst, src0, src1);
3141          mkSplit(&dst0[c], 4, dst);
3142          c++;
3143       }
3144       break;
3145    case TGSI_OPCODE_DMAD:
3146       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3147          src0 = getSSA(8);
3148          src1 = getSSA(8);
3149          src2 = getSSA(8);
3150          Value *dst = getSSA(8), *tmp[2];
3151          tmp[0] = fetchSrc(0, c);
3152          tmp[1] = fetchSrc(0, c + 1);
3153          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3154          tmp[0] = fetchSrc(1, c);
3155          tmp[1] = fetchSrc(1, c + 1);
3156          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3157          tmp[0] = fetchSrc(2, c);
3158          tmp[1] = fetchSrc(2, c + 1);
3159          mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3160          mkOp3(op, dstTy, dst, src0, src1, src2);
3161          mkSplit(&dst0[c], 4, dst);
3162          c++;
3163       }
3164       break;
3165    case TGSI_OPCODE_DROUND:
3166       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3167          src0 = getSSA(8);
3168          Value *dst = getSSA(8), *tmp[2];
3169          tmp[0] = fetchSrc(0, c);
3170          tmp[1] = fetchSrc(0, c + 1);
3171          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3172          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3173          ->rnd = ROUND_NI;
3174          mkSplit(&dst0[c], 4, dst);
3175          c++;
3176       }
3177       break;
3178    case TGSI_OPCODE_DSSG:
3179       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3180          src0 = getSSA(8);
3181          Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3182          tmp[0] = fetchSrc(0, c);
3183          tmp[1] = fetchSrc(0, c + 1);
3184          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3185
3186          val0 = getScratch();
3187          val1 = getScratch();
3188          // The zero is wrong here since it's only 32-bit, but it works out in
3189          // the end since it gets replaced with $r63.
3190          mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3191          mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3192          mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3193          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3194          mkSplit(&dst0[c], 4, dst);
3195          c++;
3196       }
3197       break;
3198    default:
3199       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3200       assert(0);
3201       break;
3202    }
3203
3204    if (tgsi.dstCount()) {
3205       for (c = 0; c < 4; ++c) {
3206          if (!dst0[c])
3207             continue;
3208          if (dst0[c] != rDst0[c])
3209             mkMov(rDst0[c], dst0[c]);
3210          storeDst(0, c, rDst0[c]);
3211       }
3212    }
3213    vtxBaseValid = 0;
3214
3215    return true;
3216 }
3217
3218 void
3219 Converter::handleUserClipPlanes()
3220 {
3221    Value *res[8];
3222    int n, i, c;
3223
3224    for (c = 0; c < 4; ++c) {
3225       for (i = 0; i < info->io.genUserClip; ++i) {
3226          Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
3227                                 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3228          Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3229          if (c == 0)
3230             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3231          else
3232             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3233       }
3234    }
3235
3236    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3237
3238    for (i = 0; i < info->io.genUserClip; ++i) {
3239       n = i / 4 + first;
3240       c = i % 4;
3241       Symbol *sym =
3242          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3243       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3244    }
3245 }
3246
3247 void
3248 Converter::exportOutputs()
3249 {
3250    for (unsigned int i = 0; i < info->numOutputs; ++i) {
3251       for (unsigned int c = 0; c < 4; ++c) {
3252          if (!oData.exists(sub.cur->values, i, c))
3253             continue;
3254          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3255                                 info->out[i].slot[c] * 4);
3256          Value *val = oData.load(sub.cur->values, i, c, NULL);
3257          if (val)
3258             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3259       }
3260    }
3261 }
3262
3263 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3264      code(code),
3265      tgsi(NULL),
3266      tData(this), aData(this), pData(this), oData(this)
3267 {
3268    info = code->info;
3269
3270    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
3271
3272    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3273    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3274    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3275    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3276
3277    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
3278    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3279    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3280    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3281
3282    zero = mkImm((uint32_t)0);
3283
3284    vtxBaseValid = 0;
3285 }
3286
3287 Converter::~Converter()
3288 {
3289 }
3290
3291 inline const Converter::Location *
3292 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3293 {
3294    ValueMap::l_iterator it = s->values.l.find(v);
3295    return it == s->values.l.end() ? NULL : &it->second;
3296 }
3297
3298 template<typename T> inline void
3299 Converter::BindArgumentsPass::updateCallArgs(
3300    Instruction *i, void (Instruction::*setArg)(int, Value *),
3301    T (Function::*proto))
3302 {
3303    Function *g = i->asFlow()->target.fn;
3304    Subroutine *subg = conv.getSubroutine(g);
3305
3306    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3307       Value *v = (g->*proto)[a].get();
3308       const Converter::Location &l = *getValueLocation(subg, v);
3309       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3310
3311       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3312    }
3313 }
3314
3315 template<typename T> inline void
3316 Converter::BindArgumentsPass::updatePrototype(
3317    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3318 {
3319    (func->*updateSet)();
3320
3321    for (unsigned i = 0; i < set->getSize(); ++i) {
3322       Value *v = func->getLValue(i);
3323       const Converter::Location *l = getValueLocation(sub, v);
3324
3325       // only include values with a matching TGSI register
3326       if (set->test(i) && l && !conv.code->locals.count(*l))
3327          (func->*proto).push_back(v);
3328    }
3329 }
3330
3331 bool
3332 Converter::BindArgumentsPass::visit(Function *f)
3333 {
3334    sub = conv.getSubroutine(f);
3335
3336    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3337         !bi.end(); bi.next()) {
3338       for (Instruction *i = BasicBlock::get(bi)->getFirst();
3339            i; i = i->next) {
3340          if (i->op == OP_CALL && !i->asFlow()->builtin) {
3341             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3342             updateCallArgs(i, &Instruction::setDef, &Function::outs);
3343          }
3344       }
3345    }
3346
3347    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3348       return true;
3349    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3350                    &Function::buildLiveSets, &Function::ins);
3351    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3352                    &Function::buildDefSets, &Function::outs);
3353
3354    return true;
3355 }
3356
3357 bool
3358 Converter::run()
3359 {
3360    BasicBlock *entry = new BasicBlock(prog->main);
3361    BasicBlock *leave = new BasicBlock(prog->main);
3362
3363    prog->main->setEntry(entry);
3364    prog->main->setExit(leave);
3365
3366    setPosition(entry, true);
3367    sub.cur = getSubroutine(prog->main);
3368
3369    if (info->io.genUserClip > 0) {
3370       for (int c = 0; c < 4; ++c)
3371          clipVtx[c] = getScratch();
3372    }
3373
3374    switch (prog->getType()) {
3375    case Program::TYPE_TESSELLATION_CONTROL:
3376       outBase = mkOp2v(
3377          OP_SUB, TYPE_U32, getSSA(),
3378          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
3379          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
3380       break;
3381    case Program::TYPE_FRAGMENT: {
3382       Symbol *sv = mkSysVal(SV_POSITION, 3);
3383       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
3384       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
3385       break;
3386    }
3387    default:
3388       break;
3389    }
3390
3391    if (info->io.viewportId >= 0)
3392       viewport = getScratch();
3393    else
3394       viewport = NULL;
3395
3396    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
3397       if (!handleInstruction(&code->insns[ip]))
3398          return false;
3399    }
3400
3401    if (!BindArgumentsPass(*this).run(prog))
3402       return false;
3403
3404    return true;
3405 }
3406
3407 } // unnamed namespace
3408
3409 namespace nv50_ir {
3410
3411 bool
3412 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
3413 {
3414    tgsi::Source src(info);
3415    if (!src.scanSource())
3416       return false;
3417    tlsSize = info->bin.tlsSpace;
3418
3419    Converter builder(this, &src);
3420    return builder.run();
3421 }
3422
3423 } // namespace nv50_ir