src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gv100.cpp

   1 /*
   2  * Copyright 2020 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "codegen/nv50_ir.h"
  23 #include "codegen/nv50_ir_build_util.h"
  24
  25 #include "codegen/nv50_ir_target_nvc0.h"
  26 #include "codegen/nv50_ir_lowering_gv100.h"
  27
  28 #include <limits>
  29
  30 namespace nv50_ir {
  31
  32 bool
  33 GV100LegalizeSSA::handleCMP(Instruction *i)
  34 {
  35    Value *pred = bld.getSSA(1, FILE_PREDICATE);
  36
  37    bld.mkCmp(OP_SET, reverseCondCode(i->asCmp()->setCond), TYPE_U8, pred,
  38              i->sType, bld.mkImm(0), i->getSrc(2));
  39    bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), i->getSrc(0), i->getSrc(1), pred);
  40    return true;
  41 }
  42
  43 // NIR deals with most of these for us, but codegen generates more in pointer
  44 // calculations from other lowering passes.
  45 bool
  46 GV100LegalizeSSA::handleIADD64(Instruction *i)
  47 {
  48    Value *carry = bld.getSSA(1, FILE_PREDICATE);
  49    Value *def[2] = { bld.getSSA(), bld.getSSA() };
  50    Value *src[2][2];
  51
  52    for (int s = 0; s < 2; s++) {
  53       if (i->getSrc(s)->reg.size == 8) {
  54          bld.mkSplit(src[s], 4, i->getSrc(s));
  55       } else {
  56          src[s][0] = i->getSrc(s);
  57          src[s][1] = bld.mkImm(0);
  58       }
  59    }
  60
  61    bld.mkOp2(OP_ADD, TYPE_U32, def[0], src[0][0], src[1][0])->
  62       setFlagsDef(1, carry);
  63    bld.mkOp2(OP_ADD, TYPE_U32, def[1], src[0][1], src[1][1])->
  64       setFlagsSrc(2, carry);
  65    bld.mkOp2(OP_MERGE, i->dType, i->getDef(0), def[0], def[1]);
  66    return true;
  67 }
  68
  69 bool
  70 GV100LegalizeSSA::handleIMAD_HIGH(Instruction *i)
  71 {
  72    Value *def = bld.getSSA(8), *defs[2];
  73    Value *src2;
  74
  75    if (i->srcExists(2) &&
  76        (!i->getSrc(2)->asImm() || i->getSrc(2)->asImm()->reg.data.u32)) {
  77       Value *src2s[2] = { bld.getSSA(), bld.getSSA() };
  78       bld.mkMov(src2s[0], bld.mkImm(0));
  79       bld.mkMov(src2s[1], i->getSrc(2));
  80       src2 = bld.mkOp2(OP_MERGE, TYPE_U64, bld.getSSA(8), src2s[0], src2s[1])->getDef(0);
  81    } else {
  82       src2 = bld.mkImm(0);
  83    }
  84
  85    bld.mkOp3(OP_MAD, isSignedType(i->sType) ? TYPE_S64 : TYPE_U64, def,
  86              i->getSrc(0), i->getSrc(1), src2);
  87
  88    bld.mkSplit(defs, 4, def);
  89    i->def(0).replace(defs[1], false);
  90    return true;
  91 }
  92
  93 // XXX: We should be able to do this in GV100LoweringPass, but codegen messes
  94 //      up somehow and swaps the condcode without swapping the sources.
  95 //      - tests/spec/glsl-1.50/execution/geometry/primitive-id-in.shader_test
  96 bool
  97 GV100LegalizeSSA::handleIMNMX(Instruction *i)
  98 {
  99    Value *pred = bld.getSSA(1, FILE_PREDICATE);
 100
 101    bld.mkCmp(OP_SET, (i->op == OP_MIN) ? CC_LT : CC_GT, i->dType, pred,
 102              i->sType, i->getSrc(0), i->getSrc(1));
 103    bld.mkOp3(OP_SELP, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1), pred);
 104    return true;
 105 }
 106
 107 bool
 108 GV100LegalizeSSA::handleIMUL(Instruction *i)
 109 {
 110    if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
 111       return handleIMAD_HIGH(i);
 112
 113    bld.mkOp3(OP_MAD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1),
 114              bld.mkImm(0));
 115    return true;
 116 }
 117
 118 bool
 119 GV100LegalizeSSA::handleLOP2(Instruction *i)
 120 {
 121    uint8_t src0 = NV50_IR_SUBOP_LOP3_LUT_SRC0;
 122    uint8_t src1 = NV50_IR_SUBOP_LOP3_LUT_SRC1;
 123    uint8_t subOp;
 124
 125    if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT))
 126       src0 = ~src0;
 127    if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT))
 128       src1 = ~src1;
 129
 130    switch (i->op) {
 131    case OP_AND: subOp = src0 & src1; break;
 132    case OP_OR : subOp = src0 | src1; break;
 133    case OP_XOR: subOp = src0 ^ src1; break;
 134    default:
 135       assert(!"invalid LOP2 opcode");
 136       break;
 137    }
 138
 139    bld.mkOp3(OP_LOP3_LUT, TYPE_U32, i->getDef(0), i->getSrc(0), i->getSrc(1),
 140              bld.mkImm(0))->subOp = subOp;
 141    return true;
 142 }
 143
 144 bool
 145 GV100LegalizeSSA::handleNOT(Instruction *i)
 146 {
 147    bld.mkOp3(OP_LOP3_LUT, TYPE_U32, i->getDef(0), bld.mkImm(0), i->getSrc(0),
 148              bld.mkImm(0))->subOp = (uint8_t)~NV50_IR_SUBOP_LOP3_LUT_SRC1;
 149    return true;
 150 }
 151
 152 bool
 153 GV100LegalizeSSA::handlePREEX2(Instruction *i)
 154 {
 155    i->def(0).replace(i->src(0), false);
 156    return true;
 157 }
 158
 159 bool
 160 GV100LegalizeSSA::handleQUADON(Instruction *i)
 161 {
 162    handleSHFL(i); // Inserts OP_WARPSYNC
 163    return true;
 164 }
 165
 166 bool
 167 GV100LegalizeSSA::handleQUADPOP(Instruction *i)
 168 {
 169    return true;
 170 }
 171
 172 bool
 173 GV100LegalizeSSA::handleSET(Instruction *i)
 174 {
 175    Value *src2 = i->srcExists(2) ? i->getSrc(2) : NULL;
 176    Value *pred = bld.getSSA(1, FILE_PREDICATE), *met;
 177    Instruction *xsetp;
 178
 179    if (isFloatType(i->dType)) {
 180       if (i->sType == TYPE_F32)
 181          return false; // HW has FSET.BF
 182       met = bld.mkImm(0x3f800000);
 183    } else {
 184       met = bld.mkImm(0xffffffff);
 185    }
 186
 187    xsetp = bld.mkCmp(i->op, i->asCmp()->setCond, TYPE_U8, pred, i->sType,
 188                      i->getSrc(0), i->getSrc(1));
 189    xsetp->src(0).mod = i->src(0).mod;
 190    xsetp->src(1).mod = i->src(1).mod;
 191    xsetp->setSrc(2, src2);
 192
 193    i = bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), bld.mkImm(0), met, pred);
 194    i->src(2).mod = Modifier(NV50_IR_MOD_NOT);
 195    return true;
 196 }
 197
 198 bool
 199 GV100LegalizeSSA::handleSHFL(Instruction *i)
 200 {
 201    Instruction *sync = new_Instruction(func, OP_WARPSYNC, TYPE_NONE);
 202    sync->fixed = 1;
 203    sync->setSrc(0, bld.mkImm(0xffffffff));
 204    i->bb->insertBefore(i, sync);
 205    return false;
 206 }
 207
 208 bool
 209 GV100LegalizeSSA::handleShift(Instruction *i)
 210 {
 211    Value *zero = bld.mkImm(0);
 212    Value *src1 = i->getSrc(1);
 213    Value *src0, *src2;
 214    uint8_t subOp = i->op == OP_SHL ? NV50_IR_SUBOP_SHF_L : NV50_IR_SUBOP_SHF_R;
 215
 216    if (i->op == OP_SHL && i->src(0).getFile() == FILE_GPR) {
 217       src0 = i->getSrc(0);
 218       src2 = zero;
 219    } else {
 220       src0 = zero;
 221       src2 = i->getSrc(0);
 222       subOp |= NV50_IR_SUBOP_SHF_HI;
 223    }
 224    if (i->subOp & NV50_IR_SUBOP_SHIFT_WRAP)
 225       subOp |= NV50_IR_SUBOP_SHF_W;
 226
 227    bld.mkOp3(OP_SHF, i->dType, i->getDef(0), src0, src1, src2)->subOp = subOp;
 228    return true;
 229 }
 230
 231 bool
 232 GV100LegalizeSSA::handleSUB(Instruction *i)
 233 {
 234    Instruction *xadd =
 235       bld.mkOp2(OP_ADD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1));
 236    xadd->src(0).mod = i->src(0).mod;
 237    xadd->src(1).mod = i->src(1).mod ^ Modifier(NV50_IR_MOD_NEG);
 238    return true;
 239 }
 240
 241 bool
 242 GV100LegalizeSSA::visit(Instruction *i)
 243 {
 244    bool lowered = false;
 245
 246    bld.setPosition(i, false);
 247
 248    switch (i->op) {
 249    case OP_AND:
 250    case OP_OR:
 251    case OP_XOR:
 252       if (i->def(0).getFile() != FILE_PREDICATE)
 253          lowered = handleLOP2(i);
 254       break;
 255    case OP_NOT:
 256       lowered = handleNOT(i);
 257       break;
 258    case OP_SHL:
 259    case OP_SHR:
 260       lowered = handleShift(i);
 261       break;
 262    case OP_SET:
 263    case OP_SET_AND:
 264    case OP_SET_OR:
 265    case OP_SET_XOR:
 266       if (i->def(0).getFile() != FILE_PREDICATE)
 267          lowered = handleSET(i);
 268       break;
 269    case OP_SLCT:
 270       lowered = handleCMP(i);
 271       break;
 272    case OP_PREEX2:
 273       lowered = handlePREEX2(i);
 274       break;
 275    case OP_MUL:
 276       if (!isFloatType(i->dType))
 277          lowered = handleIMUL(i);
 278       break;
 279    case OP_MAD:
 280       if (!isFloatType(i->dType) && i->subOp == NV50_IR_SUBOP_MUL_HIGH)
 281          lowered = handleIMAD_HIGH(i);
 282       break;
 283    case OP_SHFL:
 284       lowered = handleSHFL(i);
 285       break;
 286    case OP_QUADON:
 287       lowered = handleQUADON(i);
 288       break;
 289    case OP_QUADPOP:
 290       lowered = handleQUADPOP(i);
 291       break;
 292    case OP_SUB:
 293       lowered = handleSUB(i);
 294       break;
 295    case OP_MAX:
 296    case OP_MIN:
 297       if (!isFloatType(i->dType))
 298          lowered = handleIMNMX(i);
 299       break;
 300    case OP_ADD:
 301       if (!isFloatType(i->dType) && typeSizeof(i->dType) == 8)
 302          lowered = handleIADD64(i);
 303       break;
 304    case OP_PFETCH:
 305       handlePFETCH(i);
 306       break;
 307    case OP_LOAD:
 308       handleLOAD(i);
 309       break;
 310    default:
 311       break;
 312    }
 313
 314    if (lowered)
 315       delete_Instruction(prog, i);
 316
 317    return true;
 318 }
 319
 320 bool
 321 GV100LoweringPass::handleDMNMX(Instruction *i)
 322 {
 323    Value *pred = bld.getSSA(1, FILE_PREDICATE);
 324    Value *src0[2], *src1[2], *dest[2];
 325
 326    bld.mkCmp(OP_SET, (i->op == OP_MIN) ? CC_LT : CC_GT, TYPE_U32, pred,
 327              i->sType, i->getSrc(0), i->getSrc(1));
 328    bld.mkSplit(src0, 4, i->getSrc(0));
 329    bld.mkSplit(src1, 4, i->getSrc(1));
 330    bld.mkSplit(dest, 4, i->getDef(0));
 331    bld.mkOp3(OP_SELP, TYPE_U32, dest[0], src0[0], src1[0], pred);
 332    bld.mkOp3(OP_SELP, TYPE_U32, dest[1], src0[1], src1[1], pred);
 333    bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), dest[0], dest[1]);
 334    return true;
 335 }
 336
 337 bool
 338 GV100LoweringPass::handleEXTBF(Instruction *i)
 339 {
 340    Value *bit = bld.getScratch();
 341    Value *cnt = bld.getScratch();
 342    Value *mask = bld.getScratch();
 343    Value *zero = bld.mkImm(0);
 344
 345    bld.mkOp3(OP_PERMT, TYPE_U32, bit, i->getSrc(1), bld.mkImm(0x4440), zero);
 346    bld.mkOp3(OP_PERMT, TYPE_U32, cnt, i->getSrc(1), bld.mkImm(0x4441), zero);
 347    bld.mkOp2(OP_BMSK, TYPE_U32, mask, bit, cnt);
 348    bld.mkOp2(OP_AND, TYPE_U32, mask, i->getSrc(0), mask);
 349    bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), mask, bit);
 350    if (isSignedType(i->dType))
 351       bld.mkOp2(OP_SGXT, TYPE_S32, i->getDef(0), i->getDef(0), cnt);
 352
 353    return true;
 354 }
 355
 356 bool
 357 GV100LoweringPass::handleFLOW(Instruction *i)
 358 {
 359    i->op = OP_BRA;
 360    return false;
 361 }
 362
 363 bool
 364 GV100LoweringPass::handleI2I(Instruction *i)
 365 {
 366    bld.mkCvt(OP_CVT, TYPE_F32, i->getDef(0), i->sType, i->getSrc(0))->
 367       subOp = i->subOp;
 368    bld.mkCvt(OP_CVT, i->dType, i->getDef(0), TYPE_F32, i->getDef(0));
 369    return true;
 370 }
 371
 372 bool
 373 GV100LoweringPass::handleINSBF(Instruction *i)
 374 {
 375    Value *bit = bld.getScratch();
 376    Value *cnt = bld.getScratch();
 377    Value *mask = bld.getScratch();
 378    Value *src0 = bld.getScratch();
 379    Value *zero = bld.mkImm(0);
 380
 381    bld.mkOp3(OP_PERMT, TYPE_U32, bit, i->getSrc(1), bld.mkImm(0x4440), zero);
 382    bld.mkOp3(OP_PERMT, TYPE_U32, cnt, i->getSrc(1), bld.mkImm(0x4441), zero);
 383    bld.mkOp2(OP_BMSK, TYPE_U32, mask, zero, cnt);
 384
 385    bld.mkOp2(OP_AND, TYPE_U32, src0, i->getSrc(0), mask);
 386    bld.mkOp2(OP_SHL, TYPE_U32, src0, src0, bit);
 387
 388    bld.mkOp2(OP_SHL, TYPE_U32, mask, mask, bit);
 389    bld.mkOp3(OP_LOP3_LUT, TYPE_U32, i->getDef(0), src0, i->getSrc(2), mask)->
 390       subOp = NV50_IR_SUBOP_LOP3_LUT(a | (b & ~c));
 391
 392    return true;
 393 }
 394
 395 bool
 396 GV100LoweringPass::handlePINTERP(Instruction *i)
 397 {
 398    Value *src2 = i->srcExists(2) ? i->getSrc(2) : NULL;
 399    Instruction *ipa, *mul;
 400
 401    ipa = bld.mkOp2(OP_LINTERP, TYPE_F32, i->getDef(0), i->getSrc(0), src2);
 402    ipa->ipa = i->ipa;
 403    mul = bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(0), i->getDef(0), i->getSrc(1));
 404
 405    if (i->getInterpMode() == NV50_IR_INTERP_SC) {
 406       ipa->setDef(1, bld.getSSA(1, FILE_PREDICATE));
 407       mul->setPredicate(CC_NOT_P, ipa->getDef(1));
 408    }
 409
 410    return true;
 411 }
 412
 413 bool
 414 GV100LoweringPass::handlePREFLOW(Instruction *i)
 415 {
 416    return true;
 417 }
 418
 419 bool
 420 GV100LoweringPass::handlePRESIN(Instruction *i)
 421 {
 422    const float f = 1.0 / (2.0 * 3.14159265);
 423    bld.mkOp2(OP_MUL, i->dType, i->getDef(0), i->getSrc(0), bld.mkImm(f));
 424    return true;
 425 }
 426
 427 bool
 428 GV100LoweringPass::visit(Instruction *i)
 429 {
 430    bool lowered = false;
 431
 432    bld.setPosition(i, false);
 433
 434    switch (i->op) {
 435    case OP_BREAK:
 436    case OP_CONT:
 437       lowered = handleFLOW(i);
 438       break;
 439    case OP_PREBREAK:
 440    case OP_PRECONT:
 441       lowered = handlePREFLOW(i);
 442       break;
 443    case OP_CVT:
 444       if (i->src(0).getFile() != FILE_PREDICATE &&
 445           i->def(0).getFile() != FILE_PREDICATE &&
 446           !isFloatType(i->dType) && !isFloatType(i->sType))
 447          lowered = handleI2I(i);
 448       break;
 449    case OP_EXTBF:
 450       lowered = handleEXTBF(i);
 451       break;
 452    case OP_INSBF:
 453       lowered = handleINSBF(i);
 454       break;
 455    case OP_MAX:
 456    case OP_MIN:
 457       if (i->dType == TYPE_F64)
 458          lowered = handleDMNMX(i);
 459       break;
 460    case OP_PINTERP:
 461       lowered = handlePINTERP(i);
 462       break;
 463    case OP_PRESIN:
 464       lowered = handlePRESIN(i);
 465       break;
 466    default:
 467       break;
 468    }
 469
 470    if (lowered)
 471       delete_Instruction(prog, i);
 472
 473    return true;
 474 }
 475
 476 } // namespace nv50_ir