2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
73 assert(i
->dType
== TYPE_F64
);
74 // There are instructions that will compute the high 32 bits of the 64-bit
75 // float. We will just stick 0 in the bottom 32 bits.
77 bld
.setPosition(i
, false);
79 // 1. Take the source and it up.
80 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
81 bld
.mkSplit(src
, 4, i
->getSrc(0));
83 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
84 dst
[0] = bld
.loadImm(NULL
, 0);
85 dst
[1] = bld
.getSSA();
87 // 3. The new version of the instruction takes the high 32 bits of the
88 // source and outputs the high 32 bits of the destination.
92 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
94 // 4. Recombine the two dst pieces back into the original destination.
95 bld
.setPosition(i
, true);
96 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
100 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
102 // Only want to flush float inputs
103 assert(i
->sType
== TYPE_F32
);
105 // If we're already flushing denorms (and NaN's) to zero, no need for this.
109 // Only certain classes of operations can flush
110 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
111 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
112 cls
!= OPCLASS_CONVERT
)
119 NVC0LegalizeSSA::visit(Function
*fn
)
121 bld
.setProgram(fn
->getProgram());
126 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
129 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
131 if (i
->sType
== TYPE_F32
) {
132 if (prog
->getType() != Program::TYPE_COMPUTE
)
143 if (i
->dType
== TYPE_F64
)
153 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
156 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
161 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
162 const Instruction
*early
) const
164 if (early
->bb
== later
->bb
)
165 return early
->serial
< later
->serial
;
166 return later
->bb
->dominatedBy(early
->bb
);
170 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
171 Instruction
*usei
, const Instruction
*texi
)
174 for (std::list
<TexUse
>::iterator it
= uses
.begin();
176 if (insnDominatedBy(usei
, it
->insn
)) {
180 if (insnDominatedBy(it
->insn
, usei
))
186 uses
.push_back(TexUse(usei
, texi
));
189 // While it might be tempting to use the an algorithm that just looks at tex
190 // uses, not all texture results are guaranteed to be used on all paths. In
191 // the case where along some control flow path a texture result is never used,
192 // we might reuse that register for something else, creating a
193 // write-after-write hazard. So we have to manually look through all
194 // instructions looking for ones that reference the registers in question.
196 NVC0LegalizePostRA::findFirstUses(
197 Instruction
*texi
, std::list
<TexUse
> &uses
)
199 int minGPR
= texi
->def(0).rep()->reg
.data
.id
;
200 int maxGPR
= minGPR
+ texi
->def(0).rep()->reg
.size
/ 4 - 1;
202 unordered_set
<const BasicBlock
*> visited
;
203 findFirstUsesBB(minGPR
, maxGPR
, texi
->next
, texi
, uses
, visited
);
207 NVC0LegalizePostRA::findFirstUsesBB(
208 int minGPR
, int maxGPR
, Instruction
*start
,
209 const Instruction
*texi
, std::list
<TexUse
> &uses
,
210 unordered_set
<const BasicBlock
*> &visited
)
212 const BasicBlock
*bb
= start
->bb
;
214 // We don't process the whole bb the first time around. This is correct,
215 // however we might be in a loop and hit this BB again, and need to process
216 // the full thing. So only mark a bb as visited if we processed it from the
218 if (start
== bb
->getEntry()) {
219 if (visited
.find(bb
) != visited
.end())
224 for (Instruction
*insn
= start
; insn
!= bb
->getExit(); insn
= insn
->next
) {
228 for (int d
= 0; insn
->defExists(d
); ++d
) {
229 if (insn
->def(d
).getFile() != FILE_GPR
||
230 insn
->def(d
).rep()->reg
.data
.id
< minGPR
||
231 insn
->def(d
).rep()->reg
.data
.id
> maxGPR
)
233 addTexUse(uses
, insn
, texi
);
237 for (int s
= 0; insn
->srcExists(s
); ++s
) {
238 if (insn
->src(s
).getFile() != FILE_GPR
||
239 insn
->src(s
).rep()->reg
.data
.id
< minGPR
||
240 insn
->src(s
).rep()->reg
.data
.id
> maxGPR
)
242 addTexUse(uses
, insn
, texi
);
247 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
248 findFirstUsesBB(minGPR
, maxGPR
, BasicBlock::get(ei
.getNode())->getEntry(),
249 texi
, uses
, visited
);
254 // This pass is a bit long and ugly and can probably be optimized.
256 // 1. obtain a list of TEXes and their outputs' first use(s)
257 // 2. calculate the barrier level of each first use (minimal number of TEXes,
258 // over all paths, between the TEX and the use in question)
259 // 3. for each barrier, if all paths from the source TEX to that barrier
260 // contain a barrier of lesser level, it can be culled
262 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
264 std::list
<TexUse
> *uses
;
265 std::vector
<Instruction
*> texes
;
266 std::vector
<int> bbFirstTex
;
267 std::vector
<int> bbFirstUse
;
268 std::vector
<int> texCounts
;
269 std::vector
<TexUse
> useVec
;
272 fn
->orderInstructions(insns
);
274 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
275 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
276 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
278 // tag BB CFG nodes by their id for later
279 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
280 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
282 bb
->cfg
.tag
= bb
->getId();
285 // gather the first uses for each TEX
286 for (int i
= 0; i
< insns
.getSize(); ++i
) {
287 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
288 if (isTextureOp(tex
->op
)) {
289 texes
.push_back(tex
);
290 if (!texCounts
.at(tex
->bb
->getId()))
291 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
292 texCounts
[tex
->bb
->getId()]++;
298 uses
= new std::list
<TexUse
>[texes
.size()];
301 for (size_t i
= 0; i
< texes
.size(); ++i
) {
302 findFirstUses(texes
[i
], uses
[i
]);
305 // determine the barrier level at each use
306 for (size_t i
= 0; i
< texes
.size(); ++i
) {
307 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
309 BasicBlock
*tb
= texes
[i
]->bb
;
310 BasicBlock
*ub
= u
->insn
->bb
;
313 for (size_t j
= i
+ 1; j
< texes
.size() &&
314 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
318 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
319 &ub
->cfg
, texCounts
);
321 WARN("Failed to find path TEX -> TEXBAR\n");
325 // this counted all TEXes in the origin block, correct that
326 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
327 // and did not count the TEXes in the destination block, add those
328 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
329 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
333 assert(u
->level
>= 0);
334 useVec
.push_back(*u
);
339 // insert the barriers
340 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
341 Instruction
*prev
= useVec
[i
].insn
->prev
;
342 if (useVec
[i
].level
< 0)
344 if (prev
&& prev
->op
== OP_TEXBAR
) {
345 if (prev
->subOp
> useVec
[i
].level
)
346 prev
->subOp
= useVec
[i
].level
;
347 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
349 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
351 bar
->subOp
= useVec
[i
].level
;
352 // make use explicit to ease latency calculation
353 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
354 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
358 if (fn
->getProgram()->optLevel
< 3)
361 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
363 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
364 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
365 limitS
.resize(fn
->allBBlocks
.getSize());
367 // cull unneeded barriers (should do that earlier, but for simplicity)
368 IteratorRef bi
= fn
->cfg
.iteratorCFG();
369 // first calculate min/max outstanding TEXes for each BB
370 for (bi
->reset(); !bi
->end(); bi
->next()) {
371 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
372 BasicBlock
*bb
= BasicBlock::get(n
);
374 int max
= std::numeric_limits
<int>::max();
375 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
376 if (isTextureOp(i
->op
)) {
378 if (max
< std::numeric_limits
<int>::max())
381 if (i
->op
== OP_TEXBAR
) {
382 min
= MIN2(min
, i
->subOp
);
383 max
= MIN2(max
, i
->subOp
);
386 // limits when looking at an isolated block
387 limitS
[bb
->getId()].min
= min
;
388 limitS
[bb
->getId()].max
= max
;
390 // propagate the min/max values
391 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
392 for (bi
->reset(); !bi
->end(); bi
->next()) {
393 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
394 BasicBlock
*bb
= BasicBlock::get(n
);
395 const int bbId
= bb
->getId();
396 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
397 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
398 const int inId
= in
->getId();
399 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
400 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
402 // I just hope this is correct ...
403 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
405 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
406 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
408 // block contained a barrier
409 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
410 limitT
[bbId
].min
+ limitS
[bbId
].min
);
411 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
412 limitT
[bbId
].max
+ limitS
[bbId
].min
);
416 // finally delete unnecessary barriers
417 for (bi
->reset(); !bi
->end(); bi
->next()) {
418 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
419 BasicBlock
*bb
= BasicBlock::get(n
);
420 Instruction
*prev
= NULL
;
422 int max
= limitT
[bb
->getId()].max
;
423 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
425 if (i
->op
== OP_TEXBAR
) {
426 if (i
->subOp
>= max
) {
427 delete_Instruction(prog
, i
);
431 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
432 delete_Instruction(prog
, prev
);
437 if (isTextureOp(i
->op
)) {
440 if (i
&& !i
->isNop())
448 NVC0LegalizePostRA::visit(Function
*fn
)
451 insertTextureBarriers(fn
);
453 rZero
= new_LValue(fn
, FILE_GPR
);
454 carry
= new_LValue(fn
, FILE_FLAGS
);
456 rZero
->reg
.data
.id
= prog
->getTarget()->getFileSize(FILE_GPR
);
457 carry
->reg
.data
.id
= 0;
463 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
465 for (int s
= 0; i
->srcExists(s
); ++s
) {
466 if (s
== 2 && i
->op
== OP_SUCLAMP
)
468 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
469 if (imm
&& imm
->reg
.data
.u64
== 0)
474 // replace CONT with BRA for single unconditional continue
476 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
478 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
480 Graph::EdgeIterator ei
= bb
->cfg
.incident();
481 if (ei
.getType() != Graph::Edge::BACK
)
483 if (ei
.getType() != Graph::Edge::BACK
)
485 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
487 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
488 contBB
->getExit()->getPredicate())
490 contBB
->getExit()->op
= OP_BRA
;
491 bb
->remove(bb
->getEntry()); // delete PRECONT
494 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
498 // replace branches to join blocks with join ops
500 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
502 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
504 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
505 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
506 Instruction
*exit
= in
->getExit();
508 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
509 // there should always be a terminator instruction
510 WARN("inserted missing terminator in BB:%i\n", in
->getId());
512 if (exit
->op
== OP_BRA
) {
514 exit
->asFlow()->limit
= 1; // must-not-propagate marker
517 bb
->remove(bb
->getEntry());
521 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
523 Instruction
*i
, *next
;
525 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
526 for (i
= bb
->getFirst(); i
; i
= next
) {
528 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
529 if (!i
->getDef(0)->refCount())
531 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
532 i
->setSrc(0, rZero
); // initial value must be 0
538 if (i
->op
== OP_BAR
&& i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
&&
539 prog
->getType() != Program::TYPE_COMPUTE
) {
540 // It seems like barriers are never required for tessellation since
541 // the warp size is 32, and there are always at most 32 tcs threads.
544 if (i
->op
== OP_LOAD
&& i
->subOp
== NV50_IR_SUBOP_LDC_IS
) {
545 int offset
= i
->src(0).get()->reg
.data
.offset
;
546 if (abs(offset
) > 0x10000)
547 i
->src(0).get()->reg
.fileIndex
+= offset
>> 16;
548 i
->src(0).get()->reg
.data
.offset
= (int)(short)offset
;
550 // TODO: Move this to before register allocation for operations that
551 // need the $c register !
552 if (typeSizeof(i
->dType
) == 8) {
554 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
559 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
566 if (!tryReplaceContWithBra(bb
))
572 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
574 bld
.setProgram(prog
);
579 NVC0LoweringPass::visit(Function
*fn
)
581 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
582 assert(!strncmp(fn
->getName(), "MAIN", 4));
583 // TODO: when we generate actual functions pass this value along somehow
584 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
585 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
587 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
588 bld
.mkMovToReg(0, gpEmitAddress
);
595 NVC0LoweringPass::visit(BasicBlock
*bb
)
601 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
603 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
604 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
606 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
609 // move array source to first slot, convert to u16, add indirections
611 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
613 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
614 const int arg
= i
->tex
.target
.getArgCount();
615 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
616 const int chipset
= prog
->getTarget()->getChipset();
618 /* Only normalize in the non-explicit derivatives case. For explicit
619 * derivatives, this is handled in handleManualTXD.
621 if (i
->tex
.target
.isCube() && i
->dPdx
[0].get() == NULL
) {
624 for (c
= 0; c
< 3; ++c
)
625 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), i
->getSrc(c
));
626 val
= bld
.getScratch();
627 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
628 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
629 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
630 for (c
= 0; c
< 3; ++c
) {
631 i
->setSrc(c
, bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(),
636 // Arguments to the TEX instruction are a little insane. Even though the
637 // encoding is identical between SM20 and SM30, the arguments mean
638 // different things between Fermi and Kepler+. A lot of arguments are
639 // optional based on flags passed to the instruction. This summarizes the
649 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
650 // - other: 4 bits each, single reg
654 // array (+ offsets for txd in upper 16 bits)
659 // offsets (same as fermi, except txd which takes it with array)
676 if (chipset
>= NVISA_GK104_CHIPSET
) {
677 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
678 // XXX this ignores tsc, and assumes a 1:1 mapping
679 assert(i
->tex
.rIndirectSrc
>= 0);
680 Value
*hnd
= loadTexHandle(
681 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
682 i
->getIndirectR(), bld
.mkImm(2)),
686 i
->setIndirectR(hnd
);
687 i
->setIndirectS(NULL
);
688 } else if (i
->tex
.r
== i
->tex
.s
|| i
->op
== OP_TXF
) {
689 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
690 i
->tex
.s
= 0; // only a single cX[] value possible here
692 Value
*hnd
= bld
.getScratch();
693 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
694 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
696 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
698 i
->tex
.r
= 0; // not used for indirect tex
700 i
->setIndirectR(hnd
);
702 if (i
->tex
.target
.isArray()) {
703 LValue
*layer
= new_LValue(func
, FILE_GPR
);
704 Value
*src
= i
->getSrc(lyr
);
705 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
706 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
707 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
708 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
709 for (int s
= dim
; s
>= 1; --s
)
710 i
->setSrc(s
, i
->getSrc(s
- 1));
713 i
->setSrc(dim
, layer
);
716 // Move the indirect reference to the first place
717 if (i
->tex
.rIndirectSrc
>= 0 && (
718 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
719 Value
*hnd
= i
->getIndirectR();
721 i
->setIndirectR(NULL
);
722 i
->moveSources(0, 1);
724 i
->tex
.rIndirectSrc
= 0;
725 i
->tex
.sIndirectSrc
= -1;
728 // (nvc0) generate and move the tsc/tic/array source to the front
729 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
730 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
732 Value
*ticRel
= i
->getIndirectR();
733 Value
*tscRel
= i
->getIndirectS();
736 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
738 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
739 ticRel
, bld
.mkImm(i
->tex
.r
));
742 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
744 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
745 tscRel
, bld
.mkImm(i
->tex
.s
));
748 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
750 for (int s
= dim
; s
>= 1; --s
)
751 i
->setSrc(s
, i
->getSrc(s
- 1));
752 i
->setSrc(0, arrayIndex
);
754 i
->moveSources(0, 1);
758 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
759 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
760 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
766 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
768 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
773 // For nvc0, the sample id has to be in the second operand, as the offset
774 // does. Right now we don't know how to pass both in, and this case can't
775 // happen with OpenGL. On nve0, the sample id is part of the texture
776 // coordinate argument.
777 assert(chipset
>= NVISA_GK104_CHIPSET
||
778 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
780 // offset is between lod and dc
781 if (i
->tex
.useOffsets
) {
783 int s
= i
->srcCount(0xff, true);
784 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
785 if (i
->tex
.target
.isShadow())
787 if (i
->srcExists(s
)) // move potential predicate out of the way
788 i
->moveSources(s
, 1);
789 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
790 i
->moveSources(s
+ 1, 1);
792 if (i
->op
== OP_TXG
) {
793 // Either there is 1 offset, which goes into the 2 low bytes of the
794 // first source, or there are 4 offsets, which go into 2 sources (8
795 // values, 1 byte each).
796 Value
*offs
[2] = {NULL
, NULL
};
797 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
798 for (c
= 0; c
< 2; ++c
) {
799 if ((n
% 2) == 0 && c
== 0)
800 offs
[n
/ 2] = i
->offset
[n
][c
].get();
802 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
804 i
->offset
[n
][c
].get(),
805 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
809 i
->setSrc(s
, offs
[0]);
811 i
->setSrc(s
+ 1, offs
[1]);
814 assert(i
->tex
.useOffsets
== 1);
815 for (c
= 0; c
< 3; ++c
) {
817 if (!i
->offset
[0][c
].getImmediate(val
))
818 assert(!"non-immediate offset passed to non-TXG");
819 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
821 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
822 // The offset goes into the upper 16 bits of the array index. So
823 // create it if it's not already there, and INSBF it if it already
825 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
826 if (chipset
>= NVISA_GM107_CHIPSET
)
828 if (i
->tex
.target
.isArray()) {
829 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
830 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
833 i
->moveSources(s
, 1);
834 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
837 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
842 if (chipset
>= NVISA_GK104_CHIPSET
) {
844 // If TEX requires more than 4 sources, the 2nd register tuple must be
845 // aligned to 4, even if it consists of just a single 4-byte register.
847 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
849 int s
= i
->srcCount(0xff, true);
850 if (s
> 4 && s
< 7) {
851 if (i
->srcExists(s
)) // move potential predicate out of the way
852 i
->moveSources(s
, 7 - s
);
854 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
862 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
864 static const uint8_t qOps
[4][2] =
866 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
867 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
868 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
869 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
874 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
876 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
878 // This function is invoked after handleTEX lowering, so we have to expect
879 // the arguments in the order that the hw wants them. For Fermi, array and
880 // indirect are both in the leading arg, while for Kepler, array and
881 // indirect are separate (and both precede the coordinates). Maxwell is
882 // handled in a separate function.
884 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
885 array
= i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0;
887 array
= i
->tex
.target
.isArray() + (i
->tex
.rIndirectSrc
>= 0);
889 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
891 for (c
= 0; c
< dim
; ++c
)
892 crd
[c
] = bld
.getScratch();
894 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
895 for (l
= 0; l
< 4; ++l
) {
897 // mov coordinates from lane l to all lanes
898 for (c
= 0; c
< dim
; ++c
)
899 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
900 // add dPdx from lane l to lanes dx
901 for (c
= 0; c
< dim
; ++c
)
902 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
903 // add dPdy from lane l to lanes dy
904 for (c
= 0; c
< dim
; ++c
)
905 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
906 // normalize cube coordinates
907 if (i
->tex
.target
.isCube()) {
908 for (c
= 0; c
< 3; ++c
)
909 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), crd
[c
]);
910 val
= bld
.getScratch();
911 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
912 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
913 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
914 for (c
= 0; c
< 3; ++c
)
915 src
[c
] = bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(), crd
[c
], val
);
917 for (c
= 0; c
< dim
; ++c
)
921 bld
.insert(tex
= cloneForward(func
, i
));
922 for (c
= 0; c
< dim
; ++c
)
923 tex
->setSrc(c
+ array
, src
[c
]);
925 for (c
= 0; i
->defExists(c
); ++c
) {
927 def
[c
][l
] = bld
.getSSA();
928 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
933 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
935 for (c
= 0; i
->defExists(c
); ++c
) {
936 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
937 for (l
= 0; l
< 4; ++l
)
938 u
->setSrc(l
, def
[c
][l
]);
946 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
948 int dim
= txd
->tex
.target
.getDim() + txd
->tex
.target
.isCube();
949 unsigned arg
= txd
->tex
.target
.getArgCount();
950 unsigned expected_args
= arg
;
951 const int chipset
= prog
->getTarget()->getChipset();
953 if (chipset
>= NVISA_GK104_CHIPSET
) {
954 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
956 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
959 if (txd
->tex
.useOffsets
)
961 if (!txd
->tex
.target
.isArray() && (
962 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
966 if (expected_args
> 4 ||
968 txd
->tex
.target
.isShadow())
972 while (txd
->srcExists(arg
))
975 txd
->tex
.derivAll
= true;
976 if (txd
->op
== OP_TEX
)
977 return handleManualTXD(txd
);
979 assert(arg
== expected_args
);
980 for (int c
= 0; c
< dim
; ++c
) {
981 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
982 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
983 txd
->dPdx
[c
].set(NULL
);
984 txd
->dPdy
[c
].set(NULL
);
990 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
992 const int chipset
= prog
->getTarget()->getChipset();
993 if (chipset
>= NVISA_GK104_CHIPSET
&& txq
->tex
.rIndirectSrc
< 0)
994 txq
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
996 if (txq
->tex
.rIndirectSrc
< 0)
999 Value
*ticRel
= txq
->getIndirectR();
1001 txq
->setIndirectS(NULL
);
1002 txq
->tex
.sIndirectSrc
= -1;
1006 if (chipset
< NVISA_GK104_CHIPSET
) {
1007 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
1009 txq
->setSrc(txq
->tex
.rIndirectSrc
, NULL
);
1011 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
1012 ticRel
, bld
.mkImm(txq
->tex
.r
));
1014 bld
.mkOp2(OP_SHL
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x17));
1016 txq
->moveSources(0, 1);
1017 txq
->setSrc(0, src
);
1019 Value
*hnd
= loadTexHandle(
1020 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1021 txq
->getIndirectR(), bld
.mkImm(2)),
1026 txq
->setIndirectR(NULL
);
1027 txq
->moveSources(0, 1);
1028 txq
->setSrc(0, hnd
);
1029 txq
->tex
.rIndirectSrc
= 0;
1036 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
1038 /* The outputs are inverted compared to what the TGSI instruction
1039 * expects. Take that into account in the mask.
1041 assert((i
->tex
.mask
& ~3) == 0);
1042 if (i
->tex
.mask
== 1)
1044 else if (i
->tex
.mask
== 2)
1047 bld
.setPosition(i
, true);
1049 /* The returned values are not quite what we want:
1050 * (a) convert from s16/u16 to f32
1051 * (b) multiply by 1/256
1053 for (int def
= 0; def
< 2; ++def
) {
1054 if (!i
->defExists(def
))
1056 enum DataType type
= TYPE_S16
;
1057 if (i
->tex
.mask
== 2 || def
> 0)
1059 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
1060 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
1061 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
1063 if (i
->tex
.mask
== 3) {
1064 LValue
*t
= new_LValue(func
, FILE_GPR
);
1065 bld
.mkMov(t
, i
->getDef(0));
1066 bld
.mkMov(i
->getDef(0), i
->getDef(1));
1067 bld
.mkMov(i
->getDef(1), t
);
1073 NVC0LoweringPass::handleBUFQ(Instruction
*bufq
)
1076 bufq
->setSrc(0, loadBufLength32(bufq
->getIndirect(0, 1),
1077 bufq
->getSrc(0)->reg
.fileIndex
* 16));
1078 bufq
->setIndirect(0, 0, NULL
);
1079 bufq
->setIndirect(0, 1, NULL
);
1084 NVC0LoweringPass::handleSharedATOMNVE4(Instruction
*atom
)
1086 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1088 BasicBlock
*currBB
= atom
->bb
;
1089 BasicBlock
*tryLockBB
= atom
->bb
->splitBefore(atom
, false);
1090 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1091 BasicBlock
*setAndUnlockBB
= new BasicBlock(func
);
1092 BasicBlock
*failLockBB
= new BasicBlock(func
);
1094 bld
.setPosition(currBB
, true);
1095 assert(!currBB
->joinAt
);
1096 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1098 CmpInstruction
*pred
=
1099 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1100 TYPE_U32
, bld
.mkImm(0), bld
.mkImm(1));
1102 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_ALWAYS
, NULL
);
1103 currBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::TREE
);
1105 bld
.setPosition(tryLockBB
, true);
1108 bld
.mkLoad(TYPE_U32
, atom
->getDef(0),
1109 bld
.mkSymbol(FILE_MEMORY_SHARED
, 0, TYPE_U32
, 0), NULL
);
1110 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1111 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1113 bld
.mkFlow(OP_BRA
, setAndUnlockBB
, CC_P
, ld
->getDef(1));
1114 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1115 tryLockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::CROSS
);
1116 tryLockBB
->cfg
.attach(&setAndUnlockBB
->cfg
, Graph::Edge::TREE
);
1118 tryLockBB
->cfg
.detach(&joinBB
->cfg
);
1121 bld
.setPosition(setAndUnlockBB
, true);
1123 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1124 // Read the old value, and write the new one.
1125 stVal
= atom
->getSrc(1);
1126 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1127 CmpInstruction
*set
=
1128 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(),
1129 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1131 bld
.mkCmp(OP_SLCT
, CC_NE
, TYPE_U32
, (stVal
= bld
.getSSA()),
1132 TYPE_U32
, atom
->getSrc(2), ld
->getDef(0), set
->getDef(0));
1136 switch (atom
->subOp
) {
1137 case NV50_IR_SUBOP_ATOM_ADD
:
1140 case NV50_IR_SUBOP_ATOM_AND
:
1143 case NV50_IR_SUBOP_ATOM_OR
:
1146 case NV50_IR_SUBOP_ATOM_XOR
:
1149 case NV50_IR_SUBOP_ATOM_MIN
:
1152 case NV50_IR_SUBOP_ATOM_MAX
:
1160 stVal
= bld
.mkOp2v(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1165 bld
.mkStore(OP_STORE
, TYPE_U32
,
1166 bld
.mkSymbol(FILE_MEMORY_SHARED
, 0, TYPE_U32
, 0),
1168 st
->setDef(0, pred
->getDef(0));
1169 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1171 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1172 setAndUnlockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::TREE
);
1174 // Lock until the store has not been performed.
1175 bld
.setPosition(failLockBB
, true);
1176 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_NOT_P
, pred
->getDef(0));
1177 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1178 failLockBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::BACK
);
1179 failLockBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::TREE
);
1181 bld
.setPosition(joinBB
, false);
1182 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1186 NVC0LoweringPass::handleSharedATOM(Instruction
*atom
)
1188 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1190 BasicBlock
*currBB
= atom
->bb
;
1191 BasicBlock
*tryLockAndSetBB
= atom
->bb
->splitBefore(atom
, false);
1192 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1194 bld
.setPosition(currBB
, true);
1195 assert(!currBB
->joinAt
);
1196 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1198 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_ALWAYS
, NULL
);
1199 currBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::TREE
);
1201 bld
.setPosition(tryLockAndSetBB
, true);
1204 bld
.mkLoad(TYPE_U32
, atom
->getDef(0),
1205 bld
.mkSymbol(FILE_MEMORY_SHARED
, 0, TYPE_U32
, 0), NULL
);
1206 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1207 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1210 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1211 // Read the old value, and write the new one.
1212 stVal
= atom
->getSrc(1);
1213 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1214 CmpInstruction
*set
=
1215 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1216 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1217 set
->setPredicate(CC_P
, ld
->getDef(1));
1220 bld
.mkOp3(OP_SELP
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
1221 atom
->getSrc(2), set
->getDef(0));
1222 selp
->src(2).mod
= Modifier(NV50_IR_MOD_NOT
);
1223 selp
->setPredicate(CC_P
, ld
->getDef(1));
1225 stVal
= selp
->getDef(0);
1229 switch (atom
->subOp
) {
1230 case NV50_IR_SUBOP_ATOM_ADD
:
1233 case NV50_IR_SUBOP_ATOM_AND
:
1236 case NV50_IR_SUBOP_ATOM_OR
:
1239 case NV50_IR_SUBOP_ATOM_XOR
:
1242 case NV50_IR_SUBOP_ATOM_MIN
:
1245 case NV50_IR_SUBOP_ATOM_MAX
:
1254 bld
.mkOp2(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1256 i
->setPredicate(CC_P
, ld
->getDef(1));
1258 stVal
= i
->getDef(0);
1262 bld
.mkStore(OP_STORE
, TYPE_U32
,
1263 bld
.mkSymbol(FILE_MEMORY_SHARED
, 0, TYPE_U32
, 0),
1265 st
->setPredicate(CC_P
, ld
->getDef(1));
1266 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1268 // Loop until the lock is acquired.
1269 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_NOT_P
, ld
->getDef(1));
1270 tryLockAndSetBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::BACK
);
1271 tryLockAndSetBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::CROSS
);
1272 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1276 bld
.setPosition(joinBB
, false);
1277 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1281 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1284 Value
*ptr
= atom
->getIndirect(0, 0), *ind
= atom
->getIndirect(0, 1), *base
;
1286 switch (atom
->src(0).getFile()) {
1287 case FILE_MEMORY_LOCAL
:
1290 case FILE_MEMORY_SHARED
:
1291 // For Fermi/Kepler, we have to use ld lock/st unlock to perform atomic
1292 // operations on shared memory. For Maxwell, ATOMS is enough.
1293 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
1294 handleSharedATOM(atom
);
1295 else if (targ
->getChipset() < NVISA_GM107_CHIPSET
)
1296 handleSharedATOMNVE4(atom
);
1299 assert(atom
->src(0).getFile() == FILE_MEMORY_BUFFER
);
1300 base
= loadBufInfo64(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1301 assert(base
->reg
.size
== 8);
1303 base
= bld
.mkOp2v(OP_ADD
, TYPE_U64
, base
, base
, ptr
);
1304 assert(base
->reg
.size
== 8);
1305 atom
->setIndirect(0, 0, base
);
1306 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1310 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1312 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1313 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1315 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1316 atom
->setIndirect(0, 1, NULL
);
1317 atom
->setIndirect(0, 0, base
);
1323 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1325 if (targ
->getChipset() < NVISA_GM107_CHIPSET
) {
1326 if (cas
->src(0).getFile() == FILE_MEMORY_SHARED
) {
1327 // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
1332 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1333 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1335 bld
.setPosition(cas
, true);
1338 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1339 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1341 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1342 if (cas
->isPredicated())
1343 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1346 if (cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1347 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1348 // should be set to the high part of the double reg or bad things will
1349 // happen elsewhere in the universe.
1350 // Also, it sometimes returns the new value instead of the old one
1351 // under mysterious circumstances.
1352 Value
*dreg
= bld
.getSSA(8);
1353 bld
.setPosition(cas
, false);
1354 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1355 cas
->setSrc(1, dreg
);
1356 cas
->setSrc(2, dreg
);
1363 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
, uint16_t base
)
1365 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1369 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1373 NVC0LoweringPass::loadResInfo64(Value
*ptr
, uint32_t off
, uint16_t base
)
1375 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1379 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1382 mkLoadv(TYPE_U64
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
), ptr
);
1386 NVC0LoweringPass::loadResLength32(Value
*ptr
, uint32_t off
, uint16_t base
)
1388 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1392 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1395 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
+ 8), ptr
);
1399 NVC0LoweringPass::loadSuInfo32(Value
*ptr
, uint32_t off
)
1401 return loadResInfo32(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1405 NVC0LoweringPass::loadSuInfo64(Value
*ptr
, uint32_t off
)
1407 return loadResInfo64(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1411 NVC0LoweringPass::loadSuLength32(Value
*ptr
, uint32_t off
)
1413 return loadResLength32(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1417 NVC0LoweringPass::loadBufInfo32(Value
*ptr
, uint32_t off
)
1419 return loadResInfo32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1423 NVC0LoweringPass::loadBufInfo64(Value
*ptr
, uint32_t off
)
1425 return loadResInfo64(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1429 NVC0LoweringPass::loadBufLength32(Value
*ptr
, uint32_t off
)
1431 return loadResLength32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1435 NVC0LoweringPass::loadUboInfo32(Value
*ptr
, uint32_t off
)
1437 return loadResInfo32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1441 NVC0LoweringPass::loadUboInfo64(Value
*ptr
, uint32_t off
)
1443 return loadResInfo64(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1447 NVC0LoweringPass::loadUboLength32(Value
*ptr
, uint32_t off
)
1449 return loadResLength32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1453 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1455 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1456 off
+= prog
->driver
->io
.msInfoBase
;
1458 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1461 /* On nvc0, surface info is obtained via the surface binding points passed
1462 * to the SULD/SUST instructions.
1463 * On nve4, surface info is stored in c[] and is used by various special
1464 * instructions, e.g. for clamping coordiantes or generating an address.
1465 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1467 #define NVE4_SU_INFO_ADDR 0x00
1468 #define NVE4_SU_INFO_FMT 0x04
1469 #define NVE4_SU_INFO_DIM_X 0x08
1470 #define NVE4_SU_INFO_PITCH 0x0c
1471 #define NVE4_SU_INFO_DIM_Y 0x10
1472 #define NVE4_SU_INFO_ARRAY 0x14
1473 #define NVE4_SU_INFO_DIM_Z 0x18
1474 #define NVE4_SU_INFO_UNK1C 0x1c
1475 #define NVE4_SU_INFO_WIDTH 0x20
1476 #define NVE4_SU_INFO_HEIGHT 0x24
1477 #define NVE4_SU_INFO_DEPTH 0x28
1478 #define NVE4_SU_INFO_TARGET 0x2c
1479 #define NVE4_SU_INFO_CALL 0x30
1480 #define NVE4_SU_INFO_RAW_X 0x34
1481 #define NVE4_SU_INFO_MS_X 0x38
1482 #define NVE4_SU_INFO_MS_Y 0x3c
1484 #define NVE4_SU_INFO__STRIDE 0x40
1486 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
1487 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1488 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
1490 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1492 switch (su
->tex
.target
.getEnum()) {
1493 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1494 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1495 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1496 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1497 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1498 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1499 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1500 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1501 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1502 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1503 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1504 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1505 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1513 NVC0LoweringPass::handleSUQ(TexInstruction
*suq
)
1515 int dim
= suq
->tex
.target
.getDim();
1516 int arg
= dim
+ (suq
->tex
.target
.isArray() || suq
->tex
.target
.isCube());
1517 uint8_t s
= prog
->driver
->io
.auxCBSlot
;
1518 Value
*ind
= suq
->getIndirectR();
1522 base
= prog
->driver
->io
.suInfoBase
+ suq
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1525 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(),
1528 for (c
= 0; c
< arg
; ++c
) {
1529 if (suq
->defExists(c
)) {
1532 if (c
== 1 && suq
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1533 offset
= base
+ NVE4_SU_INFO_SIZE(2);
1535 offset
= base
+ NVE4_SU_INFO_SIZE(c
);
1537 bld
.mkLoad(TYPE_U32
, suq
->getDef(c
),
1538 bld
.mkSymbol(FILE_MEMORY_CONST
, s
, TYPE_U32
, offset
), ind
);
1542 if (suq
->tex
.target
.isCube()) {
1543 if (suq
->defExists(2)) {
1544 bld
.mkOp2(OP_DIV
, TYPE_U32
, suq
->getDef(2), suq
->getDef(2),
1545 bld
.loadImm(NULL
, 6));
1549 if (suq
->defExists(3)) {
1550 // .w contains the number of samples for multi-sampled images but we
1551 // don't support them for now.
1552 bld
.mkMov(suq
->getDef(3), bld
.loadImm(NULL
, 1));
1560 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1562 const uint16_t base
= tex
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1563 const int arg
= tex
->tex
.target
.getArgCount();
1565 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1566 tex
->tex
.target
= TEX_TARGET_2D
;
1568 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1569 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1573 Value
*x
= tex
->getSrc(0);
1574 Value
*y
= tex
->getSrc(1);
1575 Value
*s
= tex
->getSrc(arg
- 1);
1577 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1580 if (tex
->tex
.rIndirectSrc
>= 0) {
1581 assert(tex
->tex
.r
== 0);
1582 // FIXME: out of bounds
1583 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1584 tex
->getIndirectR(), bld
.mkImm(6));
1587 Value
*ms_x
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(0));
1588 Value
*ms_y
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(1));
1590 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1591 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1593 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1594 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1596 Value
*dx
= loadMsInfo32(ts
, 0x0);
1597 Value
*dy
= loadMsInfo32(ts
, 0x4);
1599 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1600 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1604 tex
->moveSources(arg
, -1);
1607 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1608 // They're computed from the coordinates using the surface info in c[] space.
1610 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1613 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1615 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1616 const int idx
= su
->tex
.r
;
1617 const int dim
= su
->tex
.target
.getDim();
1618 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
1619 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
1621 Value
*zero
= bld
.mkImm(0);
1625 Value
*bf
, *eau
, *off
;
1629 off
= bld
.getScratch(4);
1630 bf
= bld
.getScratch(4);
1631 addr
= bld
.getSSA(8);
1632 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1634 bld
.setPosition(su
, false);
1636 adjustCoordinatesMS(su
);
1638 if (su
->tex
.rIndirectSrc
>= 0) {
1639 // FIXME: out of bounds
1640 assert(su
->tex
.r
== 0);
1641 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1642 su
->getIndirectR(), bld
.mkImm(6));
1645 // calculate clamped coordinates
1646 for (c
= 0; c
< arg
; ++c
) {
1649 if (c
== 1 && su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1650 // The array index is stored in the Z component for 1D arrays.
1654 src
[c
] = bld
.getScratch();
1656 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_RAW_X
);
1658 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_DIM(dimc
));
1659 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1660 ->subOp
= getSuClampSubOp(su
, dimc
);
1665 // set predicate output
1666 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1667 src
[0]->getInsn()->setFlagsDef(1, pred
);
1669 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1670 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1671 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1674 // calculate pixel offset
1676 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1677 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1680 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_UNK1C
);
1681 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1682 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1684 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_PITCH
);
1685 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1686 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1689 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_PITCH
);
1690 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1691 ->subOp
= (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) ?
1692 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1695 // calculate effective address part 1
1696 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1700 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_FMT
);
1701 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1702 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1716 if (!su
->tex
.target
.isArray() && !su
->tex
.target
.isCube()) {
1717 z
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_UNK1C
);
1718 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1722 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1726 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1727 insn
->subOp
= subOp
;
1728 insn
->setFlagsDef(1, pred
);
1732 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ADDR
);
1734 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1737 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1739 // add array layer offset
1740 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1741 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ARRAY
);
1743 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1744 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1746 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1747 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1748 // combine predicates
1750 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1755 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1759 // bf == g[] address & 0xff
1760 // eau == g[] address >> 8
1761 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1762 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1764 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1765 // Convert from u32 to u8 address format, which is what the library code
1766 // doing SULDP currently uses.
1767 // XXX: can SUEAU do this ?
1768 // XXX: does it matter that we don't mask high bytes in bf ?
1770 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1771 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1774 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1776 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1777 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1779 // let's just set it 0 for raw access and hope it works
1781 bld
.mkImm(0) : loadSuInfo32(ind
, base
+ NVE4_SU_INFO_FMT
);
1783 // get rid of old coordinate sources, make space for fmt info and predicate
1784 su
->moveSources(arg
, 3 - arg
);
1785 // set 64 bit address and 32-bit format sources
1786 su
->setSrc(0, addr
);
1788 su
->setSrc(2, pred
);
1792 getSrcType(const TexInstruction::ImgFormatDesc
*t
, int c
)
1795 case FLOAT
: return t
->bits
[c
] == 16 ? TYPE_F16
: TYPE_F32
;
1796 case UNORM
: return t
->bits
[c
] == 8 ? TYPE_U8
: TYPE_U16
;
1797 case SNORM
: return t
->bits
[c
] == 8 ? TYPE_S8
: TYPE_S16
;
1799 return (t
->bits
[c
] == 8 ? TYPE_U8
:
1800 (t
->bits
[c
] == 16 ? TYPE_U16
: TYPE_U32
));
1802 return (t
->bits
[c
] == 8 ? TYPE_S8
:
1803 (t
->bits
[c
] == 16 ? TYPE_S16
: TYPE_S32
));
1809 getDestType(const ImgType type
) {
1820 assert(!"Impossible type");
1826 NVC0LoweringPass::convertSurfaceFormat(TexInstruction
*su
)
1828 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
1829 int width
= format
->bits
[0] + format
->bits
[1] +
1830 format
->bits
[2] + format
->bits
[3];
1831 Value
*untypedDst
[4] = {};
1832 Value
*typedDst
[4] = {};
1834 // We must convert this to a generic load.
1837 su
->dType
= typeOfSize(width
/ 8);
1838 su
->sType
= TYPE_U8
;
1840 for (int i
= 0; i
< width
/ 32; i
++)
1841 untypedDst
[i
] = bld
.getSSA();
1843 untypedDst
[0] = bld
.getSSA();
1845 for (int i
= 0; i
< 4; i
++) {
1846 typedDst
[i
] = su
->getDef(i
);
1849 // Set the untyped dsts as the su's destinations
1850 for (int i
= 0; i
< 4; i
++)
1851 su
->setDef(i
, untypedDst
[i
]);
1853 bld
.setPosition(su
, true);
1855 // Unpack each component into the typed dsts
1857 for (int i
= 0; i
< 4; bits
+= format
->bits
[i
], i
++) {
1860 if (i
>= format
->components
) {
1861 if (format
->type
== FLOAT
||
1862 format
->type
== UNORM
||
1863 format
->type
== SNORM
)
1864 bld
.loadImm(typedDst
[i
], i
== 3 ? 1.0f
: 0.0f
);
1866 bld
.loadImm(typedDst
[i
], i
== 3 ? 1 : 0);
1870 // Get just that component's data into the relevant place
1871 if (format
->bits
[i
] == 32)
1872 bld
.mkMov(typedDst
[i
], untypedDst
[i
]);
1873 else if (format
->bits
[i
] == 16)
1874 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1875 getSrcType(format
, i
), untypedDst
[i
/ 2])
1876 ->subOp
= (i
& 1) << (format
->type
== FLOAT
? 0 : 1);
1877 else if (format
->bits
[i
] == 8)
1878 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1879 getSrcType(format
, i
), untypedDst
[0])->subOp
= i
;
1881 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, typedDst
[i
], untypedDst
[bits
/ 32],
1882 bld
.mkImm((bits
% 32) | (format
->bits
[i
] << 8)));
1883 if (format
->type
== UNORM
|| format
->type
== SNORM
)
1884 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], getSrcType(format
, i
), typedDst
[i
]);
1887 // Normalize / convert as necessary
1888 if (format
->type
== UNORM
)
1889 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << format
->bits
[i
]) - 1)));
1890 else if (format
->type
== SNORM
)
1891 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << (format
->bits
[i
] - 1)) - 1)));
1892 else if (format
->type
== FLOAT
&& format
->bits
[i
] < 16) {
1893 bld
.mkOp2(OP_SHL
, TYPE_U32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 15 - format
->bits
[i
]));
1894 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], TYPE_F16
, typedDst
[i
]);
1900 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1902 processSurfaceCoordsNVE4(su
);
1904 if (su
->op
== OP_SULDP
)
1905 convertSurfaceFormat(su
);
1907 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
1908 // FIXME: for out of bounds access, destination value will be undefined !
1909 Value
*pred
= su
->getSrc(2);
1910 CondCode cc
= CC_NOT_P
;
1911 if (su
->getPredicate()) {
1912 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1914 if (cc
== CC_NOT_P
) {
1915 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1917 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1918 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
1921 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, su
->getDef(0));
1922 red
->subOp
= su
->subOp
;
1924 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
1925 red
->setSrc(0, gMemBase
);
1926 red
->setSrc(1, su
->getSrc(3));
1927 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1928 red
->setSrc(2, su
->getSrc(4));
1929 red
->setIndirect(0, 0, su
->getSrc(0));
1930 red
->setPredicate(cc
, pred
);
1931 delete_Instruction(bld
.getProgram(), su
);
1932 handleCasExch(red
, true);
1935 if (su
->op
== OP_SUSTB
|| su
->op
== OP_SUSTP
)
1936 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
1940 NVC0LoweringPass::handleWRSV(Instruction
*i
)
1946 // must replace, $sreg are not writeable
1947 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
1950 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
1952 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
1954 st
->perPatch
= i
->perPatch
;
1956 bld
.getBB()->remove(i
);
1961 NVC0LoweringPass::handleLDST(Instruction
*i
)
1963 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
1964 if (prog
->getType() == Program::TYPE_COMPUTE
) {
1965 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
1966 i
->getSrc(0)->reg
.fileIndex
= 0;
1968 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
1969 i
->src(0).isIndirect(0)) {
1970 // XXX: this assumes vec4 units
1971 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1972 i
->getIndirect(0, 0), bld
.mkImm(4));
1973 i
->setIndirect(0, 0, ptr
);
1977 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
1979 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
1980 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
1981 prog
->getType() == Program::TYPE_COMPUTE
) {
1982 // The launch descriptor only allows to set up 8 CBs, but OpenGL
1983 // requires at least 12 UBOs. To bypass this limitation, we store the
1984 // addrs into the driver constbuf and we directly load from the global
1986 int8_t fileIndex
= i
->getSrc(0)->reg
.fileIndex
- 1;
1987 Value
*ind
= i
->getIndirect(0, 1);
1988 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
1990 // TODO: clamp the offset to the maximum number of const buf.
1991 if (i
->src(0).isIndirect(1)) {
1992 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
1993 Value
*length
= loadUboLength32(ind
, fileIndex
* 16);
1994 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
1995 if (i
->src(0).isIndirect(0)) {
1996 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
1997 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
1999 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2000 i
->setIndirect(0, 1, NULL
);
2001 i
->setIndirect(0, 0, ptr
);
2002 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2003 i
->setPredicate(CC_NOT_P
, pred
);
2004 if (i
->defExists(0)) {
2005 bld
.mkMov(i
->getDef(0), bld
.mkImm(0));
2007 } else if (fileIndex
>= 0) {
2008 if (i
->src(0).isIndirect(0)) {
2009 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2011 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2012 i
->setIndirect(0, 1, NULL
);
2013 i
->setIndirect(0, 0, ptr
);
2015 } else if (i
->src(0).isIndirect(1)) {
2017 if (i
->src(0).isIndirect(0))
2018 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
2019 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
2020 i
->getIndirect(0, 0));
2022 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2023 i
->getIndirect(0, 1), bld
.mkImm(16));
2024 i
->setIndirect(0, 1, NULL
);
2025 i
->setIndirect(0, 0, ptr
);
2026 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
2028 } else if (i
->src(0).getFile() == FILE_SHADER_OUTPUT
) {
2029 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
2031 } else if (i
->src(0).getFile() == FILE_MEMORY_BUFFER
) {
2032 Value
*ind
= i
->getIndirect(0, 1);
2033 Value
*ptr
= loadBufInfo64(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2034 // XXX come up with a way not to do this for EVERY little access but
2035 // rather to batch these up somehow. Unfortunately we've lost the
2036 // information about the field width by the time we get here.
2037 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2038 Value
*length
= loadBufLength32(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2039 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2040 if (i
->src(0).isIndirect(0)) {
2041 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2042 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2044 i
->setIndirect(0, 1, NULL
);
2045 i
->setIndirect(0, 0, ptr
);
2046 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2047 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2048 i
->setPredicate(CC_NOT_P
, pred
);
2049 if (i
->defExists(0)) {
2050 bld
.mkMov(i
->getDef(0), bld
.mkImm(0));
2056 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
2058 Value
*laneid
= bld
.getSSA();
2061 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
2076 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
2078 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
2081 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
2082 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
2087 NVC0LoweringPass::handleRDSV(Instruction
*i
)
2089 Symbol
*sym
= i
->getSrc(0)->asSym();
2090 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
2093 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
2095 if (addr
>= 0x400) {
2097 if (sym
->reg
.data
.sv
.index
== 3) {
2098 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
2100 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
2102 if (sv
== SV_VERTEX_COUNT
) {
2103 bld
.setPosition(i
, true);
2104 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(0x808));
2111 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
2112 if (i
->srcExists(1)) {
2113 // Pass offset through to the interpolation logic
2114 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
2115 i
->getDef(0), addr
, NULL
);
2116 ld
->setSrc(1, i
->getSrc(1));
2118 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
2123 Value
*face
= i
->getDef(0);
2124 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
2125 if (i
->dType
== TYPE_F32
) {
2126 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
2127 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
2128 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
2133 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
2134 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
2139 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
2140 if (sym
->reg
.data
.sv
.index
== 3) {
2142 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
2145 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
2146 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2147 bld
.mkSymbol(FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2148 TYPE_U32
, addr
), NULL
);
2150 case SV_SAMPLE_INDEX
:
2151 // TODO: Properly pass source as an address in the PIX address space
2152 // (which can be of the form [r0+offset]). But this is currently
2154 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2155 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2157 case SV_SAMPLE_POS
: {
2158 Value
*off
= new_LValue(func
, FILE_GPR
);
2159 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2160 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2161 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
2162 bld
.mkLoad(TYPE_F32
,
2165 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2166 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
2167 4 * sym
->reg
.data
.sv
.index
),
2171 case SV_SAMPLE_MASK
:
2172 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2173 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
2176 case SV_BASEINSTANCE
:
2178 ld
= bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2179 bld
.mkSymbol(FILE_MEMORY_CONST
,
2180 prog
->driver
->io
.auxCBSlot
,
2182 prog
->driver
->io
.drawInfoBase
+
2183 4 * (sv
- SV_BASEVERTEX
)),
2187 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
&& !i
->perPatch
)
2188 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2189 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
2190 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
2191 ld
->perPatch
= i
->perPatch
;
2194 bld
.getBB()->remove(i
);
2199 NVC0LoweringPass::handleDIV(Instruction
*i
)
2201 if (!isFloatType(i
->dType
))
2203 bld
.setPosition(i
, false);
2204 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
2206 i
->setSrc(1, rcp
->getDef(0));
2211 NVC0LoweringPass::handleMOD(Instruction
*i
)
2213 if (!isFloatType(i
->dType
))
2215 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
2216 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
2217 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
2218 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
2219 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
2221 i
->setSrc(1, value
);
2226 NVC0LoweringPass::handleSQRT(Instruction
*i
)
2228 if (i
->dType
== TYPE_F64
) {
2229 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
2230 Value
*zero
= bld
.loadImm(NULL
, 0.0);
2231 Value
*dst
= bld
.getSSA(8);
2232 bld
.mkOp1(OP_RSQ
, i
->dType
, dst
, i
->getSrc(0));
2233 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
2234 bld
.mkOp3(OP_SELP
, TYPE_U64
, dst
, zero
, dst
, pred
);
2237 // TODO: Handle this properly with a library function
2239 bld
.setPosition(i
, true);
2241 bld
.mkOp1(OP_RCP
, i
->dType
, i
->getDef(0), i
->getDef(0));
2248 NVC0LoweringPass::handlePOW(Instruction
*i
)
2250 LValue
*val
= bld
.getScratch();
2252 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
2253 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
2254 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
2264 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
2266 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2267 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
2269 if (i
->src(0).isIndirect(0)) // TODO, ugly
2272 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
2273 i
->src(0).set(i
->src(1));
2275 i
->setDef(0, new_LValue(func
, FILE_GPR
));
2276 i
->getDef(0)->reg
.data
.id
= id
;
2278 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
2280 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
2281 i
->setIndirect(0, 1, gpEmitAddress
);
2287 NVC0LoweringPass::handleOUT(Instruction
*i
)
2289 Instruction
*prev
= i
->prev
;
2290 ImmediateValue stream
, prevStream
;
2292 // Only merge if the stream ids match. Also, note that the previous
2293 // instruction would have already been lowered, so we take arg1 from it.
2294 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
2295 i
->src(0).getImmediate(stream
) &&
2296 prev
->src(1).getImmediate(prevStream
) &&
2297 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
2298 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
2299 delete_Instruction(prog
, i
);
2301 assert(gpEmitAddress
);
2302 i
->setDef(0, gpEmitAddress
);
2303 i
->setSrc(1, i
->getSrc(0));
2304 i
->setSrc(0, gpEmitAddress
);
2309 // Generate a binary predicate if an instruction is predicated by
2310 // e.g. an f32 value.
2312 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
2314 Value
*pred
= insn
->getPredicate();
2317 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
2319 pdst
= new_LValue(func
, FILE_PREDICATE
);
2321 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
2322 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
2324 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
2326 insn
->setPredicate(insn
->cc
, pdst
);
2330 // - add quadop dance for texturing
2331 // - put FP outputs in GPRs
2332 // - convert instruction sequences
2335 NVC0LoweringPass::visit(Instruction
*i
)
2338 bld
.setPosition(i
, false);
2340 if (i
->cc
!= CC_ALWAYS
)
2349 return handleTEX(i
->asTex());
2351 return handleTXD(i
->asTex());
2353 return handleTXLQ(i
->asTex());
2355 return handleTXQ(i
->asTex());
2357 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
2358 i
->setSrc(0, i
->getDef(0));
2361 return handlePOW(i
);
2363 return handleDIV(i
);
2365 return handleMOD(i
);
2367 return handleSQRT(i
);
2369 ret
= handleEXPORT(i
);
2373 return handleOUT(i
);
2375 return handleRDSV(i
);
2377 return handleWRSV(i
);
2384 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_BUFFER
;
2386 handleCasExch(i
, cctl
);
2395 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2396 handleSurfaceOpNVE4(i
->asTex());
2399 handleSUQ(i
->asTex());
2408 /* Kepler+ has a special opcode to compute a new base address to be used
2409 * for indirect loads.
2411 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&& !i
->perPatch
&&
2412 (i
->op
== OP_VFETCH
|| i
->op
== OP_EXPORT
) && i
->src(0).isIndirect(0)) {
2413 Instruction
*afetch
= bld
.mkOp1(OP_AFETCH
, TYPE_U32
, bld
.getSSA(),
2414 cloneShallow(func
, i
->getSrc(0)));
2415 afetch
->setIndirect(0, 0, i
->getIndirect(0, 0));
2416 i
->src(0).get()->reg
.data
.offset
= 0;
2417 i
->setIndirect(0, 0, afetch
->getDef(0));
2424 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
2426 if (stage
== CG_STAGE_PRE_SSA
) {
2427 NVC0LoweringPass
pass(prog
);
2428 return pass
.run(prog
, false, true);
2430 if (stage
== CG_STAGE_POST_RA
) {
2431 NVC0LegalizePostRA
pass(prog
);
2432 return pass
.run(prog
, false, true);
2434 if (stage
== CG_STAGE_SSA
) {
2435 NVC0LegalizeSSA pass
;
2436 return pass
.run(prog
, false, true);
2441 } // namespace nv50_ir