2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
73 assert(i
->dType
== TYPE_F64
);
74 // There are instructions that will compute the high 32 bits of the 64-bit
75 // float. We will just stick 0 in the bottom 32 bits.
77 bld
.setPosition(i
, false);
79 // 1. Take the source and it up.
80 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
81 bld
.mkSplit(src
, 4, i
->getSrc(0));
83 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
84 dst
[0] = bld
.loadImm(NULL
, 0);
85 dst
[1] = bld
.getSSA();
87 // 3. The new version of the instruction takes the high 32 bits of the
88 // source and outputs the high 32 bits of the destination.
92 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
94 // 4. Recombine the two dst pieces back into the original destination.
95 bld
.setPosition(i
, true);
96 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
100 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
102 // Only want to flush float inputs
103 assert(i
->sType
== TYPE_F32
);
105 // If we're already flushing denorms (and NaN's) to zero, no need for this.
109 // Only certain classes of operations can flush
110 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
111 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
112 cls
!= OPCLASS_CONVERT
)
119 NVC0LegalizeSSA::visit(Function
*fn
)
121 bld
.setProgram(fn
->getProgram());
126 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
129 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
131 if (i
->sType
== TYPE_F32
) {
132 if (prog
->getType() != Program::TYPE_COMPUTE
)
143 if (i
->dType
== TYPE_F64
)
153 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
157 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
162 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
163 const Instruction
*early
) const
165 if (early
->bb
== later
->bb
)
166 return early
->serial
< later
->serial
;
167 return later
->bb
->dominatedBy(early
->bb
);
171 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
172 Instruction
*usei
, const Instruction
*texi
)
175 bool dominated
= insnDominatedBy(usei
, texi
);
176 // Uses before the tex have to all be included. Just because an earlier
177 // instruction dominates another instruction doesn't mean that there's no
178 // way to get from the tex to the later instruction. For example you could
179 // have nested loops, with the tex in the inner loop, and uses before it in
180 // both loops - even though the outer loop's instruction would dominate the
181 // inner's, we still want a texbar before the inner loop's instruction.
183 // However we can still use the eliding logic between uses dominated by the
184 // tex instruction, as that is unambiguously correct.
186 for (std::list
<TexUse
>::iterator it
= uses
.begin(); it
!= uses
.end();) {
188 if (insnDominatedBy(usei
, it
->insn
)) {
192 if (insnDominatedBy(it
->insn
, usei
)) {
201 uses
.push_back(TexUse(usei
, texi
, dominated
));
204 // While it might be tempting to use the an algorithm that just looks at tex
205 // uses, not all texture results are guaranteed to be used on all paths. In
206 // the case where along some control flow path a texture result is never used,
207 // we might reuse that register for something else, creating a
208 // write-after-write hazard. So we have to manually look through all
209 // instructions looking for ones that reference the registers in question.
211 NVC0LegalizePostRA::findFirstUses(
212 Instruction
*texi
, std::list
<TexUse
> &uses
)
214 int minGPR
= texi
->def(0).rep()->reg
.data
.id
;
215 int maxGPR
= minGPR
+ texi
->def(0).rep()->reg
.size
/ 4 - 1;
217 unordered_set
<const BasicBlock
*> visited
;
218 findFirstUsesBB(minGPR
, maxGPR
, texi
->next
, texi
, uses
, visited
);
222 NVC0LegalizePostRA::findFirstUsesBB(
223 int minGPR
, int maxGPR
, Instruction
*start
,
224 const Instruction
*texi
, std::list
<TexUse
> &uses
,
225 unordered_set
<const BasicBlock
*> &visited
)
227 const BasicBlock
*bb
= start
->bb
;
229 // We don't process the whole bb the first time around. This is correct,
230 // however we might be in a loop and hit this BB again, and need to process
231 // the full thing. So only mark a bb as visited if we processed it from the
233 if (start
== bb
->getEntry()) {
234 if (visited
.find(bb
) != visited
.end())
239 for (Instruction
*insn
= start
; insn
!= bb
->getExit(); insn
= insn
->next
) {
243 for (int d
= 0; insn
->defExists(d
); ++d
) {
244 const Value
*def
= insn
->def(d
).rep();
245 if (insn
->def(d
).getFile() != FILE_GPR
||
246 def
->reg
.data
.id
+ def
->reg
.size
/ 4 - 1 < minGPR
||
247 def
->reg
.data
.id
> maxGPR
)
249 addTexUse(uses
, insn
, texi
);
253 for (int s
= 0; insn
->srcExists(s
); ++s
) {
254 const Value
*src
= insn
->src(s
).rep();
255 if (insn
->src(s
).getFile() != FILE_GPR
||
256 src
->reg
.data
.id
+ src
->reg
.size
/ 4 - 1 < minGPR
||
257 src
->reg
.data
.id
> maxGPR
)
259 addTexUse(uses
, insn
, texi
);
264 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
265 findFirstUsesBB(minGPR
, maxGPR
, BasicBlock::get(ei
.getNode())->getEntry(),
266 texi
, uses
, visited
);
271 // This pass is a bit long and ugly and can probably be optimized.
273 // 1. obtain a list of TEXes and their outputs' first use(s)
274 // 2. calculate the barrier level of each first use (minimal number of TEXes,
275 // over all paths, between the TEX and the use in question)
276 // 3. for each barrier, if all paths from the source TEX to that barrier
277 // contain a barrier of lesser level, it can be culled
279 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
281 std::list
<TexUse
> *uses
;
282 std::vector
<Instruction
*> texes
;
283 std::vector
<int> bbFirstTex
;
284 std::vector
<int> bbFirstUse
;
285 std::vector
<int> texCounts
;
286 std::vector
<TexUse
> useVec
;
289 fn
->orderInstructions(insns
);
291 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
292 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
293 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
295 // tag BB CFG nodes by their id for later
296 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
297 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
299 bb
->cfg
.tag
= bb
->getId();
302 // gather the first uses for each TEX
303 for (int i
= 0; i
< insns
.getSize(); ++i
) {
304 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
305 if (isTextureOp(tex
->op
)) {
306 texes
.push_back(tex
);
307 if (!texCounts
.at(tex
->bb
->getId()))
308 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
309 texCounts
[tex
->bb
->getId()]++;
315 uses
= new std::list
<TexUse
>[texes
.size()];
318 for (size_t i
= 0; i
< texes
.size(); ++i
) {
319 findFirstUses(texes
[i
], uses
[i
]);
322 // determine the barrier level at each use
323 for (size_t i
= 0; i
< texes
.size(); ++i
) {
324 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
326 BasicBlock
*tb
= texes
[i
]->bb
;
327 BasicBlock
*ub
= u
->insn
->bb
;
330 for (size_t j
= i
+ 1; j
< texes
.size() &&
331 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
335 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
336 &ub
->cfg
, texCounts
);
338 WARN("Failed to find path TEX -> TEXBAR\n");
342 // this counted all TEXes in the origin block, correct that
343 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
344 // and did not count the TEXes in the destination block, add those
345 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
346 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
350 assert(u
->level
>= 0);
351 useVec
.push_back(*u
);
356 // insert the barriers
357 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
358 Instruction
*prev
= useVec
[i
].insn
->prev
;
359 if (useVec
[i
].level
< 0)
361 if (prev
&& prev
->op
== OP_TEXBAR
) {
362 if (prev
->subOp
> useVec
[i
].level
)
363 prev
->subOp
= useVec
[i
].level
;
364 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
366 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
368 bar
->subOp
= useVec
[i
].level
;
369 // make use explicit to ease latency calculation
370 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
371 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
375 if (fn
->getProgram()->optLevel
< 3)
378 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
380 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
381 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
382 limitS
.resize(fn
->allBBlocks
.getSize());
384 // cull unneeded barriers (should do that earlier, but for simplicity)
385 IteratorRef bi
= fn
->cfg
.iteratorCFG();
386 // first calculate min/max outstanding TEXes for each BB
387 for (bi
->reset(); !bi
->end(); bi
->next()) {
388 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
389 BasicBlock
*bb
= BasicBlock::get(n
);
391 int max
= std::numeric_limits
<int>::max();
392 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
393 if (isTextureOp(i
->op
)) {
395 if (max
< std::numeric_limits
<int>::max())
398 if (i
->op
== OP_TEXBAR
) {
399 min
= MIN2(min
, i
->subOp
);
400 max
= MIN2(max
, i
->subOp
);
403 // limits when looking at an isolated block
404 limitS
[bb
->getId()].min
= min
;
405 limitS
[bb
->getId()].max
= max
;
407 // propagate the min/max values
408 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
409 for (bi
->reset(); !bi
->end(); bi
->next()) {
410 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
411 BasicBlock
*bb
= BasicBlock::get(n
);
412 const int bbId
= bb
->getId();
413 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
414 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
415 const int inId
= in
->getId();
416 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
417 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
419 // I just hope this is correct ...
420 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
422 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
423 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
425 // block contained a barrier
426 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
427 limitT
[bbId
].min
+ limitS
[bbId
].min
);
428 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
429 limitT
[bbId
].max
+ limitS
[bbId
].min
);
433 // finally delete unnecessary barriers
434 for (bi
->reset(); !bi
->end(); bi
->next()) {
435 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
436 BasicBlock
*bb
= BasicBlock::get(n
);
437 Instruction
*prev
= NULL
;
439 int max
= limitT
[bb
->getId()].max
;
440 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
442 if (i
->op
== OP_TEXBAR
) {
443 if (i
->subOp
>= max
) {
444 delete_Instruction(prog
, i
);
448 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
449 delete_Instruction(prog
, prev
);
454 if (isTextureOp(i
->op
)) {
457 if (i
&& !i
->isNop())
465 NVC0LegalizePostRA::visit(Function
*fn
)
468 insertTextureBarriers(fn
);
470 rZero
= new_LValue(fn
, FILE_GPR
);
471 pOne
= new_LValue(fn
, FILE_PREDICATE
);
472 carry
= new_LValue(fn
, FILE_FLAGS
);
474 rZero
->reg
.data
.id
= (prog
->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET
) ? 255 : 63;
475 carry
->reg
.data
.id
= 0;
476 pOne
->reg
.data
.id
= 7;
482 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
484 for (int s
= 0; i
->srcExists(s
); ++s
) {
485 if (s
== 2 && i
->op
== OP_SUCLAMP
)
487 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
489 if (i
->op
== OP_SELP
&& s
== 2) {
491 if (imm
->reg
.data
.u64
== 0)
492 i
->src(s
).mod
= i
->src(s
).mod
^ Modifier(NV50_IR_MOD_NOT
);
493 } else if (imm
->reg
.data
.u64
== 0) {
500 // replace CONT with BRA for single unconditional continue
502 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
504 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
506 Graph::EdgeIterator ei
= bb
->cfg
.incident();
507 if (ei
.getType() != Graph::Edge::BACK
)
509 if (ei
.getType() != Graph::Edge::BACK
)
511 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
513 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
514 contBB
->getExit()->getPredicate())
516 contBB
->getExit()->op
= OP_BRA
;
517 bb
->remove(bb
->getEntry()); // delete PRECONT
520 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
524 // replace branches to join blocks with join ops
526 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
528 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
530 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
531 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
532 Instruction
*exit
= in
->getExit();
534 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
535 // there should always be a terminator instruction
536 WARN("inserted missing terminator in BB:%i\n", in
->getId());
538 if (exit
->op
== OP_BRA
) {
540 exit
->asFlow()->limit
= 1; // must-not-propagate marker
543 bb
->remove(bb
->getEntry());
547 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
549 Instruction
*i
, *next
;
551 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
552 for (i
= bb
->getFirst(); i
; i
= next
) {
554 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
555 if (!i
->getDef(0)->refCount())
557 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
558 i
->setSrc(0, rZero
); // initial value must be 0
564 if (i
->op
== OP_BAR
&& i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
&&
565 prog
->getType() != Program::TYPE_COMPUTE
) {
566 // It seems like barriers are never required for tessellation since
567 // the warp size is 32, and there are always at most 32 tcs threads.
570 if (i
->op
== OP_LOAD
&& i
->subOp
== NV50_IR_SUBOP_LDC_IS
) {
571 int offset
= i
->src(0).get()->reg
.data
.offset
;
572 if (abs(offset
) > 0x10000)
573 i
->src(0).get()->reg
.fileIndex
+= offset
>> 16;
574 i
->src(0).get()->reg
.data
.offset
= (int)(short)offset
;
576 // TODO: Move this to before register allocation for operations that
577 // need the $c register !
578 if (typeSizeof(i
->dType
) == 8) {
580 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
585 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
592 if (!tryReplaceContWithBra(bb
))
598 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
600 bld
.setProgram(prog
);
605 NVC0LoweringPass::visit(Function
*fn
)
607 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
608 assert(!strncmp(fn
->getName(), "MAIN", 4));
609 // TODO: when we generate actual functions pass this value along somehow
610 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
611 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
613 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
614 bld
.mkMovToReg(0, gpEmitAddress
);
621 NVC0LoweringPass::visit(BasicBlock
*bb
)
627 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
629 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
630 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
633 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(2));
636 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
639 // move array source to first slot, convert to u16, add indirections
641 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
643 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
644 const int arg
= i
->tex
.target
.getArgCount();
645 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
646 const int chipset
= prog
->getTarget()->getChipset();
648 /* Only normalize in the non-explicit derivatives case. For explicit
649 * derivatives, this is handled in handleManualTXD.
651 if (i
->tex
.target
.isCube() && i
->dPdx
[0].get() == NULL
) {
654 for (c
= 0; c
< 3; ++c
)
655 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), i
->getSrc(c
));
656 val
= bld
.getScratch();
657 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
658 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
659 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
660 for (c
= 0; c
< 3; ++c
) {
661 i
->setSrc(c
, bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(),
666 // Arguments to the TEX instruction are a little insane. Even though the
667 // encoding is identical between SM20 and SM30, the arguments mean
668 // different things between Fermi and Kepler+. A lot of arguments are
669 // optional based on flags passed to the instruction. This summarizes the
679 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
680 // - other: 4 bits each, single reg
684 // array (+ offsets for txd in upper 16 bits)
689 // offsets (same as fermi, except txd which takes it with array)
706 if (chipset
>= NVISA_GK104_CHIPSET
) {
707 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
708 // XXX this ignores tsc, and assumes a 1:1 mapping
709 assert(i
->tex
.rIndirectSrc
>= 0);
710 Value
*hnd
= loadTexHandle(i
->getIndirectR(), i
->tex
.r
);
713 i
->setIndirectR(hnd
);
714 i
->setIndirectS(NULL
);
715 } else if (i
->tex
.r
== i
->tex
.s
|| i
->op
== OP_TXF
) {
716 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
717 i
->tex
.s
= 0; // only a single cX[] value possible here
719 Value
*hnd
= bld
.getScratch();
720 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
721 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
723 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
725 i
->tex
.r
= 0; // not used for indirect tex
727 i
->setIndirectR(hnd
);
729 if (i
->tex
.target
.isArray()) {
730 LValue
*layer
= new_LValue(func
, FILE_GPR
);
731 Value
*src
= i
->getSrc(lyr
);
732 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
733 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
734 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
735 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
736 for (int s
= dim
; s
>= 1; --s
)
737 i
->setSrc(s
, i
->getSrc(s
- 1));
740 i
->setSrc(dim
, layer
);
743 // Move the indirect reference to the first place
744 if (i
->tex
.rIndirectSrc
>= 0 && (
745 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
746 Value
*hnd
= i
->getIndirectR();
748 i
->setIndirectR(NULL
);
749 i
->moveSources(0, 1);
751 i
->tex
.rIndirectSrc
= 0;
752 i
->tex
.sIndirectSrc
= -1;
755 // (nvc0) generate and move the tsc/tic/array source to the front
756 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
757 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
759 Value
*ticRel
= i
->getIndirectR();
760 Value
*tscRel
= i
->getIndirectS();
763 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
765 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
766 ticRel
, bld
.mkImm(i
->tex
.r
));
769 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
771 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
772 tscRel
, bld
.mkImm(i
->tex
.s
));
775 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
777 for (int s
= dim
; s
>= 1; --s
)
778 i
->setSrc(s
, i
->getSrc(s
- 1));
779 i
->setSrc(0, arrayIndex
);
781 i
->moveSources(0, 1);
785 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
786 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
787 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
793 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
795 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
800 // For nvc0, the sample id has to be in the second operand, as the offset
801 // does. Right now we don't know how to pass both in, and this case can't
802 // happen with OpenGL. On nve0, the sample id is part of the texture
803 // coordinate argument.
804 assert(chipset
>= NVISA_GK104_CHIPSET
||
805 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
807 // offset is between lod and dc
808 if (i
->tex
.useOffsets
) {
810 int s
= i
->srcCount(0xff, true);
811 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
812 if (i
->tex
.target
.isShadow())
814 if (i
->srcExists(s
)) // move potential predicate out of the way
815 i
->moveSources(s
, 1);
816 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
817 i
->moveSources(s
+ 1, 1);
819 if (i
->op
== OP_TXG
) {
820 // Either there is 1 offset, which goes into the 2 low bytes of the
821 // first source, or there are 4 offsets, which go into 2 sources (8
822 // values, 1 byte each).
823 Value
*offs
[2] = {NULL
, NULL
};
824 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
825 for (c
= 0; c
< 2; ++c
) {
826 if ((n
% 2) == 0 && c
== 0)
827 offs
[n
/ 2] = i
->offset
[n
][c
].get();
829 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
831 i
->offset
[n
][c
].get(),
832 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
836 i
->setSrc(s
, offs
[0]);
838 i
->setSrc(s
+ 1, offs
[1]);
841 assert(i
->tex
.useOffsets
== 1);
842 for (c
= 0; c
< 3; ++c
) {
844 if (!i
->offset
[0][c
].getImmediate(val
))
845 assert(!"non-immediate offset passed to non-TXG");
846 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
848 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
849 // The offset goes into the upper 16 bits of the array index. So
850 // create it if it's not already there, and INSBF it if it already
852 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
853 if (chipset
>= NVISA_GM107_CHIPSET
)
855 if (i
->tex
.target
.isArray()) {
856 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
857 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
860 i
->moveSources(s
, 1);
861 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
864 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
869 if (chipset
>= NVISA_GK104_CHIPSET
) {
871 // If TEX requires more than 4 sources, the 2nd register tuple must be
872 // aligned to 4, even if it consists of just a single 4-byte register.
874 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
876 int s
= i
->srcCount(0xff, true);
877 if (s
> 4 && s
< 7) {
878 if (i
->srcExists(s
)) // move potential predicate out of the way
879 i
->moveSources(s
, 7 - s
);
881 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
889 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
891 static const uint8_t qOps
[4][2] =
893 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
894 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
895 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
896 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
901 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
903 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
905 // This function is invoked after handleTEX lowering, so we have to expect
906 // the arguments in the order that the hw wants them. For Fermi, array and
907 // indirect are both in the leading arg, while for Kepler, array and
908 // indirect are separate (and both precede the coordinates). Maxwell is
909 // handled in a separate function.
911 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
912 array
= i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0;
914 array
= i
->tex
.target
.isArray() + (i
->tex
.rIndirectSrc
>= 0);
916 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
918 for (c
= 0; c
< dim
; ++c
)
919 crd
[c
] = bld
.getScratch();
921 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
922 for (l
= 0; l
< 4; ++l
) {
924 // mov coordinates from lane l to all lanes
925 for (c
= 0; c
< dim
; ++c
)
926 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
927 // add dPdx from lane l to lanes dx
928 for (c
= 0; c
< dim
; ++c
)
929 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
930 // add dPdy from lane l to lanes dy
931 for (c
= 0; c
< dim
; ++c
)
932 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
933 // normalize cube coordinates
934 if (i
->tex
.target
.isCube()) {
935 for (c
= 0; c
< 3; ++c
)
936 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), crd
[c
]);
937 val
= bld
.getScratch();
938 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
939 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
940 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
941 for (c
= 0; c
< 3; ++c
)
942 src
[c
] = bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(), crd
[c
], val
);
944 for (c
= 0; c
< dim
; ++c
)
948 bld
.insert(tex
= cloneForward(func
, i
));
949 for (c
= 0; c
< dim
; ++c
)
950 tex
->setSrc(c
+ array
, src
[c
]);
952 for (c
= 0; i
->defExists(c
); ++c
) {
954 def
[c
][l
] = bld
.getSSA();
955 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
960 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
962 for (c
= 0; i
->defExists(c
); ++c
) {
963 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
964 for (l
= 0; l
< 4; ++l
)
965 u
->setSrc(l
, def
[c
][l
]);
973 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
975 int dim
= txd
->tex
.target
.getDim() + txd
->tex
.target
.isCube();
976 unsigned arg
= txd
->tex
.target
.getArgCount();
977 unsigned expected_args
= arg
;
978 const int chipset
= prog
->getTarget()->getChipset();
980 if (chipset
>= NVISA_GK104_CHIPSET
) {
981 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
983 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
986 if (txd
->tex
.useOffsets
)
988 if (!txd
->tex
.target
.isArray() && (
989 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
993 if (expected_args
> 4 ||
995 txd
->tex
.target
.isShadow())
999 while (txd
->srcExists(arg
))
1002 txd
->tex
.derivAll
= true;
1003 if (txd
->op
== OP_TEX
)
1004 return handleManualTXD(txd
);
1006 assert(arg
== expected_args
);
1007 for (int c
= 0; c
< dim
; ++c
) {
1008 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
1009 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
1010 txd
->dPdx
[c
].set(NULL
);
1011 txd
->dPdy
[c
].set(NULL
);
1014 // In this case we have fewer than 4 "real" arguments, which means that
1015 // handleTEX didn't apply any padding. However we have to make sure that
1016 // the second "group" of arguments still gets padded up to 4.
1017 if (chipset
>= NVISA_GK104_CHIPSET
) {
1018 int s
= arg
+ 2 * dim
;
1019 if (s
>= 4 && s
< 7) {
1020 if (txd
->srcExists(s
)) // move potential predicate out of the way
1021 txd
->moveSources(s
, 7 - s
);
1023 txd
->setSrc(s
++, bld
.loadImm(NULL
, 0));
1031 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
1033 const int chipset
= prog
->getTarget()->getChipset();
1034 if (chipset
>= NVISA_GK104_CHIPSET
&& txq
->tex
.rIndirectSrc
< 0)
1035 txq
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
1037 if (txq
->tex
.rIndirectSrc
< 0)
1040 Value
*ticRel
= txq
->getIndirectR();
1042 txq
->setIndirectS(NULL
);
1043 txq
->tex
.sIndirectSrc
= -1;
1047 if (chipset
< NVISA_GK104_CHIPSET
) {
1048 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
1050 txq
->setSrc(txq
->tex
.rIndirectSrc
, NULL
);
1052 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
1053 ticRel
, bld
.mkImm(txq
->tex
.r
));
1055 bld
.mkOp2(OP_SHL
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x17));
1057 txq
->moveSources(0, 1);
1058 txq
->setSrc(0, src
);
1060 Value
*hnd
= loadTexHandle(txq
->getIndirectR(), txq
->tex
.r
);
1064 txq
->setIndirectR(NULL
);
1065 txq
->moveSources(0, 1);
1066 txq
->setSrc(0, hnd
);
1067 txq
->tex
.rIndirectSrc
= 0;
1074 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
1076 /* The outputs are inverted compared to what the TGSI instruction
1077 * expects. Take that into account in the mask.
1079 assert((i
->tex
.mask
& ~3) == 0);
1080 if (i
->tex
.mask
== 1)
1082 else if (i
->tex
.mask
== 2)
1085 bld
.setPosition(i
, true);
1087 /* The returned values are not quite what we want:
1088 * (a) convert from s16/u16 to f32
1089 * (b) multiply by 1/256
1091 for (int def
= 0; def
< 2; ++def
) {
1092 if (!i
->defExists(def
))
1094 enum DataType type
= TYPE_S16
;
1095 if (i
->tex
.mask
== 2 || def
> 0)
1097 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
1098 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
1099 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
1101 if (i
->tex
.mask
== 3) {
1102 LValue
*t
= new_LValue(func
, FILE_GPR
);
1103 bld
.mkMov(t
, i
->getDef(0));
1104 bld
.mkMov(i
->getDef(0), i
->getDef(1));
1105 bld
.mkMov(i
->getDef(1), t
);
1111 NVC0LoweringPass::handleBUFQ(Instruction
*bufq
)
1114 bufq
->setSrc(0, loadBufLength32(bufq
->getIndirect(0, 1),
1115 bufq
->getSrc(0)->reg
.fileIndex
* 16));
1116 bufq
->setIndirect(0, 0, NULL
);
1117 bufq
->setIndirect(0, 1, NULL
);
1122 NVC0LoweringPass::handleSharedATOMNVE4(Instruction
*atom
)
1124 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1126 BasicBlock
*currBB
= atom
->bb
;
1127 BasicBlock
*tryLockBB
= atom
->bb
->splitBefore(atom
, false);
1128 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1129 BasicBlock
*setAndUnlockBB
= new BasicBlock(func
);
1130 BasicBlock
*failLockBB
= new BasicBlock(func
);
1132 bld
.setPosition(currBB
, true);
1133 assert(!currBB
->joinAt
);
1134 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1136 CmpInstruction
*pred
=
1137 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1138 TYPE_U32
, bld
.mkImm(0), bld
.mkImm(1));
1140 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_ALWAYS
, NULL
);
1141 currBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::TREE
);
1143 bld
.setPosition(tryLockBB
, true);
1146 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1147 atom
->getIndirect(0, 0));
1148 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1149 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1151 bld
.mkFlow(OP_BRA
, setAndUnlockBB
, CC_P
, ld
->getDef(1));
1152 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1153 tryLockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::CROSS
);
1154 tryLockBB
->cfg
.attach(&setAndUnlockBB
->cfg
, Graph::Edge::TREE
);
1156 tryLockBB
->cfg
.detach(&joinBB
->cfg
);
1159 bld
.setPosition(setAndUnlockBB
, true);
1161 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1162 // Read the old value, and write the new one.
1163 stVal
= atom
->getSrc(1);
1164 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1165 CmpInstruction
*set
=
1166 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(),
1167 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1169 bld
.mkCmp(OP_SLCT
, CC_NE
, TYPE_U32
, (stVal
= bld
.getSSA()),
1170 TYPE_U32
, atom
->getSrc(2), ld
->getDef(0), set
->getDef(0));
1174 switch (atom
->subOp
) {
1175 case NV50_IR_SUBOP_ATOM_ADD
:
1178 case NV50_IR_SUBOP_ATOM_AND
:
1181 case NV50_IR_SUBOP_ATOM_OR
:
1184 case NV50_IR_SUBOP_ATOM_XOR
:
1187 case NV50_IR_SUBOP_ATOM_MIN
:
1190 case NV50_IR_SUBOP_ATOM_MAX
:
1198 stVal
= bld
.mkOp2v(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1203 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1204 atom
->getIndirect(0, 0), stVal
);
1205 st
->setDef(0, pred
->getDef(0));
1206 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1208 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1209 setAndUnlockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::TREE
);
1211 // Lock until the store has not been performed.
1212 bld
.setPosition(failLockBB
, true);
1213 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_NOT_P
, pred
->getDef(0));
1214 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1215 failLockBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::BACK
);
1216 failLockBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::TREE
);
1218 bld
.setPosition(joinBB
, false);
1219 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1223 NVC0LoweringPass::handleSharedATOM(Instruction
*atom
)
1225 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1227 BasicBlock
*currBB
= atom
->bb
;
1228 BasicBlock
*tryLockAndSetBB
= atom
->bb
->splitBefore(atom
, false);
1229 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1231 bld
.setPosition(currBB
, true);
1232 assert(!currBB
->joinAt
);
1233 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1235 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_ALWAYS
, NULL
);
1236 currBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::TREE
);
1238 bld
.setPosition(tryLockAndSetBB
, true);
1241 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1242 atom
->getIndirect(0, 0));
1243 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1244 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1247 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1248 // Read the old value, and write the new one.
1249 stVal
= atom
->getSrc(1);
1250 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1251 CmpInstruction
*set
=
1252 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1253 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1254 set
->setPredicate(CC_P
, ld
->getDef(1));
1257 bld
.mkOp3(OP_SELP
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
1258 atom
->getSrc(2), set
->getDef(0));
1259 selp
->src(2).mod
= Modifier(NV50_IR_MOD_NOT
);
1260 selp
->setPredicate(CC_P
, ld
->getDef(1));
1262 stVal
= selp
->getDef(0);
1266 switch (atom
->subOp
) {
1267 case NV50_IR_SUBOP_ATOM_ADD
:
1270 case NV50_IR_SUBOP_ATOM_AND
:
1273 case NV50_IR_SUBOP_ATOM_OR
:
1276 case NV50_IR_SUBOP_ATOM_XOR
:
1279 case NV50_IR_SUBOP_ATOM_MIN
:
1282 case NV50_IR_SUBOP_ATOM_MAX
:
1291 bld
.mkOp2(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1293 i
->setPredicate(CC_P
, ld
->getDef(1));
1295 stVal
= i
->getDef(0);
1299 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1300 atom
->getIndirect(0, 0), stVal
);
1301 st
->setPredicate(CC_P
, ld
->getDef(1));
1302 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1304 // Loop until the lock is acquired.
1305 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_NOT_P
, ld
->getDef(1));
1306 tryLockAndSetBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::BACK
);
1307 tryLockAndSetBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::CROSS
);
1308 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1312 bld
.setPosition(joinBB
, false);
1313 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1317 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1320 Value
*ptr
= atom
->getIndirect(0, 0), *ind
= atom
->getIndirect(0, 1), *base
;
1322 switch (atom
->src(0).getFile()) {
1323 case FILE_MEMORY_LOCAL
:
1326 case FILE_MEMORY_SHARED
:
1327 // For Fermi/Kepler, we have to use ld lock/st unlock to perform atomic
1328 // operations on shared memory. For Maxwell, ATOMS is enough.
1329 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
1330 handleSharedATOM(atom
);
1331 else if (targ
->getChipset() < NVISA_GM107_CHIPSET
)
1332 handleSharedATOMNVE4(atom
);
1335 assert(atom
->src(0).getFile() == FILE_MEMORY_BUFFER
);
1336 base
= loadBufInfo64(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1337 assert(base
->reg
.size
== 8);
1339 base
= bld
.mkOp2v(OP_ADD
, TYPE_U64
, base
, base
, ptr
);
1340 assert(base
->reg
.size
== 8);
1341 atom
->setIndirect(0, 0, base
);
1342 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1344 // Harden against out-of-bounds accesses
1345 Value
*offset
= bld
.loadImm(NULL
, atom
->getSrc(0)->reg
.data
.offset
+ typeSizeof(atom
->sType
));
1346 Value
*length
= loadBufLength32(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1347 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
1349 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, ptr
);
1350 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
1351 atom
->setPredicate(CC_NOT_P
, pred
);
1352 if (atom
->defExists(0)) {
1353 Value
*zero
, *dst
= atom
->getDef(0);
1354 atom
->setDef(0, bld
.getSSA());
1356 bld
.setPosition(atom
, true);
1357 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
1358 ->setPredicate(CC_P
, pred
);
1359 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, atom
->getDef(0), zero
);
1365 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1367 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1368 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1370 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1371 atom
->setIndirect(0, 1, NULL
);
1372 atom
->setIndirect(0, 0, base
);
1378 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1380 if (targ
->getChipset() < NVISA_GM107_CHIPSET
) {
1381 if (cas
->src(0).getFile() == FILE_MEMORY_SHARED
) {
1382 // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
1387 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1388 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1390 bld
.setPosition(cas
, true);
1393 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1394 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1396 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1397 if (cas
->isPredicated())
1398 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1401 if (cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1402 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1403 // should be set to the high part of the double reg or bad things will
1404 // happen elsewhere in the universe.
1405 // Also, it sometimes returns the new value instead of the old one
1406 // under mysterious circumstances.
1407 Value
*dreg
= bld
.getSSA(8);
1408 bld
.setPosition(cas
, false);
1409 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1410 cas
->setSrc(1, dreg
);
1411 cas
->setSrc(2, dreg
);
1418 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
, uint16_t base
)
1420 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1424 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1428 NVC0LoweringPass::loadResInfo64(Value
*ptr
, uint32_t off
, uint16_t base
)
1430 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1434 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1437 mkLoadv(TYPE_U64
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
), ptr
);
1441 NVC0LoweringPass::loadResLength32(Value
*ptr
, uint32_t off
, uint16_t base
)
1443 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1447 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1450 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
+ 8), ptr
);
1454 NVC0LoweringPass::loadBufInfo64(Value
*ptr
, uint32_t off
)
1456 return loadResInfo64(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1460 NVC0LoweringPass::loadBufLength32(Value
*ptr
, uint32_t off
)
1462 return loadResLength32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1466 NVC0LoweringPass::loadUboInfo64(Value
*ptr
, uint32_t off
)
1468 return loadResInfo64(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1472 NVC0LoweringPass::loadUboLength32(Value
*ptr
, uint32_t off
)
1474 return loadResLength32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1478 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1480 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1481 off
+= prog
->driver
->io
.msInfoBase
;
1483 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1486 /* On nvc0, surface info is obtained via the surface binding points passed
1487 * to the SULD/SUST instructions.
1488 * On nve4, surface info is stored in c[] and is used by various special
1489 * instructions, e.g. for clamping coordinates or generating an address.
1490 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1492 #define NVC0_SU_INFO_ADDR 0x00
1493 #define NVC0_SU_INFO_FMT 0x04
1494 #define NVC0_SU_INFO_DIM_X 0x08
1495 #define NVC0_SU_INFO_PITCH 0x0c
1496 #define NVC0_SU_INFO_DIM_Y 0x10
1497 #define NVC0_SU_INFO_ARRAY 0x14
1498 #define NVC0_SU_INFO_DIM_Z 0x18
1499 #define NVC0_SU_INFO_UNK1C 0x1c
1500 #define NVC0_SU_INFO_WIDTH 0x20
1501 #define NVC0_SU_INFO_HEIGHT 0x24
1502 #define NVC0_SU_INFO_DEPTH 0x28
1503 #define NVC0_SU_INFO_TARGET 0x2c
1504 #define NVC0_SU_INFO_BSIZE 0x30
1505 #define NVC0_SU_INFO_RAW_X 0x34
1506 #define NVC0_SU_INFO_MS_X 0x38
1507 #define NVC0_SU_INFO_MS_Y 0x3c
1509 #define NVC0_SU_INFO__STRIDE 0x40
1511 #define NVC0_SU_INFO_DIM(i) (0x08 + (i) * 8)
1512 #define NVC0_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1513 #define NVC0_SU_INFO_MS(i) (0x38 + (i) * 4)
1516 NVC0LoweringPass::loadSuInfo32(Value
*ptr
, int slot
, uint32_t off
)
1518 uint32_t base
= slot
* NVC0_SU_INFO__STRIDE
;
1521 ptr
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(slot
));
1522 ptr
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(7));
1523 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(6));
1528 return loadResInfo32(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1531 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1533 switch (su
->tex
.target
.getEnum()) {
1534 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1535 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1536 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1537 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1538 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1539 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1540 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1541 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1542 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1543 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1544 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1545 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1546 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1554 NVC0LoweringPass::handleSUQ(TexInstruction
*suq
)
1556 int mask
= suq
->tex
.mask
;
1557 int dim
= suq
->tex
.target
.getDim();
1558 int arg
= dim
+ (suq
->tex
.target
.isArray() || suq
->tex
.target
.isCube());
1559 Value
*ind
= suq
->getIndirectR();
1560 int slot
= suq
->tex
.r
;
1563 for (c
= 0, d
= 0; c
< 3; ++c
, mask
>>= 1) {
1564 if (c
>= arg
|| !(mask
& 1))
1569 if (c
== 1 && suq
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1570 offset
= NVC0_SU_INFO_SIZE(2);
1572 offset
= NVC0_SU_INFO_SIZE(c
);
1574 bld
.mkMov(suq
->getDef(d
++), loadSuInfo32(ind
, slot
, offset
));
1575 if (c
== 2 && suq
->tex
.target
.isCube())
1576 bld
.mkOp2(OP_DIV
, TYPE_U32
, suq
->getDef(d
- 1), suq
->getDef(d
- 1),
1577 bld
.loadImm(NULL
, 6));
1581 if (suq
->tex
.target
.isMS()) {
1582 Value
*ms_x
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(0));
1583 Value
*ms_y
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(1));
1584 Value
*ms
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(), ms_x
, ms_y
);
1585 bld
.mkOp2(OP_SHL
, TYPE_U32
, suq
->getDef(d
++), bld
.loadImm(NULL
, 1), ms
);
1587 bld
.mkMov(suq
->getDef(d
++), bld
.loadImm(NULL
, 1));
1596 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1598 const int arg
= tex
->tex
.target
.getArgCount();
1599 int slot
= tex
->tex
.r
;
1601 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1602 tex
->tex
.target
= TEX_TARGET_2D
;
1604 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1605 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1609 Value
*x
= tex
->getSrc(0);
1610 Value
*y
= tex
->getSrc(1);
1611 Value
*s
= tex
->getSrc(arg
- 1);
1613 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1614 Value
*ind
= tex
->getIndirectR();
1616 Value
*ms_x
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(0));
1617 Value
*ms_y
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(1));
1619 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1620 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1622 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1623 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1625 Value
*dx
= loadMsInfo32(ts
, 0x0);
1626 Value
*dy
= loadMsInfo32(ts
, 0x4);
1628 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1629 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1633 tex
->moveSources(arg
, -1);
1636 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1637 // They're computed from the coordinates using the surface info in c[] space.
1639 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1642 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1644 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1645 const int slot
= su
->tex
.r
;
1646 const int dim
= su
->tex
.target
.getDim();
1647 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
1649 Value
*zero
= bld
.mkImm(0);
1653 Value
*bf
, *eau
, *off
;
1655 Value
*ind
= su
->getIndirectR();
1657 off
= bld
.getScratch(4);
1658 bf
= bld
.getScratch(4);
1659 addr
= bld
.getSSA(8);
1660 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1662 bld
.setPosition(su
, false);
1664 adjustCoordinatesMS(su
);
1666 // calculate clamped coordinates
1667 for (c
= 0; c
< arg
; ++c
) {
1670 if (c
== 1 && su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1671 // The array index is stored in the Z component for 1D arrays.
1675 src
[c
] = bld
.getScratch();
1677 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_RAW_X
);
1679 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_DIM(dimc
));
1680 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1681 ->subOp
= getSuClampSubOp(su
, dimc
);
1686 // set predicate output
1687 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1688 src
[0]->getInsn()->setFlagsDef(1, pred
);
1690 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1691 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1692 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1695 // calculate pixel offset
1697 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1698 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1701 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_UNK1C
);
1702 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1703 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1705 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_PITCH
);
1706 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1707 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1710 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_PITCH
);
1711 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1712 ->subOp
= (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) ?
1713 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1716 // calculate effective address part 1
1717 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1721 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_FMT
);
1722 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1723 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1737 if (!su
->tex
.target
.isArray() && !su
->tex
.target
.isCube()) {
1738 z
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_UNK1C
);
1739 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1743 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1747 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1748 insn
->subOp
= subOp
;
1749 insn
->setFlagsDef(1, pred
);
1753 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
);
1755 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1758 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1760 // add array layer offset
1761 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1762 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ARRAY
);
1764 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1765 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1767 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1768 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1769 // combine predicates
1771 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1776 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1780 // bf == g[] address & 0xff
1781 // eau == g[] address >> 8
1782 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1783 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1785 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1786 // Convert from u32 to u8 address format, which is what the library code
1787 // doing SULDP currently uses.
1788 // XXX: can SUEAU do this ?
1789 // XXX: does it matter that we don't mask high bytes in bf ?
1791 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1792 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1795 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1797 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1798 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1800 // let's just set it 0 for raw access and hope it works
1802 bld
.mkImm(0) : loadSuInfo32(ind
, slot
, NVC0_SU_INFO_FMT
);
1804 // get rid of old coordinate sources, make space for fmt info and predicate
1805 su
->moveSources(arg
, 3 - arg
);
1806 // set 64 bit address and 32-bit format sources
1807 su
->setSrc(0, addr
);
1809 su
->setSrc(2, pred
);
1811 // prevent read fault when the image is not actually bound
1812 CmpInstruction
*pred1
=
1813 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1814 TYPE_U32
, bld
.mkImm(0),
1815 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
));
1817 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
1818 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
1819 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
1820 format
->bits
[2] + format
->bits
[3];
1822 // make sure that the format doesn't mismatch
1823 assert(format
->components
!= 0);
1824 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred1
->getDef(0),
1825 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
1826 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
),
1829 su
->setPredicate(CC_NOT_P
, pred1
->getDef(0));
1831 // TODO: initialize def values to 0 when the surface operation is not
1832 // performed (not needed for stores). Also, fix the "address bounds test"
1833 // subtests from arb_shader_image_load_store-invalid for buffers, because it
1834 // seems like that the predicate is not correctly set by suclamp.
1838 getSrcType(const TexInstruction::ImgFormatDesc
*t
, int c
)
1841 case FLOAT
: return t
->bits
[c
] == 16 ? TYPE_F16
: TYPE_F32
;
1842 case UNORM
: return t
->bits
[c
] == 8 ? TYPE_U8
: TYPE_U16
;
1843 case SNORM
: return t
->bits
[c
] == 8 ? TYPE_S8
: TYPE_S16
;
1845 return (t
->bits
[c
] == 8 ? TYPE_U8
:
1846 (t
->bits
[c
] == 16 ? TYPE_U16
: TYPE_U32
));
1848 return (t
->bits
[c
] == 8 ? TYPE_S8
:
1849 (t
->bits
[c
] == 16 ? TYPE_S16
: TYPE_S32
));
1855 getDestType(const ImgType type
) {
1866 assert(!"Impossible type");
1872 NVC0LoweringPass::convertSurfaceFormat(TexInstruction
*su
)
1874 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
1875 int width
= format
->bits
[0] + format
->bits
[1] +
1876 format
->bits
[2] + format
->bits
[3];
1877 Value
*untypedDst
[4] = {};
1878 Value
*typedDst
[4] = {};
1880 // We must convert this to a generic load.
1883 su
->dType
= typeOfSize(width
/ 8);
1884 su
->sType
= TYPE_U8
;
1886 for (int i
= 0; i
< width
/ 32; i
++)
1887 untypedDst
[i
] = bld
.getSSA();
1889 untypedDst
[0] = bld
.getSSA();
1891 for (int i
= 0; i
< 4; i
++) {
1892 typedDst
[i
] = su
->getDef(i
);
1895 // Set the untyped dsts as the su's destinations
1896 for (int i
= 0; i
< 4; i
++)
1897 su
->setDef(i
, untypedDst
[i
]);
1899 bld
.setPosition(su
, true);
1901 // Unpack each component into the typed dsts
1903 for (int i
= 0; i
< 4; bits
+= format
->bits
[i
], i
++) {
1906 if (i
>= format
->components
) {
1907 if (format
->type
== FLOAT
||
1908 format
->type
== UNORM
||
1909 format
->type
== SNORM
)
1910 bld
.loadImm(typedDst
[i
], i
== 3 ? 1.0f
: 0.0f
);
1912 bld
.loadImm(typedDst
[i
], i
== 3 ? 1 : 0);
1916 // Get just that component's data into the relevant place
1917 if (format
->bits
[i
] == 32)
1918 bld
.mkMov(typedDst
[i
], untypedDst
[i
]);
1919 else if (format
->bits
[i
] == 16)
1920 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1921 getSrcType(format
, i
), untypedDst
[i
/ 2])
1922 ->subOp
= (i
& 1) << (format
->type
== FLOAT
? 0 : 1);
1923 else if (format
->bits
[i
] == 8)
1924 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1925 getSrcType(format
, i
), untypedDst
[0])->subOp
= i
;
1927 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, typedDst
[i
], untypedDst
[bits
/ 32],
1928 bld
.mkImm((bits
% 32) | (format
->bits
[i
] << 8)));
1929 if (format
->type
== UNORM
|| format
->type
== SNORM
)
1930 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], getSrcType(format
, i
), typedDst
[i
]);
1933 // Normalize / convert as necessary
1934 if (format
->type
== UNORM
)
1935 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << format
->bits
[i
]) - 1)));
1936 else if (format
->type
== SNORM
)
1937 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << (format
->bits
[i
] - 1)) - 1)));
1938 else if (format
->type
== FLOAT
&& format
->bits
[i
] < 16) {
1939 bld
.mkOp2(OP_SHL
, TYPE_U32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 15 - format
->bits
[i
]));
1940 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], TYPE_F16
, typedDst
[i
]);
1945 std::swap(typedDst
[0], typedDst
[2]);
1950 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1952 processSurfaceCoordsNVE4(su
);
1954 if (su
->op
== OP_SULDP
)
1955 convertSurfaceFormat(su
);
1957 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
1958 Value
*pred
= su
->getSrc(2);
1959 CondCode cc
= CC_NOT_P
;
1960 if (su
->getPredicate()) {
1961 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1963 if (cc
== CC_NOT_P
) {
1964 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1966 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1967 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
1970 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, bld
.getSSA());
1971 red
->subOp
= su
->subOp
;
1973 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
1974 red
->setSrc(0, gMemBase
);
1975 red
->setSrc(1, su
->getSrc(3));
1976 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1977 red
->setSrc(2, su
->getSrc(4));
1978 red
->setIndirect(0, 0, su
->getSrc(0));
1980 // make sure to initialize dst value when the atomic operation is not
1982 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
1984 assert(cc
== CC_NOT_P
);
1985 red
->setPredicate(cc
, pred
);
1986 mov
->setPredicate(CC_P
, pred
);
1988 bld
.mkOp2(OP_UNION
, TYPE_U32
, su
->getDef(0),
1989 red
->getDef(0), mov
->getDef(0));
1991 delete_Instruction(bld
.getProgram(), su
);
1992 handleCasExch(red
, true);
1995 if (su
->op
== OP_SUSTB
|| su
->op
== OP_SUSTP
)
1996 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
2000 NVC0LoweringPass::processSurfaceCoordsNVC0(TexInstruction
*su
)
2002 const int slot
= su
->tex
.r
;
2003 const int dim
= su
->tex
.target
.getDim();
2004 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2006 Value
*zero
= bld
.mkImm(0);
2009 Value
*ind
= su
->getIndirectR();
2011 bld
.setPosition(su
, false);
2013 adjustCoordinatesMS(su
);
2017 ptr
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(su
->tex
.r
));
2018 ptr
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(7));
2019 su
->setIndirectR(ptr
);
2022 // get surface coordinates
2023 for (c
= 0; c
< arg
; ++c
)
2024 src
[c
] = su
->getSrc(c
);
2028 // calculate pixel offset
2029 if (su
->op
== OP_SULDP
|| su
->op
== OP_SUREDP
) {
2030 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
);
2031 su
->setSrc(0, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[0], v
));
2034 // add array layer offset
2035 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
2036 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ARRAY
);
2038 su
->setSrc(2, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[2], v
));
2041 // prevent read fault when the image is not actually bound
2042 CmpInstruction
*pred
=
2043 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2044 TYPE_U32
, bld
.mkImm(0),
2045 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
));
2046 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2047 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2048 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2049 format
->bits
[2] + format
->bits
[3];
2051 assert(format
->components
!= 0);
2052 // make sure that the format doesn't mismatch when it's not FMT_NONE
2053 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred
->getDef(0),
2054 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2055 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
),
2058 su
->setPredicate(CC_NOT_P
, pred
->getDef(0));
2062 NVC0LoweringPass::handleSurfaceOpNVC0(TexInstruction
*su
)
2064 if (su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
2065 /* As 1d arrays also need 3 coordinates, switching to TEX_TARGET_2D_ARRAY
2066 * will simplify the lowering pass and the texture constraints. */
2067 su
->moveSources(1, 1);
2068 su
->setSrc(1, bld
.loadImm(NULL
, 0));
2069 su
->tex
.target
= TEX_TARGET_2D_ARRAY
;
2072 processSurfaceCoordsNVC0(su
);
2074 if (su
->op
== OP_SULDP
)
2075 convertSurfaceFormat(su
);
2077 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
2078 const int dim
= su
->tex
.target
.getDim();
2079 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2080 LValue
*addr
= bld
.getSSA(8);
2081 Value
*def
= su
->getDef(0);
2085 // Set the destination to the address
2086 su
->dType
= TYPE_U64
;
2087 su
->setDef(0, addr
);
2088 su
->setDef(1, su
->getPredicate());
2090 bld
.setPosition(su
, true);
2092 // Perform the atomic op
2093 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->sType
, bld
.getSSA());
2094 red
->subOp
= su
->subOp
;
2095 red
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, su
->sType
, 0));
2096 red
->setSrc(1, su
->getSrc(arg
));
2097 if (red
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2098 red
->setSrc(2, su
->getSrc(arg
+ 1));
2099 red
->setIndirect(0, 0, addr
);
2101 // make sure to initialize dst value when the atomic operation is not
2103 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2105 assert(su
->cc
== CC_NOT_P
);
2106 red
->setPredicate(su
->cc
, su
->getPredicate());
2107 mov
->setPredicate(CC_P
, su
->getPredicate());
2109 bld
.mkOp2(OP_UNION
, TYPE_U32
, def
, red
->getDef(0), mov
->getDef(0));
2111 handleCasExch(red
, false);
2116 NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction
*su
)
2118 const int slot
= su
->tex
.r
;
2119 const int dim
= su
->tex
.target
.getDim();
2120 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2121 Value
*ind
= su
->getIndirectR();
2124 bld
.setPosition(su
, false);
2126 // add texture handle
2132 pos
= (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) ? 2 : 1;
2138 su
->setSrc(arg
+ pos
, loadTexHandle(ind
, slot
+ 32));
2140 // prevent read fault when the image is not actually bound
2141 CmpInstruction
*pred
=
2142 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2143 TYPE_U32
, bld
.mkImm(0),
2144 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
));
2145 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2146 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2147 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2148 format
->bits
[2] + format
->bits
[3];
2150 assert(format
->components
!= 0);
2151 // make sure that the format doesn't mismatch when it's not FMT_NONE
2152 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred
->getDef(0),
2153 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2154 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
),
2157 su
->setPredicate(CC_NOT_P
, pred
->getDef(0));
2161 NVC0LoweringPass::handleSurfaceOpGM107(TexInstruction
*su
)
2163 processSurfaceCoordsGM107(su
);
2165 if (su
->op
== OP_SULDP
)
2166 convertSurfaceFormat(su
);
2168 if (su
->op
== OP_SUREDP
) {
2169 Value
*def
= su
->getDef(0);
2172 su
->setDef(0, bld
.getSSA());
2174 bld
.setPosition(su
, true);
2176 // make sure to initialize dst value when the atomic operation is not
2178 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2180 assert(su
->cc
== CC_NOT_P
);
2181 mov
->setPredicate(CC_P
, su
->getPredicate());
2183 bld
.mkOp2(OP_UNION
, TYPE_U32
, def
, su
->getDef(0), mov
->getDef(0));
2188 NVC0LoweringPass::handleWRSV(Instruction
*i
)
2194 // must replace, $sreg are not writeable
2195 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
2198 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
2200 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
2202 st
->perPatch
= i
->perPatch
;
2204 bld
.getBB()->remove(i
);
2209 NVC0LoweringPass::handleLDST(Instruction
*i
)
2211 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
2212 if (prog
->getType() == Program::TYPE_COMPUTE
) {
2213 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
2214 i
->getSrc(0)->reg
.fileIndex
= 0;
2216 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
2217 i
->src(0).isIndirect(0)) {
2218 // XXX: this assumes vec4 units
2219 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2220 i
->getIndirect(0, 0), bld
.mkImm(4));
2221 i
->setIndirect(0, 0, ptr
);
2225 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
2227 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
2228 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
2229 prog
->getType() == Program::TYPE_COMPUTE
) {
2230 // The launch descriptor only allows to set up 8 CBs, but OpenGL
2231 // requires at least 12 UBOs. To bypass this limitation, we store the
2232 // addrs into the driver constbuf and we directly load from the global
2234 int8_t fileIndex
= i
->getSrc(0)->reg
.fileIndex
- 1;
2235 Value
*ind
= i
->getIndirect(0, 1);
2238 // Clamp the UBO index when an indirect access is used to avoid
2239 // loading information from the wrong place in the driver cb.
2240 ind
= bld
.mkOp2v(OP_MIN
, TYPE_U32
, ind
,
2241 bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(),
2242 ind
, bld
.loadImm(NULL
, fileIndex
)),
2243 bld
.loadImm(NULL
, 12));
2246 if (i
->src(0).isIndirect(1)) {
2247 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2248 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
2249 Value
*length
= loadUboLength32(ind
, fileIndex
* 16);
2250 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2251 if (i
->src(0).isIndirect(0)) {
2252 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2253 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2255 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2256 i
->setIndirect(0, 1, NULL
);
2257 i
->setIndirect(0, 0, ptr
);
2258 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2259 i
->setPredicate(CC_NOT_P
, pred
);
2260 if (i
->defExists(0)) {
2261 bld
.mkMov(i
->getDef(0), bld
.mkImm(0));
2263 } else if (fileIndex
>= 0) {
2264 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
2265 if (i
->src(0).isIndirect(0)) {
2266 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2268 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2269 i
->setIndirect(0, 1, NULL
);
2270 i
->setIndirect(0, 0, ptr
);
2272 } else if (i
->src(0).isIndirect(1)) {
2274 if (i
->src(0).isIndirect(0))
2275 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
2276 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
2277 i
->getIndirect(0, 0));
2279 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2280 i
->getIndirect(0, 1), bld
.mkImm(16));
2281 i
->setIndirect(0, 1, NULL
);
2282 i
->setIndirect(0, 0, ptr
);
2283 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
2285 } else if (i
->src(0).getFile() == FILE_SHADER_OUTPUT
) {
2286 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
2288 } else if (i
->src(0).getFile() == FILE_MEMORY_BUFFER
) {
2289 Value
*ind
= i
->getIndirect(0, 1);
2290 Value
*ptr
= loadBufInfo64(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2291 // XXX come up with a way not to do this for EVERY little access but
2292 // rather to batch these up somehow. Unfortunately we've lost the
2293 // information about the field width by the time we get here.
2294 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2295 Value
*length
= loadBufLength32(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2296 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2297 if (i
->src(0).isIndirect(0)) {
2298 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2299 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2301 i
->setIndirect(0, 1, NULL
);
2302 i
->setIndirect(0, 0, ptr
);
2303 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2304 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2305 i
->setPredicate(CC_NOT_P
, pred
);
2306 if (i
->defExists(0)) {
2307 Value
*zero
, *dst
= i
->getDef(0);
2308 i
->setDef(0, bld
.getSSA());
2310 bld
.setPosition(i
, true);
2311 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
2312 ->setPredicate(CC_P
, pred
);
2313 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, i
->getDef(0), zero
);
2319 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
2321 Value
*laneid
= bld
.getSSA();
2324 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
2335 if (prog
->driver
->prop
.tp
.domain
!= PIPE_PRIM_TRIANGLES
) {
2336 bld
.mkMov(dst
, bld
.loadImm(NULL
, 0));
2343 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
2345 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
2348 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
2349 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
2354 NVC0LoweringPass::handleRDSV(Instruction
*i
)
2356 Symbol
*sym
= i
->getSrc(0)->asSym();
2357 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
2360 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
2362 if (addr
>= 0x400) {
2364 if (sym
->reg
.data
.sv
.index
== 3) {
2365 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
2367 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
2369 if (sv
== SV_VERTEX_COUNT
) {
2370 bld
.setPosition(i
, true);
2371 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(0x808));
2378 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
2379 if (i
->srcExists(1)) {
2380 // Pass offset through to the interpolation logic
2381 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
2382 i
->getDef(0), addr
, NULL
);
2383 ld
->setSrc(1, i
->getSrc(1));
2385 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
2390 Value
*face
= i
->getDef(0);
2391 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
2392 if (i
->dType
== TYPE_F32
) {
2393 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
2394 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
2395 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
2400 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
2401 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
2406 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
2407 if (sym
->reg
.data
.sv
.index
== 3) {
2409 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
2414 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
2415 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2416 bld
.mkSymbol(FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2417 TYPE_U32
, addr
), NULL
);
2419 case SV_SAMPLE_INDEX
:
2420 // TODO: Properly pass source as an address in the PIX address space
2421 // (which can be of the form [r0+offset]). But this is currently
2423 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2424 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2426 case SV_SAMPLE_POS
: {
2427 Value
*off
= new_LValue(func
, FILE_GPR
);
2428 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2429 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2430 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
2431 bld
.mkLoad(TYPE_F32
,
2434 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2435 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
2436 4 * sym
->reg
.data
.sv
.index
),
2440 case SV_SAMPLE_MASK
: {
2441 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2442 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
2443 Instruction
*sampleid
=
2444 bld
.mkOp1(OP_PIXLD
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2445 sampleid
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2447 bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
2448 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2449 bld
.loadImm(NULL
, 1), sampleid
->getDef(0)));
2450 if (prog
->driver
->prop
.fp
.persampleInvocation
) {
2451 bld
.mkMov(i
->getDef(0), masked
);
2453 bld
.mkOp3(OP_SELP
, TYPE_U32
, i
->getDef(0), ld
->getDef(0), masked
,
2460 case SV_BASEINSTANCE
:
2462 ld
= bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2463 bld
.mkSymbol(FILE_MEMORY_CONST
,
2464 prog
->driver
->io
.auxCBSlot
,
2466 prog
->driver
->io
.drawInfoBase
+
2467 4 * (sv
- SV_BASEVERTEX
)),
2471 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
&& !i
->perPatch
)
2472 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2473 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
2474 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
2475 ld
->perPatch
= i
->perPatch
;
2478 bld
.getBB()->remove(i
);
2483 NVC0LoweringPass::handleDIV(Instruction
*i
)
2485 if (!isFloatType(i
->dType
))
2487 bld
.setPosition(i
, false);
2488 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
2490 i
->setSrc(1, rcp
->getDef(0));
2495 NVC0LoweringPass::handleMOD(Instruction
*i
)
2497 if (!isFloatType(i
->dType
))
2499 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
2500 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
2501 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
2502 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
2503 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
2505 i
->setSrc(1, value
);
2510 NVC0LoweringPass::handleSQRT(Instruction
*i
)
2512 if (i
->dType
== TYPE_F64
) {
2513 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
2514 Value
*zero
= bld
.loadImm(NULL
, 0.0);
2515 Value
*dst
= bld
.getSSA(8);
2516 bld
.mkOp1(OP_RSQ
, i
->dType
, dst
, i
->getSrc(0));
2517 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
2518 bld
.mkOp3(OP_SELP
, TYPE_U64
, dst
, zero
, dst
, pred
);
2521 // TODO: Handle this properly with a library function
2523 bld
.setPosition(i
, true);
2525 bld
.mkOp1(OP_RCP
, i
->dType
, i
->getDef(0), i
->getDef(0));
2532 NVC0LoweringPass::handlePOW(Instruction
*i
)
2534 LValue
*val
= bld
.getScratch();
2536 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
2537 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
2538 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
2548 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
2550 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2551 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
2553 if (i
->src(0).isIndirect(0)) // TODO, ugly
2556 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
2557 i
->src(0).set(i
->src(1));
2559 i
->setDef(0, new_LValue(func
, FILE_GPR
));
2560 i
->getDef(0)->reg
.data
.id
= id
;
2562 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
2564 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
2565 i
->setIndirect(0, 1, gpEmitAddress
);
2571 NVC0LoweringPass::handleOUT(Instruction
*i
)
2573 Instruction
*prev
= i
->prev
;
2574 ImmediateValue stream
, prevStream
;
2576 // Only merge if the stream ids match. Also, note that the previous
2577 // instruction would have already been lowered, so we take arg1 from it.
2578 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
2579 i
->src(0).getImmediate(stream
) &&
2580 prev
->src(1).getImmediate(prevStream
) &&
2581 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
2582 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
2583 delete_Instruction(prog
, i
);
2585 assert(gpEmitAddress
);
2586 i
->setDef(0, gpEmitAddress
);
2587 i
->setSrc(1, i
->getSrc(0));
2588 i
->setSrc(0, gpEmitAddress
);
2593 // Generate a binary predicate if an instruction is predicated by
2594 // e.g. an f32 value.
2596 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
2598 Value
*pred
= insn
->getPredicate();
2601 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
2603 pdst
= new_LValue(func
, FILE_PREDICATE
);
2605 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
2606 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
2608 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
2610 insn
->setPredicate(insn
->cc
, pdst
);
2614 // - add quadop dance for texturing
2615 // - put FP outputs in GPRs
2616 // - convert instruction sequences
2619 NVC0LoweringPass::visit(Instruction
*i
)
2622 bld
.setPosition(i
, false);
2624 if (i
->cc
!= CC_ALWAYS
)
2633 return handleTEX(i
->asTex());
2635 return handleTXD(i
->asTex());
2637 return handleTXLQ(i
->asTex());
2639 return handleTXQ(i
->asTex());
2641 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
2642 i
->setSrc(0, i
->getDef(0));
2645 return handlePOW(i
);
2647 return handleDIV(i
);
2649 return handleMOD(i
);
2651 return handleSQRT(i
);
2653 ret
= handleEXPORT(i
);
2657 return handleOUT(i
);
2659 return handleRDSV(i
);
2661 return handleWRSV(i
);
2668 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_BUFFER
;
2670 handleCasExch(i
, cctl
);
2679 if (targ
->getChipset() >= NVISA_GM107_CHIPSET
)
2680 handleSurfaceOpGM107(i
->asTex());
2681 else if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2682 handleSurfaceOpNVE4(i
->asTex());
2684 handleSurfaceOpNVC0(i
->asTex());
2687 handleSUQ(i
->asTex());
2696 /* Kepler+ has a special opcode to compute a new base address to be used
2697 * for indirect loads.
2699 * Maxwell+ has an additional similar requirement for indirect
2700 * interpolation ops in frag shaders.
2702 bool doAfetch
= false;
2703 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
2705 (i
->op
== OP_VFETCH
|| i
->op
== OP_EXPORT
) &&
2706 i
->src(0).isIndirect(0)) {
2709 if (targ
->getChipset() >= NVISA_GM107_CHIPSET
&&
2710 (i
->op
== OP_LINTERP
|| i
->op
== OP_PINTERP
) &&
2711 i
->src(0).isIndirect(0)) {
2716 Value
*addr
= cloneShallow(func
, i
->getSrc(0));
2717 Instruction
*afetch
= bld
.mkOp1(OP_AFETCH
, TYPE_U32
, bld
.getSSA(),
2719 afetch
->setIndirect(0, 0, i
->getIndirect(0, 0));
2720 addr
->reg
.data
.offset
= 0;
2722 i
->setIndirect(0, 0, afetch
->getDef(0));
2729 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
2731 if (stage
== CG_STAGE_PRE_SSA
) {
2732 NVC0LoweringPass
pass(prog
);
2733 return pass
.run(prog
, false, true);
2735 if (stage
== CG_STAGE_POST_RA
) {
2736 NVC0LegalizePostRA
pass(prog
);
2737 return pass
.run(prog
, false, true);
2739 if (stage
== CG_STAGE_SSA
) {
2740 NVC0LegalizeSSA pass
;
2741 return pass
.run(prog
, false, true);
2746 } // namespace nv50_ir