2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
77 NVC0LegalizeSSA::visit(Function
*fn
)
79 bld
.setProgram(fn
->getProgram());
84 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
87 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
89 if (i
->dType
== TYPE_F32
)
98 if (i
->dType
== TYPE_F64
)
108 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
111 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
116 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
117 const Instruction
*early
) const
119 if (early
->bb
== later
->bb
)
120 return early
->serial
< later
->serial
;
121 return later
->bb
->dominatedBy(early
->bb
);
125 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
126 Instruction
*usei
, const Instruction
*insn
)
129 for (std::list
<TexUse
>::iterator it
= uses
.begin();
131 if (insnDominatedBy(usei
, it
->insn
)) {
135 if (insnDominatedBy(it
->insn
, usei
))
141 uses
.push_back(TexUse(usei
, insn
));
145 NVC0LegalizePostRA::findOverwritingDefs(const Instruction
*texi
,
147 const BasicBlock
*term
,
148 std::list
<TexUse
> &uses
)
150 while (insn
->op
== OP_MOV
&& insn
->getDef(0)->equals(insn
->getSrc(0)))
151 insn
= insn
->getSrc(0)->getUniqueInsn();
153 if (!insn
->bb
->reachableBy(texi
->bb
, term
))
157 /* Values not connected to the tex's definition through any of these should
158 * not be conflicting.
165 for (int s
= 0; insn
->srcExists(s
); ++s
)
166 findOverwritingDefs(texi
, insn
->getSrc(s
)->getUniqueInsn(), term
,
170 // if (!isTextureOp(insn->op)) // TODO: are TEXes always ordered ?
171 addTexUse(uses
, insn
, texi
);
177 NVC0LegalizePostRA::findFirstUses(
178 const Instruction
*texi
,
179 const Instruction
*insn
,
180 std::list
<TexUse
> &uses
,
181 std::tr1::unordered_set
<const Instruction
*>& visited
)
183 for (int d
= 0; insn
->defExists(d
); ++d
) {
184 Value
*v
= insn
->getDef(d
);
185 for (Value::UseIterator u
= v
->uses
.begin(); u
!= v
->uses
.end(); ++u
) {
186 Instruction
*usei
= (*u
)->getInsn();
188 // NOTE: In case of a loop that overwrites a value but never uses
189 // it, it can happen that we have a cycle of uses that consists only
190 // of phis and no-op moves and will thus cause an infinite loop here
191 // since these are not considered actual uses.
192 // The most obvious (and perhaps the only) way to prevent this is to
193 // remember which instructions we've already visited.
195 if (visited
.find(usei
) != visited
.end())
198 visited
.insert(usei
);
200 if (usei
->op
== OP_PHI
|| usei
->op
== OP_UNION
) {
201 // need a barrier before WAW cases
202 for (int s
= 0; usei
->srcExists(s
); ++s
) {
203 Instruction
*defi
= usei
->getSrc(s
)->getUniqueInsn();
204 if (defi
&& &usei
->src(s
) != *u
)
205 findOverwritingDefs(texi
, defi
, usei
->bb
, uses
);
209 if (usei
->op
== OP_SPLIT
||
210 usei
->op
== OP_MERGE
||
211 usei
->op
== OP_PHI
||
212 usei
->op
== OP_UNION
) {
213 // these uses don't manifest in the machine code
214 findFirstUses(texi
, usei
, uses
, visited
);
216 if (usei
->op
== OP_MOV
&& usei
->getDef(0)->equals(usei
->getSrc(0)) &&
217 usei
->subOp
!= NV50_IR_SUBOP_MOV_FINAL
) {
218 findFirstUses(texi
, usei
, uses
, visited
);
220 addTexUse(uses
, usei
, insn
);
227 // This pass is a bit long and ugly and can probably be optimized.
229 // 1. obtain a list of TEXes and their outputs' first use(s)
230 // 2. calculate the barrier level of each first use (minimal number of TEXes,
231 // over all paths, between the TEX and the use in question)
232 // 3. for each barrier, if all paths from the source TEX to that barrier
233 // contain a barrier of lesser level, it can be culled
235 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
237 std::list
<TexUse
> *uses
;
238 std::vector
<Instruction
*> texes
;
239 std::vector
<int> bbFirstTex
;
240 std::vector
<int> bbFirstUse
;
241 std::vector
<int> texCounts
;
242 std::vector
<TexUse
> useVec
;
245 fn
->orderInstructions(insns
);
247 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
248 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
249 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
251 // tag BB CFG nodes by their id for later
252 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
253 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
255 bb
->cfg
.tag
= bb
->getId();
258 // gather the first uses for each TEX
259 for (int i
= 0; i
< insns
.getSize(); ++i
) {
260 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
261 if (isTextureOp(tex
->op
)) {
262 texes
.push_back(tex
);
263 if (!texCounts
.at(tex
->bb
->getId()))
264 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
265 texCounts
[tex
->bb
->getId()]++;
271 uses
= new std::list
<TexUse
>[texes
.size()];
274 for (size_t i
= 0; i
< texes
.size(); ++i
) {
275 std::tr1::unordered_set
<const Instruction
*> visited
;
276 findFirstUses(texes
[i
], texes
[i
], uses
[i
], visited
);
279 // determine the barrier level at each use
280 for (size_t i
= 0; i
< texes
.size(); ++i
) {
281 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
283 BasicBlock
*tb
= texes
[i
]->bb
;
284 BasicBlock
*ub
= u
->insn
->bb
;
287 for (size_t j
= i
+ 1; j
< texes
.size() &&
288 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
292 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
293 &ub
->cfg
, texCounts
);
295 WARN("Failed to find path TEX -> TEXBAR\n");
299 // this counted all TEXes in the origin block, correct that
300 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
301 // and did not count the TEXes in the destination block, add those
302 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
303 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
307 assert(u
->level
>= 0);
308 useVec
.push_back(*u
);
313 // insert the barriers
314 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
315 Instruction
*prev
= useVec
[i
].insn
->prev
;
316 if (useVec
[i
].level
< 0)
318 if (prev
&& prev
->op
== OP_TEXBAR
) {
319 if (prev
->subOp
> useVec
[i
].level
)
320 prev
->subOp
= useVec
[i
].level
;
321 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
323 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
325 bar
->subOp
= useVec
[i
].level
;
326 // make use explicit to ease latency calculation
327 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
328 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
332 if (fn
->getProgram()->optLevel
< 3)
335 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
337 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
338 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
339 limitS
.resize(fn
->allBBlocks
.getSize());
341 // cull unneeded barriers (should do that earlier, but for simplicity)
342 IteratorRef bi
= fn
->cfg
.iteratorCFG();
343 // first calculate min/max outstanding TEXes for each BB
344 for (bi
->reset(); !bi
->end(); bi
->next()) {
345 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
346 BasicBlock
*bb
= BasicBlock::get(n
);
348 int max
= std::numeric_limits
<int>::max();
349 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
350 if (isTextureOp(i
->op
)) {
352 if (max
< std::numeric_limits
<int>::max())
355 if (i
->op
== OP_TEXBAR
) {
356 min
= MIN2(min
, i
->subOp
);
357 max
= MIN2(max
, i
->subOp
);
360 // limits when looking at an isolated block
361 limitS
[bb
->getId()].min
= min
;
362 limitS
[bb
->getId()].max
= max
;
364 // propagate the min/max values
365 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
366 for (bi
->reset(); !bi
->end(); bi
->next()) {
367 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
368 BasicBlock
*bb
= BasicBlock::get(n
);
369 const int bbId
= bb
->getId();
370 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
371 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
372 const int inId
= in
->getId();
373 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
374 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
376 // I just hope this is correct ...
377 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
379 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
380 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
382 // block contained a barrier
383 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
384 limitT
[bbId
].min
+ limitS
[bbId
].min
);
385 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
386 limitT
[bbId
].max
+ limitS
[bbId
].min
);
390 // finally delete unnecessary barriers
391 for (bi
->reset(); !bi
->end(); bi
->next()) {
392 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
393 BasicBlock
*bb
= BasicBlock::get(n
);
394 Instruction
*prev
= NULL
;
396 int max
= limitT
[bb
->getId()].max
;
397 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
399 if (i
->op
== OP_TEXBAR
) {
400 if (i
->subOp
>= max
) {
401 delete_Instruction(prog
, i
);
405 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
406 delete_Instruction(prog
, prev
);
411 if (isTextureOp(i
->op
)) {
414 if (i
&& !i
->isNop())
422 NVC0LegalizePostRA::visit(Function
*fn
)
425 insertTextureBarriers(fn
);
427 rZero
= new_LValue(fn
, FILE_GPR
);
428 carry
= new_LValue(fn
, FILE_FLAGS
);
430 rZero
->reg
.data
.id
= prog
->getTarget()->getFileSize(FILE_GPR
);
431 carry
->reg
.data
.id
= 0;
437 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
439 for (int s
= 0; i
->srcExists(s
); ++s
) {
440 if (s
== 2 && i
->op
== OP_SUCLAMP
)
442 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
443 if (imm
&& imm
->reg
.data
.u64
== 0)
448 // replace CONT with BRA for single unconditional continue
450 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
452 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
454 Graph::EdgeIterator ei
= bb
->cfg
.incident();
455 if (ei
.getType() != Graph::Edge::BACK
)
457 if (ei
.getType() != Graph::Edge::BACK
)
459 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
461 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
462 contBB
->getExit()->getPredicate())
464 contBB
->getExit()->op
= OP_BRA
;
465 bb
->remove(bb
->getEntry()); // delete PRECONT
468 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
472 // replace branches to join blocks with join ops
474 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
476 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
478 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
479 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
480 Instruction
*exit
= in
->getExit();
482 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
483 // there should always be a terminator instruction
484 WARN("inserted missing terminator in BB:%i\n", in
->getId());
486 if (exit
->op
== OP_BRA
) {
488 exit
->asFlow()->limit
= 1; // must-not-propagate marker
491 bb
->remove(bb
->getEntry());
495 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
497 Instruction
*i
, *next
;
499 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
500 for (i
= bb
->getFirst(); i
; i
= next
) {
502 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
503 if (!i
->getDef(0)->refCount())
505 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
506 i
->setSrc(0, rZero
); // initial value must be 0
512 // TODO: Move this to before register allocation for operations that
513 // need the $c register !
514 if (typeSizeof(i
->dType
) == 8) {
516 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
521 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
528 if (!tryReplaceContWithBra(bb
))
534 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
536 bld
.setProgram(prog
);
541 NVC0LoweringPass::visit(Function
*fn
)
543 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
544 assert(!strncmp(fn
->getName(), "MAIN", 4));
545 // TODO: when we generate actual functions pass this value along somehow
546 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
547 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
549 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
550 bld
.mkMovToReg(0, gpEmitAddress
);
557 NVC0LoweringPass::visit(BasicBlock
*bb
)
563 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
565 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
566 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
568 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
571 // move array source to first slot, convert to u16, add indirections
573 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
575 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
576 const int arg
= i
->tex
.target
.getArgCount();
577 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
578 const int chipset
= prog
->getTarget()->getChipset();
580 // Arguments to the TEX instruction are a little insane. Even though the
581 // encoding is identical between SM20 and SM30, the arguments mean
582 // different things between Fermi and Kepler+. A lot of arguments are
583 // optional based on flags passed to the instruction. This summarizes the
593 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
594 // - other: 4 bits each, single reg
598 // array (+ offsets for txd in upper 16 bits)
603 // offsets (same as fermi, except txd which takes it with array)
620 if (chipset
>= NVISA_GK104_CHIPSET
) {
621 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
622 // XXX this ignores tsc, and assumes a 1:1 mapping
623 assert(i
->tex
.rIndirectSrc
>= 0);
624 Value
*hnd
= loadTexHandle(
625 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
626 i
->getIndirectR(), bld
.mkImm(2)),
630 i
->setIndirectR(hnd
);
631 i
->setIndirectS(NULL
);
632 } else if (i
->tex
.r
== i
->tex
.s
) {
633 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
634 i
->tex
.s
= 0; // only a single cX[] value possible here
636 Value
*hnd
= bld
.getScratch();
637 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
638 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
640 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
642 i
->tex
.r
= 0; // not used for indirect tex
644 i
->setIndirectR(hnd
);
646 if (i
->tex
.target
.isArray()) {
647 LValue
*layer
= new_LValue(func
, FILE_GPR
);
648 Value
*src
= i
->getSrc(lyr
);
649 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
650 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
651 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
652 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
653 for (int s
= dim
; s
>= 1; --s
)
654 i
->setSrc(s
, i
->getSrc(s
- 1));
657 i
->setSrc(dim
, layer
);
660 // Move the indirect reference to the first place
661 if (i
->tex
.rIndirectSrc
>= 0 && (
662 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
663 Value
*hnd
= i
->getIndirectR();
665 i
->setIndirectR(NULL
);
666 i
->moveSources(0, 1);
668 i
->tex
.rIndirectSrc
= 0;
669 i
->tex
.sIndirectSrc
= -1;
672 // (nvc0) generate and move the tsc/tic/array source to the front
673 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
674 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
676 Value
*ticRel
= i
->getIndirectR();
677 Value
*tscRel
= i
->getIndirectS();
680 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
682 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
683 ticRel
, bld
.mkImm(i
->tex
.r
));
686 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
688 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
689 tscRel
, bld
.mkImm(i
->tex
.s
));
692 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
693 for (int s
= dim
; s
>= 1; --s
)
694 i
->setSrc(s
, i
->getSrc(s
- 1));
695 i
->setSrc(0, arrayIndex
);
698 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
699 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
700 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
706 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
708 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
713 // For nvc0, the sample id has to be in the second operand, as the offset
714 // does. Right now we don't know how to pass both in, and this case can't
715 // happen with OpenGL. On nve0, the sample id is part of the texture
716 // coordinate argument.
717 assert(chipset
>= NVISA_GK104_CHIPSET
||
718 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
720 // offset is between lod and dc
721 if (i
->tex
.useOffsets
) {
723 int s
= i
->srcCount(0xff, true);
724 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
725 if (i
->tex
.target
.isShadow())
727 if (i
->srcExists(s
)) // move potential predicate out of the way
728 i
->moveSources(s
, 1);
729 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
730 i
->moveSources(s
+ 1, 1);
732 if (i
->op
== OP_TXG
) {
733 // Either there is 1 offset, which goes into the 2 low bytes of the
734 // first source, or there are 4 offsets, which go into 2 sources (8
735 // values, 1 byte each).
736 Value
*offs
[2] = {NULL
, NULL
};
737 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
738 for (c
= 0; c
< 2; ++c
) {
739 if ((n
% 2) == 0 && c
== 0)
740 offs
[n
/ 2] = i
->offset
[n
][c
].get();
742 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
744 i
->offset
[n
][c
].get(),
745 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
749 i
->setSrc(s
, offs
[0]);
751 i
->setSrc(s
+ 1, offs
[1]);
754 assert(i
->tex
.useOffsets
== 1);
755 for (c
= 0; c
< 3; ++c
) {
757 assert(i
->offset
[0][c
].getImmediate(val
));
758 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
760 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
761 // The offset goes into the upper 16 bits of the array index. So
762 // create it if it's not already there, and INSBF it if it already
764 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
765 if (chipset
>= NVISA_GM107_CHIPSET
)
767 if (i
->tex
.target
.isArray()) {
768 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
769 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
772 i
->moveSources(s
, 1);
773 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
776 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
781 if (chipset
>= NVISA_GK104_CHIPSET
) {
783 // If TEX requires more than 4 sources, the 2nd register tuple must be
784 // aligned to 4, even if it consists of just a single 4-byte register.
786 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
788 int s
= i
->srcCount(0xff, true);
789 if (s
> 4 && s
< 7) {
790 if (i
->srcExists(s
)) // move potential predicate out of the way
791 i
->moveSources(s
, 7 - s
);
793 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
801 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
803 static const uint8_t qOps
[4][2] =
805 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
806 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
807 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
808 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
813 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
815 const int dim
= i
->tex
.target
.getDim();
816 const int array
= i
->tex
.target
.isArray();
818 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
820 for (c
= 0; c
< dim
; ++c
)
821 crd
[c
] = bld
.getScratch();
823 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
824 for (l
= 0; l
< 4; ++l
) {
825 // mov coordinates from lane l to all lanes
826 for (c
= 0; c
< dim
; ++c
)
827 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
828 // add dPdx from lane l to lanes dx
829 for (c
= 0; c
< dim
; ++c
)
830 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
831 // add dPdy from lane l to lanes dy
832 for (c
= 0; c
< dim
; ++c
)
833 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
835 bld
.insert(tex
= cloneForward(func
, i
));
836 for (c
= 0; c
< dim
; ++c
)
837 tex
->setSrc(c
+ array
, crd
[c
]);
839 for (c
= 0; i
->defExists(c
); ++c
) {
841 def
[c
][l
] = bld
.getSSA();
842 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
847 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
849 for (c
= 0; i
->defExists(c
); ++c
) {
850 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
851 for (l
= 0; l
< 4; ++l
)
852 u
->setSrc(l
, def
[c
][l
]);
860 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
862 int dim
= txd
->tex
.target
.getDim();
863 unsigned arg
= txd
->tex
.target
.getArgCount();
864 unsigned expected_args
= arg
;
865 const int chipset
= prog
->getTarget()->getChipset();
867 if (chipset
>= NVISA_GK104_CHIPSET
) {
868 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
870 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
873 if (txd
->tex
.useOffsets
)
875 if (!txd
->tex
.target
.isArray() && (
876 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
880 if (expected_args
> 4 ||
882 txd
->tex
.target
.isShadow() ||
883 txd
->tex
.target
.isCube())
887 while (txd
->srcExists(arg
))
890 txd
->tex
.derivAll
= true;
891 if (txd
->op
== OP_TEX
)
892 return handleManualTXD(txd
);
894 assert(arg
== expected_args
);
895 for (int c
= 0; c
< dim
; ++c
) {
896 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
897 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
898 txd
->dPdx
[c
].set(NULL
);
899 txd
->dPdy
[c
].set(NULL
);
905 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
907 // TODO: indirect resource/sampler index
912 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
914 /* The outputs are inverted compared to what the TGSI instruction
915 * expects. Take that into account in the mask.
917 assert((i
->tex
.mask
& ~3) == 0);
918 if (i
->tex
.mask
== 1)
920 else if (i
->tex
.mask
== 2)
923 bld
.setPosition(i
, true);
925 /* The returned values are not quite what we want:
926 * (a) convert from s16/u16 to f32
927 * (b) multiply by 1/256
929 for (int def
= 0; def
< 2; ++def
) {
930 if (!i
->defExists(def
))
932 enum DataType type
= TYPE_S16
;
933 if (i
->tex
.mask
== 2 || def
> 0)
935 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
936 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
937 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
939 if (i
->tex
.mask
== 3) {
940 LValue
*t
= new_LValue(func
, FILE_GPR
);
941 bld
.mkMov(t
, i
->getDef(0));
942 bld
.mkMov(i
->getDef(0), i
->getDef(1));
943 bld
.mkMov(i
->getDef(1), t
);
950 NVC0LoweringPass::handleATOM(Instruction
*atom
)
954 switch (atom
->src(0).getFile()) {
955 case FILE_MEMORY_LOCAL
:
958 case FILE_MEMORY_SHARED
:
962 assert(atom
->src(0).getFile() == FILE_MEMORY_GLOBAL
);
966 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
967 Value
*ptr
= atom
->getIndirect(0, 0);
969 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
970 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
972 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
973 atom
->setIndirect(0, 0, base
);
979 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
981 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
982 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
984 bld
.setPosition(cas
, true);
987 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
988 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
990 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
991 if (cas
->isPredicated())
992 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
995 if (cas
->defExists(0) && cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
996 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
997 // should be set to the high part of the double reg or bad things will
998 // happen elsewhere in the universe.
999 // Also, it sometimes returns the new value instead of the old one
1000 // under mysterious circumstances.
1001 Value
*dreg
= bld
.getSSA(8);
1002 bld
.setPosition(cas
, false);
1003 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1004 cas
->setSrc(1, dreg
);
1011 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
)
1013 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
1014 off
+= prog
->driver
->io
.suInfoBase
;
1016 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1020 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1022 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1023 off
+= prog
->driver
->io
.msInfoBase
;
1025 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1028 /* On nvc0, surface info is obtained via the surface binding points passed
1029 * to the SULD/SUST instructions.
1030 * On nve4, surface info is stored in c[] and is used by various special
1031 * instructions, e.g. for clamping coordiantes or generating an address.
1032 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1034 #define NVE4_SU_INFO_ADDR 0x00
1035 #define NVE4_SU_INFO_FMT 0x04
1036 #define NVE4_SU_INFO_DIM_X 0x08
1037 #define NVE4_SU_INFO_PITCH 0x0c
1038 #define NVE4_SU_INFO_DIM_Y 0x10
1039 #define NVE4_SU_INFO_ARRAY 0x14
1040 #define NVE4_SU_INFO_DIM_Z 0x18
1041 #define NVE4_SU_INFO_UNK1C 0x1c
1042 #define NVE4_SU_INFO_WIDTH 0x20
1043 #define NVE4_SU_INFO_HEIGHT 0x24
1044 #define NVE4_SU_INFO_DEPTH 0x28
1045 #define NVE4_SU_INFO_TARGET 0x2c
1046 #define NVE4_SU_INFO_CALL 0x30
1047 #define NVE4_SU_INFO_RAW_X 0x34
1048 #define NVE4_SU_INFO_MS_X 0x38
1049 #define NVE4_SU_INFO_MS_Y 0x3c
1051 #define NVE4_SU_INFO__STRIDE 0x40
1053 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
1054 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1055 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
1057 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1059 switch (su
->tex
.target
.getEnum()) {
1060 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1061 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1062 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1063 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1064 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1065 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1066 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1067 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1068 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1069 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1070 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1071 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1072 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1080 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1082 const uint16_t base
= tex
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1083 const int arg
= tex
->tex
.target
.getArgCount();
1085 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1086 tex
->tex
.target
= TEX_TARGET_2D
;
1088 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1089 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1093 Value
*x
= tex
->getSrc(0);
1094 Value
*y
= tex
->getSrc(1);
1095 Value
*s
= tex
->getSrc(arg
- 1);
1097 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1099 Value
*ms_x
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(0));
1100 Value
*ms_y
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(1));
1102 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1103 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1105 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1106 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1108 Value
*dx
= loadMsInfo32(ts
, 0x0);
1109 Value
*dy
= loadMsInfo32(ts
, 0x4);
1111 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1112 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1116 tex
->moveSources(arg
, -1);
1119 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1120 // They're computed from the coordinates using the surface info in c[] space.
1122 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1125 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1127 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1128 const int idx
= su
->tex
.r
;
1129 const int dim
= su
->tex
.target
.getDim();
1130 const int arg
= dim
+ (su
->tex
.target
.isArray() ? 1 : 0);
1131 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
1133 Value
*zero
= bld
.mkImm(0);
1137 Value
*bf
, *eau
, *off
;
1140 off
= bld
.getScratch(4);
1141 bf
= bld
.getScratch(4);
1142 addr
= bld
.getSSA(8);
1143 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1145 bld
.setPosition(su
, false);
1147 adjustCoordinatesMS(su
);
1149 // calculate clamped coordinates
1150 for (c
= 0; c
< arg
; ++c
) {
1151 src
[c
] = bld
.getScratch();
1153 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_RAW_X
);
1155 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_DIM(c
));
1156 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1157 ->subOp
= getSuClampSubOp(su
, c
);
1162 // set predicate output
1163 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1164 src
[0]->getInsn()->setFlagsDef(1, pred
);
1166 if (su
->tex
.target
.isArray()) {
1167 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1168 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1171 // calculate pixel offset
1173 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1174 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1177 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1178 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1179 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1181 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1182 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1183 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1186 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1187 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1188 ->subOp
= su
->tex
.target
.isArray() ?
1189 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1192 // calculate effective address part 1
1193 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1197 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1198 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1199 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1213 if (!su
->tex
.target
.isArray()) {
1214 z
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1215 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1219 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1223 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1224 insn
->subOp
= subOp
;
1225 insn
->setFlagsDef(1, pred
);
1229 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ADDR
);
1231 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1234 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1236 // add array layer offset
1237 if (su
->tex
.target
.isArray()) {
1238 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ARRAY
);
1240 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1241 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1243 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1244 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1245 // combine predicates
1247 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1252 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1256 // bf == g[] address & 0xff
1257 // eau == g[] address >> 8
1258 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1259 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1261 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1262 // Convert from u32 to u8 address format, which is what the library code
1263 // doing SULDP currently uses.
1264 // XXX: can SUEAU do this ?
1265 // XXX: does it matter that we don't mask high bytes in bf ?
1267 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1268 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1271 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1273 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1274 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1276 // let's just set it 0 for raw access and hope it works
1278 bld
.mkImm(0) : loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1280 // get rid of old coordinate sources, make space for fmt info and predicate
1281 su
->moveSources(arg
, 3 - arg
);
1282 // set 64 bit address and 32-bit format sources
1283 su
->setSrc(0, addr
);
1285 su
->setSrc(2, pred
);
1289 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1291 processSurfaceCoordsNVE4(su
);
1293 // Who do we hate more ? The person who decided that nvc0's SULD doesn't
1294 // have to support conversion or the person who decided that, in OpenCL,
1295 // you don't have to specify the format here like you do in OpenGL ?
1297 if (su
->op
== OP_SULDP
) {
1298 // We don't patch shaders. Ever.
1299 // You get an indirect call to our library blob here.
1300 // But at least it's uniform.
1301 FlowInstruction
*call
;
1304 uint16_t base
= su
->tex
.r
* NVE4_SU_INFO__STRIDE
+ NVE4_SU_INFO_CALL
;
1306 for (int i
= 0; i
< 4; ++i
)
1307 (r
[i
] = bld
.getScratch(4, FILE_GPR
))->reg
.data
.id
= i
;
1308 for (int i
= 0; i
< 3; ++i
)
1309 (p
[i
] = bld
.getScratch(1, FILE_PREDICATE
))->reg
.data
.id
= i
;
1310 (r
[4] = bld
.getScratch(8, FILE_GPR
))->reg
.data
.id
= 4;
1312 bld
.mkMov(p
[1], bld
.mkImm((su
->cache
== CACHE_CA
) ? 1 : 0), TYPE_U8
);
1313 bld
.mkMov(p
[2], bld
.mkImm((su
->cache
== CACHE_CG
) ? 1 : 0), TYPE_U8
);
1314 bld
.mkMov(p
[0], su
->getSrc(2), TYPE_U8
);
1315 bld
.mkMov(r
[4], su
->getSrc(0), TYPE_U64
);
1316 bld
.mkMov(r
[2], su
->getSrc(1), TYPE_U32
);
1318 call
= bld
.mkFlow(OP_CALL
, NULL
, su
->cc
, su
->getPredicate());
1322 call
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_CONST
,
1323 prog
->driver
->io
.resInfoCBSlot
, TYPE_U32
,
1324 prog
->driver
->io
.suInfoBase
+ base
));
1325 call
->setSrc(1, r
[2]);
1326 call
->setSrc(2, r
[4]);
1327 for (int i
= 0; i
< 3; ++i
)
1328 call
->setSrc(3 + i
, p
[i
]);
1329 for (int i
= 0; i
< 4; ++i
) {
1330 call
->setDef(i
, r
[i
]);
1331 bld
.mkMov(su
->getDef(i
), r
[i
]);
1333 call
->setDef(4, p
[1]);
1334 delete_Instruction(bld
.getProgram(), su
);
1337 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
1338 // FIXME: for out of bounds access, destination value will be undefined !
1339 Value
*pred
= su
->getSrc(2);
1340 CondCode cc
= CC_NOT_P
;
1341 if (su
->getPredicate()) {
1342 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1344 if (cc
== CC_NOT_P
) {
1345 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1347 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1348 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
1351 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, su
->getDef(0));
1352 red
->subOp
= su
->subOp
;
1354 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
1355 red
->setSrc(0, gMemBase
);
1356 red
->setSrc(1, su
->getSrc(3));
1357 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1358 red
->setSrc(2, su
->getSrc(4));
1359 red
->setIndirect(0, 0, su
->getSrc(0));
1360 red
->setPredicate(cc
, pred
);
1361 delete_Instruction(bld
.getProgram(), su
);
1362 handleCasExch(red
, true);
1364 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
1369 NVC0LoweringPass::handleWRSV(Instruction
*i
)
1375 // must replace, $sreg are not writeable
1376 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
1379 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
1381 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
1383 st
->perPatch
= i
->perPatch
;
1385 bld
.getBB()->remove(i
);
1390 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
1392 Value
*laneid
= bld
.getSSA();
1395 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
1410 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
1412 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
1415 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
1416 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
1421 NVC0LoweringPass::handleRDSV(Instruction
*i
)
1423 Symbol
*sym
= i
->getSrc(0)->asSym();
1424 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
1427 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
1429 if (addr
>= 0x400) {
1431 if (sym
->reg
.data
.sv
.index
== 3) {
1432 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
1434 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
1441 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
1442 if (i
->srcExists(1)) {
1443 // Pass offset through to the interpolation logic
1444 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
1445 i
->getDef(0), addr
, NULL
);
1446 ld
->setSrc(1, i
->getSrc(1));
1448 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
1453 Value
*face
= i
->getDef(0);
1454 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
1455 if (i
->dType
== TYPE_F32
) {
1456 bld
.mkOp2(OP_AND
, TYPE_U32
, face
, face
, bld
.mkImm(0x80000000));
1457 bld
.mkOp2(OP_XOR
, TYPE_U32
, face
, face
, bld
.mkImm(0xbf800000));
1462 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
1463 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
1468 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
1469 if (sym
->reg
.data
.sv
.index
== 3) {
1471 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
1474 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
1475 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
1476 bld
.mkSymbol(FILE_MEMORY_CONST
, 0, TYPE_U32
, addr
), NULL
);
1478 case SV_SAMPLE_INDEX
:
1479 // TODO: Properly pass source as an address in the PIX address space
1480 // (which can be of the form [r0+offset]). But this is currently
1482 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1483 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1485 case SV_SAMPLE_POS
: {
1486 Value
*off
= new_LValue(func
, FILE_GPR
);
1487 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1488 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1489 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
1490 bld
.mkLoad(TYPE_F32
,
1493 FILE_MEMORY_CONST
, prog
->driver
->io
.resInfoCBSlot
,
1494 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
1495 4 * sym
->reg
.data
.sv
.index
),
1499 case SV_SAMPLE_MASK
:
1500 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1501 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
1504 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
)
1505 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
1506 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
1507 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
1508 ld
->perPatch
= i
->perPatch
;
1511 bld
.getBB()->remove(i
);
1516 NVC0LoweringPass::handleDIV(Instruction
*i
)
1518 if (!isFloatType(i
->dType
))
1520 bld
.setPosition(i
, false);
1521 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(), i
->getSrc(1));
1523 i
->setSrc(1, rcp
->getDef(0));
1528 NVC0LoweringPass::handleMOD(Instruction
*i
)
1530 if (i
->dType
!= TYPE_F32
)
1532 LValue
*value
= bld
.getScratch();
1533 bld
.mkOp1(OP_RCP
, TYPE_F32
, value
, i
->getSrc(1));
1534 bld
.mkOp2(OP_MUL
, TYPE_F32
, value
, i
->getSrc(0), value
);
1535 bld
.mkOp1(OP_TRUNC
, TYPE_F32
, value
, value
);
1536 bld
.mkOp2(OP_MUL
, TYPE_F32
, value
, i
->getSrc(1), value
);
1538 i
->setSrc(1, value
);
1543 NVC0LoweringPass::handleSQRT(Instruction
*i
)
1545 Instruction
*rsq
= bld
.mkOp1(OP_RSQ
, TYPE_F32
,
1546 bld
.getSSA(), i
->getSrc(0));
1548 i
->setSrc(1, rsq
->getDef(0));
1554 NVC0LoweringPass::handlePOW(Instruction
*i
)
1556 LValue
*val
= bld
.getScratch();
1558 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
1559 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
1560 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
1570 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
1572 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1573 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
1575 if (i
->src(0).isIndirect(0)) // TODO, ugly
1578 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
1579 i
->src(0).set(i
->src(1));
1581 i
->setDef(0, new_LValue(func
, FILE_GPR
));
1582 i
->getDef(0)->reg
.data
.id
= id
;
1584 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
1586 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
1587 i
->setIndirect(0, 1, gpEmitAddress
);
1593 NVC0LoweringPass::handleOUT(Instruction
*i
)
1595 Instruction
*prev
= i
->prev
;
1596 ImmediateValue stream
, prevStream
;
1598 // Only merge if the stream ids match. Also, note that the previous
1599 // instruction would have already been lowered, so we take arg1 from it.
1600 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
1601 i
->src(0).getImmediate(stream
) &&
1602 prev
->src(1).getImmediate(prevStream
) &&
1603 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
1604 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
1605 delete_Instruction(prog
, i
);
1607 assert(gpEmitAddress
);
1608 i
->setDef(0, gpEmitAddress
);
1609 i
->setSrc(1, i
->getSrc(0));
1610 i
->setSrc(0, gpEmitAddress
);
1615 // Generate a binary predicate if an instruction is predicated by
1616 // e.g. an f32 value.
1618 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
1620 Value
*pred
= insn
->getPredicate();
1623 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
1625 pdst
= new_LValue(func
, FILE_PREDICATE
);
1627 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
1628 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
1630 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
1632 insn
->setPredicate(insn
->cc
, pdst
);
1636 // - add quadop dance for texturing
1637 // - put FP outputs in GPRs
1638 // - convert instruction sequences
1641 NVC0LoweringPass::visit(Instruction
*i
)
1643 bld
.setPosition(i
, false);
1645 if (i
->cc
!= CC_ALWAYS
)
1654 return handleTEX(i
->asTex());
1656 return handleTXD(i
->asTex());
1658 return handleTXLQ(i
->asTex());
1660 return handleTXQ(i
->asTex());
1662 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
1663 i
->setSrc(0, i
->getDef(0));
1666 return handlePOW(i
);
1668 return handleDIV(i
);
1670 return handleMOD(i
);
1672 return handleSQRT(i
);
1674 return handleEXPORT(i
);
1677 return handleOUT(i
);
1679 return handleRDSV(i
);
1681 return handleWRSV(i
);
1683 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
1684 if (prog
->getType() == Program::TYPE_COMPUTE
) {
1685 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
1686 i
->getSrc(0)->reg
.fileIndex
= 0;
1688 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
1689 i
->src(0).isIndirect(0)) {
1690 // XXX: this assumes vec4 units
1691 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1692 i
->getIndirect(0, 0), bld
.mkImm(4));
1693 i
->setIndirect(0, 0, ptr
);
1696 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
1698 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
1699 if (i
->src(0).isIndirect(1)) {
1701 if (i
->src(0).isIndirect(0))
1702 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
1703 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
1704 i
->getIndirect(0, 0));
1706 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1707 i
->getIndirect(0, 1), bld
.mkImm(16));
1708 i
->setIndirect(0, 1, NULL
);
1709 i
->setIndirect(0, 0, ptr
);
1710 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
1716 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_GLOBAL
;
1718 handleCasExch(i
, cctl
);
1727 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1728 handleSurfaceOpNVE4(i
->asTex());
1737 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
1739 if (stage
== CG_STAGE_PRE_SSA
) {
1740 NVC0LoweringPass
pass(prog
);
1741 return pass
.run(prog
, false, true);
1743 if (stage
== CG_STAGE_POST_RA
) {
1744 NVC0LegalizePostRA
pass(prog
);
1745 return pass
.run(prog
, false, true);
1747 if (stage
== CG_STAGE_SSA
) {
1748 NVC0LegalizeSSA pass
;
1749 return pass
.run(prog
, false, true);
1754 } // namespace nv50_ir