2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
49 bld
.setPosition(i
, false);
51 // Generate movs to the input regs for the call we want to generate
52 for (int s
= 0; i
->srcExists(s
); ++s
) {
53 Instruction
*ld
= i
->getSrc(s
)->getInsn();
54 assert(ld
->getSrc(0) != NULL
);
55 // check if we are moving an immediate, propagate it in that case
56 if (!ld
|| ld
->fixed
|| (ld
->op
!= OP_LOAD
&& ld
->op
!= OP_MOV
) ||
57 !(ld
->src(0).getFile() == FILE_IMMEDIATE
))
58 bld
.mkMovToReg(s
, i
->getSrc(s
));
60 bld
.mkMovToReg(s
, ld
->getSrc(0));
61 // Clear the src, to make code elimination possible here before we
62 // delete the instruction i later
65 delete_Instruction(prog
, ld
);
70 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
71 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
75 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
76 bld
.mkMovFromReg(i
->getDef(0), i
->op
== OP_DIV
? 0 : 1);
77 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
78 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
81 call
->absolute
= call
->builtin
= 1;
82 call
->target
.builtin
= builtin
;
83 delete_Instruction(prog
, i
);
87 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
89 assert(i
->dType
== TYPE_F64
);
90 // There are instructions that will compute the high 32 bits of the 64-bit
91 // float. We will just stick 0 in the bottom 32 bits.
93 bld
.setPosition(i
, false);
95 // 1. Take the source and it up.
96 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
97 bld
.mkSplit(src
, 4, i
->getSrc(0));
99 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
100 dst
[0] = bld
.loadImm(NULL
, 0);
101 dst
[1] = bld
.getSSA();
103 // 3. The new version of the instruction takes the high 32 bits of the
104 // source and outputs the high 32 bits of the destination.
105 i
->setSrc(0, src
[1]);
106 i
->setDef(0, dst
[1]);
107 i
->setType(TYPE_F32
);
108 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
110 // 4. Recombine the two dst pieces back into the original destination.
111 bld
.setPosition(i
, true);
112 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
116 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
118 // Only want to flush float inputs
119 assert(i
->sType
== TYPE_F32
);
121 // If we're already flushing denorms (and NaN's) to zero, no need for this.
125 // Only certain classes of operations can flush
126 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
127 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
128 cls
!= OPCLASS_CONVERT
)
135 NVC0LegalizeSSA::handleTEXLOD(TexInstruction
*i
)
137 if (i
->tex
.levelZero
)
142 // The LOD argument comes right after the coordinates (before depth bias,
144 int arg
= i
->tex
.target
.getArgCount();
146 // SM30+ stores the indirect handle as a separate arg, which comes before
148 if (prog
->getTarget()->getChipset() >= NVISA_GK104_CHIPSET
&&
149 i
->tex
.rIndirectSrc
>= 0)
151 // SM20 stores indirect handle combined with array coordinate
152 if (prog
->getTarget()->getChipset() < NVISA_GK104_CHIPSET
&&
153 !i
->tex
.target
.isArray() &&
154 i
->tex
.rIndirectSrc
>= 0)
157 if (!i
->src(arg
).getImmediate(lod
) || !lod
.isInteger(0))
162 i
->tex
.levelZero
= true;
163 i
->moveSources(arg
+ 1, -1);
167 NVC0LegalizeSSA::handleShift(Instruction
*lo
)
169 Value
*shift
= lo
->getSrc(1);
170 Value
*dst64
= lo
->getDef(0);
171 Value
*src
[2], *dst
[2];
172 operation op
= lo
->op
;
174 bld
.setPosition(lo
, false);
176 bld
.mkSplit(src
, 4, lo
->getSrc(0));
178 // SM30 and prior don't have the fancy new SHF.L/R ops. So the logic has to
179 // be completely emulated. For SM35+, we can use the more directed SHF
181 if (prog
->getTarget()->getChipset() < NVISA_GK20A_CHIPSET
) {
182 // The strategy here is to handle shifts >= 32 and less than 32 as
186 // If the shift is <= 32, then
187 // (HI,LO) << x = (HI << x | (LO >> (32 - x)), LO << x)
188 // If the shift is > 32, then
189 // (HI,LO) << x = (LO << (x - 32), 0)
192 // If the shift is <= 32, then
193 // (HI,LO) >> x = (HI >> x, (HI << (32 - x)) | LO >> x)
194 // If the shift is > 32, then
195 // (HI,LO) >> x = (0, HI >> (x - 32))
197 // Note that on NVIDIA hardware, a shift > 32 yields a 0 value, which we
198 // can use to our advantage. Also note the structural similarities
199 // between the right/left cases. The main difference is swapping hi/lo
200 // on input and output.
202 Value
*x32_minus_shift
, *pred
, *hi1
, *hi2
;
203 DataType type
= isSignedIntType(lo
->dType
) ? TYPE_S32
: TYPE_U32
;
204 operation antiop
= op
== OP_SHR
? OP_SHL
: OP_SHR
;
206 std::swap(src
[0], src
[1]);
207 bld
.mkOp2(OP_ADD
, TYPE_U32
, (x32_minus_shift
= bld
.getSSA()), shift
, bld
.mkImm(0x20))
208 ->src(0).mod
= Modifier(NV50_IR_MOD_NEG
);
209 bld
.mkCmp(OP_SET
, CC_LE
, TYPE_U8
, (pred
= bld
.getSSA(1, FILE_PREDICATE
)),
210 TYPE_U32
, shift
, bld
.mkImm(32));
211 // Compute HI (shift <= 32)
212 bld
.mkOp2(OP_OR
, TYPE_U32
, (hi1
= bld
.getSSA()),
213 bld
.mkOp2v(op
, TYPE_U32
, bld
.getSSA(), src
[1], shift
),
214 bld
.mkOp2v(antiop
, TYPE_U32
, bld
.getSSA(), src
[0], x32_minus_shift
))
215 ->setPredicate(CC_P
, pred
);
216 // Compute LO (all shift values)
217 bld
.mkOp2(op
, type
, (dst
[0] = bld
.getSSA()), src
[0], shift
);
218 // Compute HI (shift > 32)
219 bld
.mkOp2(op
, type
, (hi2
= bld
.getSSA()), src
[0],
220 bld
.mkOp1v(OP_NEG
, TYPE_S32
, bld
.getSSA(), x32_minus_shift
))
221 ->setPredicate(CC_NOT_P
, pred
);
222 bld
.mkOp2(OP_UNION
, TYPE_U32
, (dst
[1] = bld
.getSSA()), hi1
, hi2
);
224 std::swap(dst
[0], dst
[1]);
225 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dst64
, dst
[0], dst
[1]);
226 delete_Instruction(prog
, lo
);
230 Instruction
*hi
= new_Instruction(func
, op
, TYPE_U32
);
231 lo
->bb
->insertAfter(lo
, hi
);
233 hi
->sType
= lo
->sType
;
234 lo
->dType
= TYPE_U32
;
236 hi
->setDef(0, (dst
[1] = bld
.getSSA()));
237 if (lo
->op
== OP_SHR
)
238 hi
->subOp
|= NV50_IR_SUBOP_SHIFT_HIGH
;
239 lo
->setDef(0, (dst
[0] = bld
.getSSA()));
241 bld
.setPosition(hi
, true);
243 if (lo
->op
== OP_SHL
)
246 hi
->setSrc(0, new_ImmediateValue(prog
, 0u));
247 hi
->setSrc(1, shift
);
248 hi
->setSrc(2, lo
->op
== OP_SHL
? src
[0] : src
[1]);
250 lo
->setSrc(0, src
[0]);
251 lo
->setSrc(1, shift
);
252 lo
->setSrc(2, src
[1]);
254 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dst64
, dst
[0], dst
[1]);
258 NVC0LegalizeSSA::handleSET(CmpInstruction
*cmp
)
260 DataType hTy
= cmp
->sType
== TYPE_S64
? TYPE_S32
: TYPE_U32
;
262 Value
*src0
[2], *src1
[2];
263 bld
.setPosition(cmp
, false);
265 bld
.mkSplit(src0
, 4, cmp
->getSrc(0));
266 bld
.mkSplit(src1
, 4, cmp
->getSrc(1));
267 bld
.mkOp2(OP_SUB
, hTy
, NULL
, src0
[0], src1
[0])
268 ->setFlagsDef(0, (carry
= bld
.getSSA(1, FILE_FLAGS
)));
269 cmp
->setFlagsSrc(cmp
->srcCount(), carry
);
270 cmp
->setSrc(0, src0
[1]);
271 cmp
->setSrc(1, src1
[1]);
276 NVC0LegalizeSSA::visit(Function
*fn
)
278 bld
.setProgram(fn
->getProgram());
283 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
286 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
289 if (i
->sType
== TYPE_F32
&& prog
->getType() != Program::TYPE_COMPUTE
)
295 if (i
->sType
!= TYPE_F32
)
300 if (i
->dType
== TYPE_F64
)
305 handleTEXLOD(i
->asTex());
309 if (typeSizeof(i
->sType
) == 8)
316 if (typeSizeof(i
->sType
) == 8 && i
->sType
!= TYPE_F64
)
317 handleSET(i
->asCmp());
326 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
330 needTexBar(prog
->getTarget()->getChipset() >= 0xe0 &&
331 prog
->getTarget()->getChipset() < 0x110)
336 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
337 const Instruction
*early
) const
339 if (early
->bb
== later
->bb
)
340 return early
->serial
< later
->serial
;
341 return later
->bb
->dominatedBy(early
->bb
);
345 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
346 Instruction
*usei
, const Instruction
*texi
)
349 bool dominated
= insnDominatedBy(usei
, texi
);
350 // Uses before the tex have to all be included. Just because an earlier
351 // instruction dominates another instruction doesn't mean that there's no
352 // way to get from the tex to the later instruction. For example you could
353 // have nested loops, with the tex in the inner loop, and uses before it in
354 // both loops - even though the outer loop's instruction would dominate the
355 // inner's, we still want a texbar before the inner loop's instruction.
357 // However we can still use the eliding logic between uses dominated by the
358 // tex instruction, as that is unambiguously correct.
360 for (std::list
<TexUse
>::iterator it
= uses
.begin(); it
!= uses
.end();) {
362 if (insnDominatedBy(usei
, it
->insn
)) {
366 if (insnDominatedBy(it
->insn
, usei
)) {
375 uses
.push_back(TexUse(usei
, texi
, dominated
));
378 // While it might be tempting to use the an algorithm that just looks at tex
379 // uses, not all texture results are guaranteed to be used on all paths. In
380 // the case where along some control flow path a texture result is never used,
381 // we might reuse that register for something else, creating a
382 // write-after-write hazard. So we have to manually look through all
383 // instructions looking for ones that reference the registers in question.
385 NVC0LegalizePostRA::findFirstUses(
386 Instruction
*texi
, std::list
<TexUse
> &uses
)
388 int minGPR
= texi
->def(0).rep()->reg
.data
.id
;
389 int maxGPR
= minGPR
+ texi
->def(0).rep()->reg
.size
/ 4 - 1;
391 unordered_set
<const BasicBlock
*> visited
;
392 findFirstUsesBB(minGPR
, maxGPR
, texi
->next
, texi
, uses
, visited
);
396 NVC0LegalizePostRA::findFirstUsesBB(
397 int minGPR
, int maxGPR
, Instruction
*start
,
398 const Instruction
*texi
, std::list
<TexUse
> &uses
,
399 unordered_set
<const BasicBlock
*> &visited
)
401 const BasicBlock
*bb
= start
->bb
;
403 // We don't process the whole bb the first time around. This is correct,
404 // however we might be in a loop and hit this BB again, and need to process
405 // the full thing. So only mark a bb as visited if we processed it from the
407 if (start
== bb
->getEntry()) {
408 if (visited
.find(bb
) != visited
.end())
413 for (Instruction
*insn
= start
; insn
!= bb
->getExit(); insn
= insn
->next
) {
417 for (int d
= 0; insn
->defExists(d
); ++d
) {
418 const Value
*def
= insn
->def(d
).rep();
419 if (insn
->def(d
).getFile() != FILE_GPR
||
420 def
->reg
.data
.id
+ def
->reg
.size
/ 4 - 1 < minGPR
||
421 def
->reg
.data
.id
> maxGPR
)
423 addTexUse(uses
, insn
, texi
);
427 for (int s
= 0; insn
->srcExists(s
); ++s
) {
428 const Value
*src
= insn
->src(s
).rep();
429 if (insn
->src(s
).getFile() != FILE_GPR
||
430 src
->reg
.data
.id
+ src
->reg
.size
/ 4 - 1 < minGPR
||
431 src
->reg
.data
.id
> maxGPR
)
433 addTexUse(uses
, insn
, texi
);
438 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
439 findFirstUsesBB(minGPR
, maxGPR
, BasicBlock::get(ei
.getNode())->getEntry(),
440 texi
, uses
, visited
);
445 // This pass is a bit long and ugly and can probably be optimized.
447 // 1. obtain a list of TEXes and their outputs' first use(s)
448 // 2. calculate the barrier level of each first use (minimal number of TEXes,
449 // over all paths, between the TEX and the use in question)
450 // 3. for each barrier, if all paths from the source TEX to that barrier
451 // contain a barrier of lesser level, it can be culled
453 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
455 std::list
<TexUse
> *uses
;
456 std::vector
<Instruction
*> texes
;
457 std::vector
<int> bbFirstTex
;
458 std::vector
<int> bbFirstUse
;
459 std::vector
<int> texCounts
;
460 std::vector
<TexUse
> useVec
;
463 fn
->orderInstructions(insns
);
465 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
466 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
467 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
469 // tag BB CFG nodes by their id for later
470 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
471 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
473 bb
->cfg
.tag
= bb
->getId();
476 // gather the first uses for each TEX
477 for (int i
= 0; i
< insns
.getSize(); ++i
) {
478 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
479 if (isTextureOp(tex
->op
)) {
480 texes
.push_back(tex
);
481 if (!texCounts
.at(tex
->bb
->getId()))
482 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
483 texCounts
[tex
->bb
->getId()]++;
489 uses
= new std::list
<TexUse
>[texes
.size()];
492 for (size_t i
= 0; i
< texes
.size(); ++i
) {
493 findFirstUses(texes
[i
], uses
[i
]);
496 // determine the barrier level at each use
497 for (size_t i
= 0; i
< texes
.size(); ++i
) {
498 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
500 BasicBlock
*tb
= texes
[i
]->bb
;
501 BasicBlock
*ub
= u
->insn
->bb
;
504 for (size_t j
= i
+ 1; j
< texes
.size() &&
505 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
509 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
510 &ub
->cfg
, texCounts
);
512 WARN("Failed to find path TEX -> TEXBAR\n");
516 // this counted all TEXes in the origin block, correct that
517 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
518 // and did not count the TEXes in the destination block, add those
519 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
520 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
524 assert(u
->level
>= 0);
525 useVec
.push_back(*u
);
530 // insert the barriers
531 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
532 Instruction
*prev
= useVec
[i
].insn
->prev
;
533 if (useVec
[i
].level
< 0)
535 if (prev
&& prev
->op
== OP_TEXBAR
) {
536 if (prev
->subOp
> useVec
[i
].level
)
537 prev
->subOp
= useVec
[i
].level
;
538 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
540 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
542 bar
->subOp
= useVec
[i
].level
;
543 // make use explicit to ease latency calculation
544 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
545 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
549 if (fn
->getProgram()->optLevel
< 3)
552 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
554 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
555 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
556 limitS
.resize(fn
->allBBlocks
.getSize());
558 // cull unneeded barriers (should do that earlier, but for simplicity)
559 IteratorRef bi
= fn
->cfg
.iteratorCFG();
560 // first calculate min/max outstanding TEXes for each BB
561 for (bi
->reset(); !bi
->end(); bi
->next()) {
562 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
563 BasicBlock
*bb
= BasicBlock::get(n
);
565 int max
= std::numeric_limits
<int>::max();
566 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
567 if (isTextureOp(i
->op
)) {
569 if (max
< std::numeric_limits
<int>::max())
572 if (i
->op
== OP_TEXBAR
) {
573 min
= MIN2(min
, i
->subOp
);
574 max
= MIN2(max
, i
->subOp
);
577 // limits when looking at an isolated block
578 limitS
[bb
->getId()].min
= min
;
579 limitS
[bb
->getId()].max
= max
;
581 // propagate the min/max values
582 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
583 for (bi
->reset(); !bi
->end(); bi
->next()) {
584 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
585 BasicBlock
*bb
= BasicBlock::get(n
);
586 const int bbId
= bb
->getId();
587 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
588 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
589 const int inId
= in
->getId();
590 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
591 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
593 // I just hope this is correct ...
594 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
596 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
597 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
599 // block contained a barrier
600 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
601 limitT
[bbId
].min
+ limitS
[bbId
].min
);
602 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
603 limitT
[bbId
].max
+ limitS
[bbId
].min
);
607 // finally delete unnecessary barriers
608 for (bi
->reset(); !bi
->end(); bi
->next()) {
609 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
610 BasicBlock
*bb
= BasicBlock::get(n
);
611 Instruction
*prev
= NULL
;
613 int max
= limitT
[bb
->getId()].max
;
614 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
616 if (i
->op
== OP_TEXBAR
) {
617 if (i
->subOp
>= max
) {
618 delete_Instruction(prog
, i
);
622 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
623 delete_Instruction(prog
, prev
);
628 if (isTextureOp(i
->op
)) {
631 if (i
&& !i
->isNop())
639 NVC0LegalizePostRA::visit(Function
*fn
)
642 insertTextureBarriers(fn
);
644 rZero
= new_LValue(fn
, FILE_GPR
);
645 pOne
= new_LValue(fn
, FILE_PREDICATE
);
646 carry
= new_LValue(fn
, FILE_FLAGS
);
648 rZero
->reg
.data
.id
= (prog
->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET
) ? 255 : 63;
649 carry
->reg
.data
.id
= 0;
650 pOne
->reg
.data
.id
= 7;
656 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
658 for (int s
= 0; i
->srcExists(s
); ++s
) {
659 if (s
== 2 && i
->op
== OP_SUCLAMP
)
661 if (s
== 1 && i
->op
== OP_SHLADD
)
663 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
665 if (i
->op
== OP_SELP
&& s
== 2) {
667 if (imm
->reg
.data
.u64
== 0)
668 i
->src(s
).mod
= i
->src(s
).mod
^ Modifier(NV50_IR_MOD_NOT
);
669 } else if (imm
->reg
.data
.u64
== 0) {
676 // replace CONT with BRA for single unconditional continue
678 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
680 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
682 Graph::EdgeIterator ei
= bb
->cfg
.incident();
683 if (ei
.getType() != Graph::Edge::BACK
)
685 if (ei
.getType() != Graph::Edge::BACK
)
687 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
689 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
690 contBB
->getExit()->getPredicate())
692 contBB
->getExit()->op
= OP_BRA
;
693 bb
->remove(bb
->getEntry()); // delete PRECONT
696 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
700 // replace branches to join blocks with join ops
702 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
704 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
706 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
707 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
708 Instruction
*exit
= in
->getExit();
710 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
711 // there should always be a terminator instruction
712 WARN("inserted missing terminator in BB:%i\n", in
->getId());
714 if (exit
->op
== OP_BRA
) {
716 exit
->asFlow()->limit
= 1; // must-not-propagate marker
719 bb
->remove(bb
->getEntry());
723 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
725 Instruction
*i
, *next
;
727 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
728 for (i
= bb
->getFirst(); i
; i
= next
) {
730 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
731 if (!i
->getDef(0)->refCount())
733 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
734 i
->setSrc(0, rZero
); // initial value must be 0
740 if (i
->op
== OP_BAR
&& i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
&&
741 prog
->getType() != Program::TYPE_COMPUTE
) {
742 // It seems like barriers are never required for tessellation since
743 // the warp size is 32, and there are always at most 32 tcs threads.
746 if (i
->op
== OP_LOAD
&& i
->subOp
== NV50_IR_SUBOP_LDC_IS
) {
747 int offset
= i
->src(0).get()->reg
.data
.offset
;
748 if (abs(offset
) >= 0x10000)
749 i
->src(0).get()->reg
.fileIndex
+= offset
>> 16;
750 i
->src(0).get()->reg
.data
.offset
= (int)(short)offset
;
752 // TODO: Move this to before register allocation for operations that
753 // need the $c register !
754 if (typeSizeof(i
->sType
) == 8 || typeSizeof(i
->dType
) == 8) {
756 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
761 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
768 if (!tryReplaceContWithBra(bb
))
774 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
776 bld
.setProgram(prog
);
780 NVC0LoweringPass::visit(Function
*fn
)
782 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
783 assert(!strncmp(fn
->getName(), "MAIN", 4));
784 // TODO: when we generate actual functions pass this value along somehow
785 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
786 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
788 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
789 bld
.mkMovToReg(0, gpEmitAddress
);
796 NVC0LoweringPass::visit(BasicBlock
*bb
)
802 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
804 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
805 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
808 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(2));
811 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
814 // move array source to first slot, convert to u16, add indirections
816 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
818 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
819 const int arg
= i
->tex
.target
.getArgCount();
820 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
821 const int chipset
= prog
->getTarget()->getChipset();
823 /* Only normalize in the non-explicit derivatives case. For explicit
824 * derivatives, this is handled in handleManualTXD.
826 if (i
->tex
.target
.isCube() && i
->dPdx
[0].get() == NULL
) {
829 for (c
= 0; c
< 3; ++c
)
830 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), i
->getSrc(c
));
831 val
= bld
.getScratch();
832 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
833 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
834 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
835 for (c
= 0; c
< 3; ++c
) {
836 i
->setSrc(c
, bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(),
841 // Arguments to the TEX instruction are a little insane. Even though the
842 // encoding is identical between SM20 and SM30, the arguments mean
843 // different things between Fermi and Kepler+. A lot of arguments are
844 // optional based on flags passed to the instruction. This summarizes the
854 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
855 // - other: 4 bits each, single reg
859 // array (+ offsets for txd in upper 16 bits)
864 // offsets (same as fermi, except txd which takes it with array)
881 if (chipset
>= NVISA_GK104_CHIPSET
) {
882 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
883 // XXX this ignores tsc, and assumes a 1:1 mapping
884 assert(i
->tex
.rIndirectSrc
>= 0);
885 if (!i
->tex
.bindless
) {
886 Value
*hnd
= loadTexHandle(i
->getIndirectR(), i
->tex
.r
);
889 i
->setIndirectR(hnd
);
891 i
->setIndirectS(NULL
);
892 } else if (i
->tex
.r
== i
->tex
.s
|| i
->op
== OP_TXF
) {
893 if (i
->tex
.r
== 0xffff)
894 i
->tex
.r
= prog
->driver
->io
.fbtexBindBase
/ 4;
896 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
897 i
->tex
.s
= 0; // only a single cX[] value possible here
899 Value
*hnd
= bld
.getScratch();
900 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
901 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
903 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
905 i
->tex
.r
= 0; // not used for indirect tex
907 i
->setIndirectR(hnd
);
909 if (i
->tex
.target
.isArray()) {
910 LValue
*layer
= new_LValue(func
, FILE_GPR
);
911 Value
*src
= i
->getSrc(lyr
);
912 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
913 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
914 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
915 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
916 for (int s
= dim
; s
>= 1; --s
)
917 i
->setSrc(s
, i
->getSrc(s
- 1));
920 i
->setSrc(dim
, layer
);
923 // Move the indirect reference to the first place
924 if (i
->tex
.rIndirectSrc
>= 0 && (
925 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
926 Value
*hnd
= i
->getIndirectR();
928 i
->setIndirectR(NULL
);
929 i
->moveSources(0, 1);
931 i
->tex
.rIndirectSrc
= 0;
932 i
->tex
.sIndirectSrc
= -1;
934 // Move the indirect reference to right after the coords
935 else if (i
->tex
.rIndirectSrc
>= 0 && chipset
>= NVISA_GM107_CHIPSET
) {
936 Value
*hnd
= i
->getIndirectR();
938 i
->setIndirectR(NULL
);
939 i
->moveSources(arg
, 1);
941 i
->tex
.rIndirectSrc
= 0;
942 i
->tex
.sIndirectSrc
= -1;
945 // (nvc0) generate and move the tsc/tic/array source to the front
946 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
947 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
949 Value
*ticRel
= i
->getIndirectR();
950 Value
*tscRel
= i
->getIndirectS();
952 if (i
->tex
.r
== 0xffff) {
958 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
960 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
961 ticRel
, bld
.mkImm(i
->tex
.r
));
964 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
966 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
967 tscRel
, bld
.mkImm(i
->tex
.s
));
970 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
972 for (int s
= dim
; s
>= 1; --s
)
973 i
->setSrc(s
, i
->getSrc(s
- 1));
974 i
->setSrc(0, arrayIndex
);
976 i
->moveSources(0, 1);
980 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
981 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
982 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
988 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
990 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
995 // For nvc0, the sample id has to be in the second operand, as the offset
996 // does. Right now we don't know how to pass both in, and this case can't
997 // happen with OpenGL. On nve0, the sample id is part of the texture
998 // coordinate argument.
999 assert(chipset
>= NVISA_GK104_CHIPSET
||
1000 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
1002 // offset is between lod and dc
1003 if (i
->tex
.useOffsets
) {
1005 int s
= i
->srcCount(0xff, true);
1006 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
1007 if (i
->tex
.target
.isShadow())
1009 if (i
->srcExists(s
)) // move potential predicate out of the way
1010 i
->moveSources(s
, 1);
1011 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
1012 i
->moveSources(s
+ 1, 1);
1014 if (i
->op
== OP_TXG
) {
1015 // Either there is 1 offset, which goes into the 2 low bytes of the
1016 // first source, or there are 4 offsets, which go into 2 sources (8
1017 // values, 1 byte each).
1018 Value
*offs
[2] = {NULL
, NULL
};
1019 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
1020 for (c
= 0; c
< 2; ++c
) {
1021 if ((n
% 2) == 0 && c
== 0)
1022 bld
.mkMov(offs
[n
/ 2] = bld
.getScratch(), i
->offset
[n
][c
].get());
1024 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
1026 i
->offset
[n
][c
].get(),
1027 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
1031 i
->setSrc(s
, offs
[0]);
1033 i
->setSrc(s
+ 1, offs
[1]);
1036 assert(i
->tex
.useOffsets
== 1);
1037 for (c
= 0; c
< 3; ++c
) {
1039 if (!i
->offset
[0][c
].getImmediate(val
))
1040 assert(!"non-immediate offset passed to non-TXG");
1041 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
1043 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
1044 // The offset goes into the upper 16 bits of the array index. So
1045 // create it if it's not already there, and INSBF it if it already
1047 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
1048 if (chipset
>= NVISA_GM107_CHIPSET
)
1050 if (i
->tex
.target
.isArray()) {
1051 Value
*offset
= bld
.getScratch();
1052 bld
.mkOp3(OP_INSBF
, TYPE_U32
, offset
,
1053 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
1055 i
->setSrc(s
, offset
);
1057 i
->moveSources(s
, 1);
1058 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
1061 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
1066 if (chipset
>= NVISA_GK104_CHIPSET
) {
1068 // If TEX requires more than 4 sources, the 2nd register tuple must be
1069 // aligned to 4, even if it consists of just a single 4-byte register.
1071 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
1073 int s
= i
->srcCount(0xff, true);
1074 if (s
> 4 && s
< 7) {
1075 if (i
->srcExists(s
)) // move potential predicate out of the way
1076 i
->moveSources(s
, 7 - s
);
1078 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
1086 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
1088 // Always done from the l0 perspective. This is the way that NVIDIA's
1089 // driver does it, and doing it from the "current" lane's perpsective
1090 // doesn't seem to always work for reasons that aren't altogether clear,
1091 // even in frag shaders.
1093 // Note that we must move not only the coordinates into lane0, but also all
1094 // ancillary arguments, like array indices and depth compare as they may
1095 // differ between lanes. Offsets for TXD are supposed to be uniform, so we
1096 // leave them alone.
1097 static const uint8_t qOps
[2] =
1098 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) };
1101 Value
*crd
[3], *arr
[2], *shadow
;
1103 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
1105 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
1107 // This function is invoked after handleTEX lowering, so we have to expect
1108 // the arguments in the order that the hw wants them. For Fermi, array and
1109 // indirect are both in the leading arg, while for Kepler, array and
1110 // indirect are separate (and both precede the coordinates). Maxwell is
1111 // handled in a separate function.
1113 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
1114 array
= i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0;
1116 array
= i
->tex
.target
.isArray() + (i
->tex
.rIndirectSrc
>= 0);
1118 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
1120 for (c
= 0; c
< dim
; ++c
)
1121 crd
[c
] = bld
.getScratch();
1122 for (c
= 0; c
< array
; ++c
)
1123 arr
[c
] = bld
.getScratch();
1124 shadow
= bld
.getScratch();
1126 for (l
= 0; l
< 4; ++l
) {
1127 Value
*src
[3], *val
;
1129 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
1130 // we're using the texture result from lane 0 in all cases, so make sure
1131 // that lane 0 is pointing at the proper array index, indirect value,
1132 // and depth compare.
1134 for (c
= 0; c
< array
; ++c
)
1135 bld
.mkQuadop(0x00, arr
[c
], l
, i
->getSrc(c
), zero
);
1136 if (i
->tex
.target
.isShadow()) {
1137 // The next argument after coords is the depth compare
1138 bld
.mkQuadop(0x00, shadow
, l
, i
->getSrc(array
+ dim
), zero
);
1141 // mov position coordinates from lane l to all lanes
1142 for (c
= 0; c
< dim
; ++c
)
1143 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
1144 // add dPdx from lane l to lanes dx
1145 for (c
= 0; c
< dim
; ++c
)
1146 bld
.mkQuadop(qOps
[0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
1147 // add dPdy from lane l to lanes dy
1148 for (c
= 0; c
< dim
; ++c
)
1149 bld
.mkQuadop(qOps
[1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
1150 // normalize cube coordinates
1151 if (i
->tex
.target
.isCube()) {
1152 for (c
= 0; c
< 3; ++c
)
1153 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), crd
[c
]);
1154 val
= bld
.getScratch();
1155 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
1156 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
1157 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
1158 for (c
= 0; c
< 3; ++c
)
1159 src
[c
] = bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(), crd
[c
], val
);
1161 for (c
= 0; c
< dim
; ++c
)
1165 bld
.insert(tex
= cloneForward(func
, i
));
1167 for (c
= 0; c
< array
; ++c
)
1168 tex
->setSrc(c
, arr
[c
]);
1169 if (i
->tex
.target
.isShadow())
1170 tex
->setSrc(array
+ dim
, shadow
);
1172 for (c
= 0; c
< dim
; ++c
)
1173 tex
->setSrc(c
+ array
, src
[c
]);
1174 // broadcast results from lane 0 to all lanes so that the moves *into*
1175 // the target lane pick up the proper value.
1177 for (c
= 0; i
->defExists(c
); ++c
)
1178 bld
.mkQuadop(0x00, tex
->getDef(c
), 0, tex
->getDef(c
), zero
);
1179 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
1182 for (c
= 0; i
->defExists(c
); ++c
) {
1184 def
[c
][l
] = bld
.getSSA();
1185 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
1187 mov
->lanes
= 1 << l
;
1191 for (c
= 0; i
->defExists(c
); ++c
) {
1192 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
1193 for (l
= 0; l
< 4; ++l
)
1194 u
->setSrc(l
, def
[c
][l
]);
1202 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
1204 int dim
= txd
->tex
.target
.getDim() + txd
->tex
.target
.isCube();
1205 unsigned arg
= txd
->tex
.target
.getArgCount();
1206 unsigned expected_args
= arg
;
1207 const int chipset
= prog
->getTarget()->getChipset();
1209 if (chipset
>= NVISA_GK104_CHIPSET
) {
1210 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
1212 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
1215 if (txd
->tex
.useOffsets
)
1217 if (!txd
->tex
.target
.isArray() && (
1218 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
1222 if (expected_args
> 4 ||
1224 txd
->tex
.target
.isShadow())
1228 while (txd
->srcExists(arg
))
1231 txd
->tex
.derivAll
= true;
1232 if (txd
->op
== OP_TEX
)
1233 return handleManualTXD(txd
);
1235 assert(arg
== expected_args
);
1236 for (int c
= 0; c
< dim
; ++c
) {
1237 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
1238 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
1239 txd
->dPdx
[c
].set(NULL
);
1240 txd
->dPdy
[c
].set(NULL
);
1243 // In this case we have fewer than 4 "real" arguments, which means that
1244 // handleTEX didn't apply any padding. However we have to make sure that
1245 // the second "group" of arguments still gets padded up to 4.
1246 if (chipset
>= NVISA_GK104_CHIPSET
) {
1247 int s
= arg
+ 2 * dim
;
1248 if (s
>= 4 && s
< 7) {
1249 if (txd
->srcExists(s
)) // move potential predicate out of the way
1250 txd
->moveSources(s
, 7 - s
);
1252 txd
->setSrc(s
++, bld
.loadImm(NULL
, 0));
1260 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
1262 const int chipset
= prog
->getTarget()->getChipset();
1263 if (chipset
>= NVISA_GK104_CHIPSET
&& txq
->tex
.rIndirectSrc
< 0)
1264 txq
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
1266 if (txq
->tex
.rIndirectSrc
< 0)
1269 Value
*ticRel
= txq
->getIndirectR();
1271 txq
->setIndirectS(NULL
);
1272 txq
->tex
.sIndirectSrc
= -1;
1276 if (chipset
< NVISA_GK104_CHIPSET
) {
1277 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
1279 txq
->setSrc(txq
->tex
.rIndirectSrc
, NULL
);
1281 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
1282 ticRel
, bld
.mkImm(txq
->tex
.r
));
1284 bld
.mkOp2(OP_SHL
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x17));
1286 txq
->moveSources(0, 1);
1287 txq
->setSrc(0, src
);
1289 Value
*hnd
= loadTexHandle(txq
->getIndirectR(), txq
->tex
.r
);
1293 txq
->setIndirectR(NULL
);
1294 txq
->moveSources(0, 1);
1295 txq
->setSrc(0, hnd
);
1296 txq
->tex
.rIndirectSrc
= 0;
1303 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
1305 /* The outputs are inverted compared to what the TGSI instruction
1306 * expects. Take that into account in the mask.
1308 assert((i
->tex
.mask
& ~3) == 0);
1309 if (i
->tex
.mask
== 1)
1311 else if (i
->tex
.mask
== 2)
1314 bld
.setPosition(i
, true);
1316 /* The returned values are not quite what we want:
1317 * (a) convert from s16/u16 to f32
1318 * (b) multiply by 1/256
1320 for (int def
= 0; def
< 2; ++def
) {
1321 if (!i
->defExists(def
))
1323 enum DataType type
= TYPE_S16
;
1324 if (i
->tex
.mask
== 2 || def
> 0)
1326 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
1327 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
1328 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
1330 if (i
->tex
.mask
== 3) {
1331 LValue
*t
= new_LValue(func
, FILE_GPR
);
1332 bld
.mkMov(t
, i
->getDef(0));
1333 bld
.mkMov(i
->getDef(0), i
->getDef(1));
1334 bld
.mkMov(i
->getDef(1), t
);
1340 NVC0LoweringPass::handleBUFQ(Instruction
*bufq
)
1343 bufq
->setSrc(0, loadBufLength32(bufq
->getIndirect(0, 1),
1344 bufq
->getSrc(0)->reg
.fileIndex
* 16));
1345 bufq
->setIndirect(0, 0, NULL
);
1346 bufq
->setIndirect(0, 1, NULL
);
1351 NVC0LoweringPass::handleSharedATOMNVE4(Instruction
*atom
)
1353 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1355 BasicBlock
*currBB
= atom
->bb
;
1356 BasicBlock
*tryLockBB
= atom
->bb
->splitBefore(atom
, false);
1357 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1358 BasicBlock
*setAndUnlockBB
= new BasicBlock(func
);
1359 BasicBlock
*failLockBB
= new BasicBlock(func
);
1361 bld
.setPosition(currBB
, true);
1362 assert(!currBB
->joinAt
);
1363 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1365 CmpInstruction
*pred
=
1366 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1367 TYPE_U32
, bld
.mkImm(0), bld
.mkImm(1));
1369 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_ALWAYS
, NULL
);
1370 currBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::TREE
);
1372 bld
.setPosition(tryLockBB
, true);
1375 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1376 atom
->getIndirect(0, 0));
1377 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1378 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1380 bld
.mkFlow(OP_BRA
, setAndUnlockBB
, CC_P
, ld
->getDef(1));
1381 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1382 tryLockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::CROSS
);
1383 tryLockBB
->cfg
.attach(&setAndUnlockBB
->cfg
, Graph::Edge::TREE
);
1385 tryLockBB
->cfg
.detach(&joinBB
->cfg
);
1388 bld
.setPosition(setAndUnlockBB
, true);
1390 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1391 // Read the old value, and write the new one.
1392 stVal
= atom
->getSrc(1);
1393 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1394 CmpInstruction
*set
=
1395 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(),
1396 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1398 bld
.mkCmp(OP_SLCT
, CC_NE
, TYPE_U32
, (stVal
= bld
.getSSA()),
1399 TYPE_U32
, atom
->getSrc(2), ld
->getDef(0), set
->getDef(0));
1403 switch (atom
->subOp
) {
1404 case NV50_IR_SUBOP_ATOM_ADD
:
1407 case NV50_IR_SUBOP_ATOM_AND
:
1410 case NV50_IR_SUBOP_ATOM_OR
:
1413 case NV50_IR_SUBOP_ATOM_XOR
:
1416 case NV50_IR_SUBOP_ATOM_MIN
:
1419 case NV50_IR_SUBOP_ATOM_MAX
:
1427 stVal
= bld
.mkOp2v(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1432 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1433 atom
->getIndirect(0, 0), stVal
);
1434 st
->setDef(0, pred
->getDef(0));
1435 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1437 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1438 setAndUnlockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::TREE
);
1440 // Lock until the store has not been performed.
1441 bld
.setPosition(failLockBB
, true);
1442 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_NOT_P
, pred
->getDef(0));
1443 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1444 failLockBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::BACK
);
1445 failLockBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::TREE
);
1447 bld
.setPosition(joinBB
, false);
1448 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1452 NVC0LoweringPass::handleSharedATOM(Instruction
*atom
)
1454 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1456 BasicBlock
*currBB
= atom
->bb
;
1457 BasicBlock
*tryLockAndSetBB
= atom
->bb
->splitBefore(atom
, false);
1458 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1460 bld
.setPosition(currBB
, true);
1461 assert(!currBB
->joinAt
);
1462 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1464 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_ALWAYS
, NULL
);
1465 currBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::TREE
);
1467 bld
.setPosition(tryLockAndSetBB
, true);
1470 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1471 atom
->getIndirect(0, 0));
1472 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1473 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1476 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1477 // Read the old value, and write the new one.
1478 stVal
= atom
->getSrc(1);
1479 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1480 CmpInstruction
*set
=
1481 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1482 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1483 set
->setPredicate(CC_P
, ld
->getDef(1));
1486 bld
.mkOp3(OP_SELP
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
1487 atom
->getSrc(2), set
->getDef(0));
1488 selp
->src(2).mod
= Modifier(NV50_IR_MOD_NOT
);
1489 selp
->setPredicate(CC_P
, ld
->getDef(1));
1491 stVal
= selp
->getDef(0);
1495 switch (atom
->subOp
) {
1496 case NV50_IR_SUBOP_ATOM_ADD
:
1499 case NV50_IR_SUBOP_ATOM_AND
:
1502 case NV50_IR_SUBOP_ATOM_OR
:
1505 case NV50_IR_SUBOP_ATOM_XOR
:
1508 case NV50_IR_SUBOP_ATOM_MIN
:
1511 case NV50_IR_SUBOP_ATOM_MAX
:
1520 bld
.mkOp2(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1522 i
->setPredicate(CC_P
, ld
->getDef(1));
1524 stVal
= i
->getDef(0);
1528 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1529 atom
->getIndirect(0, 0), stVal
);
1530 st
->setPredicate(CC_P
, ld
->getDef(1));
1531 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1533 // Loop until the lock is acquired.
1534 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_NOT_P
, ld
->getDef(1));
1535 tryLockAndSetBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::BACK
);
1536 tryLockAndSetBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::CROSS
);
1537 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1541 bld
.setPosition(joinBB
, false);
1542 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1546 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1549 Value
*ptr
= atom
->getIndirect(0, 0), *ind
= atom
->getIndirect(0, 1), *base
;
1551 switch (atom
->src(0).getFile()) {
1552 case FILE_MEMORY_LOCAL
:
1555 case FILE_MEMORY_SHARED
:
1556 // For Fermi/Kepler, we have to use ld lock/st unlock to perform atomic
1557 // operations on shared memory. For Maxwell, ATOMS is enough.
1558 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
1559 handleSharedATOM(atom
);
1560 else if (targ
->getChipset() < NVISA_GM107_CHIPSET
)
1561 handleSharedATOMNVE4(atom
);
1564 assert(atom
->src(0).getFile() == FILE_MEMORY_BUFFER
);
1565 base
= loadBufInfo64(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1566 assert(base
->reg
.size
== 8);
1568 base
= bld
.mkOp2v(OP_ADD
, TYPE_U64
, base
, base
, ptr
);
1569 assert(base
->reg
.size
== 8);
1570 atom
->setIndirect(0, 0, base
);
1571 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1573 // Harden against out-of-bounds accesses
1574 Value
*offset
= bld
.loadImm(NULL
, atom
->getSrc(0)->reg
.data
.offset
+ typeSizeof(atom
->sType
));
1575 Value
*length
= loadBufLength32(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1576 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
1578 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, ptr
);
1579 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
1580 atom
->setPredicate(CC_NOT_P
, pred
);
1581 if (atom
->defExists(0)) {
1582 Value
*zero
, *dst
= atom
->getDef(0);
1583 atom
->setDef(0, bld
.getSSA());
1585 bld
.setPosition(atom
, true);
1586 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
1587 ->setPredicate(CC_P
, pred
);
1588 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, atom
->getDef(0), zero
);
1594 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1596 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1597 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1599 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1600 atom
->setIndirect(0, 1, NULL
);
1601 atom
->setIndirect(0, 0, base
);
1607 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1609 if (targ
->getChipset() < NVISA_GM107_CHIPSET
) {
1610 if (cas
->src(0).getFile() == FILE_MEMORY_SHARED
) {
1611 // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
1616 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1617 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1619 bld
.setPosition(cas
, true);
1622 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1623 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1625 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1626 if (cas
->isPredicated())
1627 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1630 if (cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1631 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1632 // should be set to the high part of the double reg or bad things will
1633 // happen elsewhere in the universe.
1634 // Also, it sometimes returns the new value instead of the old one
1635 // under mysterious circumstances.
1636 Value
*dreg
= bld
.getSSA(8);
1637 bld
.setPosition(cas
, false);
1638 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1639 cas
->setSrc(1, dreg
);
1640 cas
->setSrc(2, dreg
);
1647 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
, uint16_t base
)
1649 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1653 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1657 NVC0LoweringPass::loadResInfo64(Value
*ptr
, uint32_t off
, uint16_t base
)
1659 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1663 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1666 mkLoadv(TYPE_U64
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
), ptr
);
1670 NVC0LoweringPass::loadResLength32(Value
*ptr
, uint32_t off
, uint16_t base
)
1672 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1676 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1679 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
+ 8), ptr
);
1683 NVC0LoweringPass::loadBufInfo64(Value
*ptr
, uint32_t off
)
1685 return loadResInfo64(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1689 NVC0LoweringPass::loadBufLength32(Value
*ptr
, uint32_t off
)
1691 return loadResLength32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1695 NVC0LoweringPass::loadUboInfo64(Value
*ptr
, uint32_t off
)
1697 return loadResInfo64(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1701 NVC0LoweringPass::loadUboLength32(Value
*ptr
, uint32_t off
)
1703 return loadResLength32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1707 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1709 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1710 off
+= prog
->driver
->io
.msInfoBase
;
1712 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1716 NVC0LoweringPass::loadSuInfo32(Value
*ptr
, int slot
, uint32_t off
, bool bindless
)
1718 uint32_t base
= slot
* NVC0_SU_INFO__STRIDE
;
1721 ptr
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(slot
));
1723 ptr
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(511));
1725 ptr
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(7));
1726 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(6));
1731 return loadResInfo32(ptr
, off
, bindless
? prog
->driver
->io
.bindlessBase
:
1732 prog
->driver
->io
.suInfoBase
);
1735 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1737 switch (su
->tex
.target
.getEnum()) {
1738 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1739 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1740 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1741 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1742 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1743 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1744 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1745 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1746 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1747 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1748 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1749 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1750 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1758 NVC0LoweringPass::handleSUQ(TexInstruction
*suq
)
1760 int mask
= suq
->tex
.mask
;
1761 int dim
= suq
->tex
.target
.getDim();
1762 int arg
= dim
+ (suq
->tex
.target
.isArray() || suq
->tex
.target
.isCube());
1763 Value
*ind
= suq
->getIndirectR();
1764 int slot
= suq
->tex
.r
;
1767 for (c
= 0, d
= 0; c
< 3; ++c
, mask
>>= 1) {
1768 if (c
>= arg
|| !(mask
& 1))
1773 if (c
== 1 && suq
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1774 offset
= NVC0_SU_INFO_SIZE(2);
1776 offset
= NVC0_SU_INFO_SIZE(c
);
1778 bld
.mkMov(suq
->getDef(d
++), loadSuInfo32(ind
, slot
, offset
, suq
->tex
.bindless
));
1779 if (c
== 2 && suq
->tex
.target
.isCube())
1780 bld
.mkOp2(OP_DIV
, TYPE_U32
, suq
->getDef(d
- 1), suq
->getDef(d
- 1),
1781 bld
.loadImm(NULL
, 6));
1785 if (suq
->tex
.target
.isMS()) {
1786 Value
*ms_x
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(0), suq
->tex
.bindless
);
1787 Value
*ms_y
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(1), suq
->tex
.bindless
);
1788 Value
*ms
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(), ms_x
, ms_y
);
1789 bld
.mkOp2(OP_SHL
, TYPE_U32
, suq
->getDef(d
++), bld
.loadImm(NULL
, 1), ms
);
1791 bld
.mkMov(suq
->getDef(d
++), bld
.loadImm(NULL
, 1));
1800 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1802 const int arg
= tex
->tex
.target
.getArgCount();
1803 int slot
= tex
->tex
.r
;
1805 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1806 tex
->tex
.target
= TEX_TARGET_2D
;
1808 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1809 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1813 Value
*x
= tex
->getSrc(0);
1814 Value
*y
= tex
->getSrc(1);
1815 Value
*s
= tex
->getSrc(arg
- 1);
1817 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1818 Value
*ind
= tex
->getIndirectR();
1820 Value
*ms_x
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(0), tex
->tex
.bindless
);
1821 Value
*ms_y
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_MS(1), tex
->tex
.bindless
);
1823 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1824 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1826 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1827 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1829 Value
*dx
= loadMsInfo32(ts
, 0x0);
1830 Value
*dy
= loadMsInfo32(ts
, 0x4);
1832 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1833 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1837 tex
->moveSources(arg
, -1);
1840 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1841 // They're computed from the coordinates using the surface info in c[] space.
1843 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1846 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1848 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1849 const int slot
= su
->tex
.r
;
1850 const int dim
= su
->tex
.target
.getDim();
1851 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
1853 Value
*zero
= bld
.mkImm(0);
1857 Value
*bf
, *eau
, *off
;
1859 Value
*ind
= su
->getIndirectR();
1861 off
= bld
.getScratch(4);
1862 bf
= bld
.getScratch(4);
1863 addr
= bld
.getSSA(8);
1864 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1866 bld
.setPosition(su
, false);
1868 adjustCoordinatesMS(su
);
1870 // calculate clamped coordinates
1871 for (c
= 0; c
< arg
; ++c
) {
1874 if (c
== 1 && su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1875 // The array index is stored in the Z component for 1D arrays.
1879 src
[c
] = bld
.getScratch();
1881 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_RAW_X
, su
->tex
.bindless
);
1883 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_DIM(dimc
), su
->tex
.bindless
);
1884 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1885 ->subOp
= getSuClampSubOp(su
, dimc
);
1890 // set predicate output
1891 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1892 src
[0]->getInsn()->setFlagsDef(1, pred
);
1894 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1895 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1896 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1899 // calculate pixel offset
1901 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1902 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1905 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_UNK1C
, su
->tex
.bindless
);
1906 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1907 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1909 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_PITCH
, su
->tex
.bindless
);
1910 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1911 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1914 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_PITCH
, su
->tex
.bindless
);
1915 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1916 ->subOp
= (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) ?
1917 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1920 // calculate effective address part 1
1921 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1925 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_FMT
, su
->tex
.bindless
);
1926 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1927 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1941 if (!su
->tex
.target
.isArray() && !su
->tex
.target
.isCube()) {
1942 z
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_UNK1C
, su
->tex
.bindless
);
1943 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1947 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1951 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1952 insn
->subOp
= subOp
;
1953 insn
->setFlagsDef(1, pred
);
1957 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
, su
->tex
.bindless
);
1959 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1962 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1964 // add array layer offset
1965 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1966 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ARRAY
, su
->tex
.bindless
);
1968 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1969 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1971 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1972 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1973 // combine predicates
1975 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1980 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1984 // bf == g[] address & 0xff
1985 // eau == g[] address >> 8
1986 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1987 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1989 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1990 // Convert from u32 to u8 address format, which is what the library code
1991 // doing SULDP currently uses.
1992 // XXX: can SUEAU do this ?
1993 // XXX: does it matter that we don't mask high bytes in bf ?
1995 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1996 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1999 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
2001 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
2002 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
2004 // let's just set it 0 for raw access and hope it works
2006 bld
.mkImm(0) : loadSuInfo32(ind
, slot
, NVC0_SU_INFO_FMT
, su
->tex
.bindless
);
2008 // get rid of old coordinate sources, make space for fmt info and predicate
2009 su
->moveSources(arg
, 3 - arg
);
2010 // set 64 bit address and 32-bit format sources
2011 su
->setSrc(0, addr
);
2013 su
->setSrc(2, pred
);
2014 su
->setIndirectR(NULL
);
2016 // prevent read fault when the image is not actually bound
2017 CmpInstruction
*pred1
=
2018 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2019 TYPE_U32
, bld
.mkImm(0),
2020 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
, su
->tex
.bindless
));
2022 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2023 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2024 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2025 format
->bits
[2] + format
->bits
[3];
2027 // make sure that the format doesn't mismatch
2028 assert(format
->components
!= 0);
2029 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred1
->getDef(0),
2030 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2031 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
, su
->tex
.bindless
),
2034 su
->setPredicate(CC_NOT_P
, pred1
->getDef(0));
2036 // TODO: initialize def values to 0 when the surface operation is not
2037 // performed (not needed for stores). Also, fix the "address bounds test"
2038 // subtests from arb_shader_image_load_store-invalid for buffers, because it
2039 // seems like that the predicate is not correctly set by suclamp.
2043 getSrcType(const TexInstruction::ImgFormatDesc
*t
, int c
)
2046 case FLOAT
: return t
->bits
[c
] == 16 ? TYPE_F16
: TYPE_F32
;
2047 case UNORM
: return t
->bits
[c
] == 8 ? TYPE_U8
: TYPE_U16
;
2048 case SNORM
: return t
->bits
[c
] == 8 ? TYPE_S8
: TYPE_S16
;
2050 return (t
->bits
[c
] == 8 ? TYPE_U8
:
2051 (t
->bits
[c
] == 16 ? TYPE_U16
: TYPE_U32
));
2053 return (t
->bits
[c
] == 8 ? TYPE_S8
:
2054 (t
->bits
[c
] == 16 ? TYPE_S16
: TYPE_S32
));
2060 getDestType(const ImgType type
) {
2071 assert(!"Impossible type");
2077 NVC0LoweringPass::convertSurfaceFormat(TexInstruction
*su
)
2079 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2080 int width
= format
->bits
[0] + format
->bits
[1] +
2081 format
->bits
[2] + format
->bits
[3];
2082 Value
*untypedDst
[4] = {};
2083 Value
*typedDst
[4] = {};
2085 // We must convert this to a generic load.
2088 su
->dType
= typeOfSize(width
/ 8);
2089 su
->sType
= TYPE_U8
;
2091 for (int i
= 0; i
< width
/ 32; i
++)
2092 untypedDst
[i
] = bld
.getSSA();
2094 untypedDst
[0] = bld
.getSSA();
2096 for (int i
= 0; i
< 4; i
++) {
2097 typedDst
[i
] = su
->getDef(i
);
2100 // Set the untyped dsts as the su's destinations
2101 for (int i
= 0; i
< 4; i
++)
2102 su
->setDef(i
, untypedDst
[i
]);
2104 bld
.setPosition(su
, true);
2106 // Unpack each component into the typed dsts
2108 for (int i
= 0; i
< 4; bits
+= format
->bits
[i
], i
++) {
2111 if (i
>= format
->components
) {
2112 if (format
->type
== FLOAT
||
2113 format
->type
== UNORM
||
2114 format
->type
== SNORM
)
2115 bld
.loadImm(typedDst
[i
], i
== 3 ? 1.0f
: 0.0f
);
2117 bld
.loadImm(typedDst
[i
], i
== 3 ? 1 : 0);
2121 // Get just that component's data into the relevant place
2122 if (format
->bits
[i
] == 32)
2123 bld
.mkMov(typedDst
[i
], untypedDst
[i
]);
2124 else if (format
->bits
[i
] == 16)
2125 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
2126 getSrcType(format
, i
), untypedDst
[i
/ 2])
2127 ->subOp
= (i
& 1) << (format
->type
== FLOAT
? 0 : 1);
2128 else if (format
->bits
[i
] == 8)
2129 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
2130 getSrcType(format
, i
), untypedDst
[0])->subOp
= i
;
2132 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, typedDst
[i
], untypedDst
[bits
/ 32],
2133 bld
.mkImm((bits
% 32) | (format
->bits
[i
] << 8)));
2134 if (format
->type
== UNORM
|| format
->type
== SNORM
)
2135 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], getSrcType(format
, i
), typedDst
[i
]);
2138 // Normalize / convert as necessary
2139 if (format
->type
== UNORM
)
2140 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << format
->bits
[i
]) - 1)));
2141 else if (format
->type
== SNORM
)
2142 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << (format
->bits
[i
] - 1)) - 1)));
2143 else if (format
->type
== FLOAT
&& format
->bits
[i
] < 16) {
2144 bld
.mkOp2(OP_SHL
, TYPE_U32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 15 - format
->bits
[i
]));
2145 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], TYPE_F16
, typedDst
[i
]);
2150 std::swap(typedDst
[0], typedDst
[2]);
2155 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
2157 processSurfaceCoordsNVE4(su
);
2159 if (su
->op
== OP_SULDP
)
2160 convertSurfaceFormat(su
);
2162 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
2163 assert(su
->getPredicate());
2165 bld
.mkOp2v(OP_OR
, TYPE_U8
, bld
.getScratch(1, FILE_PREDICATE
),
2166 su
->getPredicate(), su
->getSrc(2));
2168 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, bld
.getSSA());
2169 red
->subOp
= su
->subOp
;
2170 red
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0));
2171 red
->setSrc(1, su
->getSrc(3));
2172 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2173 red
->setSrc(2, su
->getSrc(4));
2174 red
->setIndirect(0, 0, su
->getSrc(0));
2176 // make sure to initialize dst value when the atomic operation is not
2178 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2180 assert(su
->cc
== CC_NOT_P
);
2181 red
->setPredicate(su
->cc
, pred
);
2182 mov
->setPredicate(CC_P
, pred
);
2184 bld
.mkOp2(OP_UNION
, TYPE_U32
, su
->getDef(0),
2185 red
->getDef(0), mov
->getDef(0));
2187 delete_Instruction(bld
.getProgram(), su
);
2188 handleCasExch(red
, true);
2191 if (su
->op
== OP_SUSTB
|| su
->op
== OP_SUSTP
)
2192 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
2196 NVC0LoweringPass::processSurfaceCoordsNVC0(TexInstruction
*su
)
2198 const int slot
= su
->tex
.r
;
2199 const int dim
= su
->tex
.target
.getDim();
2200 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2202 Value
*zero
= bld
.mkImm(0);
2205 Value
*ind
= su
->getIndirectR();
2207 bld
.setPosition(su
, false);
2209 adjustCoordinatesMS(su
);
2213 ptr
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(su
->tex
.r
));
2214 ptr
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ptr
, bld
.mkImm(7));
2215 su
->setIndirectR(ptr
);
2218 // get surface coordinates
2219 for (c
= 0; c
< arg
; ++c
)
2220 src
[c
] = su
->getSrc(c
);
2224 // calculate pixel offset
2225 if (su
->op
== OP_SULDP
|| su
->op
== OP_SUREDP
) {
2226 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
, su
->tex
.bindless
);
2227 su
->setSrc(0, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[0], v
));
2230 // add array layer offset
2231 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
2232 v
= loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ARRAY
, su
->tex
.bindless
);
2234 su
->setSrc(2, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[2], v
));
2237 // prevent read fault when the image is not actually bound
2238 CmpInstruction
*pred
=
2239 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2240 TYPE_U32
, bld
.mkImm(0),
2241 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
, su
->tex
.bindless
));
2242 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2243 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2244 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2245 format
->bits
[2] + format
->bits
[3];
2247 assert(format
->components
!= 0);
2248 // make sure that the format doesn't mismatch when it's not FMT_NONE
2249 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred
->getDef(0),
2250 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2251 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
, su
->tex
.bindless
),
2254 su
->setPredicate(CC_NOT_P
, pred
->getDef(0));
2258 NVC0LoweringPass::handleSurfaceOpNVC0(TexInstruction
*su
)
2260 if (su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
2261 /* As 1d arrays also need 3 coordinates, switching to TEX_TARGET_2D_ARRAY
2262 * will simplify the lowering pass and the texture constraints. */
2263 su
->moveSources(1, 1);
2264 su
->setSrc(1, bld
.loadImm(NULL
, 0));
2265 su
->tex
.target
= TEX_TARGET_2D_ARRAY
;
2268 processSurfaceCoordsNVC0(su
);
2270 if (su
->op
== OP_SULDP
)
2271 convertSurfaceFormat(su
);
2273 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
2274 const int dim
= su
->tex
.target
.getDim();
2275 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2276 LValue
*addr
= bld
.getSSA(8);
2277 Value
*def
= su
->getDef(0);
2281 // Set the destination to the address
2282 su
->dType
= TYPE_U64
;
2283 su
->setDef(0, addr
);
2284 su
->setDef(1, su
->getPredicate());
2286 bld
.setPosition(su
, true);
2288 // Perform the atomic op
2289 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->sType
, bld
.getSSA());
2290 red
->subOp
= su
->subOp
;
2291 red
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, su
->sType
, 0));
2292 red
->setSrc(1, su
->getSrc(arg
));
2293 if (red
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2294 red
->setSrc(2, su
->getSrc(arg
+ 1));
2295 red
->setIndirect(0, 0, addr
);
2297 // make sure to initialize dst value when the atomic operation is not
2299 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2301 assert(su
->cc
== CC_NOT_P
);
2302 red
->setPredicate(su
->cc
, su
->getPredicate());
2303 mov
->setPredicate(CC_P
, su
->getPredicate());
2305 bld
.mkOp2(OP_UNION
, TYPE_U32
, def
, red
->getDef(0), mov
->getDef(0));
2307 handleCasExch(red
, false);
2312 NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction
*su
)
2314 const int slot
= su
->tex
.r
;
2315 const int dim
= su
->tex
.target
.getDim();
2316 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2317 Value
*ind
= su
->getIndirectR();
2321 bld
.setPosition(su
, false);
2323 adjustCoordinatesMS(su
);
2325 // add texture handle
2331 pos
= (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) ? 2 : 1;
2337 if (su
->tex
.bindless
)
2340 handle
= loadTexHandle(ind
, slot
+ 32);
2341 su
->setSrc(arg
+ pos
, handle
);
2343 // The address check doesn't make sense here. The format check could make
2344 // sense but it's a bit of a pain.
2345 if (su
->tex
.bindless
)
2348 // prevent read fault when the image is not actually bound
2349 CmpInstruction
*pred
=
2350 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2351 TYPE_U32
, bld
.mkImm(0),
2352 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_ADDR
, su
->tex
.bindless
));
2353 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2354 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2355 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2356 format
->bits
[2] + format
->bits
[3];
2358 assert(format
->components
!= 0);
2359 // make sure that the format doesn't mismatch when it's not FMT_NONE
2360 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred
->getDef(0),
2361 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2362 loadSuInfo32(ind
, slot
, NVC0_SU_INFO_BSIZE
, su
->tex
.bindless
),
2365 su
->setPredicate(CC_NOT_P
, pred
->getDef(0));
2369 NVC0LoweringPass::handleSurfaceOpGM107(TexInstruction
*su
)
2371 processSurfaceCoordsGM107(su
);
2373 if (su
->op
== OP_SULDP
)
2374 convertSurfaceFormat(su
);
2376 if (su
->op
== OP_SUREDP
) {
2377 Value
*def
= su
->getDef(0);
2381 // There may not be a predicate in the bindless case.
2382 if (su
->getPredicate()) {
2383 su
->setDef(0, bld
.getSSA());
2385 bld
.setPosition(su
, true);
2387 // make sure to initialize dst value when the atomic operation is not
2389 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2391 assert(su
->cc
== CC_NOT_P
);
2392 mov
->setPredicate(CC_P
, su
->getPredicate());
2394 bld
.mkOp2(OP_UNION
, TYPE_U32
, def
, su
->getDef(0), mov
->getDef(0));
2400 NVC0LoweringPass::handleWRSV(Instruction
*i
)
2406 // must replace, $sreg are not writeable
2407 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
2410 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
2412 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
2414 st
->perPatch
= i
->perPatch
;
2416 bld
.getBB()->remove(i
);
2421 NVC0LoweringPass::handleLDST(Instruction
*i
)
2423 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
2424 if (prog
->getType() == Program::TYPE_COMPUTE
) {
2425 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
2426 i
->getSrc(0)->reg
.fileIndex
= 0;
2428 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
2429 i
->src(0).isIndirect(0)) {
2430 // XXX: this assumes vec4 units
2431 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2432 i
->getIndirect(0, 0), bld
.mkImm(4));
2433 i
->setIndirect(0, 0, ptr
);
2437 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
2439 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
2440 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
2441 prog
->getType() == Program::TYPE_COMPUTE
) {
2442 // The launch descriptor only allows to set up 8 CBs, but OpenGL
2443 // requires at least 12 UBOs. To bypass this limitation, we store the
2444 // addrs into the driver constbuf and we directly load from the global
2446 int8_t fileIndex
= i
->getSrc(0)->reg
.fileIndex
- 1;
2447 Value
*ind
= i
->getIndirect(0, 1);
2449 if (!ind
&& fileIndex
== -1)
2453 // Clamp the UBO index when an indirect access is used to avoid
2454 // loading information from the wrong place in the driver cb.
2455 // TODO - synchronize the max with the driver.
2456 ind
= bld
.mkOp2v(OP_MIN
, TYPE_U32
, bld
.getSSA(),
2457 bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(),
2458 ind
, bld
.loadImm(NULL
, fileIndex
)),
2459 bld
.loadImm(NULL
, 13));
2463 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2464 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
2465 Value
*length
= loadUboLength32(ind
, fileIndex
* 16);
2466 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2467 if (i
->src(0).isIndirect(0)) {
2468 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2469 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2471 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2472 i
->setIndirect(0, 1, NULL
);
2473 i
->setIndirect(0, 0, ptr
);
2474 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2475 i
->setPredicate(CC_NOT_P
, pred
);
2476 Value
*zero
, *dst
= i
->getDef(0);
2477 i
->setDef(0, bld
.getSSA());
2479 bld
.setPosition(i
, true);
2480 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
2481 ->setPredicate(CC_P
, pred
);
2482 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, i
->getDef(0), zero
);
2483 } else if (i
->src(0).isIndirect(1)) {
2485 if (i
->src(0).isIndirect(0))
2486 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
2487 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
2488 i
->getIndirect(0, 0));
2490 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2491 i
->getIndirect(0, 1), bld
.mkImm(16));
2492 i
->setIndirect(0, 1, NULL
);
2493 i
->setIndirect(0, 0, ptr
);
2494 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
2496 } else if (i
->src(0).getFile() == FILE_SHADER_OUTPUT
) {
2497 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
2499 } else if (i
->src(0).getFile() == FILE_MEMORY_BUFFER
) {
2500 Value
*ind
= i
->getIndirect(0, 1);
2501 Value
*ptr
= loadBufInfo64(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2502 // XXX come up with a way not to do this for EVERY little access but
2503 // rather to batch these up somehow. Unfortunately we've lost the
2504 // information about the field width by the time we get here.
2505 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2506 Value
*length
= loadBufLength32(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2507 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2508 if (i
->src(0).isIndirect(0)) {
2509 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2510 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2512 i
->setIndirect(0, 1, NULL
);
2513 i
->setIndirect(0, 0, ptr
);
2514 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2515 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2516 i
->setPredicate(CC_NOT_P
, pred
);
2517 if (i
->defExists(0)) {
2518 Value
*zero
, *dst
= i
->getDef(0);
2519 i
->setDef(0, bld
.getSSA());
2521 bld
.setPosition(i
, true);
2522 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
2523 ->setPredicate(CC_P
, pred
);
2524 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, i
->getDef(0), zero
);
2530 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
2532 Value
*laneid
= bld
.getSSA();
2535 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
2546 if (prog
->driver
->prop
.tp
.domain
!= PIPE_PRIM_TRIANGLES
) {
2547 bld
.mkMov(dst
, bld
.loadImm(NULL
, 0));
2554 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
2556 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
2559 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
2560 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
2565 NVC0LoweringPass::handleRDSV(Instruction
*i
)
2567 Symbol
*sym
= i
->getSrc(0)->asSym();
2568 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
2571 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
2573 if (addr
>= 0x400) {
2575 if (sym
->reg
.data
.sv
.index
== 3) {
2576 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
2578 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
2581 // Help CSE combine TID fetches
2582 Value
*tid
= bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(),
2583 bld
.mkSysVal(SV_COMBINED_TID
, 0));
2586 switch (sym
->reg
.data
.sv
.index
) {
2587 case 0: i
->setSrc(1, bld
.mkImm(0x1000)); break;
2588 case 1: i
->setSrc(1, bld
.mkImm(0x0a10)); break;
2589 case 2: i
->setSrc(1, bld
.mkImm(0x061a)); break;
2592 if (sv
== SV_VERTEX_COUNT
) {
2593 bld
.setPosition(i
, true);
2594 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(0x808));
2601 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
2602 if (i
->srcExists(1)) {
2603 // Pass offset through to the interpolation logic
2604 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
2605 i
->getDef(0), addr
, NULL
);
2606 ld
->setSrc(1, i
->getSrc(1));
2608 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
2613 Value
*face
= i
->getDef(0);
2614 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
2615 if (i
->dType
== TYPE_F32
) {
2616 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
2617 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
2618 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
2623 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
2624 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
2629 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
2630 if (sym
->reg
.data
.sv
.index
== 3) {
2632 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
2637 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
2638 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2639 bld
.mkSymbol(FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2640 TYPE_U32
, addr
), NULL
);
2642 case SV_SAMPLE_INDEX
:
2643 // TODO: Properly pass source as an address in the PIX address space
2644 // (which can be of the form [r0+offset]). But this is currently
2646 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2647 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2649 case SV_SAMPLE_POS
: {
2650 Value
*sampleID
= bld
.getScratch();
2651 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, sampleID
, bld
.mkImm(0));
2652 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2653 Value
*offset
= calculateSampleOffset(sampleID
);
2655 assert(prog
->driver
->prop
.fp
.readsSampleLocations
);
2657 if (targ
->getChipset() >= NVISA_GM200_CHIPSET
) {
2658 bld
.mkLoad(TYPE_F32
,
2661 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2662 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
),
2664 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0),
2665 bld
.mkImm(0x040c + sym
->reg
.data
.sv
.index
* 16));
2666 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(0), TYPE_U32
, i
->getDef(0));
2667 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(1.0f
/ 16.0f
));
2669 bld
.mkLoad(TYPE_F32
,
2672 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2673 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
2674 4 * sym
->reg
.data
.sv
.index
),
2679 case SV_SAMPLE_MASK
: {
2680 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2681 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
2682 Instruction
*sampleid
=
2683 bld
.mkOp1(OP_PIXLD
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2684 sampleid
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2686 bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
2687 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2688 bld
.loadImm(NULL
, 1), sampleid
->getDef(0)));
2689 if (prog
->driver
->prop
.fp
.persampleInvocation
) {
2690 bld
.mkMov(i
->getDef(0), masked
);
2692 bld
.mkOp3(OP_SELP
, TYPE_U32
, i
->getDef(0), ld
->getDef(0), masked
,
2699 case SV_BASEINSTANCE
:
2701 ld
= bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2702 bld
.mkSymbol(FILE_MEMORY_CONST
,
2703 prog
->driver
->io
.auxCBSlot
,
2705 prog
->driver
->io
.drawInfoBase
+
2706 4 * (sv
- SV_BASEVERTEX
)),
2710 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
&& !i
->perPatch
)
2711 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2712 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2713 bld
.mkInterp(NV50_IR_INTERP_FLAT
, i
->getDef(0), addr
, NULL
);
2715 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
2716 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
2717 ld
->perPatch
= i
->perPatch
;
2721 bld
.getBB()->remove(i
);
2726 NVC0LoweringPass::handleDIV(Instruction
*i
)
2728 if (!isFloatType(i
->dType
))
2730 bld
.setPosition(i
, false);
2731 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
2733 i
->setSrc(1, rcp
->getDef(0));
2738 NVC0LoweringPass::handleMOD(Instruction
*i
)
2740 if (!isFloatType(i
->dType
))
2742 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
2743 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
2744 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
2745 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
2746 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
2748 i
->setSrc(1, value
);
2753 NVC0LoweringPass::handleSQRT(Instruction
*i
)
2755 if (targ
->isOpSupported(OP_SQRT
, i
->dType
))
2758 if (i
->dType
== TYPE_F64
) {
2759 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
2760 Value
*zero
= bld
.loadImm(NULL
, 0.0);
2761 Value
*dst
= bld
.getSSA(8);
2762 bld
.mkOp1(OP_RSQ
, i
->dType
, dst
, i
->getSrc(0));
2763 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
2764 bld
.mkOp3(OP_SELP
, TYPE_U64
, dst
, zero
, dst
, pred
);
2767 // TODO: Handle this properly with a library function
2769 bld
.setPosition(i
, true);
2771 bld
.mkOp1(OP_RCP
, i
->dType
, i
->getDef(0), i
->getDef(0));
2778 NVC0LoweringPass::handlePOW(Instruction
*i
)
2780 LValue
*val
= bld
.getScratch();
2782 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
2783 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
2784 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
2794 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
2796 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2797 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
2799 if (i
->src(0).isIndirect(0)) // TODO, ugly
2802 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
2803 i
->src(0).set(i
->src(1));
2805 i
->setDef(0, new_LValue(func
, FILE_GPR
));
2806 i
->getDef(0)->reg
.data
.id
= id
;
2808 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
2810 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
2811 i
->setIndirect(0, 1, gpEmitAddress
);
2817 NVC0LoweringPass::handleOUT(Instruction
*i
)
2819 Instruction
*prev
= i
->prev
;
2820 ImmediateValue stream
, prevStream
;
2822 // Only merge if the stream ids match. Also, note that the previous
2823 // instruction would have already been lowered, so we take arg1 from it.
2824 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
2825 i
->src(0).getImmediate(stream
) &&
2826 prev
->src(1).getImmediate(prevStream
) &&
2827 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
2828 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
2829 delete_Instruction(prog
, i
);
2831 assert(gpEmitAddress
);
2832 i
->setDef(0, gpEmitAddress
);
2833 i
->setSrc(1, i
->getSrc(0));
2834 i
->setSrc(0, gpEmitAddress
);
2840 NVC0LoweringPass::calculateSampleOffset(Value
*sampleID
)
2842 Value
*offset
= bld
.getScratch();
2843 if (targ
->getChipset() >= NVISA_GM200_CHIPSET
) {
2844 // Sample location offsets (in bytes) are calculated like so:
2845 // offset = (SV_POSITION.y % 4 * 2) + (SV_POSITION.x % 2)
2846 // offset = offset * 32 + sampleID % 8 * 4;
2847 // which is equivalent to:
2848 // offset = (SV_POSITION.y & 0x3) << 6 + (SV_POSITION.x & 0x1) << 5;
2849 // offset += sampleID << 2
2851 // The second operand (src1) of the INSBF instructions are like so:
2852 // 0xssll where ss is the size and ll is the offset.
2853 // so: dest = src2 | (src0 & (1 << ss - 1)) << ll
2855 // Add sample ID (offset = (sampleID & 0x7) << 2)
2856 bld
.mkOp3(OP_INSBF
, TYPE_U32
, offset
, sampleID
, bld
.mkImm(0x0302), bld
.mkImm(0x0));
2858 Symbol
*xSym
= bld
.mkSysVal(SV_POSITION
, 0);
2859 Symbol
*ySym
= bld
.mkSysVal(SV_POSITION
, 1);
2860 Value
*coord
= bld
.getScratch();
2862 // Add X coordinate (offset |= (SV_POSITION.x & 0x1) << 5)
2863 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, coord
,
2864 targ
->getSVAddress(FILE_SHADER_INPUT
, xSym
), NULL
);
2865 bld
.mkCvt(OP_CVT
, TYPE_U32
, coord
, TYPE_F32
, coord
)
2867 bld
.mkOp3(OP_INSBF
, TYPE_U32
, offset
, coord
, bld
.mkImm(0x0105), offset
);
2869 // Add Y coordinate (offset |= (SV_POSITION.y & 0x3) << 6)
2870 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, coord
,
2871 targ
->getSVAddress(FILE_SHADER_INPUT
, ySym
), NULL
);
2872 bld
.mkCvt(OP_CVT
, TYPE_U32
, coord
, TYPE_F32
, coord
)
2874 bld
.mkOp3(OP_INSBF
, TYPE_U32
, offset
, coord
, bld
.mkImm(0x0206), offset
);
2876 bld
.mkOp2(OP_SHL
, TYPE_U32
, offset
, sampleID
, bld
.mkImm(3));
2881 // Handle programmable sample locations for GM20x+
2883 NVC0LoweringPass::handlePIXLD(Instruction
*i
)
2885 if (i
->subOp
!= NV50_IR_SUBOP_PIXLD_OFFSET
)
2887 if (targ
->getChipset() < NVISA_GM200_CHIPSET
)
2890 assert(prog
->driver
->prop
.fp
.readsSampleLocations
);
2892 bld
.mkLoad(TYPE_F32
,
2895 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2896 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
),
2897 calculateSampleOffset(i
->getSrc(0)));
2899 bld
.getBB()->remove(i
);
2902 // Generate a binary predicate if an instruction is predicated by
2903 // e.g. an f32 value.
2905 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
2907 Value
*pred
= insn
->getPredicate();
2910 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
2912 pdst
= new_LValue(func
, FILE_PREDICATE
);
2914 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
2915 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
2917 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
2919 insn
->setPredicate(insn
->cc
, pdst
);
2923 // - add quadop dance for texturing
2924 // - put FP outputs in GPRs
2925 // - convert instruction sequences
2928 NVC0LoweringPass::visit(Instruction
*i
)
2931 bld
.setPosition(i
, false);
2933 if (i
->cc
!= CC_ALWAYS
)
2942 return handleTEX(i
->asTex());
2944 return handleTXD(i
->asTex());
2946 return handleTXLQ(i
->asTex());
2948 return handleTXQ(i
->asTex());
2950 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
2951 i
->setSrc(0, i
->getDef(0));
2954 return handlePOW(i
);
2956 return handleDIV(i
);
2958 return handleMOD(i
);
2960 return handleSQRT(i
);
2962 ret
= handleEXPORT(i
);
2966 return handleOUT(i
);
2968 return handleRDSV(i
);
2970 return handleWRSV(i
);
2977 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_BUFFER
;
2979 handleCasExch(i
, cctl
);
2988 if (targ
->getChipset() >= NVISA_GM107_CHIPSET
)
2989 handleSurfaceOpGM107(i
->asTex());
2990 else if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2991 handleSurfaceOpNVE4(i
->asTex());
2993 handleSurfaceOpNVC0(i
->asTex());
2996 handleSUQ(i
->asTex());
3008 /* Kepler+ has a special opcode to compute a new base address to be used
3009 * for indirect loads.
3011 * Maxwell+ has an additional similar requirement for indirect
3012 * interpolation ops in frag shaders.
3014 bool doAfetch
= false;
3015 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
3017 (i
->op
== OP_VFETCH
|| i
->op
== OP_EXPORT
) &&
3018 i
->src(0).isIndirect(0)) {
3021 if (targ
->getChipset() >= NVISA_GM107_CHIPSET
&&
3022 (i
->op
== OP_LINTERP
|| i
->op
== OP_PINTERP
) &&
3023 i
->src(0).isIndirect(0)) {
3028 Value
*addr
= cloneShallow(func
, i
->getSrc(0));
3029 Instruction
*afetch
= bld
.mkOp1(OP_AFETCH
, TYPE_U32
, bld
.getSSA(),
3031 afetch
->setIndirect(0, 0, i
->getIndirect(0, 0));
3032 addr
->reg
.data
.offset
= 0;
3034 i
->setIndirect(0, 0, afetch
->getDef(0));
3041 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
3043 if (stage
== CG_STAGE_PRE_SSA
) {
3044 NVC0LoweringPass
pass(prog
);
3045 return pass
.run(prog
, false, true);
3047 if (stage
== CG_STAGE_POST_RA
) {
3048 NVC0LegalizePostRA
pass(prog
);
3049 return pass
.run(prog
, false, true);
3051 if (stage
== CG_STAGE_SSA
) {
3052 NVC0LegalizeSSA pass
;
3053 return pass
.run(prog
, false, true);
3058 } // namespace nv50_ir