2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
73 assert(i
->dType
== TYPE_F64
);
74 // There are instructions that will compute the high 32 bits of the 64-bit
75 // float. We will just stick 0 in the bottom 32 bits.
77 bld
.setPosition(i
, false);
79 // 1. Take the source and it up.
80 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
81 bld
.mkSplit(src
, 4, i
->getSrc(0));
83 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
84 dst
[0] = bld
.loadImm(NULL
, 0);
85 dst
[1] = bld
.getSSA();
87 // 3. The new version of the instruction takes the high 32 bits of the
88 // source and outputs the high 32 bits of the destination.
92 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
94 // 4. Recombine the two dst pieces back into the original destination.
95 bld
.setPosition(i
, true);
96 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
100 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
102 // Only want to flush float inputs
103 assert(i
->sType
== TYPE_F32
);
105 // If we're already flushing denorms (and NaN's) to zero, no need for this.
109 // Only certain classes of operations can flush
110 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
111 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
112 cls
!= OPCLASS_CONVERT
)
119 NVC0LegalizeSSA::visit(Function
*fn
)
121 bld
.setProgram(fn
->getProgram());
126 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
129 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
131 if (i
->sType
== TYPE_F32
) {
132 if (prog
->getType() != Program::TYPE_COMPUTE
)
143 if (i
->dType
== TYPE_F64
)
153 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
156 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
161 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
162 const Instruction
*early
) const
164 if (early
->bb
== later
->bb
)
165 return early
->serial
< later
->serial
;
166 return later
->bb
->dominatedBy(early
->bb
);
170 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
171 Instruction
*usei
, const Instruction
*texi
)
174 for (std::list
<TexUse
>::iterator it
= uses
.begin();
176 if (insnDominatedBy(usei
, it
->insn
)) {
180 if (insnDominatedBy(it
->insn
, usei
))
186 uses
.push_back(TexUse(usei
, texi
));
190 NVC0LegalizePostRA::findOverwritingDefs(const Instruction
*texi
,
192 const BasicBlock
*term
,
193 std::list
<TexUse
> &uses
)
195 while (insn
->op
== OP_MOV
&& insn
->getDef(0)->equals(insn
->getSrc(0)))
196 insn
= insn
->getSrc(0)->getUniqueInsn();
198 // NOTE: the tex itself is, of course, not an overwriting definition
199 if (insn
== texi
|| !insn
->bb
->reachableBy(texi
->bb
, term
))
203 /* Values not connected to the tex's definition through any of these should
204 * not be conflicting.
211 for (int s
= 0; insn
->srcExists(s
); ++s
)
212 findOverwritingDefs(texi
, insn
->getSrc(s
)->getUniqueInsn(), term
,
216 // if (!isTextureOp(insn->op)) // TODO: are TEXes always ordered ?
217 addTexUse(uses
, insn
, texi
);
223 NVC0LegalizePostRA::findFirstUses(
224 const Instruction
*texi
,
225 const Instruction
*insn
,
226 std::list
<TexUse
> &uses
,
227 std::tr1::unordered_set
<const Instruction
*>& visited
)
229 for (int d
= 0; insn
->defExists(d
); ++d
) {
230 Value
*v
= insn
->getDef(d
);
231 for (Value::UseIterator u
= v
->uses
.begin(); u
!= v
->uses
.end(); ++u
) {
232 Instruction
*usei
= (*u
)->getInsn();
234 // NOTE: In case of a loop that overwrites a value but never uses
235 // it, it can happen that we have a cycle of uses that consists only
236 // of phis and no-op moves and will thus cause an infinite loop here
237 // since these are not considered actual uses.
238 // The most obvious (and perhaps the only) way to prevent this is to
239 // remember which instructions we've already visited.
241 if (visited
.find(usei
) != visited
.end())
244 visited
.insert(usei
);
246 if (usei
->op
== OP_PHI
|| usei
->op
== OP_UNION
) {
247 // need a barrier before WAW cases, like:
250 // texbar <- is required or tex might replace x again
251 // %r1 = x <- overwriting def
252 // %r2 = phi %r0, %r1
253 for (int s
= 0; usei
->srcExists(s
); ++s
) {
254 Instruction
*defi
= usei
->getSrc(s
)->getUniqueInsn();
255 if (defi
&& &usei
->src(s
) != *u
)
256 findOverwritingDefs(texi
, defi
, usei
->bb
, uses
);
260 if (usei
->op
== OP_SPLIT
||
261 usei
->op
== OP_MERGE
||
262 usei
->op
== OP_PHI
||
263 usei
->op
== OP_UNION
) {
264 // these uses don't manifest in the machine code
265 findFirstUses(texi
, usei
, uses
, visited
);
267 if (usei
->op
== OP_MOV
&& usei
->getDef(0)->equals(usei
->getSrc(0)) &&
268 usei
->subOp
!= NV50_IR_SUBOP_MOV_FINAL
) {
269 findFirstUses(texi
, usei
, uses
, visited
);
271 addTexUse(uses
, usei
, texi
);
278 // This pass is a bit long and ugly and can probably be optimized.
280 // 1. obtain a list of TEXes and their outputs' first use(s)
281 // 2. calculate the barrier level of each first use (minimal number of TEXes,
282 // over all paths, between the TEX and the use in question)
283 // 3. for each barrier, if all paths from the source TEX to that barrier
284 // contain a barrier of lesser level, it can be culled
286 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
288 std::list
<TexUse
> *uses
;
289 std::vector
<Instruction
*> texes
;
290 std::vector
<int> bbFirstTex
;
291 std::vector
<int> bbFirstUse
;
292 std::vector
<int> texCounts
;
293 std::vector
<TexUse
> useVec
;
296 fn
->orderInstructions(insns
);
298 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
299 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
300 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
302 // tag BB CFG nodes by their id for later
303 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
304 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
306 bb
->cfg
.tag
= bb
->getId();
309 // gather the first uses for each TEX
310 for (int i
= 0; i
< insns
.getSize(); ++i
) {
311 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
312 if (isTextureOp(tex
->op
)) {
313 texes
.push_back(tex
);
314 if (!texCounts
.at(tex
->bb
->getId()))
315 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
316 texCounts
[tex
->bb
->getId()]++;
322 uses
= new std::list
<TexUse
>[texes
.size()];
325 for (size_t i
= 0; i
< texes
.size(); ++i
) {
326 std::tr1::unordered_set
<const Instruction
*> visited
;
327 findFirstUses(texes
[i
], texes
[i
], uses
[i
], visited
);
330 // determine the barrier level at each use
331 for (size_t i
= 0; i
< texes
.size(); ++i
) {
332 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
334 BasicBlock
*tb
= texes
[i
]->bb
;
335 BasicBlock
*ub
= u
->insn
->bb
;
338 for (size_t j
= i
+ 1; j
< texes
.size() &&
339 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
343 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
344 &ub
->cfg
, texCounts
);
346 WARN("Failed to find path TEX -> TEXBAR\n");
350 // this counted all TEXes in the origin block, correct that
351 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
352 // and did not count the TEXes in the destination block, add those
353 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
354 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
358 assert(u
->level
>= 0);
359 useVec
.push_back(*u
);
364 // insert the barriers
365 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
366 Instruction
*prev
= useVec
[i
].insn
->prev
;
367 if (useVec
[i
].level
< 0)
369 if (prev
&& prev
->op
== OP_TEXBAR
) {
370 if (prev
->subOp
> useVec
[i
].level
)
371 prev
->subOp
= useVec
[i
].level
;
372 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
374 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
376 bar
->subOp
= useVec
[i
].level
;
377 // make use explicit to ease latency calculation
378 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
379 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
383 if (fn
->getProgram()->optLevel
< 3)
386 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
388 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
389 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
390 limitS
.resize(fn
->allBBlocks
.getSize());
392 // cull unneeded barriers (should do that earlier, but for simplicity)
393 IteratorRef bi
= fn
->cfg
.iteratorCFG();
394 // first calculate min/max outstanding TEXes for each BB
395 for (bi
->reset(); !bi
->end(); bi
->next()) {
396 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
397 BasicBlock
*bb
= BasicBlock::get(n
);
399 int max
= std::numeric_limits
<int>::max();
400 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
401 if (isTextureOp(i
->op
)) {
403 if (max
< std::numeric_limits
<int>::max())
406 if (i
->op
== OP_TEXBAR
) {
407 min
= MIN2(min
, i
->subOp
);
408 max
= MIN2(max
, i
->subOp
);
411 // limits when looking at an isolated block
412 limitS
[bb
->getId()].min
= min
;
413 limitS
[bb
->getId()].max
= max
;
415 // propagate the min/max values
416 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
417 for (bi
->reset(); !bi
->end(); bi
->next()) {
418 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
419 BasicBlock
*bb
= BasicBlock::get(n
);
420 const int bbId
= bb
->getId();
421 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
422 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
423 const int inId
= in
->getId();
424 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
425 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
427 // I just hope this is correct ...
428 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
430 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
431 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
433 // block contained a barrier
434 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
435 limitT
[bbId
].min
+ limitS
[bbId
].min
);
436 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
437 limitT
[bbId
].max
+ limitS
[bbId
].min
);
441 // finally delete unnecessary barriers
442 for (bi
->reset(); !bi
->end(); bi
->next()) {
443 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
444 BasicBlock
*bb
= BasicBlock::get(n
);
445 Instruction
*prev
= NULL
;
447 int max
= limitT
[bb
->getId()].max
;
448 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
450 if (i
->op
== OP_TEXBAR
) {
451 if (i
->subOp
>= max
) {
452 delete_Instruction(prog
, i
);
456 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
457 delete_Instruction(prog
, prev
);
462 if (isTextureOp(i
->op
)) {
465 if (i
&& !i
->isNop())
473 NVC0LegalizePostRA::visit(Function
*fn
)
476 insertTextureBarriers(fn
);
478 rZero
= new_LValue(fn
, FILE_GPR
);
479 carry
= new_LValue(fn
, FILE_FLAGS
);
481 rZero
->reg
.data
.id
= prog
->getTarget()->getFileSize(FILE_GPR
);
482 carry
->reg
.data
.id
= 0;
488 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
490 for (int s
= 0; i
->srcExists(s
); ++s
) {
491 if (s
== 2 && i
->op
== OP_SUCLAMP
)
493 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
494 if (imm
&& imm
->reg
.data
.u64
== 0)
499 // replace CONT with BRA for single unconditional continue
501 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
503 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
505 Graph::EdgeIterator ei
= bb
->cfg
.incident();
506 if (ei
.getType() != Graph::Edge::BACK
)
508 if (ei
.getType() != Graph::Edge::BACK
)
510 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
512 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
513 contBB
->getExit()->getPredicate())
515 contBB
->getExit()->op
= OP_BRA
;
516 bb
->remove(bb
->getEntry()); // delete PRECONT
519 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
523 // replace branches to join blocks with join ops
525 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
527 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
529 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
530 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
531 Instruction
*exit
= in
->getExit();
533 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
534 // there should always be a terminator instruction
535 WARN("inserted missing terminator in BB:%i\n", in
->getId());
537 if (exit
->op
== OP_BRA
) {
539 exit
->asFlow()->limit
= 1; // must-not-propagate marker
542 bb
->remove(bb
->getEntry());
546 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
548 Instruction
*i
, *next
;
550 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
551 for (i
= bb
->getFirst(); i
; i
= next
) {
553 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
554 if (!i
->getDef(0)->refCount())
556 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
557 i
->setSrc(0, rZero
); // initial value must be 0
563 if (i
->op
== OP_BAR
&& i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
&&
564 prog
->getType() != Program::TYPE_COMPUTE
) {
565 // It seems like barriers are never required for tessellation since
566 // the warp size is 32, and there are always at most 32 tcs threads.
569 // TODO: Move this to before register allocation for operations that
570 // need the $c register !
571 if (typeSizeof(i
->dType
) == 8) {
573 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
578 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
585 if (!tryReplaceContWithBra(bb
))
591 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
593 bld
.setProgram(prog
);
598 NVC0LoweringPass::visit(Function
*fn
)
600 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
601 assert(!strncmp(fn
->getName(), "MAIN", 4));
602 // TODO: when we generate actual functions pass this value along somehow
603 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
604 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
606 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
607 bld
.mkMovToReg(0, gpEmitAddress
);
614 NVC0LoweringPass::visit(BasicBlock
*bb
)
620 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
622 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
623 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
625 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
628 // move array source to first slot, convert to u16, add indirections
630 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
632 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
633 const int arg
= i
->tex
.target
.getArgCount();
634 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
635 const int chipset
= prog
->getTarget()->getChipset();
637 // Arguments to the TEX instruction are a little insane. Even though the
638 // encoding is identical between SM20 and SM30, the arguments mean
639 // different things between Fermi and Kepler+. A lot of arguments are
640 // optional based on flags passed to the instruction. This summarizes the
650 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
651 // - other: 4 bits each, single reg
655 // array (+ offsets for txd in upper 16 bits)
660 // offsets (same as fermi, except txd which takes it with array)
677 if (chipset
>= NVISA_GK104_CHIPSET
) {
678 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
679 // XXX this ignores tsc, and assumes a 1:1 mapping
680 assert(i
->tex
.rIndirectSrc
>= 0);
681 Value
*hnd
= loadTexHandle(
682 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
683 i
->getIndirectR(), bld
.mkImm(2)),
687 i
->setIndirectR(hnd
);
688 i
->setIndirectS(NULL
);
689 } else if (i
->tex
.r
== i
->tex
.s
) {
690 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
691 i
->tex
.s
= 0; // only a single cX[] value possible here
693 Value
*hnd
= bld
.getScratch();
694 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
695 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
697 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
699 i
->tex
.r
= 0; // not used for indirect tex
701 i
->setIndirectR(hnd
);
703 if (i
->tex
.target
.isArray()) {
704 LValue
*layer
= new_LValue(func
, FILE_GPR
);
705 Value
*src
= i
->getSrc(lyr
);
706 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
707 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
708 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
709 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
710 for (int s
= dim
; s
>= 1; --s
)
711 i
->setSrc(s
, i
->getSrc(s
- 1));
714 i
->setSrc(dim
, layer
);
717 // Move the indirect reference to the first place
718 if (i
->tex
.rIndirectSrc
>= 0 && (
719 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
720 Value
*hnd
= i
->getIndirectR();
722 i
->setIndirectR(NULL
);
723 i
->moveSources(0, 1);
725 i
->tex
.rIndirectSrc
= 0;
726 i
->tex
.sIndirectSrc
= -1;
729 // (nvc0) generate and move the tsc/tic/array source to the front
730 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
731 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
733 Value
*ticRel
= i
->getIndirectR();
734 Value
*tscRel
= i
->getIndirectS();
737 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
739 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
740 ticRel
, bld
.mkImm(i
->tex
.r
));
743 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
745 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
746 tscRel
, bld
.mkImm(i
->tex
.s
));
749 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
750 for (int s
= dim
; s
>= 1; --s
)
751 i
->setSrc(s
, i
->getSrc(s
- 1));
752 i
->setSrc(0, arrayIndex
);
755 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
756 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
757 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
763 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
765 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
770 // For nvc0, the sample id has to be in the second operand, as the offset
771 // does. Right now we don't know how to pass both in, and this case can't
772 // happen with OpenGL. On nve0, the sample id is part of the texture
773 // coordinate argument.
774 assert(chipset
>= NVISA_GK104_CHIPSET
||
775 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
777 // offset is between lod and dc
778 if (i
->tex
.useOffsets
) {
780 int s
= i
->srcCount(0xff, true);
781 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
782 if (i
->tex
.target
.isShadow())
784 if (i
->srcExists(s
)) // move potential predicate out of the way
785 i
->moveSources(s
, 1);
786 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
787 i
->moveSources(s
+ 1, 1);
789 if (i
->op
== OP_TXG
) {
790 // Either there is 1 offset, which goes into the 2 low bytes of the
791 // first source, or there are 4 offsets, which go into 2 sources (8
792 // values, 1 byte each).
793 Value
*offs
[2] = {NULL
, NULL
};
794 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
795 for (c
= 0; c
< 2; ++c
) {
796 if ((n
% 2) == 0 && c
== 0)
797 offs
[n
/ 2] = i
->offset
[n
][c
].get();
799 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
801 i
->offset
[n
][c
].get(),
802 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
806 i
->setSrc(s
, offs
[0]);
808 i
->setSrc(s
+ 1, offs
[1]);
811 assert(i
->tex
.useOffsets
== 1);
812 for (c
= 0; c
< 3; ++c
) {
814 if (!i
->offset
[0][c
].getImmediate(val
))
815 assert(!"non-immediate offset passed to non-TXG");
816 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
818 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
819 // The offset goes into the upper 16 bits of the array index. So
820 // create it if it's not already there, and INSBF it if it already
822 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
823 if (chipset
>= NVISA_GM107_CHIPSET
)
825 if (i
->tex
.target
.isArray()) {
826 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
827 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
830 i
->moveSources(s
, 1);
831 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
834 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
839 if (chipset
>= NVISA_GK104_CHIPSET
) {
841 // If TEX requires more than 4 sources, the 2nd register tuple must be
842 // aligned to 4, even if it consists of just a single 4-byte register.
844 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
846 int s
= i
->srcCount(0xff, true);
847 if (s
> 4 && s
< 7) {
848 if (i
->srcExists(s
)) // move potential predicate out of the way
849 i
->moveSources(s
, 7 - s
);
851 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
859 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
861 static const uint8_t qOps
[4][2] =
863 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
864 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
865 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
866 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
871 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
873 const int dim
= i
->tex
.target
.getDim();
874 const int array
= i
->tex
.target
.isArray();
876 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
878 for (c
= 0; c
< dim
; ++c
)
879 crd
[c
] = bld
.getScratch();
881 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
882 for (l
= 0; l
< 4; ++l
) {
883 // mov coordinates from lane l to all lanes
884 for (c
= 0; c
< dim
; ++c
)
885 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
886 // add dPdx from lane l to lanes dx
887 for (c
= 0; c
< dim
; ++c
)
888 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
889 // add dPdy from lane l to lanes dy
890 for (c
= 0; c
< dim
; ++c
)
891 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
893 bld
.insert(tex
= cloneForward(func
, i
));
894 for (c
= 0; c
< dim
; ++c
)
895 tex
->setSrc(c
+ array
, crd
[c
]);
897 for (c
= 0; i
->defExists(c
); ++c
) {
899 def
[c
][l
] = bld
.getSSA();
900 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
905 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
907 for (c
= 0; i
->defExists(c
); ++c
) {
908 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
909 for (l
= 0; l
< 4; ++l
)
910 u
->setSrc(l
, def
[c
][l
]);
918 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
920 int dim
= txd
->tex
.target
.getDim();
921 unsigned arg
= txd
->tex
.target
.getArgCount();
922 unsigned expected_args
= arg
;
923 const int chipset
= prog
->getTarget()->getChipset();
925 if (chipset
>= NVISA_GK104_CHIPSET
) {
926 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
928 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
931 if (txd
->tex
.useOffsets
)
933 if (!txd
->tex
.target
.isArray() && (
934 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
938 if (expected_args
> 4 ||
940 txd
->tex
.target
.isShadow() ||
941 txd
->tex
.target
.isCube())
945 while (txd
->srcExists(arg
))
948 txd
->tex
.derivAll
= true;
949 if (txd
->op
== OP_TEX
)
950 return handleManualTXD(txd
);
952 assert(arg
== expected_args
);
953 for (int c
= 0; c
< dim
; ++c
) {
954 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
955 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
956 txd
->dPdx
[c
].set(NULL
);
957 txd
->dPdy
[c
].set(NULL
);
963 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
965 if (txq
->tex
.rIndirectSrc
< 0)
968 Value
*ticRel
= txq
->getIndirectR();
969 const int chipset
= prog
->getTarget()->getChipset();
971 txq
->setIndirectS(NULL
);
972 txq
->tex
.sIndirectSrc
= -1;
976 if (chipset
< NVISA_GK104_CHIPSET
) {
977 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
979 txq
->setSrc(txq
->tex
.rIndirectSrc
, NULL
);
981 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
982 ticRel
, bld
.mkImm(txq
->tex
.r
));
984 bld
.mkOp2(OP_SHL
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x17));
986 txq
->moveSources(0, 1);
989 Value
*hnd
= loadTexHandle(
990 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
991 txq
->getIndirectR(), bld
.mkImm(2)),
996 if (chipset
< NVISA_GM107_CHIPSET
) {
997 txq
->setIndirectR(NULL
);
998 txq
->moveSources(0, 1);
1000 txq
->tex
.rIndirectSrc
= 0;
1002 txq
->setIndirectR(hnd
);
1010 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
1012 /* The outputs are inverted compared to what the TGSI instruction
1013 * expects. Take that into account in the mask.
1015 assert((i
->tex
.mask
& ~3) == 0);
1016 if (i
->tex
.mask
== 1)
1018 else if (i
->tex
.mask
== 2)
1021 bld
.setPosition(i
, true);
1023 /* The returned values are not quite what we want:
1024 * (a) convert from s16/u16 to f32
1025 * (b) multiply by 1/256
1027 for (int def
= 0; def
< 2; ++def
) {
1028 if (!i
->defExists(def
))
1030 enum DataType type
= TYPE_S16
;
1031 if (i
->tex
.mask
== 2 || def
> 0)
1033 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
1034 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
1035 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
1037 if (i
->tex
.mask
== 3) {
1038 LValue
*t
= new_LValue(func
, FILE_GPR
);
1039 bld
.mkMov(t
, i
->getDef(0));
1040 bld
.mkMov(i
->getDef(0), i
->getDef(1));
1041 bld
.mkMov(i
->getDef(1), t
);
1048 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1052 switch (atom
->src(0).getFile()) {
1053 case FILE_MEMORY_LOCAL
:
1056 case FILE_MEMORY_SHARED
:
1060 assert(atom
->src(0).getFile() == FILE_MEMORY_GLOBAL
);
1064 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1065 Value
*ptr
= atom
->getIndirect(0, 0);
1067 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1068 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1070 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1071 atom
->setIndirect(0, 0, base
);
1077 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1079 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1080 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1082 bld
.setPosition(cas
, true);
1085 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1086 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1088 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1089 if (cas
->isPredicated())
1090 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1093 if (cas
->defExists(0) && cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1094 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1095 // should be set to the high part of the double reg or bad things will
1096 // happen elsewhere in the universe.
1097 // Also, it sometimes returns the new value instead of the old one
1098 // under mysterious circumstances.
1099 Value
*dreg
= bld
.getSSA(8);
1100 bld
.setPosition(cas
, false);
1101 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1102 cas
->setSrc(1, dreg
);
1109 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
)
1111 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
1112 off
+= prog
->driver
->io
.suInfoBase
;
1114 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1118 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1120 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1121 off
+= prog
->driver
->io
.msInfoBase
;
1123 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1126 /* On nvc0, surface info is obtained via the surface binding points passed
1127 * to the SULD/SUST instructions.
1128 * On nve4, surface info is stored in c[] and is used by various special
1129 * instructions, e.g. for clamping coordiantes or generating an address.
1130 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1132 #define NVE4_SU_INFO_ADDR 0x00
1133 #define NVE4_SU_INFO_FMT 0x04
1134 #define NVE4_SU_INFO_DIM_X 0x08
1135 #define NVE4_SU_INFO_PITCH 0x0c
1136 #define NVE4_SU_INFO_DIM_Y 0x10
1137 #define NVE4_SU_INFO_ARRAY 0x14
1138 #define NVE4_SU_INFO_DIM_Z 0x18
1139 #define NVE4_SU_INFO_UNK1C 0x1c
1140 #define NVE4_SU_INFO_WIDTH 0x20
1141 #define NVE4_SU_INFO_HEIGHT 0x24
1142 #define NVE4_SU_INFO_DEPTH 0x28
1143 #define NVE4_SU_INFO_TARGET 0x2c
1144 #define NVE4_SU_INFO_CALL 0x30
1145 #define NVE4_SU_INFO_RAW_X 0x34
1146 #define NVE4_SU_INFO_MS_X 0x38
1147 #define NVE4_SU_INFO_MS_Y 0x3c
1149 #define NVE4_SU_INFO__STRIDE 0x40
1151 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
1152 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1153 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
1155 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1157 switch (su
->tex
.target
.getEnum()) {
1158 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1159 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1160 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1161 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1162 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1163 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1164 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1165 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1166 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1167 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1168 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1169 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1170 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1178 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1180 const uint16_t base
= tex
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1181 const int arg
= tex
->tex
.target
.getArgCount();
1183 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1184 tex
->tex
.target
= TEX_TARGET_2D
;
1186 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1187 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1191 Value
*x
= tex
->getSrc(0);
1192 Value
*y
= tex
->getSrc(1);
1193 Value
*s
= tex
->getSrc(arg
- 1);
1195 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1197 Value
*ms_x
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(0));
1198 Value
*ms_y
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(1));
1200 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1201 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1203 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1204 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1206 Value
*dx
= loadMsInfo32(ts
, 0x0);
1207 Value
*dy
= loadMsInfo32(ts
, 0x4);
1209 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1210 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1214 tex
->moveSources(arg
, -1);
1217 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1218 // They're computed from the coordinates using the surface info in c[] space.
1220 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1223 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1225 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1226 const int idx
= su
->tex
.r
;
1227 const int dim
= su
->tex
.target
.getDim();
1228 const int arg
= dim
+ (su
->tex
.target
.isArray() ? 1 : 0);
1229 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
1231 Value
*zero
= bld
.mkImm(0);
1235 Value
*bf
, *eau
, *off
;
1238 off
= bld
.getScratch(4);
1239 bf
= bld
.getScratch(4);
1240 addr
= bld
.getSSA(8);
1241 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1243 bld
.setPosition(su
, false);
1245 adjustCoordinatesMS(su
);
1247 // calculate clamped coordinates
1248 for (c
= 0; c
< arg
; ++c
) {
1249 src
[c
] = bld
.getScratch();
1251 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_RAW_X
);
1253 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_DIM(c
));
1254 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1255 ->subOp
= getSuClampSubOp(su
, c
);
1260 // set predicate output
1261 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1262 src
[0]->getInsn()->setFlagsDef(1, pred
);
1264 if (su
->tex
.target
.isArray()) {
1265 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1266 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1269 // calculate pixel offset
1271 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1272 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1275 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1276 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1277 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1279 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1280 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1281 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1284 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1285 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1286 ->subOp
= su
->tex
.target
.isArray() ?
1287 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1290 // calculate effective address part 1
1291 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1295 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1296 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1297 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1311 if (!su
->tex
.target
.isArray()) {
1312 z
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1313 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1317 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1321 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1322 insn
->subOp
= subOp
;
1323 insn
->setFlagsDef(1, pred
);
1327 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ADDR
);
1329 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1332 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1334 // add array layer offset
1335 if (su
->tex
.target
.isArray()) {
1336 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ARRAY
);
1338 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1339 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1341 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1342 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1343 // combine predicates
1345 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1350 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1354 // bf == g[] address & 0xff
1355 // eau == g[] address >> 8
1356 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1357 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1359 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1360 // Convert from u32 to u8 address format, which is what the library code
1361 // doing SULDP currently uses.
1362 // XXX: can SUEAU do this ?
1363 // XXX: does it matter that we don't mask high bytes in bf ?
1365 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1366 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1369 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1371 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1372 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1374 // let's just set it 0 for raw access and hope it works
1376 bld
.mkImm(0) : loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1378 // get rid of old coordinate sources, make space for fmt info and predicate
1379 su
->moveSources(arg
, 3 - arg
);
1380 // set 64 bit address and 32-bit format sources
1381 su
->setSrc(0, addr
);
1383 su
->setSrc(2, pred
);
1387 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1389 processSurfaceCoordsNVE4(su
);
1391 // Who do we hate more ? The person who decided that nvc0's SULD doesn't
1392 // have to support conversion or the person who decided that, in OpenCL,
1393 // you don't have to specify the format here like you do in OpenGL ?
1395 if (su
->op
== OP_SULDP
) {
1396 // We don't patch shaders. Ever.
1397 // You get an indirect call to our library blob here.
1398 // But at least it's uniform.
1399 FlowInstruction
*call
;
1402 uint16_t base
= su
->tex
.r
* NVE4_SU_INFO__STRIDE
+ NVE4_SU_INFO_CALL
;
1404 for (int i
= 0; i
< 4; ++i
)
1405 (r
[i
] = bld
.getScratch(4, FILE_GPR
))->reg
.data
.id
= i
;
1406 for (int i
= 0; i
< 3; ++i
)
1407 (p
[i
] = bld
.getScratch(1, FILE_PREDICATE
))->reg
.data
.id
= i
;
1408 (r
[4] = bld
.getScratch(8, FILE_GPR
))->reg
.data
.id
= 4;
1410 bld
.mkMov(p
[1], bld
.mkImm((su
->cache
== CACHE_CA
) ? 1 : 0), TYPE_U8
);
1411 bld
.mkMov(p
[2], bld
.mkImm((su
->cache
== CACHE_CG
) ? 1 : 0), TYPE_U8
);
1412 bld
.mkMov(p
[0], su
->getSrc(2), TYPE_U8
);
1413 bld
.mkMov(r
[4], su
->getSrc(0), TYPE_U64
);
1414 bld
.mkMov(r
[2], su
->getSrc(1), TYPE_U32
);
1416 call
= bld
.mkFlow(OP_CALL
, NULL
, su
->cc
, su
->getPredicate());
1420 call
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_CONST
,
1421 prog
->driver
->io
.resInfoCBSlot
, TYPE_U32
,
1422 prog
->driver
->io
.suInfoBase
+ base
));
1423 call
->setSrc(1, r
[2]);
1424 call
->setSrc(2, r
[4]);
1425 for (int i
= 0; i
< 3; ++i
)
1426 call
->setSrc(3 + i
, p
[i
]);
1427 for (int i
= 0; i
< 4; ++i
) {
1428 call
->setDef(i
, r
[i
]);
1429 bld
.mkMov(su
->getDef(i
), r
[i
]);
1431 call
->setDef(4, p
[1]);
1432 delete_Instruction(bld
.getProgram(), su
);
1435 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
1436 // FIXME: for out of bounds access, destination value will be undefined !
1437 Value
*pred
= su
->getSrc(2);
1438 CondCode cc
= CC_NOT_P
;
1439 if (su
->getPredicate()) {
1440 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1442 if (cc
== CC_NOT_P
) {
1443 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1445 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1446 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
1449 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, su
->getDef(0));
1450 red
->subOp
= su
->subOp
;
1452 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
1453 red
->setSrc(0, gMemBase
);
1454 red
->setSrc(1, su
->getSrc(3));
1455 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1456 red
->setSrc(2, su
->getSrc(4));
1457 red
->setIndirect(0, 0, su
->getSrc(0));
1458 red
->setPredicate(cc
, pred
);
1459 delete_Instruction(bld
.getProgram(), su
);
1460 handleCasExch(red
, true);
1462 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
1467 NVC0LoweringPass::handleWRSV(Instruction
*i
)
1473 // must replace, $sreg are not writeable
1474 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
1477 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
1479 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
1481 st
->perPatch
= i
->perPatch
;
1483 bld
.getBB()->remove(i
);
1488 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
1490 Value
*laneid
= bld
.getSSA();
1493 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
1508 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
1510 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
1513 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
1514 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
1519 NVC0LoweringPass::handleRDSV(Instruction
*i
)
1521 Symbol
*sym
= i
->getSrc(0)->asSym();
1522 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
1525 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
1527 if (addr
>= 0x400) {
1529 if (sym
->reg
.data
.sv
.index
== 3) {
1530 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
1532 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
1534 if (sv
== SV_VERTEX_COUNT
) {
1535 bld
.setPosition(i
, true);
1536 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(0x808));
1543 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
1544 if (i
->srcExists(1)) {
1545 // Pass offset through to the interpolation logic
1546 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
1547 i
->getDef(0), addr
, NULL
);
1548 ld
->setSrc(1, i
->getSrc(1));
1550 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
1555 Value
*face
= i
->getDef(0);
1556 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
1557 if (i
->dType
== TYPE_F32
) {
1558 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
1559 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
1560 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
1565 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
1566 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
1571 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
1572 if (sym
->reg
.data
.sv
.index
== 3) {
1574 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
1577 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
1578 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
1579 bld
.mkSymbol(FILE_MEMORY_CONST
, 0, TYPE_U32
, addr
), NULL
);
1581 case SV_SAMPLE_INDEX
:
1582 // TODO: Properly pass source as an address in the PIX address space
1583 // (which can be of the form [r0+offset]). But this is currently
1585 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1586 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1588 case SV_SAMPLE_POS
: {
1589 Value
*off
= new_LValue(func
, FILE_GPR
);
1590 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1591 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1592 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
1593 bld
.mkLoad(TYPE_F32
,
1596 FILE_MEMORY_CONST
, prog
->driver
->io
.resInfoCBSlot
,
1597 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
1598 4 * sym
->reg
.data
.sv
.index
),
1602 case SV_SAMPLE_MASK
:
1603 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1604 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
1607 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
&& !i
->perPatch
)
1608 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
1609 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
1610 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
1611 ld
->perPatch
= i
->perPatch
;
1614 bld
.getBB()->remove(i
);
1619 NVC0LoweringPass::handleDIV(Instruction
*i
)
1621 if (!isFloatType(i
->dType
))
1623 bld
.setPosition(i
, false);
1624 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
1626 i
->setSrc(1, rcp
->getDef(0));
1631 NVC0LoweringPass::handleMOD(Instruction
*i
)
1633 if (!isFloatType(i
->dType
))
1635 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
1636 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
1637 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
1638 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
1639 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
1641 i
->setSrc(1, value
);
1646 NVC0LoweringPass::handleSQRT(Instruction
*i
)
1648 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
1649 Value
*zero
= bld
.getSSA();
1652 bld
.mkOp1(OP_MOV
, TYPE_U32
, zero
, bld
.mkImm(0));
1653 if (i
->dType
== TYPE_F64
)
1654 zero
= bld
.mkOp2v(OP_MERGE
, TYPE_U64
, bld
.getSSA(8), zero
, zero
);
1655 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
1656 bld
.mkOp1(OP_MOV
, i
->dType
, i
->getDef(0), zero
)->setPredicate(CC_P
, pred
);
1657 rsq
= bld
.mkOp1(OP_RSQ
, i
->dType
,
1658 bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(0));
1659 rsq
->setPredicate(CC_NOT_P
, pred
);
1661 i
->setSrc(1, rsq
->getDef(0));
1662 i
->setPredicate(CC_NOT_P
, pred
);
1669 NVC0LoweringPass::handlePOW(Instruction
*i
)
1671 LValue
*val
= bld
.getScratch();
1673 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
1674 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
1675 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
1685 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
1687 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1688 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
1690 if (i
->src(0).isIndirect(0)) // TODO, ugly
1693 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
1694 i
->src(0).set(i
->src(1));
1696 i
->setDef(0, new_LValue(func
, FILE_GPR
));
1697 i
->getDef(0)->reg
.data
.id
= id
;
1699 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
1701 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
1702 i
->setIndirect(0, 1, gpEmitAddress
);
1708 NVC0LoweringPass::handleOUT(Instruction
*i
)
1710 Instruction
*prev
= i
->prev
;
1711 ImmediateValue stream
, prevStream
;
1713 // Only merge if the stream ids match. Also, note that the previous
1714 // instruction would have already been lowered, so we take arg1 from it.
1715 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
1716 i
->src(0).getImmediate(stream
) &&
1717 prev
->src(1).getImmediate(prevStream
) &&
1718 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
1719 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
1720 delete_Instruction(prog
, i
);
1722 assert(gpEmitAddress
);
1723 i
->setDef(0, gpEmitAddress
);
1724 i
->setSrc(1, i
->getSrc(0));
1725 i
->setSrc(0, gpEmitAddress
);
1730 // Generate a binary predicate if an instruction is predicated by
1731 // e.g. an f32 value.
1733 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
1735 Value
*pred
= insn
->getPredicate();
1738 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
1740 pdst
= new_LValue(func
, FILE_PREDICATE
);
1742 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
1743 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
1745 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
1747 insn
->setPredicate(insn
->cc
, pdst
);
1751 // - add quadop dance for texturing
1752 // - put FP outputs in GPRs
1753 // - convert instruction sequences
1756 NVC0LoweringPass::visit(Instruction
*i
)
1759 bld
.setPosition(i
, false);
1761 if (i
->cc
!= CC_ALWAYS
)
1770 return handleTEX(i
->asTex());
1772 return handleTXD(i
->asTex());
1774 return handleTXLQ(i
->asTex());
1776 return handleTXQ(i
->asTex());
1778 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
1779 i
->setSrc(0, i
->getDef(0));
1782 return handlePOW(i
);
1784 return handleDIV(i
);
1786 return handleMOD(i
);
1788 return handleSQRT(i
);
1790 ret
= handleEXPORT(i
);
1794 return handleOUT(i
);
1796 return handleRDSV(i
);
1798 return handleWRSV(i
);
1800 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
1801 if (prog
->getType() == Program::TYPE_COMPUTE
) {
1802 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
1803 i
->getSrc(0)->reg
.fileIndex
= 0;
1805 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
1806 i
->src(0).isIndirect(0)) {
1807 // XXX: this assumes vec4 units
1808 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1809 i
->getIndirect(0, 0), bld
.mkImm(4));
1810 i
->setIndirect(0, 0, ptr
);
1814 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
1816 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
1817 if (i
->src(0).isIndirect(1)) {
1819 if (i
->src(0).isIndirect(0))
1820 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
1821 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
1822 i
->getIndirect(0, 0));
1824 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1825 i
->getIndirect(0, 1), bld
.mkImm(16));
1826 i
->setIndirect(0, 1, NULL
);
1827 i
->setIndirect(0, 0, ptr
);
1828 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
1830 } else if (i
->src(0).getFile() == FILE_SHADER_OUTPUT
) {
1831 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
1837 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_GLOBAL
;
1839 handleCasExch(i
, cctl
);
1848 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1849 handleSurfaceOpNVE4(i
->asTex());
1855 /* Kepler+ has a special opcode to compute a new base address to be used
1856 * for indirect loads.
1858 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&& !i
->perPatch
&&
1859 (i
->op
== OP_VFETCH
|| i
->op
== OP_EXPORT
) && i
->src(0).isIndirect(0)) {
1860 Instruction
*afetch
= bld
.mkOp1(OP_AFETCH
, TYPE_U32
, bld
.getSSA(),
1861 cloneShallow(func
, i
->getSrc(0)));
1862 afetch
->setIndirect(0, 0, i
->getIndirect(0, 0));
1863 i
->src(0).get()->reg
.data
.offset
= 0;
1864 i
->setIndirect(0, 0, afetch
->getDef(0));
1871 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
1873 if (stage
== CG_STAGE_PRE_SSA
) {
1874 NVC0LoweringPass
pass(prog
);
1875 return pass
.run(prog
, false, true);
1877 if (stage
== CG_STAGE_POST_RA
) {
1878 NVC0LegalizePostRA
pass(prog
);
1879 return pass
.run(prog
, false, true);
1881 if (stage
== CG_STAGE_SSA
) {
1882 NVC0LegalizeSSA pass
;
1883 return pass
.run(prog
, false, true);
1888 } // namespace nv50_ir