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nvc0/ir: support 2d constbuf indexing
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_lowering_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
25
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
28
29 #include <limits>
30
31 namespace nv50_ir {
32
33 #define QOP_ADD 0
34 #define QOP_SUBR 1
35 #define QOP_SUB 2
36 #define QOP_MOV2 3
37
38 // UL UR LL LR
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
42
43 void
44 NVC0LegalizeSSA::handleDIV(Instruction *i)
45 {
46 FlowInstruction *call;
47 int builtin;
48 Value *def[2];
49
50 bld.setPosition(i, false);
51 def[0] = bld.mkMovToReg(0, i->getSrc(0))->getDef(0);
52 def[1] = bld.mkMovToReg(1, i->getSrc(1))->getDef(0);
53 switch (i->dType) {
54 case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break;
55 case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break;
56 default:
57 return;
58 }
59 call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
60 bld.mkMov(i->getDef(0), def[(i->op == OP_DIV) ? 0 : 1]);
61 bld.mkClobber(FILE_GPR, (i->op == OP_DIV) ? 0xe : 0xd, 2);
62 bld.mkClobber(FILE_PREDICATE, (i->dType == TYPE_S32) ? 0xf : 0x3, 0);
63
64 call->fixed = 1;
65 call->absolute = call->builtin = 1;
66 call->target.builtin = builtin;
67 delete_Instruction(prog, i);
68 }
69
70 void
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
72 {
73 // TODO
74 }
75
76 bool
77 NVC0LegalizeSSA::visit(Function *fn)
78 {
79 bld.setProgram(fn->getProgram());
80 return true;
81 }
82
83 bool
84 NVC0LegalizeSSA::visit(BasicBlock *bb)
85 {
86 Instruction *next;
87 for (Instruction *i = bb->getEntry(); i; i = next) {
88 next = i->next;
89 if (i->dType == TYPE_F32)
90 continue;
91 switch (i->op) {
92 case OP_DIV:
93 case OP_MOD:
94 handleDIV(i);
95 break;
96 case OP_RCP:
97 case OP_RSQ:
98 if (i->dType == TYPE_F64)
99 handleRCPRSQ(i);
100 break;
101 default:
102 break;
103 }
104 }
105 return true;
106 }
107
108 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program *prog)
109 : rZero(NULL),
110 carry(NULL),
111 needTexBar(prog->getTarget()->getChipset() >= 0xe0)
112 {
113 }
114
115 bool
116 NVC0LegalizePostRA::insnDominatedBy(const Instruction *later,
117 const Instruction *early) const
118 {
119 if (early->bb == later->bb)
120 return early->serial < later->serial;
121 return later->bb->dominatedBy(early->bb);
122 }
123
124 void
125 NVC0LegalizePostRA::addTexUse(std::list<TexUse> &uses,
126 Instruction *usei, const Instruction *insn)
127 {
128 bool add = true;
129 for (std::list<TexUse>::iterator it = uses.begin();
130 it != uses.end();) {
131 if (insnDominatedBy(usei, it->insn)) {
132 add = false;
133 break;
134 }
135 if (insnDominatedBy(it->insn, usei))
136 it = uses.erase(it);
137 else
138 ++it;
139 }
140 if (add)
141 uses.push_back(TexUse(usei, insn));
142 }
143
144 void
145 NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
146 Instruction *insn,
147 const BasicBlock *term,
148 std::list<TexUse> &uses)
149 {
150 while (insn->op == OP_MOV && insn->getDef(0)->equals(insn->getSrc(0)))
151 insn = insn->getSrc(0)->getUniqueInsn();
152
153 if (!insn || !insn->bb->reachableBy(texi->bb, term))
154 return;
155
156 switch (insn->op) {
157 /* Values not connected to the tex's definition through any of these should
158 * not be conflicting.
159 */
160 case OP_SPLIT:
161 case OP_MERGE:
162 case OP_PHI:
163 case OP_UNION:
164 /* recurse again */
165 for (int s = 0; insn->srcExists(s); ++s)
166 findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsn(), term,
167 uses);
168 break;
169 default:
170 // if (!isTextureOp(insn->op)) // TODO: are TEXes always ordered ?
171 addTexUse(uses, insn, texi);
172 break;
173 }
174 }
175
176 void
177 NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
178 const Instruction *insn,
179 std::list<TexUse> &uses)
180 {
181 for (int d = 0; insn->defExists(d); ++d) {
182 Value *v = insn->getDef(d);
183 for (Value::UseIterator u = v->uses.begin(); u != v->uses.end(); ++u) {
184 Instruction *usei = (*u)->getInsn();
185
186 if (usei->op == OP_PHI || usei->op == OP_UNION) {
187 // need a barrier before WAW cases
188 for (int s = 0; usei->srcExists(s); ++s) {
189 Instruction *defi = usei->getSrc(s)->getUniqueInsn();
190 if (defi && &usei->src(s) != *u)
191 findOverwritingDefs(texi, defi, usei->bb, uses);
192 }
193 }
194
195 if (usei->op == OP_SPLIT ||
196 usei->op == OP_MERGE ||
197 usei->op == OP_PHI ||
198 usei->op == OP_UNION) {
199 // these uses don't manifest in the machine code
200 findFirstUses(texi, usei, uses);
201 } else
202 if (usei->op == OP_MOV && usei->getDef(0)->equals(usei->getSrc(0)) &&
203 usei->subOp != NV50_IR_SUBOP_MOV_FINAL) {
204 findFirstUses(texi, usei, uses);
205 } else {
206 addTexUse(uses, usei, insn);
207 }
208 }
209 }
210 }
211
212 // Texture barriers:
213 // This pass is a bit long and ugly and can probably be optimized.
214 //
215 // 1. obtain a list of TEXes and their outputs' first use(s)
216 // 2. calculate the barrier level of each first use (minimal number of TEXes,
217 // over all paths, between the TEX and the use in question)
218 // 3. for each barrier, if all paths from the source TEX to that barrier
219 // contain a barrier of lesser level, it can be culled
220 bool
221 NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
222 {
223 std::list<TexUse> *uses;
224 std::vector<Instruction *> texes;
225 std::vector<int> bbFirstTex;
226 std::vector<int> bbFirstUse;
227 std::vector<int> texCounts;
228 std::vector<TexUse> useVec;
229 ArrayList insns;
230
231 fn->orderInstructions(insns);
232
233 texCounts.resize(fn->allBBlocks.getSize(), 0);
234 bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
235 bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
236
237 // tag BB CFG nodes by their id for later
238 for (ArrayList::Iterator i = fn->allBBlocks.iterator(); !i.end(); i.next()) {
239 BasicBlock *bb = reinterpret_cast<BasicBlock *>(i.get());
240 if (bb)
241 bb->cfg.tag = bb->getId();
242 }
243
244 // gather the first uses for each TEX
245 for (int i = 0; i < insns.getSize(); ++i) {
246 Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
247 if (isTextureOp(tex->op)) {
248 texes.push_back(tex);
249 if (!texCounts.at(tex->bb->getId()))
250 bbFirstTex[tex->bb->getId()] = texes.size() - 1;
251 texCounts[tex->bb->getId()]++;
252 }
253 }
254 insns.clear();
255 if (texes.empty())
256 return false;
257 uses = new std::list<TexUse>[texes.size()];
258 if (!uses)
259 return false;
260 for (size_t i = 0; i < texes.size(); ++i)
261 findFirstUses(texes[i], texes[i], uses[i]);
262
263 // determine the barrier level at each use
264 for (size_t i = 0; i < texes.size(); ++i) {
265 for (std::list<TexUse>::iterator u = uses[i].begin(); u != uses[i].end();
266 ++u) {
267 BasicBlock *tb = texes[i]->bb;
268 BasicBlock *ub = u->insn->bb;
269 if (tb == ub) {
270 u->level = 0;
271 for (size_t j = i + 1; j < texes.size() &&
272 texes[j]->bb == tb && texes[j]->serial < u->insn->serial;
273 ++j)
274 u->level++;
275 } else {
276 u->level = fn->cfg.findLightestPathWeight(&tb->cfg,
277 &ub->cfg, texCounts);
278 if (u->level < 0) {
279 WARN("Failed to find path TEX -> TEXBAR\n");
280 u->level = 0;
281 continue;
282 }
283 // this counted all TEXes in the origin block, correct that
284 u->level -= i - bbFirstTex.at(tb->getId()) + 1 /* this TEX */;
285 // and did not count the TEXes in the destination block, add those
286 for (size_t j = bbFirstTex.at(ub->getId()); j < texes.size() &&
287 texes[j]->bb == ub && texes[j]->serial < u->insn->serial;
288 ++j)
289 u->level++;
290 }
291 assert(u->level >= 0);
292 useVec.push_back(*u);
293 }
294 }
295 delete[] uses;
296 uses = NULL;
297
298 // insert the barriers
299 for (size_t i = 0; i < useVec.size(); ++i) {
300 Instruction *prev = useVec[i].insn->prev;
301 if (useVec[i].level < 0)
302 continue;
303 if (prev && prev->op == OP_TEXBAR) {
304 if (prev->subOp > useVec[i].level)
305 prev->subOp = useVec[i].level;
306 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0));
307 } else {
308 Instruction *bar = new_Instruction(func, OP_TEXBAR, TYPE_NONE);
309 bar->fixed = 1;
310 bar->subOp = useVec[i].level;
311 // make use explicit to ease latency calculation
312 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0));
313 useVec[i].insn->bb->insertBefore(useVec[i].insn, bar);
314 }
315 }
316
317 if (fn->getProgram()->optLevel < 3) {
318 if (uses)
319 delete[] uses;
320 return true;
321 }
322
323 std::vector<Limits> limitT, limitB, limitS; // entry, exit, single
324
325 limitT.resize(fn->allBBlocks.getSize(), Limits(0, 0));
326 limitB.resize(fn->allBBlocks.getSize(), Limits(0, 0));
327 limitS.resize(fn->allBBlocks.getSize());
328
329 // cull unneeded barriers (should do that earlier, but for simplicity)
330 IteratorRef bi = fn->cfg.iteratorCFG();
331 // first calculate min/max outstanding TEXes for each BB
332 for (bi->reset(); !bi->end(); bi->next()) {
333 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
334 BasicBlock *bb = BasicBlock::get(n);
335 int min = 0;
336 int max = std::numeric_limits<int>::max();
337 for (Instruction *i = bb->getFirst(); i; i = i->next) {
338 if (isTextureOp(i->op)) {
339 min++;
340 if (max < std::numeric_limits<int>::max())
341 max++;
342 } else
343 if (i->op == OP_TEXBAR) {
344 min = MIN2(min, i->subOp);
345 max = MIN2(max, i->subOp);
346 }
347 }
348 // limits when looking at an isolated block
349 limitS[bb->getId()].min = min;
350 limitS[bb->getId()].max = max;
351 }
352 // propagate the min/max values
353 for (unsigned int l = 0; l <= fn->loopNestingBound; ++l) {
354 for (bi->reset(); !bi->end(); bi->next()) {
355 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
356 BasicBlock *bb = BasicBlock::get(n);
357 const int bbId = bb->getId();
358 for (Graph::EdgeIterator ei = n->incident(); !ei.end(); ei.next()) {
359 BasicBlock *in = BasicBlock::get(ei.getNode());
360 const int inId = in->getId();
361 limitT[bbId].min = MAX2(limitT[bbId].min, limitB[inId].min);
362 limitT[bbId].max = MAX2(limitT[bbId].max, limitB[inId].max);
363 }
364 // I just hope this is correct ...
365 if (limitS[bbId].max == std::numeric_limits<int>::max()) {
366 // no barrier
367 limitB[bbId].min = limitT[bbId].min + limitS[bbId].min;
368 limitB[bbId].max = limitT[bbId].max + limitS[bbId].min;
369 } else {
370 // block contained a barrier
371 limitB[bbId].min = MIN2(limitS[bbId].max,
372 limitT[bbId].min + limitS[bbId].min);
373 limitB[bbId].max = MIN2(limitS[bbId].max,
374 limitT[bbId].max + limitS[bbId].min);
375 }
376 }
377 }
378 // finally delete unnecessary barriers
379 for (bi->reset(); !bi->end(); bi->next()) {
380 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
381 BasicBlock *bb = BasicBlock::get(n);
382 Instruction *prev = NULL;
383 Instruction *next;
384 int max = limitT[bb->getId()].max;
385 for (Instruction *i = bb->getFirst(); i; i = next) {
386 next = i->next;
387 if (i->op == OP_TEXBAR) {
388 if (i->subOp >= max) {
389 delete_Instruction(prog, i);
390 i = NULL;
391 } else {
392 max = i->subOp;
393 if (prev && prev->op == OP_TEXBAR && prev->subOp >= max) {
394 delete_Instruction(prog, prev);
395 prev = NULL;
396 }
397 }
398 } else
399 if (isTextureOp(i->op)) {
400 max++;
401 }
402 if (i && !i->isNop())
403 prev = i;
404 }
405 }
406 if (uses)
407 delete[] uses;
408 return true;
409 }
410
411 bool
412 NVC0LegalizePostRA::visit(Function *fn)
413 {
414 if (needTexBar)
415 insertTextureBarriers(fn);
416
417 rZero = new_LValue(fn, FILE_GPR);
418 carry = new_LValue(fn, FILE_FLAGS);
419
420 rZero->reg.data.id = prog->getTarget()->getFileSize(FILE_GPR);
421 carry->reg.data.id = 0;
422
423 return true;
424 }
425
426 void
427 NVC0LegalizePostRA::replaceZero(Instruction *i)
428 {
429 for (int s = 0; i->srcExists(s); ++s) {
430 if (s == 2 && i->op == OP_SUCLAMP)
431 continue;
432 ImmediateValue *imm = i->getSrc(s)->asImm();
433 if (imm && imm->reg.data.u64 == 0)
434 i->setSrc(s, rZero);
435 }
436 }
437
438 // replace CONT with BRA for single unconditional continue
439 bool
440 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock *bb)
441 {
442 if (bb->cfg.incidentCount() != 2 || bb->getEntry()->op != OP_PRECONT)
443 return false;
444 Graph::EdgeIterator ei = bb->cfg.incident();
445 if (ei.getType() != Graph::Edge::BACK)
446 ei.next();
447 if (ei.getType() != Graph::Edge::BACK)
448 return false;
449 BasicBlock *contBB = BasicBlock::get(ei.getNode());
450
451 if (!contBB->getExit() || contBB->getExit()->op != OP_CONT ||
452 contBB->getExit()->getPredicate())
453 return false;
454 contBB->getExit()->op = OP_BRA;
455 bb->remove(bb->getEntry()); // delete PRECONT
456
457 ei.next();
458 assert(ei.end() || ei.getType() != Graph::Edge::BACK);
459 return true;
460 }
461
462 // replace branches to join blocks with join ops
463 void
464 NVC0LegalizePostRA::propagateJoin(BasicBlock *bb)
465 {
466 if (bb->getEntry()->op != OP_JOIN || bb->getEntry()->asFlow()->limit)
467 return;
468 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
469 BasicBlock *in = BasicBlock::get(ei.getNode());
470 Instruction *exit = in->getExit();
471 if (!exit) {
472 in->insertTail(new FlowInstruction(func, OP_JOIN, bb));
473 // there should always be a terminator instruction
474 WARN("inserted missing terminator in BB:%i\n", in->getId());
475 } else
476 if (exit->op == OP_BRA) {
477 exit->op = OP_JOIN;
478 exit->asFlow()->limit = 1; // must-not-propagate marker
479 }
480 }
481 bb->remove(bb->getEntry());
482 }
483
484 bool
485 NVC0LegalizePostRA::visit(BasicBlock *bb)
486 {
487 Instruction *i, *next;
488
489 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
490 for (i = bb->getFirst(); i; i = next) {
491 next = i->next;
492 if (i->op == OP_EMIT || i->op == OP_RESTART) {
493 if (!i->getDef(0)->refCount())
494 i->setDef(0, NULL);
495 if (i->src(0).getFile() == FILE_IMMEDIATE)
496 i->setSrc(0, rZero); // initial value must be 0
497 replaceZero(i);
498 } else
499 if (i->isNop()) {
500 bb->remove(i);
501 } else {
502 // TODO: Move this to before register allocation for operations that
503 // need the $c register !
504 if (typeSizeof(i->dType) == 8) {
505 Instruction *hi;
506 hi = BuildUtil::split64BitOpPostRA(func, i, rZero, carry);
507 if (hi)
508 next = hi;
509 }
510
511 if (i->op != OP_MOV && i->op != OP_PFETCH)
512 replaceZero(i);
513 }
514 }
515 if (!bb->getEntry())
516 return true;
517
518 if (!tryReplaceContWithBra(bb))
519 propagateJoin(bb);
520
521 return true;
522 }
523
524 NVC0LoweringPass::NVC0LoweringPass(Program *prog) : targ(prog->getTarget())
525 {
526 bld.setProgram(prog);
527 gMemBase = NULL;
528 }
529
530 bool
531 NVC0LoweringPass::visit(Function *fn)
532 {
533 if (prog->getType() == Program::TYPE_GEOMETRY) {
534 assert(!strncmp(fn->getName(), "MAIN", 4));
535 // TODO: when we generate actual functions pass this value along somehow
536 bld.setPosition(BasicBlock::get(fn->cfg.getRoot()), false);
537 gpEmitAddress = bld.loadImm(NULL, 0)->asLValue();
538 if (fn->cfgExit) {
539 bld.setPosition(BasicBlock::get(fn->cfgExit)->getExit(), false);
540 bld.mkMovToReg(0, gpEmitAddress);
541 }
542 }
543 return true;
544 }
545
546 bool
547 NVC0LoweringPass::visit(BasicBlock *bb)
548 {
549 return true;
550 }
551
552 inline Value *
553 NVC0LoweringPass::loadTexHandle(Value *ptr, unsigned int slot)
554 {
555 uint8_t b = prog->driver->io.resInfoCBSlot;
556 uint32_t off = prog->driver->io.texBindBase + slot * 4;
557 return bld.
558 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
559 }
560
561 // move array source to first slot, convert to u16, add indirections
562 bool
563 NVC0LoweringPass::handleTEX(TexInstruction *i)
564 {
565 const int dim = i->tex.target.getDim() + i->tex.target.isCube();
566 const int arg = i->tex.target.getArgCount();
567 const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
568 const int chipset = prog->getTarget()->getChipset();
569
570 if (chipset >= NVISA_GK104_CHIPSET) {
571 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
572 WARN("indirect TEX not implemented\n");
573 }
574 if (i->tex.r == i->tex.s) {
575 i->tex.r += prog->driver->io.texBindBase / 4;
576 i->tex.s = 0; // only a single cX[] value possible here
577 } else {
578 Value *hnd = bld.getScratch();
579 Value *rHnd = loadTexHandle(NULL, i->tex.r);
580 Value *sHnd = loadTexHandle(NULL, i->tex.s);
581
582 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
583
584 i->tex.r = 0; // not used for indirect tex
585 i->tex.s = 0;
586 i->setIndirectR(hnd);
587 }
588 if (i->tex.target.isArray()) {
589 LValue *layer = new_LValue(func, FILE_GPR);
590 Value *src = i->getSrc(lyr);
591 const int sat = (i->op == OP_TXF) ? 1 : 0;
592 DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
593 bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat;
594 for (int s = dim; s >= 1; --s)
595 i->setSrc(s, i->getSrc(s - 1));
596 i->setSrc(0, layer);
597 }
598 } else
599 // (nvc0) generate and move the tsc/tic/array source to the front
600 if (i->tex.target.isArray() || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
601 LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
602
603 Value *ticRel = i->getIndirectR();
604 Value *tscRel = i->getIndirectS();
605
606 if (ticRel)
607 i->setSrc(i->tex.rIndirectSrc, NULL);
608 if (tscRel)
609 i->setSrc(i->tex.sIndirectSrc, NULL);
610
611 Value *arrayIndex = i->tex.target.isArray() ? i->getSrc(lyr) : NULL;
612 for (int s = dim; s >= 1; --s)
613 i->setSrc(s, i->getSrc(s - 1));
614 i->setSrc(0, arrayIndex);
615
616 if (arrayIndex) {
617 int sat = (i->op == OP_TXF) ? 1 : 0;
618 DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
619 bld.mkCvt(OP_CVT, TYPE_U16, src, sTy, arrayIndex)->saturate = sat;
620 } else {
621 bld.loadImm(src, 0);
622 }
623
624 if (ticRel)
625 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
626 if (tscRel)
627 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
628
629 i->setSrc(0, src);
630 }
631
632 // For nvc0, the sample id has to be in the second operand, as the offset
633 // does. Right now we don't know how to pass both in, and this case can't
634 // happen with OpenGL. On nve0, the sample id is part of the texture
635 // coordinate argument.
636 assert(chipset >= NVISA_GK104_CHIPSET ||
637 !i->tex.useOffsets || !i->tex.target.isMS());
638
639 // offset is between lod and dc
640 if (i->tex.useOffsets) {
641 int n, c;
642 int s = i->srcCount(0xff, true);
643 if (i->op != OP_TXD || chipset < NVISA_GK104_CHIPSET) {
644 if (i->tex.target.isShadow())
645 s--;
646 if (i->srcExists(s)) // move potential predicate out of the way
647 i->moveSources(s, 1);
648 if (i->tex.useOffsets == 4 && i->srcExists(s + 1))
649 i->moveSources(s + 1, 1);
650 }
651 if (i->op == OP_TXG) {
652 // Either there is 1 offset, which goes into the 2 low bytes of the
653 // first source, or there are 4 offsets, which go into 2 sources (8
654 // values, 1 byte each).
655 Value *offs[2] = {NULL, NULL};
656 for (n = 0; n < i->tex.useOffsets; n++) {
657 for (c = 0; c < 2; ++c) {
658 if ((n % 2) == 0 && c == 0)
659 offs[n / 2] = i->offset[n][c].get();
660 else
661 bld.mkOp3(OP_INSBF, TYPE_U32,
662 offs[n / 2],
663 i->offset[n][c].get(),
664 bld.mkImm(0x800 | ((n * 16 + c * 8) % 32)),
665 offs[n / 2]);
666 }
667 }
668 i->setSrc(s, offs[0]);
669 if (offs[1])
670 i->setSrc(s + 1, offs[1]);
671 } else {
672 unsigned imm = 0;
673 assert(i->tex.useOffsets == 1);
674 for (c = 0; c < 3; ++c) {
675 ImmediateValue val;
676 assert(i->offset[0][c].getImmediate(val));
677 imm |= (val.reg.data.u32 & 0xf) << (c * 4);
678 }
679 if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
680 // The offset goes into the upper 16 bits of the array index. So
681 // create it if it's not already there, and INSBF it if it already
682 // is.
683 if (i->tex.target.isArray()) {
684 bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(0),
685 bld.loadImm(NULL, imm), bld.mkImm(0xc10),
686 i->getSrc(0));
687 } else {
688 for (int s = dim; s >= 1; --s)
689 i->setSrc(s, i->getSrc(s - 1));
690 i->setSrc(0, bld.loadImm(NULL, imm << 16));
691 }
692 } else {
693 i->setSrc(s, bld.loadImm(NULL, imm));
694 }
695 }
696 }
697
698 if (chipset >= NVISA_GK104_CHIPSET) {
699 //
700 // If TEX requires more than 4 sources, the 2nd register tuple must be
701 // aligned to 4, even if it consists of just a single 4-byte register.
702 //
703 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
704 //
705 int s = i->srcCount(0xff, true);
706 if (s > 4 && s < 7) {
707 if (i->srcExists(s)) // move potential predicate out of the way
708 i->moveSources(s, 7 - s);
709 while (s < 7)
710 i->setSrc(s++, bld.loadImm(NULL, 0));
711 }
712 }
713
714 return true;
715 }
716
717 bool
718 NVC0LoweringPass::handleManualTXD(TexInstruction *i)
719 {
720 static const uint8_t qOps[4][2] =
721 {
722 { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) }, // l0
723 { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(MOV2, MOV2, ADD, ADD) }, // l1
724 { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(SUBR, SUBR, MOV2, MOV2) }, // l2
725 { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(SUBR, SUBR, MOV2, MOV2) }, // l3
726 };
727 Value *def[4][4];
728 Value *crd[3];
729 Instruction *tex;
730 Value *zero = bld.loadImm(bld.getSSA(), 0);
731 int l, c;
732 const int dim = i->tex.target.getDim();
733 const int array = i->tex.target.isArray();
734
735 i->op = OP_TEX; // no need to clone dPdx/dPdy later
736
737 for (c = 0; c < dim; ++c)
738 crd[c] = bld.getScratch();
739
740 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
741 for (l = 0; l < 4; ++l) {
742 // mov coordinates from lane l to all lanes
743 for (c = 0; c < dim; ++c)
744 bld.mkQuadop(0x00, crd[c], l, i->getSrc(c + array), zero);
745 // add dPdx from lane l to lanes dx
746 for (c = 0; c < dim; ++c)
747 bld.mkQuadop(qOps[l][0], crd[c], l, i->dPdx[c].get(), crd[c]);
748 // add dPdy from lane l to lanes dy
749 for (c = 0; c < dim; ++c)
750 bld.mkQuadop(qOps[l][1], crd[c], l, i->dPdy[c].get(), crd[c]);
751 // texture
752 bld.insert(tex = cloneForward(func, i));
753 for (c = 0; c < dim; ++c)
754 tex->setSrc(c + array, crd[c]);
755 // save results
756 for (c = 0; i->defExists(c); ++c) {
757 Instruction *mov;
758 def[c][l] = bld.getSSA();
759 mov = bld.mkMov(def[c][l], tex->getDef(c));
760 mov->fixed = 1;
761 mov->lanes = 1 << l;
762 }
763 }
764 bld.mkOp(OP_QUADPOP, TYPE_NONE, NULL);
765
766 for (c = 0; i->defExists(c); ++c) {
767 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c));
768 for (l = 0; l < 4; ++l)
769 u->setSrc(l, def[c][l]);
770 }
771
772 i->bb->remove(i);
773 return true;
774 }
775
776 bool
777 NVC0LoweringPass::handleTXD(TexInstruction *txd)
778 {
779 int dim = txd->tex.target.getDim();
780 unsigned arg = txd->tex.target.getArgCount();
781 unsigned expected_args = arg;
782 const int chipset = prog->getTarget()->getChipset();
783
784 if (chipset >= NVISA_GK104_CHIPSET) {
785 if (!txd->tex.target.isArray() && txd->tex.useOffsets)
786 expected_args++;
787 } else {
788 if (txd->tex.useOffsets)
789 expected_args++;
790 if (!txd->tex.target.isArray() && (
791 txd->tex.rIndirectSrc >= 0 || txd->tex.sIndirectSrc >= 0))
792 expected_args++;
793 }
794
795 if (expected_args > 4 ||
796 dim > 2 ||
797 txd->tex.target.isShadow() ||
798 txd->tex.target.isCube())
799 txd->op = OP_TEX;
800
801 handleTEX(txd);
802 while (txd->srcExists(arg))
803 ++arg;
804
805 txd->tex.derivAll = true;
806 if (txd->op == OP_TEX)
807 return handleManualTXD(txd);
808
809 assert(arg == expected_args);
810 for (int c = 0; c < dim; ++c) {
811 txd->setSrc(arg + c * 2 + 0, txd->dPdx[c]);
812 txd->setSrc(arg + c * 2 + 1, txd->dPdy[c]);
813 txd->dPdx[c].set(NULL);
814 txd->dPdy[c].set(NULL);
815 }
816 return true;
817 }
818
819 bool
820 NVC0LoweringPass::handleTXQ(TexInstruction *txq)
821 {
822 // TODO: indirect resource/sampler index
823 return true;
824 }
825
826 bool
827 NVC0LoweringPass::handleTXLQ(TexInstruction *i)
828 {
829 /* The outputs are inverted compared to what the TGSI instruction
830 * expects. Take that into account in the mask.
831 */
832 assert((i->tex.mask & ~3) == 0);
833 if (i->tex.mask == 1)
834 i->tex.mask = 2;
835 else if (i->tex.mask == 2)
836 i->tex.mask = 1;
837 handleTEX(i);
838 bld.setPosition(i, true);
839
840 /* The returned values are not quite what we want:
841 * (a) convert from s16/u16 to f32
842 * (b) multiply by 1/256
843 */
844 for (int def = 0; def < 2; ++def) {
845 if (!i->defExists(def))
846 continue;
847 enum DataType type = TYPE_S16;
848 if (i->tex.mask == 2 || def > 0)
849 type = TYPE_U16;
850 bld.mkCvt(OP_CVT, TYPE_F32, i->getDef(def), type, i->getDef(def));
851 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(def),
852 i->getDef(def), bld.loadImm(NULL, 1.0f / 256));
853 }
854 if (i->tex.mask == 3) {
855 LValue *t = new_LValue(func, FILE_GPR);
856 bld.mkMov(t, i->getDef(0));
857 bld.mkMov(i->getDef(0), i->getDef(1));
858 bld.mkMov(i->getDef(1), t);
859 }
860 return true;
861 }
862
863
864 bool
865 NVC0LoweringPass::handleATOM(Instruction *atom)
866 {
867 SVSemantic sv;
868
869 switch (atom->src(0).getFile()) {
870 case FILE_MEMORY_LOCAL:
871 sv = SV_LBASE;
872 break;
873 case FILE_MEMORY_SHARED:
874 sv = SV_SBASE;
875 break;
876 default:
877 assert(atom->src(0).getFile() == FILE_MEMORY_GLOBAL);
878 return true;
879 }
880 Value *base =
881 bld.mkOp1v(OP_RDSV, TYPE_U32, bld.getScratch(), bld.mkSysVal(sv, 0));
882 Value *ptr = atom->getIndirect(0, 0);
883
884 atom->setSrc(0, cloneShallow(func, atom->getSrc(0)));
885 atom->getSrc(0)->reg.file = FILE_MEMORY_GLOBAL;
886 if (ptr)
887 base = bld.mkOp2v(OP_ADD, TYPE_U32, base, base, ptr);
888 atom->setIndirect(0, 0, base);
889
890 return true;
891 }
892
893 bool
894 NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl)
895 {
896 if (cas->subOp != NV50_IR_SUBOP_ATOM_CAS &&
897 cas->subOp != NV50_IR_SUBOP_ATOM_EXCH)
898 return false;
899 bld.setPosition(cas, true);
900
901 if (needCctl) {
902 Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, cas->getSrc(0));
903 cctl->setIndirect(0, 0, cas->getIndirect(0, 0));
904 cctl->fixed = 1;
905 cctl->subOp = NV50_IR_SUBOP_CCTL_IV;
906 if (cas->isPredicated())
907 cctl->setPredicate(cas->cc, cas->getPredicate());
908 }
909
910 if (cas->defExists(0) && cas->subOp == NV50_IR_SUBOP_ATOM_CAS) {
911 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
912 // should be set to the high part of the double reg or bad things will
913 // happen elsewhere in the universe.
914 // Also, it sometimes returns the new value instead of the old one
915 // under mysterious circumstances.
916 Value *dreg = bld.getSSA(8);
917 bld.setPosition(cas, false);
918 bld.mkOp2(OP_MERGE, TYPE_U64, dreg, cas->getSrc(1), cas->getSrc(2));
919 cas->setSrc(1, dreg);
920 }
921
922 return true;
923 }
924
925 inline Value *
926 NVC0LoweringPass::loadResInfo32(Value *ptr, uint32_t off)
927 {
928 uint8_t b = prog->driver->io.resInfoCBSlot;
929 off += prog->driver->io.suInfoBase;
930 return bld.
931 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
932 }
933
934 inline Value *
935 NVC0LoweringPass::loadMsInfo32(Value *ptr, uint32_t off)
936 {
937 uint8_t b = prog->driver->io.msInfoCBSlot;
938 off += prog->driver->io.msInfoBase;
939 return bld.
940 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
941 }
942
943 /* On nvc0, surface info is obtained via the surface binding points passed
944 * to the SULD/SUST instructions.
945 * On nve4, surface info is stored in c[] and is used by various special
946 * instructions, e.g. for clamping coordiantes or generating an address.
947 * They couldn't just have added an equivalent to TIC now, couldn't they ?
948 */
949 #define NVE4_SU_INFO_ADDR 0x00
950 #define NVE4_SU_INFO_FMT 0x04
951 #define NVE4_SU_INFO_DIM_X 0x08
952 #define NVE4_SU_INFO_PITCH 0x0c
953 #define NVE4_SU_INFO_DIM_Y 0x10
954 #define NVE4_SU_INFO_ARRAY 0x14
955 #define NVE4_SU_INFO_DIM_Z 0x18
956 #define NVE4_SU_INFO_UNK1C 0x1c
957 #define NVE4_SU_INFO_WIDTH 0x20
958 #define NVE4_SU_INFO_HEIGHT 0x24
959 #define NVE4_SU_INFO_DEPTH 0x28
960 #define NVE4_SU_INFO_TARGET 0x2c
961 #define NVE4_SU_INFO_CALL 0x30
962 #define NVE4_SU_INFO_RAW_X 0x34
963 #define NVE4_SU_INFO_MS_X 0x38
964 #define NVE4_SU_INFO_MS_Y 0x3c
965
966 #define NVE4_SU_INFO__STRIDE 0x40
967
968 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
969 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
970 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
971
972 static inline uint16_t getSuClampSubOp(const TexInstruction *su, int c)
973 {
974 switch (su->tex.target.getEnum()) {
975 case TEX_TARGET_BUFFER: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
976 case TEX_TARGET_RECT: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
977 case TEX_TARGET_1D: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
978 case TEX_TARGET_1D_ARRAY: return (c == 1) ?
979 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
980 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
981 case TEX_TARGET_2D: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
982 case TEX_TARGET_2D_MS: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
983 case TEX_TARGET_2D_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
984 case TEX_TARGET_2D_MS_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
985 case TEX_TARGET_3D: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
986 case TEX_TARGET_CUBE: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
987 case TEX_TARGET_CUBE_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
988 default:
989 assert(0);
990 return 0;
991 }
992 }
993
994 void
995 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction *tex)
996 {
997 const uint16_t base = tex->tex.r * NVE4_SU_INFO__STRIDE;
998 const int arg = tex->tex.target.getArgCount();
999
1000 if (tex->tex.target == TEX_TARGET_2D_MS)
1001 tex->tex.target = TEX_TARGET_2D;
1002 else
1003 if (tex->tex.target == TEX_TARGET_2D_MS_ARRAY)
1004 tex->tex.target = TEX_TARGET_2D_ARRAY;
1005 else
1006 return;
1007
1008 Value *x = tex->getSrc(0);
1009 Value *y = tex->getSrc(1);
1010 Value *s = tex->getSrc(arg - 1);
1011
1012 Value *tx = bld.getSSA(), *ty = bld.getSSA(), *ts = bld.getSSA();
1013
1014 Value *ms_x = loadResInfo32(NULL, base + NVE4_SU_INFO_MS(0));
1015 Value *ms_y = loadResInfo32(NULL, base + NVE4_SU_INFO_MS(1));
1016
1017 bld.mkOp2(OP_SHL, TYPE_U32, tx, x, ms_x);
1018 bld.mkOp2(OP_SHL, TYPE_U32, ty, y, ms_y);
1019
1020 s = bld.mkOp2v(OP_AND, TYPE_U32, ts, s, bld.loadImm(NULL, 0x7));
1021 s = bld.mkOp2v(OP_SHL, TYPE_U32, ts, ts, bld.mkImm(3));
1022
1023 Value *dx = loadMsInfo32(ts, 0x0);
1024 Value *dy = loadMsInfo32(ts, 0x4);
1025
1026 bld.mkOp2(OP_ADD, TYPE_U32, tx, tx, dx);
1027 bld.mkOp2(OP_ADD, TYPE_U32, ty, ty, dy);
1028
1029 tex->setSrc(0, tx);
1030 tex->setSrc(1, ty);
1031 tex->moveSources(arg, -1);
1032 }
1033
1034 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1035 // They're computed from the coordinates using the surface info in c[] space.
1036 void
1037 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
1038 {
1039 Instruction *insn;
1040 const bool atom = su->op == OP_SUREDB || su->op == OP_SUREDP;
1041 const bool raw =
1042 su->op == OP_SULDB || su->op == OP_SUSTB || su->op == OP_SUREDB;
1043 const int idx = su->tex.r;
1044 const int dim = su->tex.target.getDim();
1045 const int arg = dim + (su->tex.target.isArray() ? 1 : 0);
1046 const uint16_t base = idx * NVE4_SU_INFO__STRIDE;
1047 int c;
1048 Value *zero = bld.mkImm(0);
1049 Value *p1 = NULL;
1050 Value *v;
1051 Value *src[3];
1052 Value *bf, *eau, *off;
1053 Value *addr, *pred;
1054
1055 off = bld.getScratch(4);
1056 bf = bld.getScratch(4);
1057 addr = bld.getSSA(8);
1058 pred = bld.getScratch(1, FILE_PREDICATE);
1059
1060 bld.setPosition(su, false);
1061
1062 adjustCoordinatesMS(su);
1063
1064 // calculate clamped coordinates
1065 for (c = 0; c < arg; ++c) {
1066 src[c] = bld.getScratch();
1067 if (c == 0 && raw)
1068 v = loadResInfo32(NULL, base + NVE4_SU_INFO_RAW_X);
1069 else
1070 v = loadResInfo32(NULL, base + NVE4_SU_INFO_DIM(c));
1071 bld.mkOp3(OP_SUCLAMP, TYPE_S32, src[c], su->getSrc(c), v, zero)
1072 ->subOp = getSuClampSubOp(su, c);
1073 }
1074 for (; c < 3; ++c)
1075 src[c] = zero;
1076
1077 // set predicate output
1078 if (su->tex.target == TEX_TARGET_BUFFER) {
1079 src[0]->getInsn()->setFlagsDef(1, pred);
1080 } else
1081 if (su->tex.target.isArray()) {
1082 p1 = bld.getSSA(1, FILE_PREDICATE);
1083 src[dim]->getInsn()->setFlagsDef(1, p1);
1084 }
1085
1086 // calculate pixel offset
1087 if (dim == 1) {
1088 if (su->tex.target != TEX_TARGET_BUFFER)
1089 bld.mkOp2(OP_AND, TYPE_U32, off, src[0], bld.loadImm(NULL, 0xffff));
1090 } else
1091 if (dim == 3) {
1092 v = loadResInfo32(NULL, base + NVE4_SU_INFO_UNK1C);
1093 bld.mkOp3(OP_MADSP, TYPE_U32, off, src[2], v, src[1])
1094 ->subOp = NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1095
1096 v = loadResInfo32(NULL, base + NVE4_SU_INFO_PITCH);
1097 bld.mkOp3(OP_MADSP, TYPE_U32, off, off, v, src[0])
1098 ->subOp = NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1099 } else {
1100 assert(dim == 2);
1101 v = loadResInfo32(NULL, base + NVE4_SU_INFO_PITCH);
1102 bld.mkOp3(OP_MADSP, TYPE_U32, off, src[1], v, src[0])
1103 ->subOp = su->tex.target.isArray() ?
1104 NV50_IR_SUBOP_MADSP_SD : NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1105 }
1106
1107 // calculate effective address part 1
1108 if (su->tex.target == TEX_TARGET_BUFFER) {
1109 if (raw) {
1110 bf = src[0];
1111 } else {
1112 v = loadResInfo32(NULL, base + NVE4_SU_INFO_FMT);
1113 bld.mkOp3(OP_VSHL, TYPE_U32, bf, src[0], v, zero)
1114 ->subOp = NV50_IR_SUBOP_V1(7,6,8|2);
1115 }
1116 } else {
1117 Value *y = src[1];
1118 Value *z = src[2];
1119 uint16_t subOp = 0;
1120
1121 switch (dim) {
1122 case 1:
1123 y = zero;
1124 z = zero;
1125 break;
1126 case 2:
1127 z = off;
1128 if (!su->tex.target.isArray()) {
1129 z = loadResInfo32(NULL, base + NVE4_SU_INFO_UNK1C);
1130 subOp = NV50_IR_SUBOP_SUBFM_3D;
1131 }
1132 break;
1133 default:
1134 subOp = NV50_IR_SUBOP_SUBFM_3D;
1135 assert(dim == 3);
1136 break;
1137 }
1138 insn = bld.mkOp3(OP_SUBFM, TYPE_U32, bf, src[0], y, z);
1139 insn->subOp = subOp;
1140 insn->setFlagsDef(1, pred);
1141 }
1142
1143 // part 2
1144 v = loadResInfo32(NULL, base + NVE4_SU_INFO_ADDR);
1145
1146 if (su->tex.target == TEX_TARGET_BUFFER) {
1147 eau = v;
1148 } else {
1149 eau = bld.mkOp3v(OP_SUEAU, TYPE_U32, bld.getScratch(4), off, bf, v);
1150 }
1151 // add array layer offset
1152 if (su->tex.target.isArray()) {
1153 v = loadResInfo32(NULL, base + NVE4_SU_INFO_ARRAY);
1154 if (dim == 1)
1155 bld.mkOp3(OP_MADSP, TYPE_U32, eau, src[1], v, eau)
1156 ->subOp = NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1157 else
1158 bld.mkOp3(OP_MADSP, TYPE_U32, eau, v, src[2], eau)
1159 ->subOp = NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1160 // combine predicates
1161 assert(p1);
1162 bld.mkOp2(OP_OR, TYPE_U8, pred, pred, p1);
1163 }
1164
1165 if (atom) {
1166 Value *lo = bf;
1167 if (su->tex.target == TEX_TARGET_BUFFER) {
1168 lo = zero;
1169 bld.mkMov(off, bf);
1170 }
1171 // bf == g[] address & 0xff
1172 // eau == g[] address >> 8
1173 bld.mkOp3(OP_PERMT, TYPE_U32, bf, lo, bld.loadImm(NULL, 0x6540), eau);
1174 bld.mkOp3(OP_PERMT, TYPE_U32, eau, zero, bld.loadImm(NULL, 0x0007), eau);
1175 } else
1176 if (su->op == OP_SULDP && su->tex.target == TEX_TARGET_BUFFER) {
1177 // Convert from u32 to u8 address format, which is what the library code
1178 // doing SULDP currently uses.
1179 // XXX: can SUEAU do this ?
1180 // XXX: does it matter that we don't mask high bytes in bf ?
1181 // Grrr.
1182 bld.mkOp2(OP_SHR, TYPE_U32, off, bf, bld.mkImm(8));
1183 bld.mkOp2(OP_ADD, TYPE_U32, eau, eau, off);
1184 }
1185
1186 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau);
1187
1188 if (atom && su->tex.target == TEX_TARGET_BUFFER)
1189 bld.mkOp2(OP_ADD, TYPE_U64, addr, addr, off);
1190
1191 // let's just set it 0 for raw access and hope it works
1192 v = raw ?
1193 bld.mkImm(0) : loadResInfo32(NULL, base + NVE4_SU_INFO_FMT);
1194
1195 // get rid of old coordinate sources, make space for fmt info and predicate
1196 su->moveSources(arg, 3 - arg);
1197 // set 64 bit address and 32-bit format sources
1198 su->setSrc(0, addr);
1199 su->setSrc(1, v);
1200 su->setSrc(2, pred);
1201 }
1202
1203 void
1204 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction *su)
1205 {
1206 processSurfaceCoordsNVE4(su);
1207
1208 // Who do we hate more ? The person who decided that nvc0's SULD doesn't
1209 // have to support conversion or the person who decided that, in OpenCL,
1210 // you don't have to specify the format here like you do in OpenGL ?
1211
1212 if (su->op == OP_SULDP) {
1213 // We don't patch shaders. Ever.
1214 // You get an indirect call to our library blob here.
1215 // But at least it's uniform.
1216 FlowInstruction *call;
1217 LValue *p[3];
1218 LValue *r[5];
1219 uint16_t base = su->tex.r * NVE4_SU_INFO__STRIDE + NVE4_SU_INFO_CALL;
1220
1221 for (int i = 0; i < 4; ++i)
1222 (r[i] = bld.getScratch(4, FILE_GPR))->reg.data.id = i;
1223 for (int i = 0; i < 3; ++i)
1224 (p[i] = bld.getScratch(1, FILE_PREDICATE))->reg.data.id = i;
1225 (r[4] = bld.getScratch(8, FILE_GPR))->reg.data.id = 4;
1226
1227 bld.mkMov(p[1], bld.mkImm((su->cache == CACHE_CA) ? 1 : 0), TYPE_U8);
1228 bld.mkMov(p[2], bld.mkImm((su->cache == CACHE_CG) ? 1 : 0), TYPE_U8);
1229 bld.mkMov(p[0], su->getSrc(2), TYPE_U8);
1230 bld.mkMov(r[4], su->getSrc(0), TYPE_U64);
1231 bld.mkMov(r[2], su->getSrc(1), TYPE_U32);
1232
1233 call = bld.mkFlow(OP_CALL, NULL, su->cc, su->getPredicate());
1234
1235 call->indirect = 1;
1236 call->absolute = 1;
1237 call->setSrc(0, bld.mkSymbol(FILE_MEMORY_CONST,
1238 prog->driver->io.resInfoCBSlot, TYPE_U32,
1239 prog->driver->io.suInfoBase + base));
1240 call->setSrc(1, r[2]);
1241 call->setSrc(2, r[4]);
1242 for (int i = 0; i < 3; ++i)
1243 call->setSrc(3 + i, p[i]);
1244 for (int i = 0; i < 4; ++i) {
1245 call->setDef(i, r[i]);
1246 bld.mkMov(su->getDef(i), r[i]);
1247 }
1248 call->setDef(4, p[1]);
1249 delete_Instruction(bld.getProgram(), su);
1250 }
1251
1252 if (su->op == OP_SUREDB || su->op == OP_SUREDP) {
1253 // FIXME: for out of bounds access, destination value will be undefined !
1254 Value *pred = su->getSrc(2);
1255 CondCode cc = CC_NOT_P;
1256 if (su->getPredicate()) {
1257 pred = bld.getScratch(1, FILE_PREDICATE);
1258 cc = su->cc;
1259 if (cc == CC_NOT_P) {
1260 bld.mkOp2(OP_OR, TYPE_U8, pred, su->getPredicate(), su->getSrc(2));
1261 } else {
1262 bld.mkOp2(OP_AND, TYPE_U8, pred, su->getPredicate(), su->getSrc(2));
1263 pred->getInsn()->src(1).mod = Modifier(NV50_IR_MOD_NOT);
1264 }
1265 }
1266 Instruction *red = bld.mkOp(OP_ATOM, su->dType, su->getDef(0));
1267 red->subOp = su->subOp;
1268 if (!gMemBase)
1269 gMemBase = bld.mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, 0);
1270 red->setSrc(0, gMemBase);
1271 red->setSrc(1, su->getSrc(3));
1272 if (su->subOp == NV50_IR_SUBOP_ATOM_CAS)
1273 red->setSrc(2, su->getSrc(4));
1274 red->setIndirect(0, 0, su->getSrc(0));
1275 red->setPredicate(cc, pred);
1276 delete_Instruction(bld.getProgram(), su);
1277 handleCasExch(red, true);
1278 } else {
1279 su->sType = (su->tex.target == TEX_TARGET_BUFFER) ? TYPE_U32 : TYPE_U8;
1280 }
1281 }
1282
1283 bool
1284 NVC0LoweringPass::handleWRSV(Instruction *i)
1285 {
1286 Instruction *st;
1287 Symbol *sym;
1288 uint32_t addr;
1289
1290 // must replace, $sreg are not writeable
1291 addr = targ->getSVAddress(FILE_SHADER_OUTPUT, i->getSrc(0)->asSym());
1292 if (addr >= 0x400)
1293 return false;
1294 sym = bld.mkSymbol(FILE_SHADER_OUTPUT, 0, i->sType, addr);
1295
1296 st = bld.mkStore(OP_EXPORT, i->dType, sym, i->getIndirect(0, 0),
1297 i->getSrc(1));
1298 st->perPatch = i->perPatch;
1299
1300 bld.getBB()->remove(i);
1301 return true;
1302 }
1303
1304 void
1305 NVC0LoweringPass::readTessCoord(LValue *dst, int c)
1306 {
1307 Value *laneid = bld.getSSA();
1308 Value *x, *y;
1309
1310 bld.mkOp1(OP_RDSV, TYPE_U32, laneid, bld.mkSysVal(SV_LANEID, 0));
1311
1312 if (c == 0) {
1313 x = dst;
1314 y = NULL;
1315 } else
1316 if (c == 1) {
1317 x = NULL;
1318 y = dst;
1319 } else {
1320 assert(c == 2);
1321 x = bld.getSSA();
1322 y = bld.getSSA();
1323 }
1324 if (x)
1325 bld.mkFetch(x, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f0, NULL, laneid);
1326 if (y)
1327 bld.mkFetch(y, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f4, NULL, laneid);
1328
1329 if (c == 2) {
1330 bld.mkOp2(OP_ADD, TYPE_F32, dst, x, y);
1331 bld.mkOp2(OP_SUB, TYPE_F32, dst, bld.loadImm(NULL, 1.0f), dst);
1332 }
1333 }
1334
1335 bool
1336 NVC0LoweringPass::handleRDSV(Instruction *i)
1337 {
1338 Symbol *sym = i->getSrc(0)->asSym();
1339 const SVSemantic sv = sym->reg.data.sv.sv;
1340 Value *vtx = NULL;
1341 Instruction *ld;
1342 uint32_t addr = targ->getSVAddress(FILE_SHADER_INPUT, sym);
1343
1344 if (addr >= 0x400) {
1345 // mov $sreg
1346 if (sym->reg.data.sv.index == 3) {
1347 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
1348 i->op = OP_MOV;
1349 i->setSrc(0, bld.mkImm((sv == SV_NTID || sv == SV_NCTAID) ? 1 : 0));
1350 }
1351 return true;
1352 }
1353
1354 switch (sv) {
1355 case SV_POSITION:
1356 assert(prog->getType() == Program::TYPE_FRAGMENT);
1357 if (i->srcExists(1)) {
1358 // Pass offset through to the interpolation logic
1359 ld = bld.mkInterp(NV50_IR_INTERP_LINEAR | NV50_IR_INTERP_OFFSET,
1360 i->getDef(0), addr, NULL);
1361 ld->setSrc(1, i->getSrc(1));
1362 } else {
1363 bld.mkInterp(NV50_IR_INTERP_LINEAR, i->getDef(0), addr, NULL);
1364 }
1365 break;
1366 case SV_FACE:
1367 {
1368 Value *face = i->getDef(0);
1369 bld.mkInterp(NV50_IR_INTERP_FLAT, face, addr, NULL);
1370 if (i->dType == TYPE_F32) {
1371 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
1372 bld.mkOp2(OP_XOR, TYPE_U32, face, face, bld.mkImm(0xbf800000));
1373 }
1374 }
1375 break;
1376 case SV_TESS_COORD:
1377 assert(prog->getType() == Program::TYPE_TESSELLATION_EVAL);
1378 readTessCoord(i->getDef(0)->asLValue(), i->getSrc(0)->reg.data.sv.index);
1379 break;
1380 case SV_NTID:
1381 case SV_NCTAID:
1382 case SV_GRIDID:
1383 assert(targ->getChipset() >= NVISA_GK104_CHIPSET); // mov $sreg otherwise
1384 if (sym->reg.data.sv.index == 3) {
1385 i->op = OP_MOV;
1386 i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
1387 return true;
1388 }
1389 addr += prog->driver->prop.cp.gridInfoBase;
1390 bld.mkLoad(TYPE_U32, i->getDef(0),
1391 bld.mkSymbol(FILE_MEMORY_CONST, 0, TYPE_U32, addr), NULL);
1392 break;
1393 case SV_SAMPLE_INDEX:
1394 // TODO: Properly pass source as an address in the PIX address space
1395 // (which can be of the form [r0+offset]). But this is currently
1396 // unnecessary.
1397 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1398 ld->subOp = NV50_IR_SUBOP_PIXLD_SAMPLEID;
1399 break;
1400 case SV_SAMPLE_POS: {
1401 Value *off = new_LValue(func, FILE_GPR);
1402 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1403 ld->subOp = NV50_IR_SUBOP_PIXLD_SAMPLEID;
1404 bld.mkOp2(OP_SHL, TYPE_U32, off, i->getDef(0), bld.mkImm(3));
1405 bld.mkLoad(TYPE_F32,
1406 i->getDef(0),
1407 bld.mkSymbol(
1408 FILE_MEMORY_CONST, prog->driver->io.resInfoCBSlot,
1409 TYPE_U32, prog->driver->io.sampleInfoBase +
1410 4 * sym->reg.data.sv.index),
1411 off);
1412 break;
1413 }
1414 case SV_SAMPLE_MASK:
1415 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1416 ld->subOp = NV50_IR_SUBOP_PIXLD_COVMASK;
1417 break;
1418 default:
1419 if (prog->getType() == Program::TYPE_TESSELLATION_EVAL)
1420 vtx = bld.mkOp1v(OP_PFETCH, TYPE_U32, bld.getSSA(), bld.mkImm(0));
1421 ld = bld.mkFetch(i->getDef(0), i->dType,
1422 FILE_SHADER_INPUT, addr, i->getIndirect(0, 0), vtx);
1423 ld->perPatch = i->perPatch;
1424 break;
1425 }
1426 bld.getBB()->remove(i);
1427 return true;
1428 }
1429
1430 bool
1431 NVC0LoweringPass::handleDIV(Instruction *i)
1432 {
1433 if (!isFloatType(i->dType))
1434 return true;
1435 bld.setPosition(i, false);
1436 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
1437 i->op = OP_MUL;
1438 i->setSrc(1, rcp->getDef(0));
1439 return true;
1440 }
1441
1442 bool
1443 NVC0LoweringPass::handleMOD(Instruction *i)
1444 {
1445 if (i->dType != TYPE_F32)
1446 return true;
1447 LValue *value = bld.getScratch();
1448 bld.mkOp1(OP_RCP, TYPE_F32, value, i->getSrc(1));
1449 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(0), value);
1450 bld.mkOp1(OP_TRUNC, TYPE_F32, value, value);
1451 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(1), value);
1452 i->op = OP_SUB;
1453 i->setSrc(1, value);
1454 return true;
1455 }
1456
1457 bool
1458 NVC0LoweringPass::handleSQRT(Instruction *i)
1459 {
1460 Instruction *rsq = bld.mkOp1(OP_RSQ, TYPE_F32,
1461 bld.getSSA(), i->getSrc(0));
1462 i->op = OP_MUL;
1463 i->setSrc(1, rsq->getDef(0));
1464
1465 return true;
1466 }
1467
1468 bool
1469 NVC0LoweringPass::handlePOW(Instruction *i)
1470 {
1471 LValue *val = bld.getScratch();
1472
1473 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
1474 bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
1475 bld.mkOp1(OP_PREEX2, TYPE_F32, val, val);
1476
1477 i->op = OP_EX2;
1478 i->setSrc(0, val);
1479 i->setSrc(1, NULL);
1480
1481 return true;
1482 }
1483
1484 bool
1485 NVC0LoweringPass::handleEXPORT(Instruction *i)
1486 {
1487 if (prog->getType() == Program::TYPE_FRAGMENT) {
1488 int id = i->getSrc(0)->reg.data.offset / 4;
1489
1490 if (i->src(0).isIndirect(0)) // TODO, ugly
1491 return false;
1492 i->op = OP_MOV;
1493 i->subOp = NV50_IR_SUBOP_MOV_FINAL;
1494 i->src(0).set(i->src(1));
1495 i->setSrc(1, NULL);
1496 i->setDef(0, new_LValue(func, FILE_GPR));
1497 i->getDef(0)->reg.data.id = id;
1498
1499 prog->maxGPR = MAX2(prog->maxGPR, id);
1500 } else
1501 if (prog->getType() == Program::TYPE_GEOMETRY) {
1502 i->setIndirect(0, 1, gpEmitAddress);
1503 }
1504 return true;
1505 }
1506
1507 bool
1508 NVC0LoweringPass::handleOUT(Instruction *i)
1509 {
1510 Instruction *prev = i->prev;
1511 ImmediateValue stream, prevStream;
1512
1513 // Only merge if the stream ids match. Also, note that the previous
1514 // instruction would have already been lowered, so we take arg1 from it.
1515 if (i->op == OP_RESTART && prev && prev->op == OP_EMIT &&
1516 i->src(0).getImmediate(stream) &&
1517 prev->src(1).getImmediate(prevStream) &&
1518 stream.reg.data.u32 == prevStream.reg.data.u32) {
1519 i->prev->subOp = NV50_IR_SUBOP_EMIT_RESTART;
1520 delete_Instruction(prog, i);
1521 } else {
1522 assert(gpEmitAddress);
1523 i->setDef(0, gpEmitAddress);
1524 i->setSrc(1, i->getSrc(0));
1525 i->setSrc(0, gpEmitAddress);
1526 }
1527 return true;
1528 }
1529
1530 // Generate a binary predicate if an instruction is predicated by
1531 // e.g. an f32 value.
1532 void
1533 NVC0LoweringPass::checkPredicate(Instruction *insn)
1534 {
1535 Value *pred = insn->getPredicate();
1536 Value *pdst;
1537
1538 if (!pred || pred->reg.file == FILE_PREDICATE)
1539 return;
1540 pdst = new_LValue(func, FILE_PREDICATE);
1541
1542 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
1543 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
1544
1545 bld.mkCmp(OP_SET, CC_NEU, insn->dType, pdst, insn->dType, bld.mkImm(0), pred);
1546
1547 insn->setPredicate(insn->cc, pdst);
1548 }
1549
1550 //
1551 // - add quadop dance for texturing
1552 // - put FP outputs in GPRs
1553 // - convert instruction sequences
1554 //
1555 bool
1556 NVC0LoweringPass::visit(Instruction *i)
1557 {
1558 bld.setPosition(i, false);
1559
1560 if (i->cc != CC_ALWAYS)
1561 checkPredicate(i);
1562
1563 switch (i->op) {
1564 case OP_TEX:
1565 case OP_TXB:
1566 case OP_TXL:
1567 case OP_TXF:
1568 case OP_TXG:
1569 return handleTEX(i->asTex());
1570 case OP_TXD:
1571 return handleTXD(i->asTex());
1572 case OP_TXLQ:
1573 return handleTXLQ(i->asTex());
1574 case OP_TXQ:
1575 return handleTXQ(i->asTex());
1576 case OP_EX2:
1577 bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
1578 i->setSrc(0, i->getDef(0));
1579 break;
1580 case OP_POW:
1581 return handlePOW(i);
1582 case OP_DIV:
1583 return handleDIV(i);
1584 case OP_MOD:
1585 return handleMOD(i);
1586 case OP_SQRT:
1587 return handleSQRT(i);
1588 case OP_EXPORT:
1589 return handleEXPORT(i);
1590 case OP_EMIT:
1591 case OP_RESTART:
1592 return handleOUT(i);
1593 case OP_RDSV:
1594 return handleRDSV(i);
1595 case OP_WRSV:
1596 return handleWRSV(i);
1597 case OP_LOAD:
1598 if (i->src(0).getFile() == FILE_SHADER_INPUT) {
1599 if (prog->getType() == Program::TYPE_COMPUTE) {
1600 i->getSrc(0)->reg.file = FILE_MEMORY_CONST;
1601 i->getSrc(0)->reg.fileIndex = 0;
1602 } else
1603 if (prog->getType() == Program::TYPE_GEOMETRY &&
1604 i->src(0).isIndirect(0)) {
1605 // XXX: this assumes vec4 units
1606 Value *ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
1607 i->getIndirect(0, 0), bld.mkImm(4));
1608 i->setIndirect(0, 0, ptr);
1609 } else {
1610 i->op = OP_VFETCH;
1611 assert(prog->getType() != Program::TYPE_FRAGMENT); // INTERP
1612 }
1613 } else if (i->src(0).getFile() == FILE_MEMORY_CONST) {
1614 if (i->src(0).isIndirect(1)) {
1615 Value *ptr;
1616 if (i->src(0).isIndirect(0))
1617 ptr = bld.mkOp3v(OP_INSBF, TYPE_U32, bld.getSSA(),
1618 i->getIndirect(0, 1), bld.mkImm(0x1010),
1619 i->getIndirect(0, 0));
1620 else
1621 ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
1622 i->getIndirect(0, 1), bld.mkImm(16));
1623 i->setIndirect(0, 1, NULL);
1624 i->setIndirect(0, 0, ptr);
1625 i->subOp = NV50_IR_SUBOP_LDC_IS;
1626 }
1627 }
1628 break;
1629 case OP_ATOM:
1630 {
1631 const bool cctl = i->src(0).getFile() == FILE_MEMORY_GLOBAL;
1632 handleATOM(i);
1633 handleCasExch(i, cctl);
1634 }
1635 break;
1636 case OP_SULDB:
1637 case OP_SULDP:
1638 case OP_SUSTB:
1639 case OP_SUSTP:
1640 case OP_SUREDB:
1641 case OP_SUREDP:
1642 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1643 handleSurfaceOpNVE4(i->asTex());
1644 break;
1645 default:
1646 break;
1647 }
1648 return true;
1649 }
1650
1651 bool
1652 TargetNVC0::runLegalizePass(Program *prog, CGStage stage) const
1653 {
1654 if (stage == CG_STAGE_PRE_SSA) {
1655 NVC0LoweringPass pass(prog);
1656 return pass.run(prog, false, true);
1657 } else
1658 if (stage == CG_STAGE_POST_RA) {
1659 NVC0LegalizePostRA pass(prog);
1660 return pass.run(prog, false, true);
1661 } else
1662 if (stage == CG_STAGE_SSA) {
1663 NVC0LegalizeSSA pass;
1664 return pass.run(prog, false, true);
1665 }
1666 return false;
1667 }
1668
1669 } // namespace nv50_ir