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nvc0: move nvc0 lowering pass class definitions into header
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_lowering_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
25
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
28
29 #include <limits>
30
31 namespace nv50_ir {
32
33 #define QOP_ADD 0
34 #define QOP_SUBR 1
35 #define QOP_SUB 2
36 #define QOP_MOV2 3
37
38 // UL UR LL LR
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
42
43 void
44 NVC0LegalizeSSA::handleDIV(Instruction *i)
45 {
46 FlowInstruction *call;
47 int builtin;
48 Value *def[2];
49
50 bld.setPosition(i, false);
51 def[0] = bld.mkMovToReg(0, i->getSrc(0))->getDef(0);
52 def[1] = bld.mkMovToReg(1, i->getSrc(1))->getDef(0);
53 switch (i->dType) {
54 case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break;
55 case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break;
56 default:
57 return;
58 }
59 call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
60 bld.mkMov(i->getDef(0), def[(i->op == OP_DIV) ? 0 : 1]);
61 bld.mkClobber(FILE_GPR, (i->op == OP_DIV) ? 0xe : 0xd, 2);
62 bld.mkClobber(FILE_PREDICATE, (i->dType == TYPE_S32) ? 0xf : 0x3, 0);
63
64 call->fixed = 1;
65 call->absolute = call->builtin = 1;
66 call->target.builtin = builtin;
67 delete_Instruction(prog, i);
68 }
69
70 void
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
72 {
73 // TODO
74 }
75
76 bool
77 NVC0LegalizeSSA::visit(Function *fn)
78 {
79 bld.setProgram(fn->getProgram());
80 return true;
81 }
82
83 bool
84 NVC0LegalizeSSA::visit(BasicBlock *bb)
85 {
86 Instruction *next;
87 for (Instruction *i = bb->getEntry(); i; i = next) {
88 next = i->next;
89 if (i->dType == TYPE_F32)
90 continue;
91 switch (i->op) {
92 case OP_DIV:
93 case OP_MOD:
94 handleDIV(i);
95 break;
96 case OP_RCP:
97 case OP_RSQ:
98 if (i->dType == TYPE_F64)
99 handleRCPRSQ(i);
100 break;
101 default:
102 break;
103 }
104 }
105 return true;
106 }
107
108 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program *prog)
109 : rZero(NULL),
110 carry(NULL),
111 needTexBar(prog->getTarget()->getChipset() >= 0xe0)
112 {
113 }
114
115 bool
116 NVC0LegalizePostRA::insnDominatedBy(const Instruction *later,
117 const Instruction *early) const
118 {
119 if (early->bb == later->bb)
120 return early->serial < later->serial;
121 return later->bb->dominatedBy(early->bb);
122 }
123
124 void
125 NVC0LegalizePostRA::addTexUse(std::list<TexUse> &uses,
126 Instruction *usei, const Instruction *insn)
127 {
128 bool add = true;
129 for (std::list<TexUse>::iterator it = uses.begin();
130 it != uses.end();) {
131 if (insnDominatedBy(usei, it->insn)) {
132 add = false;
133 break;
134 }
135 if (insnDominatedBy(it->insn, usei))
136 it = uses.erase(it);
137 else
138 ++it;
139 }
140 if (add)
141 uses.push_back(TexUse(usei, insn));
142 }
143
144 void
145 NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
146 Instruction *insn,
147 const BasicBlock *term,
148 std::list<TexUse> &uses)
149 {
150 while (insn->op == OP_MOV && insn->getDef(0)->equals(insn->getSrc(0)))
151 insn = insn->getSrc(0)->getUniqueInsn();
152
153 if (!insn || !insn->bb->reachableBy(texi->bb, term))
154 return;
155
156 switch (insn->op) {
157 /* Values not connected to the tex's definition through any of these should
158 * not be conflicting.
159 */
160 case OP_SPLIT:
161 case OP_MERGE:
162 case OP_PHI:
163 case OP_UNION:
164 /* recurse again */
165 for (int s = 0; insn->srcExists(s); ++s)
166 findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsn(), term,
167 uses);
168 break;
169 default:
170 // if (!isTextureOp(insn->op)) // TODO: are TEXes always ordered ?
171 addTexUse(uses, insn, texi);
172 break;
173 }
174 }
175
176 void
177 NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
178 const Instruction *insn,
179 std::list<TexUse> &uses)
180 {
181 for (int d = 0; insn->defExists(d); ++d) {
182 Value *v = insn->getDef(d);
183 for (Value::UseIterator u = v->uses.begin(); u != v->uses.end(); ++u) {
184 Instruction *usei = (*u)->getInsn();
185
186 if (usei->op == OP_PHI || usei->op == OP_UNION) {
187 // need a barrier before WAW cases
188 for (int s = 0; usei->srcExists(s); ++s) {
189 Instruction *defi = usei->getSrc(s)->getUniqueInsn();
190 if (defi && &usei->src(s) != *u)
191 findOverwritingDefs(texi, defi, usei->bb, uses);
192 }
193 }
194
195 if (usei->op == OP_SPLIT ||
196 usei->op == OP_MERGE ||
197 usei->op == OP_PHI ||
198 usei->op == OP_UNION) {
199 // these uses don't manifest in the machine code
200 findFirstUses(texi, usei, uses);
201 } else
202 if (usei->op == OP_MOV && usei->getDef(0)->equals(usei->getSrc(0)) &&
203 usei->subOp != NV50_IR_SUBOP_MOV_FINAL) {
204 findFirstUses(texi, usei, uses);
205 } else {
206 addTexUse(uses, usei, insn);
207 }
208 }
209 }
210 }
211
212 // Texture barriers:
213 // This pass is a bit long and ugly and can probably be optimized.
214 //
215 // 1. obtain a list of TEXes and their outputs' first use(s)
216 // 2. calculate the barrier level of each first use (minimal number of TEXes,
217 // over all paths, between the TEX and the use in question)
218 // 3. for each barrier, if all paths from the source TEX to that barrier
219 // contain a barrier of lesser level, it can be culled
220 bool
221 NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
222 {
223 std::list<TexUse> *uses;
224 std::vector<Instruction *> texes;
225 std::vector<int> bbFirstTex;
226 std::vector<int> bbFirstUse;
227 std::vector<int> texCounts;
228 std::vector<TexUse> useVec;
229 ArrayList insns;
230
231 fn->orderInstructions(insns);
232
233 texCounts.resize(fn->allBBlocks.getSize(), 0);
234 bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
235 bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
236
237 // tag BB CFG nodes by their id for later
238 for (ArrayList::Iterator i = fn->allBBlocks.iterator(); !i.end(); i.next()) {
239 BasicBlock *bb = reinterpret_cast<BasicBlock *>(i.get());
240 if (bb)
241 bb->cfg.tag = bb->getId();
242 }
243
244 // gather the first uses for each TEX
245 for (int i = 0; i < insns.getSize(); ++i) {
246 Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
247 if (isTextureOp(tex->op)) {
248 texes.push_back(tex);
249 if (!texCounts.at(tex->bb->getId()))
250 bbFirstTex[tex->bb->getId()] = texes.size() - 1;
251 texCounts[tex->bb->getId()]++;
252 }
253 }
254 insns.clear();
255 if (texes.empty())
256 return false;
257 uses = new std::list<TexUse>[texes.size()];
258 if (!uses)
259 return false;
260 for (size_t i = 0; i < texes.size(); ++i)
261 findFirstUses(texes[i], texes[i], uses[i]);
262
263 // determine the barrier level at each use
264 for (size_t i = 0; i < texes.size(); ++i) {
265 for (std::list<TexUse>::iterator u = uses[i].begin(); u != uses[i].end();
266 ++u) {
267 BasicBlock *tb = texes[i]->bb;
268 BasicBlock *ub = u->insn->bb;
269 if (tb == ub) {
270 u->level = 0;
271 for (size_t j = i + 1; j < texes.size() &&
272 texes[j]->bb == tb && texes[j]->serial < u->insn->serial;
273 ++j)
274 u->level++;
275 } else {
276 u->level = fn->cfg.findLightestPathWeight(&tb->cfg,
277 &ub->cfg, texCounts);
278 if (u->level < 0) {
279 WARN("Failed to find path TEX -> TEXBAR\n");
280 u->level = 0;
281 continue;
282 }
283 // this counted all TEXes in the origin block, correct that
284 u->level -= i - bbFirstTex.at(tb->getId()) + 1 /* this TEX */;
285 // and did not count the TEXes in the destination block, add those
286 for (size_t j = bbFirstTex.at(ub->getId()); j < texes.size() &&
287 texes[j]->bb == ub && texes[j]->serial < u->insn->serial;
288 ++j)
289 u->level++;
290 }
291 assert(u->level >= 0);
292 useVec.push_back(*u);
293 }
294 }
295 delete[] uses;
296 uses = NULL;
297
298 // insert the barriers
299 for (size_t i = 0; i < useVec.size(); ++i) {
300 Instruction *prev = useVec[i].insn->prev;
301 if (useVec[i].level < 0)
302 continue;
303 if (prev && prev->op == OP_TEXBAR) {
304 if (prev->subOp > useVec[i].level)
305 prev->subOp = useVec[i].level;
306 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0));
307 } else {
308 Instruction *bar = new_Instruction(func, OP_TEXBAR, TYPE_NONE);
309 bar->fixed = 1;
310 bar->subOp = useVec[i].level;
311 // make use explicit to ease latency calculation
312 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0));
313 useVec[i].insn->bb->insertBefore(useVec[i].insn, bar);
314 }
315 }
316
317 if (fn->getProgram()->optLevel < 3) {
318 if (uses)
319 delete[] uses;
320 return true;
321 }
322
323 std::vector<Limits> limitT, limitB, limitS; // entry, exit, single
324
325 limitT.resize(fn->allBBlocks.getSize(), Limits(0, 0));
326 limitB.resize(fn->allBBlocks.getSize(), Limits(0, 0));
327 limitS.resize(fn->allBBlocks.getSize());
328
329 // cull unneeded barriers (should do that earlier, but for simplicity)
330 IteratorRef bi = fn->cfg.iteratorCFG();
331 // first calculate min/max outstanding TEXes for each BB
332 for (bi->reset(); !bi->end(); bi->next()) {
333 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
334 BasicBlock *bb = BasicBlock::get(n);
335 int min = 0;
336 int max = std::numeric_limits<int>::max();
337 for (Instruction *i = bb->getFirst(); i; i = i->next) {
338 if (isTextureOp(i->op)) {
339 min++;
340 if (max < std::numeric_limits<int>::max())
341 max++;
342 } else
343 if (i->op == OP_TEXBAR) {
344 min = MIN2(min, i->subOp);
345 max = MIN2(max, i->subOp);
346 }
347 }
348 // limits when looking at an isolated block
349 limitS[bb->getId()].min = min;
350 limitS[bb->getId()].max = max;
351 }
352 // propagate the min/max values
353 for (unsigned int l = 0; l <= fn->loopNestingBound; ++l) {
354 for (bi->reset(); !bi->end(); bi->next()) {
355 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
356 BasicBlock *bb = BasicBlock::get(n);
357 const int bbId = bb->getId();
358 for (Graph::EdgeIterator ei = n->incident(); !ei.end(); ei.next()) {
359 BasicBlock *in = BasicBlock::get(ei.getNode());
360 const int inId = in->getId();
361 limitT[bbId].min = MAX2(limitT[bbId].min, limitB[inId].min);
362 limitT[bbId].max = MAX2(limitT[bbId].max, limitB[inId].max);
363 }
364 // I just hope this is correct ...
365 if (limitS[bbId].max == std::numeric_limits<int>::max()) {
366 // no barrier
367 limitB[bbId].min = limitT[bbId].min + limitS[bbId].min;
368 limitB[bbId].max = limitT[bbId].max + limitS[bbId].min;
369 } else {
370 // block contained a barrier
371 limitB[bbId].min = MIN2(limitS[bbId].max,
372 limitT[bbId].min + limitS[bbId].min);
373 limitB[bbId].max = MIN2(limitS[bbId].max,
374 limitT[bbId].max + limitS[bbId].min);
375 }
376 }
377 }
378 // finally delete unnecessary barriers
379 for (bi->reset(); !bi->end(); bi->next()) {
380 Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
381 BasicBlock *bb = BasicBlock::get(n);
382 Instruction *prev = NULL;
383 Instruction *next;
384 int max = limitT[bb->getId()].max;
385 for (Instruction *i = bb->getFirst(); i; i = next) {
386 next = i->next;
387 if (i->op == OP_TEXBAR) {
388 if (i->subOp >= max) {
389 delete_Instruction(prog, i);
390 i = NULL;
391 } else {
392 max = i->subOp;
393 if (prev && prev->op == OP_TEXBAR && prev->subOp >= max) {
394 delete_Instruction(prog, prev);
395 prev = NULL;
396 }
397 }
398 } else
399 if (isTextureOp(i->op)) {
400 max++;
401 }
402 if (i && !i->isNop())
403 prev = i;
404 }
405 }
406 if (uses)
407 delete[] uses;
408 return true;
409 }
410
411 bool
412 NVC0LegalizePostRA::visit(Function *fn)
413 {
414 if (needTexBar)
415 insertTextureBarriers(fn);
416
417 rZero = new_LValue(fn, FILE_GPR);
418 carry = new_LValue(fn, FILE_FLAGS);
419
420 rZero->reg.data.id = prog->getTarget()->getFileSize(FILE_GPR);
421 carry->reg.data.id = 0;
422
423 return true;
424 }
425
426 void
427 NVC0LegalizePostRA::replaceZero(Instruction *i)
428 {
429 for (int s = 0; i->srcExists(s); ++s) {
430 if (s == 2 && i->op == OP_SUCLAMP)
431 continue;
432 ImmediateValue *imm = i->getSrc(s)->asImm();
433 if (imm && imm->reg.data.u64 == 0)
434 i->setSrc(s, rZero);
435 }
436 }
437
438 // replace CONT with BRA for single unconditional continue
439 bool
440 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock *bb)
441 {
442 if (bb->cfg.incidentCount() != 2 || bb->getEntry()->op != OP_PRECONT)
443 return false;
444 Graph::EdgeIterator ei = bb->cfg.incident();
445 if (ei.getType() != Graph::Edge::BACK)
446 ei.next();
447 if (ei.getType() != Graph::Edge::BACK)
448 return false;
449 BasicBlock *contBB = BasicBlock::get(ei.getNode());
450
451 if (!contBB->getExit() || contBB->getExit()->op != OP_CONT ||
452 contBB->getExit()->getPredicate())
453 return false;
454 contBB->getExit()->op = OP_BRA;
455 bb->remove(bb->getEntry()); // delete PRECONT
456
457 ei.next();
458 assert(ei.end() || ei.getType() != Graph::Edge::BACK);
459 return true;
460 }
461
462 // replace branches to join blocks with join ops
463 void
464 NVC0LegalizePostRA::propagateJoin(BasicBlock *bb)
465 {
466 if (bb->getEntry()->op != OP_JOIN || bb->getEntry()->asFlow()->limit)
467 return;
468 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
469 BasicBlock *in = BasicBlock::get(ei.getNode());
470 Instruction *exit = in->getExit();
471 if (!exit) {
472 in->insertTail(new FlowInstruction(func, OP_JOIN, bb));
473 // there should always be a terminator instruction
474 WARN("inserted missing terminator in BB:%i\n", in->getId());
475 } else
476 if (exit->op == OP_BRA) {
477 exit->op = OP_JOIN;
478 exit->asFlow()->limit = 1; // must-not-propagate marker
479 }
480 }
481 bb->remove(bb->getEntry());
482 }
483
484 bool
485 NVC0LegalizePostRA::visit(BasicBlock *bb)
486 {
487 Instruction *i, *next;
488
489 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
490 for (i = bb->getFirst(); i; i = next) {
491 next = i->next;
492 if (i->op == OP_EMIT || i->op == OP_RESTART) {
493 if (!i->getDef(0)->refCount())
494 i->setDef(0, NULL);
495 if (i->src(0).getFile() == FILE_IMMEDIATE)
496 i->setSrc(0, rZero); // initial value must be 0
497 } else
498 if (i->isNop()) {
499 bb->remove(i);
500 } else {
501 // TODO: Move this to before register allocation for operations that
502 // need the $c register !
503 if (typeSizeof(i->dType) == 8) {
504 Instruction *hi;
505 hi = BuildUtil::split64BitOpPostRA(func, i, rZero, carry);
506 if (hi)
507 next = hi;
508 }
509
510 if (i->op != OP_MOV && i->op != OP_PFETCH)
511 replaceZero(i);
512 }
513 }
514 if (!bb->getEntry())
515 return true;
516
517 if (!tryReplaceContWithBra(bb))
518 propagateJoin(bb);
519
520 return true;
521 }
522
523 NVC0LoweringPass::NVC0LoweringPass(Program *prog) : targ(prog->getTarget())
524 {
525 bld.setProgram(prog);
526 gMemBase = NULL;
527 }
528
529 bool
530 NVC0LoweringPass::visit(Function *fn)
531 {
532 if (prog->getType() == Program::TYPE_GEOMETRY) {
533 assert(!strncmp(fn->getName(), "MAIN", 4));
534 // TODO: when we generate actual functions pass this value along somehow
535 bld.setPosition(BasicBlock::get(fn->cfg.getRoot()), false);
536 gpEmitAddress = bld.loadImm(NULL, 0)->asLValue();
537 if (fn->cfgExit) {
538 bld.setPosition(BasicBlock::get(fn->cfgExit)->getExit(), false);
539 bld.mkMovToReg(0, gpEmitAddress);
540 }
541 }
542 return true;
543 }
544
545 bool
546 NVC0LoweringPass::visit(BasicBlock *bb)
547 {
548 return true;
549 }
550
551 inline Value *
552 NVC0LoweringPass::loadTexHandle(Value *ptr, unsigned int slot)
553 {
554 uint8_t b = prog->driver->io.resInfoCBSlot;
555 uint32_t off = prog->driver->io.texBindBase + slot * 4;
556 return bld.
557 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
558 }
559
560 // move array source to first slot, convert to u16, add indirections
561 bool
562 NVC0LoweringPass::handleTEX(TexInstruction *i)
563 {
564 const int dim = i->tex.target.getDim() + i->tex.target.isCube();
565 const int arg = i->tex.target.getArgCount();
566 const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
567 const int chipset = prog->getTarget()->getChipset();
568
569 if (chipset >= NVISA_GK104_CHIPSET) {
570 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
571 WARN("indirect TEX not implemented\n");
572 }
573 if (i->tex.r == i->tex.s) {
574 i->tex.r += prog->driver->io.texBindBase / 4;
575 i->tex.s = 0; // only a single cX[] value possible here
576 } else {
577 Value *hnd = bld.getScratch();
578 Value *rHnd = loadTexHandle(NULL, i->tex.r);
579 Value *sHnd = loadTexHandle(NULL, i->tex.s);
580
581 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
582
583 i->tex.r = 0; // not used for indirect tex
584 i->tex.s = 0;
585 i->setIndirectR(hnd);
586 }
587 if (i->tex.target.isArray()) {
588 LValue *layer = new_LValue(func, FILE_GPR);
589 Value *src = i->getSrc(lyr);
590 const int sat = (i->op == OP_TXF) ? 1 : 0;
591 DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
592 bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat;
593 for (int s = dim; s >= 1; --s)
594 i->setSrc(s, i->getSrc(s - 1));
595 i->setSrc(0, layer);
596 }
597 } else
598 // (nvc0) generate and move the tsc/tic/array source to the front
599 if (i->tex.target.isArray() || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
600 LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
601
602 Value *arrayIndex = i->tex.target.isArray() ? i->getSrc(lyr) : NULL;
603 for (int s = dim; s >= 1; --s)
604 i->setSrc(s, i->getSrc(s - 1));
605 i->setSrc(0, arrayIndex);
606
607 Value *ticRel = i->getIndirectR();
608 Value *tscRel = i->getIndirectS();
609
610 if (arrayIndex) {
611 int sat = (i->op == OP_TXF) ? 1 : 0;
612 DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
613 bld.mkCvt(OP_CVT, TYPE_U16, src, sTy, arrayIndex)->saturate = sat;
614 } else {
615 bld.loadImm(src, 0);
616 }
617
618 if (ticRel) {
619 i->setSrc(i->tex.rIndirectSrc, NULL);
620 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
621 }
622 if (tscRel) {
623 i->setSrc(i->tex.sIndirectSrc, NULL);
624 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
625 }
626
627 i->setSrc(0, src);
628 }
629
630 // For nvc0, the sample id has to be in the second operand, as the offset
631 // does. Right now we don't know how to pass both in, and this case can't
632 // happen with OpenGL. On nve0, the sample id is part of the texture
633 // coordinate argument.
634 assert(chipset >= NVISA_GK104_CHIPSET ||
635 !i->tex.useOffsets || !i->tex.target.isMS());
636
637 // offset is between lod and dc
638 if (i->tex.useOffsets) {
639 int n, c;
640 int s = i->srcCount(0xff, true);
641 if (i->tex.target.isShadow())
642 s--;
643 if (i->srcExists(s)) // move potential predicate out of the way
644 i->moveSources(s, 1);
645 if (i->tex.useOffsets == 4 && i->srcExists(s + 1))
646 i->moveSources(s + 1, 1);
647 if (i->op == OP_TXG) {
648 // Either there is 1 offset, which goes into the 2 low bytes of the
649 // first source, or there are 4 offsets, which go into 2 sources (8
650 // values, 1 byte each).
651 Value *offs[2] = {NULL, NULL};
652 for (n = 0; n < i->tex.useOffsets; n++) {
653 for (c = 0; c < 2; ++c) {
654 if ((n % 2) == 0 && c == 0)
655 offs[n / 2] = i->offset[n][c].get();
656 else
657 bld.mkOp3(OP_INSBF, TYPE_U32,
658 offs[n / 2],
659 i->offset[n][c].get(),
660 bld.mkImm(0x800 | ((n * 16 + c * 8) % 32)),
661 offs[n / 2]);
662 }
663 }
664 i->setSrc(s, offs[0]);
665 if (offs[1])
666 i->setSrc(s + 1, offs[1]);
667 } else {
668 unsigned imm = 0;
669 assert(i->tex.useOffsets == 1);
670 for (c = 0; c < 3; ++c) {
671 ImmediateValue val;
672 assert(i->offset[0][c].getImmediate(val));
673 imm |= (val.reg.data.u32 & 0xf) << (c * 4);
674 }
675 i->setSrc(s, bld.loadImm(NULL, imm));
676 }
677 }
678
679 if (chipset >= NVISA_GK104_CHIPSET) {
680 //
681 // If TEX requires more than 4 sources, the 2nd register tuple must be
682 // aligned to 4, even if it consists of just a single 4-byte register.
683 //
684 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
685 //
686 int s = i->srcCount(0xff, true);
687 if (s > 4 && s < 7) {
688 if (i->srcExists(s)) // move potential predicate out of the way
689 i->moveSources(s, 7 - s);
690 while (s < 7)
691 i->setSrc(s++, bld.loadImm(NULL, 0));
692 }
693 }
694
695 return true;
696 }
697
698 bool
699 NVC0LoweringPass::handleManualTXD(TexInstruction *i)
700 {
701 static const uint8_t qOps[4][2] =
702 {
703 { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) }, // l0
704 { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(MOV2, MOV2, ADD, ADD) }, // l1
705 { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(SUBR, SUBR, MOV2, MOV2) }, // l2
706 { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(SUBR, SUBR, MOV2, MOV2) }, // l3
707 };
708 Value *def[4][4];
709 Value *crd[3];
710 Instruction *tex;
711 Value *zero = bld.loadImm(bld.getSSA(), 0);
712 int l, c;
713 const int dim = i->tex.target.getDim();
714
715 i->op = OP_TEX; // no need to clone dPdx/dPdy later
716
717 for (c = 0; c < dim; ++c)
718 crd[c] = bld.getScratch();
719
720 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
721 for (l = 0; l < 4; ++l) {
722 // mov coordinates from lane l to all lanes
723 for (c = 0; c < dim; ++c)
724 bld.mkQuadop(0x00, crd[c], l, i->getSrc(c), zero);
725 // add dPdx from lane l to lanes dx
726 for (c = 0; c < dim; ++c)
727 bld.mkQuadop(qOps[l][0], crd[c], l, i->dPdx[c].get(), crd[c]);
728 // add dPdy from lane l to lanes dy
729 for (c = 0; c < dim; ++c)
730 bld.mkQuadop(qOps[l][1], crd[c], l, i->dPdy[c].get(), crd[c]);
731 // texture
732 bld.insert(tex = cloneForward(func, i));
733 for (c = 0; c < dim; ++c)
734 tex->setSrc(c, crd[c]);
735 // save results
736 for (c = 0; i->defExists(c); ++c) {
737 Instruction *mov;
738 def[c][l] = bld.getSSA();
739 mov = bld.mkMov(def[c][l], tex->getDef(c));
740 mov->fixed = 1;
741 mov->lanes = 1 << l;
742 }
743 }
744 bld.mkOp(OP_QUADPOP, TYPE_NONE, NULL);
745
746 for (c = 0; i->defExists(c); ++c) {
747 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c));
748 for (l = 0; l < 4; ++l)
749 u->setSrc(l, def[c][l]);
750 }
751
752 i->bb->remove(i);
753 return true;
754 }
755
756 bool
757 NVC0LoweringPass::handleTXD(TexInstruction *txd)
758 {
759 int dim = txd->tex.target.getDim();
760 int arg = txd->tex.target.getArgCount();
761
762 handleTEX(txd);
763 while (txd->srcExists(arg))
764 ++arg;
765
766 txd->tex.derivAll = true;
767 if (dim > 2 ||
768 txd->tex.target.isCube() ||
769 arg > 4 ||
770 txd->tex.target.isShadow())
771 return handleManualTXD(txd);
772
773 for (int c = 0; c < dim; ++c) {
774 txd->setSrc(arg + c * 2 + 0, txd->dPdx[c]);
775 txd->setSrc(arg + c * 2 + 1, txd->dPdy[c]);
776 txd->dPdx[c].set(NULL);
777 txd->dPdy[c].set(NULL);
778 }
779 return true;
780 }
781
782 bool
783 NVC0LoweringPass::handleTXQ(TexInstruction *txq)
784 {
785 // TODO: indirect resource/sampler index
786 return true;
787 }
788
789 bool
790 NVC0LoweringPass::handleTXLQ(TexInstruction *i)
791 {
792 /* The outputs are inverted compared to what the TGSI instruction
793 * expects. Take that into account in the mask.
794 */
795 assert((i->tex.mask & ~3) == 0);
796 if (i->tex.mask == 1)
797 i->tex.mask = 2;
798 else if (i->tex.mask == 2)
799 i->tex.mask = 1;
800 handleTEX(i);
801 bld.setPosition(i, true);
802
803 /* The returned values are not quite what we want:
804 * (a) convert from s16/u16 to f32
805 * (b) multiply by 1/256
806 */
807 for (int def = 0; def < 2; ++def) {
808 if (!i->defExists(def))
809 continue;
810 enum DataType type = TYPE_S16;
811 if (i->tex.mask == 2 || def > 0)
812 type = TYPE_U16;
813 bld.mkCvt(OP_CVT, TYPE_F32, i->getDef(def), type, i->getDef(def));
814 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(def),
815 i->getDef(def), bld.loadImm(NULL, 1.0f / 256));
816 }
817 if (i->tex.mask == 3) {
818 LValue *t = new_LValue(func, FILE_GPR);
819 bld.mkMov(t, i->getDef(0));
820 bld.mkMov(i->getDef(0), i->getDef(1));
821 bld.mkMov(i->getDef(1), t);
822 }
823 return true;
824 }
825
826
827 bool
828 NVC0LoweringPass::handleATOM(Instruction *atom)
829 {
830 SVSemantic sv;
831
832 switch (atom->src(0).getFile()) {
833 case FILE_MEMORY_LOCAL:
834 sv = SV_LBASE;
835 break;
836 case FILE_MEMORY_SHARED:
837 sv = SV_SBASE;
838 break;
839 default:
840 assert(atom->src(0).getFile() == FILE_MEMORY_GLOBAL);
841 return true;
842 }
843 Value *base =
844 bld.mkOp1v(OP_RDSV, TYPE_U32, bld.getScratch(), bld.mkSysVal(sv, 0));
845 Value *ptr = atom->getIndirect(0, 0);
846
847 atom->setSrc(0, cloneShallow(func, atom->getSrc(0)));
848 atom->getSrc(0)->reg.file = FILE_MEMORY_GLOBAL;
849 if (ptr)
850 base = bld.mkOp2v(OP_ADD, TYPE_U32, base, base, ptr);
851 atom->setIndirect(0, 0, base);
852
853 return true;
854 }
855
856 bool
857 NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl)
858 {
859 if (cas->subOp != NV50_IR_SUBOP_ATOM_CAS &&
860 cas->subOp != NV50_IR_SUBOP_ATOM_EXCH)
861 return false;
862 bld.setPosition(cas, true);
863
864 if (needCctl) {
865 Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, cas->getSrc(0));
866 cctl->setIndirect(0, 0, cas->getIndirect(0, 0));
867 cctl->fixed = 1;
868 cctl->subOp = NV50_IR_SUBOP_CCTL_IV;
869 if (cas->isPredicated())
870 cctl->setPredicate(cas->cc, cas->getPredicate());
871 }
872
873 if (cas->defExists(0) && cas->subOp == NV50_IR_SUBOP_ATOM_CAS) {
874 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
875 // should be set to the high part of the double reg or bad things will
876 // happen elsewhere in the universe.
877 // Also, it sometimes returns the new value instead of the old one
878 // under mysterious circumstances.
879 Value *dreg = bld.getSSA(8);
880 bld.setPosition(cas, false);
881 bld.mkOp2(OP_MERGE, TYPE_U64, dreg, cas->getSrc(1), cas->getSrc(2));
882 cas->setSrc(1, dreg);
883 }
884
885 return true;
886 }
887
888 inline Value *
889 NVC0LoweringPass::loadResInfo32(Value *ptr, uint32_t off)
890 {
891 uint8_t b = prog->driver->io.resInfoCBSlot;
892 off += prog->driver->io.suInfoBase;
893 return bld.
894 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
895 }
896
897 inline Value *
898 NVC0LoweringPass::loadMsInfo32(Value *ptr, uint32_t off)
899 {
900 uint8_t b = prog->driver->io.msInfoCBSlot;
901 off += prog->driver->io.msInfoBase;
902 return bld.
903 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
904 }
905
906 /* On nvc0, surface info is obtained via the surface binding points passed
907 * to the SULD/SUST instructions.
908 * On nve4, surface info is stored in c[] and is used by various special
909 * instructions, e.g. for clamping coordiantes or generating an address.
910 * They couldn't just have added an equivalent to TIC now, couldn't they ?
911 */
912 #define NVE4_SU_INFO_ADDR 0x00
913 #define NVE4_SU_INFO_FMT 0x04
914 #define NVE4_SU_INFO_DIM_X 0x08
915 #define NVE4_SU_INFO_PITCH 0x0c
916 #define NVE4_SU_INFO_DIM_Y 0x10
917 #define NVE4_SU_INFO_ARRAY 0x14
918 #define NVE4_SU_INFO_DIM_Z 0x18
919 #define NVE4_SU_INFO_UNK1C 0x1c
920 #define NVE4_SU_INFO_WIDTH 0x20
921 #define NVE4_SU_INFO_HEIGHT 0x24
922 #define NVE4_SU_INFO_DEPTH 0x28
923 #define NVE4_SU_INFO_TARGET 0x2c
924 #define NVE4_SU_INFO_CALL 0x30
925 #define NVE4_SU_INFO_RAW_X 0x34
926 #define NVE4_SU_INFO_MS_X 0x38
927 #define NVE4_SU_INFO_MS_Y 0x3c
928
929 #define NVE4_SU_INFO__STRIDE 0x40
930
931 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
932 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
933 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
934
935 static inline uint16_t getSuClampSubOp(const TexInstruction *su, int c)
936 {
937 switch (su->tex.target.getEnum()) {
938 case TEX_TARGET_BUFFER: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
939 case TEX_TARGET_RECT: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
940 case TEX_TARGET_1D: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
941 case TEX_TARGET_1D_ARRAY: return (c == 1) ?
942 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
943 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
944 case TEX_TARGET_2D: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
945 case TEX_TARGET_2D_MS: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
946 case TEX_TARGET_2D_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
947 case TEX_TARGET_2D_MS_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
948 case TEX_TARGET_3D: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
949 case TEX_TARGET_CUBE: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
950 case TEX_TARGET_CUBE_ARRAY: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
951 default:
952 assert(0);
953 return 0;
954 }
955 }
956
957 void
958 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction *tex)
959 {
960 const uint16_t base = tex->tex.r * NVE4_SU_INFO__STRIDE;
961 const int arg = tex->tex.target.getArgCount();
962
963 if (tex->tex.target == TEX_TARGET_2D_MS)
964 tex->tex.target = TEX_TARGET_2D;
965 else
966 if (tex->tex.target == TEX_TARGET_2D_MS_ARRAY)
967 tex->tex.target = TEX_TARGET_2D_ARRAY;
968 else
969 return;
970
971 Value *x = tex->getSrc(0);
972 Value *y = tex->getSrc(1);
973 Value *s = tex->getSrc(arg - 1);
974
975 Value *tx = bld.getSSA(), *ty = bld.getSSA(), *ts = bld.getSSA();
976
977 Value *ms_x = loadResInfo32(NULL, base + NVE4_SU_INFO_MS(0));
978 Value *ms_y = loadResInfo32(NULL, base + NVE4_SU_INFO_MS(1));
979
980 bld.mkOp2(OP_SHL, TYPE_U32, tx, x, ms_x);
981 bld.mkOp2(OP_SHL, TYPE_U32, ty, y, ms_y);
982
983 s = bld.mkOp2v(OP_AND, TYPE_U32, ts, s, bld.loadImm(NULL, 0x7));
984 s = bld.mkOp2v(OP_SHL, TYPE_U32, ts, ts, bld.mkImm(3));
985
986 Value *dx = loadMsInfo32(ts, 0x0);
987 Value *dy = loadMsInfo32(ts, 0x4);
988
989 bld.mkOp2(OP_ADD, TYPE_U32, tx, tx, dx);
990 bld.mkOp2(OP_ADD, TYPE_U32, ty, ty, dy);
991
992 tex->setSrc(0, tx);
993 tex->setSrc(1, ty);
994 tex->moveSources(arg, -1);
995 }
996
997 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
998 // They're computed from the coordinates using the surface info in c[] space.
999 void
1000 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
1001 {
1002 Instruction *insn;
1003 const bool atom = su->op == OP_SUREDB || su->op == OP_SUREDP;
1004 const bool raw =
1005 su->op == OP_SULDB || su->op == OP_SUSTB || su->op == OP_SUREDB;
1006 const int idx = su->tex.r;
1007 const int dim = su->tex.target.getDim();
1008 const int arg = dim + (su->tex.target.isArray() ? 1 : 0);
1009 const uint16_t base = idx * NVE4_SU_INFO__STRIDE;
1010 int c;
1011 Value *zero = bld.mkImm(0);
1012 Value *p1 = NULL;
1013 Value *v;
1014 Value *src[3];
1015 Value *bf, *eau, *off;
1016 Value *addr, *pred;
1017
1018 off = bld.getScratch(4);
1019 bf = bld.getScratch(4);
1020 addr = bld.getSSA(8);
1021 pred = bld.getScratch(1, FILE_PREDICATE);
1022
1023 bld.setPosition(su, false);
1024
1025 adjustCoordinatesMS(su);
1026
1027 // calculate clamped coordinates
1028 for (c = 0; c < arg; ++c) {
1029 src[c] = bld.getScratch();
1030 if (c == 0 && raw)
1031 v = loadResInfo32(NULL, base + NVE4_SU_INFO_RAW_X);
1032 else
1033 v = loadResInfo32(NULL, base + NVE4_SU_INFO_DIM(c));
1034 bld.mkOp3(OP_SUCLAMP, TYPE_S32, src[c], su->getSrc(c), v, zero)
1035 ->subOp = getSuClampSubOp(su, c);
1036 }
1037 for (; c < 3; ++c)
1038 src[c] = zero;
1039
1040 // set predicate output
1041 if (su->tex.target == TEX_TARGET_BUFFER) {
1042 src[0]->getInsn()->setFlagsDef(1, pred);
1043 } else
1044 if (su->tex.target.isArray()) {
1045 p1 = bld.getSSA(1, FILE_PREDICATE);
1046 src[dim]->getInsn()->setFlagsDef(1, p1);
1047 }
1048
1049 // calculate pixel offset
1050 if (dim == 1) {
1051 if (su->tex.target != TEX_TARGET_BUFFER)
1052 bld.mkOp2(OP_AND, TYPE_U32, off, src[0], bld.loadImm(NULL, 0xffff));
1053 } else
1054 if (dim == 3) {
1055 v = loadResInfo32(NULL, base + NVE4_SU_INFO_UNK1C);
1056 bld.mkOp3(OP_MADSP, TYPE_U32, off, src[2], v, src[1])
1057 ->subOp = NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1058
1059 v = loadResInfo32(NULL, base + NVE4_SU_INFO_PITCH);
1060 bld.mkOp3(OP_MADSP, TYPE_U32, off, off, v, src[0])
1061 ->subOp = NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1062 } else {
1063 assert(dim == 2);
1064 v = loadResInfo32(NULL, base + NVE4_SU_INFO_PITCH);
1065 bld.mkOp3(OP_MADSP, TYPE_U32, off, src[1], v, src[0])
1066 ->subOp = su->tex.target.isArray() ?
1067 NV50_IR_SUBOP_MADSP_SD : NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1068 }
1069
1070 // calculate effective address part 1
1071 if (su->tex.target == TEX_TARGET_BUFFER) {
1072 if (raw) {
1073 bf = src[0];
1074 } else {
1075 v = loadResInfo32(NULL, base + NVE4_SU_INFO_FMT);
1076 bld.mkOp3(OP_VSHL, TYPE_U32, bf, src[0], v, zero)
1077 ->subOp = NV50_IR_SUBOP_V1(7,6,8|2);
1078 }
1079 } else {
1080 Value *y = src[1];
1081 Value *z = src[2];
1082 uint16_t subOp = 0;
1083
1084 switch (dim) {
1085 case 1:
1086 y = zero;
1087 z = zero;
1088 break;
1089 case 2:
1090 z = off;
1091 if (!su->tex.target.isArray()) {
1092 z = loadResInfo32(NULL, base + NVE4_SU_INFO_UNK1C);
1093 subOp = NV50_IR_SUBOP_SUBFM_3D;
1094 }
1095 break;
1096 default:
1097 subOp = NV50_IR_SUBOP_SUBFM_3D;
1098 assert(dim == 3);
1099 break;
1100 }
1101 insn = bld.mkOp3(OP_SUBFM, TYPE_U32, bf, src[0], y, z);
1102 insn->subOp = subOp;
1103 insn->setFlagsDef(1, pred);
1104 }
1105
1106 // part 2
1107 v = loadResInfo32(NULL, base + NVE4_SU_INFO_ADDR);
1108
1109 if (su->tex.target == TEX_TARGET_BUFFER) {
1110 eau = v;
1111 } else {
1112 eau = bld.mkOp3v(OP_SUEAU, TYPE_U32, bld.getScratch(4), off, bf, v);
1113 }
1114 // add array layer offset
1115 if (su->tex.target.isArray()) {
1116 v = loadResInfo32(NULL, base + NVE4_SU_INFO_ARRAY);
1117 if (dim == 1)
1118 bld.mkOp3(OP_MADSP, TYPE_U32, eau, src[1], v, eau)
1119 ->subOp = NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1120 else
1121 bld.mkOp3(OP_MADSP, TYPE_U32, eau, v, src[2], eau)
1122 ->subOp = NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1123 // combine predicates
1124 assert(p1);
1125 bld.mkOp2(OP_OR, TYPE_U8, pred, pred, p1);
1126 }
1127
1128 if (atom) {
1129 Value *lo = bf;
1130 if (su->tex.target == TEX_TARGET_BUFFER) {
1131 lo = zero;
1132 bld.mkMov(off, bf);
1133 }
1134 // bf == g[] address & 0xff
1135 // eau == g[] address >> 8
1136 bld.mkOp3(OP_PERMT, TYPE_U32, bf, lo, bld.loadImm(NULL, 0x6540), eau);
1137 bld.mkOp3(OP_PERMT, TYPE_U32, eau, zero, bld.loadImm(NULL, 0x0007), eau);
1138 } else
1139 if (su->op == OP_SULDP && su->tex.target == TEX_TARGET_BUFFER) {
1140 // Convert from u32 to u8 address format, which is what the library code
1141 // doing SULDP currently uses.
1142 // XXX: can SUEAU do this ?
1143 // XXX: does it matter that we don't mask high bytes in bf ?
1144 // Grrr.
1145 bld.mkOp2(OP_SHR, TYPE_U32, off, bf, bld.mkImm(8));
1146 bld.mkOp2(OP_ADD, TYPE_U32, eau, eau, off);
1147 }
1148
1149 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau);
1150
1151 if (atom && su->tex.target == TEX_TARGET_BUFFER)
1152 bld.mkOp2(OP_ADD, TYPE_U64, addr, addr, off);
1153
1154 // let's just set it 0 for raw access and hope it works
1155 v = raw ?
1156 bld.mkImm(0) : loadResInfo32(NULL, base + NVE4_SU_INFO_FMT);
1157
1158 // get rid of old coordinate sources, make space for fmt info and predicate
1159 su->moveSources(arg, 3 - arg);
1160 // set 64 bit address and 32-bit format sources
1161 su->setSrc(0, addr);
1162 su->setSrc(1, v);
1163 su->setSrc(2, pred);
1164 }
1165
1166 void
1167 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction *su)
1168 {
1169 processSurfaceCoordsNVE4(su);
1170
1171 // Who do we hate more ? The person who decided that nvc0's SULD doesn't
1172 // have to support conversion or the person who decided that, in OpenCL,
1173 // you don't have to specify the format here like you do in OpenGL ?
1174
1175 if (su->op == OP_SULDP) {
1176 // We don't patch shaders. Ever.
1177 // You get an indirect call to our library blob here.
1178 // But at least it's uniform.
1179 FlowInstruction *call;
1180 LValue *p[3];
1181 LValue *r[5];
1182 uint16_t base = su->tex.r * NVE4_SU_INFO__STRIDE + NVE4_SU_INFO_CALL;
1183
1184 for (int i = 0; i < 4; ++i)
1185 (r[i] = bld.getScratch(4, FILE_GPR))->reg.data.id = i;
1186 for (int i = 0; i < 3; ++i)
1187 (p[i] = bld.getScratch(1, FILE_PREDICATE))->reg.data.id = i;
1188 (r[4] = bld.getScratch(8, FILE_GPR))->reg.data.id = 4;
1189
1190 bld.mkMov(p[1], bld.mkImm((su->cache == CACHE_CA) ? 1 : 0), TYPE_U8);
1191 bld.mkMov(p[2], bld.mkImm((su->cache == CACHE_CG) ? 1 : 0), TYPE_U8);
1192 bld.mkMov(p[0], su->getSrc(2), TYPE_U8);
1193 bld.mkMov(r[4], su->getSrc(0), TYPE_U64);
1194 bld.mkMov(r[2], su->getSrc(1), TYPE_U32);
1195
1196 call = bld.mkFlow(OP_CALL, NULL, su->cc, su->getPredicate());
1197
1198 call->indirect = 1;
1199 call->absolute = 1;
1200 call->setSrc(0, bld.mkSymbol(FILE_MEMORY_CONST,
1201 prog->driver->io.resInfoCBSlot, TYPE_U32,
1202 prog->driver->io.suInfoBase + base));
1203 call->setSrc(1, r[2]);
1204 call->setSrc(2, r[4]);
1205 for (int i = 0; i < 3; ++i)
1206 call->setSrc(3 + i, p[i]);
1207 for (int i = 0; i < 4; ++i) {
1208 call->setDef(i, r[i]);
1209 bld.mkMov(su->getDef(i), r[i]);
1210 }
1211 call->setDef(4, p[1]);
1212 delete_Instruction(bld.getProgram(), su);
1213 }
1214
1215 if (su->op == OP_SUREDB || su->op == OP_SUREDP) {
1216 // FIXME: for out of bounds access, destination value will be undefined !
1217 Value *pred = su->getSrc(2);
1218 CondCode cc = CC_NOT_P;
1219 if (su->getPredicate()) {
1220 pred = bld.getScratch(1, FILE_PREDICATE);
1221 cc = su->cc;
1222 if (cc == CC_NOT_P) {
1223 bld.mkOp2(OP_OR, TYPE_U8, pred, su->getPredicate(), su->getSrc(2));
1224 } else {
1225 bld.mkOp2(OP_AND, TYPE_U8, pred, su->getPredicate(), su->getSrc(2));
1226 pred->getInsn()->src(1).mod = Modifier(NV50_IR_MOD_NOT);
1227 }
1228 }
1229 Instruction *red = bld.mkOp(OP_ATOM, su->dType, su->getDef(0));
1230 red->subOp = su->subOp;
1231 if (!gMemBase)
1232 gMemBase = bld.mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, 0);
1233 red->setSrc(0, gMemBase);
1234 red->setSrc(1, su->getSrc(3));
1235 if (su->subOp == NV50_IR_SUBOP_ATOM_CAS)
1236 red->setSrc(2, su->getSrc(4));
1237 red->setIndirect(0, 0, su->getSrc(0));
1238 red->setPredicate(cc, pred);
1239 delete_Instruction(bld.getProgram(), su);
1240 handleCasExch(red, true);
1241 } else {
1242 su->sType = (su->tex.target == TEX_TARGET_BUFFER) ? TYPE_U32 : TYPE_U8;
1243 }
1244 }
1245
1246 bool
1247 NVC0LoweringPass::handleWRSV(Instruction *i)
1248 {
1249 Instruction *st;
1250 Symbol *sym;
1251 uint32_t addr;
1252
1253 // must replace, $sreg are not writeable
1254 addr = targ->getSVAddress(FILE_SHADER_OUTPUT, i->getSrc(0)->asSym());
1255 if (addr >= 0x400)
1256 return false;
1257 sym = bld.mkSymbol(FILE_SHADER_OUTPUT, 0, i->sType, addr);
1258
1259 st = bld.mkStore(OP_EXPORT, i->dType, sym, i->getIndirect(0, 0),
1260 i->getSrc(1));
1261 st->perPatch = i->perPatch;
1262
1263 bld.getBB()->remove(i);
1264 return true;
1265 }
1266
1267 void
1268 NVC0LoweringPass::readTessCoord(LValue *dst, int c)
1269 {
1270 Value *laneid = bld.getSSA();
1271 Value *x, *y;
1272
1273 bld.mkOp1(OP_RDSV, TYPE_U32, laneid, bld.mkSysVal(SV_LANEID, 0));
1274
1275 if (c == 0) {
1276 x = dst;
1277 y = NULL;
1278 } else
1279 if (c == 1) {
1280 x = NULL;
1281 y = dst;
1282 } else {
1283 assert(c == 2);
1284 x = bld.getSSA();
1285 y = bld.getSSA();
1286 }
1287 if (x)
1288 bld.mkFetch(x, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f0, NULL, laneid);
1289 if (y)
1290 bld.mkFetch(y, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f4, NULL, laneid);
1291
1292 if (c == 2) {
1293 bld.mkOp2(OP_ADD, TYPE_F32, dst, x, y);
1294 bld.mkOp2(OP_SUB, TYPE_F32, dst, bld.loadImm(NULL, 1.0f), dst);
1295 }
1296 }
1297
1298 bool
1299 NVC0LoweringPass::handleRDSV(Instruction *i)
1300 {
1301 Symbol *sym = i->getSrc(0)->asSym();
1302 const SVSemantic sv = sym->reg.data.sv.sv;
1303 Value *vtx = NULL;
1304 Instruction *ld;
1305 uint32_t addr = targ->getSVAddress(FILE_SHADER_INPUT, sym);
1306
1307 if (addr >= 0x400) {
1308 // mov $sreg
1309 if (sym->reg.data.sv.index == 3) {
1310 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
1311 i->op = OP_MOV;
1312 i->setSrc(0, bld.mkImm((sv == SV_NTID || sv == SV_NCTAID) ? 1 : 0));
1313 }
1314 return true;
1315 }
1316
1317 switch (sv) {
1318 case SV_POSITION:
1319 assert(prog->getType() == Program::TYPE_FRAGMENT);
1320 bld.mkInterp(NV50_IR_INTERP_LINEAR, i->getDef(0), addr, NULL);
1321 break;
1322 case SV_FACE:
1323 {
1324 Value *face = i->getDef(0);
1325 bld.mkInterp(NV50_IR_INTERP_FLAT, face, addr, NULL);
1326 if (i->dType == TYPE_F32) {
1327 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
1328 bld.mkOp2(OP_XOR, TYPE_U32, face, face, bld.mkImm(0xbf800000));
1329 }
1330 }
1331 break;
1332 case SV_TESS_COORD:
1333 assert(prog->getType() == Program::TYPE_TESSELLATION_EVAL);
1334 readTessCoord(i->getDef(0)->asLValue(), i->getSrc(0)->reg.data.sv.index);
1335 break;
1336 case SV_NTID:
1337 case SV_NCTAID:
1338 case SV_GRIDID:
1339 assert(targ->getChipset() >= NVISA_GK104_CHIPSET); // mov $sreg otherwise
1340 if (sym->reg.data.sv.index == 3) {
1341 i->op = OP_MOV;
1342 i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
1343 return true;
1344 }
1345 addr += prog->driver->prop.cp.gridInfoBase;
1346 bld.mkLoad(TYPE_U32, i->getDef(0),
1347 bld.mkSymbol(FILE_MEMORY_CONST, 0, TYPE_U32, addr), NULL);
1348 break;
1349 case SV_SAMPLE_INDEX:
1350 // TODO: Properly pass source as an address in the PIX address space
1351 // (which can be of the form [r0+offset]). But this is currently
1352 // unnecessary.
1353 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1354 ld->subOp = NV50_IR_SUBOP_PIXLD_SAMPLEID;
1355 break;
1356 case SV_SAMPLE_POS: {
1357 Value *off = new_LValue(func, FILE_GPR);
1358 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1359 ld->subOp = NV50_IR_SUBOP_PIXLD_SAMPLEID;
1360 bld.mkOp2(OP_SHL, TYPE_U32, off, i->getDef(0), bld.mkImm(3));
1361 bld.mkLoad(TYPE_F32,
1362 i->getDef(0),
1363 bld.mkSymbol(
1364 FILE_MEMORY_CONST, prog->driver->io.resInfoCBSlot,
1365 TYPE_U32, prog->driver->io.sampleInfoBase +
1366 4 * sym->reg.data.sv.index),
1367 off);
1368 break;
1369 }
1370 case SV_SAMPLE_MASK:
1371 ld = bld.mkOp1(OP_PIXLD, TYPE_U32, i->getDef(0), bld.mkImm(0));
1372 ld->subOp = NV50_IR_SUBOP_PIXLD_COVMASK;
1373 break;
1374 default:
1375 if (prog->getType() == Program::TYPE_TESSELLATION_EVAL)
1376 vtx = bld.mkOp1v(OP_PFETCH, TYPE_U32, bld.getSSA(), bld.mkImm(0));
1377 ld = bld.mkFetch(i->getDef(0), i->dType,
1378 FILE_SHADER_INPUT, addr, i->getIndirect(0, 0), vtx);
1379 ld->perPatch = i->perPatch;
1380 break;
1381 }
1382 bld.getBB()->remove(i);
1383 return true;
1384 }
1385
1386 bool
1387 NVC0LoweringPass::handleDIV(Instruction *i)
1388 {
1389 if (!isFloatType(i->dType))
1390 return true;
1391 bld.setPosition(i, false);
1392 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
1393 i->op = OP_MUL;
1394 i->setSrc(1, rcp->getDef(0));
1395 return true;
1396 }
1397
1398 bool
1399 NVC0LoweringPass::handleMOD(Instruction *i)
1400 {
1401 if (i->dType != TYPE_F32)
1402 return true;
1403 LValue *value = bld.getScratch();
1404 bld.mkOp1(OP_RCP, TYPE_F32, value, i->getSrc(1));
1405 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(0), value);
1406 bld.mkOp1(OP_TRUNC, TYPE_F32, value, value);
1407 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(1), value);
1408 i->op = OP_SUB;
1409 i->setSrc(1, value);
1410 return true;
1411 }
1412
1413 bool
1414 NVC0LoweringPass::handleSQRT(Instruction *i)
1415 {
1416 Instruction *rsq = bld.mkOp1(OP_RSQ, TYPE_F32,
1417 bld.getSSA(), i->getSrc(0));
1418 i->op = OP_MUL;
1419 i->setSrc(1, rsq->getDef(0));
1420
1421 return true;
1422 }
1423
1424 bool
1425 NVC0LoweringPass::handlePOW(Instruction *i)
1426 {
1427 LValue *val = bld.getScratch();
1428
1429 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
1430 bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
1431 bld.mkOp1(OP_PREEX2, TYPE_F32, val, val);
1432
1433 i->op = OP_EX2;
1434 i->setSrc(0, val);
1435 i->setSrc(1, NULL);
1436
1437 return true;
1438 }
1439
1440 bool
1441 NVC0LoweringPass::handleEXPORT(Instruction *i)
1442 {
1443 if (prog->getType() == Program::TYPE_FRAGMENT) {
1444 int id = i->getSrc(0)->reg.data.offset / 4;
1445
1446 if (i->src(0).isIndirect(0)) // TODO, ugly
1447 return false;
1448 i->op = OP_MOV;
1449 i->subOp = NV50_IR_SUBOP_MOV_FINAL;
1450 i->src(0).set(i->src(1));
1451 i->setSrc(1, NULL);
1452 i->setDef(0, new_LValue(func, FILE_GPR));
1453 i->getDef(0)->reg.data.id = id;
1454
1455 prog->maxGPR = MAX2(prog->maxGPR, id);
1456 } else
1457 if (prog->getType() == Program::TYPE_GEOMETRY) {
1458 i->setIndirect(0, 1, gpEmitAddress);
1459 }
1460 return true;
1461 }
1462
1463 bool
1464 NVC0LoweringPass::handleOUT(Instruction *i)
1465 {
1466 if (i->op == OP_RESTART && i->prev && i->prev->op == OP_EMIT) {
1467 i->prev->subOp = NV50_IR_SUBOP_EMIT_RESTART;
1468 delete_Instruction(prog, i);
1469 } else {
1470 assert(gpEmitAddress);
1471 i->setDef(0, gpEmitAddress);
1472 if (i->srcExists(0))
1473 i->setSrc(1, i->getSrc(0));
1474 i->setSrc(0, gpEmitAddress);
1475 }
1476 return true;
1477 }
1478
1479 // Generate a binary predicate if an instruction is predicated by
1480 // e.g. an f32 value.
1481 void
1482 NVC0LoweringPass::checkPredicate(Instruction *insn)
1483 {
1484 Value *pred = insn->getPredicate();
1485 Value *pdst;
1486
1487 if (!pred || pred->reg.file == FILE_PREDICATE)
1488 return;
1489 pdst = new_LValue(func, FILE_PREDICATE);
1490
1491 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
1492 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
1493
1494 bld.mkCmp(OP_SET, CC_NEU, insn->dType, pdst, insn->dType, bld.mkImm(0), pred);
1495
1496 insn->setPredicate(insn->cc, pdst);
1497 }
1498
1499 //
1500 // - add quadop dance for texturing
1501 // - put FP outputs in GPRs
1502 // - convert instruction sequences
1503 //
1504 bool
1505 NVC0LoweringPass::visit(Instruction *i)
1506 {
1507 bld.setPosition(i, false);
1508
1509 if (i->cc != CC_ALWAYS)
1510 checkPredicate(i);
1511
1512 switch (i->op) {
1513 case OP_TEX:
1514 case OP_TXB:
1515 case OP_TXL:
1516 case OP_TXF:
1517 case OP_TXG:
1518 return handleTEX(i->asTex());
1519 case OP_TXD:
1520 return handleTXD(i->asTex());
1521 case OP_TXLQ:
1522 return handleTXLQ(i->asTex());
1523 case OP_TXQ:
1524 return handleTXQ(i->asTex());
1525 case OP_EX2:
1526 bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
1527 i->setSrc(0, i->getDef(0));
1528 break;
1529 case OP_POW:
1530 return handlePOW(i);
1531 case OP_DIV:
1532 return handleDIV(i);
1533 case OP_MOD:
1534 return handleMOD(i);
1535 case OP_SQRT:
1536 return handleSQRT(i);
1537 case OP_EXPORT:
1538 return handleEXPORT(i);
1539 case OP_EMIT:
1540 case OP_RESTART:
1541 return handleOUT(i);
1542 case OP_RDSV:
1543 return handleRDSV(i);
1544 case OP_WRSV:
1545 return handleWRSV(i);
1546 case OP_LOAD:
1547 if (i->src(0).getFile() == FILE_SHADER_INPUT) {
1548 if (prog->getType() == Program::TYPE_COMPUTE) {
1549 i->getSrc(0)->reg.file = FILE_MEMORY_CONST;
1550 i->getSrc(0)->reg.fileIndex = 0;
1551 } else
1552 if (prog->getType() == Program::TYPE_GEOMETRY &&
1553 i->src(0).isIndirect(0)) {
1554 // XXX: this assumes vec4 units
1555 Value *ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
1556 i->getIndirect(0, 0), bld.mkImm(4));
1557 i->setIndirect(0, 0, ptr);
1558 } else {
1559 i->op = OP_VFETCH;
1560 assert(prog->getType() != Program::TYPE_FRAGMENT); // INTERP
1561 }
1562 }
1563 break;
1564 case OP_ATOM:
1565 {
1566 const bool cctl = i->src(0).getFile() == FILE_MEMORY_GLOBAL;
1567 handleATOM(i);
1568 handleCasExch(i, cctl);
1569 }
1570 break;
1571 case OP_SULDB:
1572 case OP_SULDP:
1573 case OP_SUSTB:
1574 case OP_SUSTP:
1575 case OP_SUREDB:
1576 case OP_SUREDP:
1577 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1578 handleSurfaceOpNVE4(i->asTex());
1579 break;
1580 default:
1581 break;
1582 }
1583 return true;
1584 }
1585
1586 bool
1587 TargetNVC0::runLegalizePass(Program *prog, CGStage stage) const
1588 {
1589 if (stage == CG_STAGE_PRE_SSA) {
1590 NVC0LoweringPass pass(prog);
1591 return pass.run(prog, false, true);
1592 } else
1593 if (stage == CG_STAGE_POST_RA) {
1594 NVC0LegalizePostRA pass(prog);
1595 return pass.run(prog, false, true);
1596 } else
1597 if (stage == CG_STAGE_SSA) {
1598 NVC0LegalizeSSA pass;
1599 return pass.run(prog, false, true);
1600 }
1601 return false;
1602 }
1603
1604 } // namespace nv50_ir