2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
73 assert(i
->dType
== TYPE_F64
);
74 // There are instructions that will compute the high 32 bits of the 64-bit
75 // float. We will just stick 0 in the bottom 32 bits.
77 bld
.setPosition(i
, false);
79 // 1. Take the source and it up.
80 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
81 bld
.mkSplit(src
, 4, i
->getSrc(0));
83 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
84 dst
[0] = bld
.loadImm(NULL
, 0);
85 dst
[1] = bld
.getSSA();
87 // 3. The new version of the instruction takes the high 32 bits of the
88 // source and outputs the high 32 bits of the destination.
92 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
94 // 4. Recombine the two dst pieces back into the original destination.
95 bld
.setPosition(i
, true);
96 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
100 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
102 // Only want to flush float inputs
103 if (i
->sType
!= TYPE_F32
)
106 // If we're already flushing denorms (and NaN's) to zero, no need for this.
110 // Only certain classes of operations can flush
111 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
112 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
113 cls
!= OPCLASS_CONVERT
)
120 NVC0LegalizeSSA::visit(Function
*fn
)
122 bld
.setProgram(fn
->getProgram());
127 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
130 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
132 if (i
->dType
== TYPE_F32
) {
133 if (prog
->getType() != Program::TYPE_COMPUTE
)
144 if (i
->dType
== TYPE_F64
)
154 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
157 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
162 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
163 const Instruction
*early
) const
165 if (early
->bb
== later
->bb
)
166 return early
->serial
< later
->serial
;
167 return later
->bb
->dominatedBy(early
->bb
);
171 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
172 Instruction
*usei
, const Instruction
*insn
)
175 for (std::list
<TexUse
>::iterator it
= uses
.begin();
177 if (insnDominatedBy(usei
, it
->insn
)) {
181 if (insnDominatedBy(it
->insn
, usei
))
187 uses
.push_back(TexUse(usei
, insn
));
191 NVC0LegalizePostRA::findOverwritingDefs(const Instruction
*texi
,
193 const BasicBlock
*term
,
194 std::list
<TexUse
> &uses
)
196 while (insn
->op
== OP_MOV
&& insn
->getDef(0)->equals(insn
->getSrc(0)))
197 insn
= insn
->getSrc(0)->getUniqueInsn();
199 if (!insn
->bb
->reachableBy(texi
->bb
, term
))
203 /* Values not connected to the tex's definition through any of these should
204 * not be conflicting.
211 for (int s
= 0; insn
->srcExists(s
); ++s
)
212 findOverwritingDefs(texi
, insn
->getSrc(s
)->getUniqueInsn(), term
,
216 // if (!isTextureOp(insn->op)) // TODO: are TEXes always ordered ?
217 addTexUse(uses
, insn
, texi
);
223 NVC0LegalizePostRA::findFirstUses(
224 const Instruction
*texi
,
225 const Instruction
*insn
,
226 std::list
<TexUse
> &uses
,
227 std::tr1::unordered_set
<const Instruction
*>& visited
)
229 for (int d
= 0; insn
->defExists(d
); ++d
) {
230 Value
*v
= insn
->getDef(d
);
231 for (Value::UseIterator u
= v
->uses
.begin(); u
!= v
->uses
.end(); ++u
) {
232 Instruction
*usei
= (*u
)->getInsn();
234 // NOTE: In case of a loop that overwrites a value but never uses
235 // it, it can happen that we have a cycle of uses that consists only
236 // of phis and no-op moves and will thus cause an infinite loop here
237 // since these are not considered actual uses.
238 // The most obvious (and perhaps the only) way to prevent this is to
239 // remember which instructions we've already visited.
241 if (visited
.find(usei
) != visited
.end())
244 visited
.insert(usei
);
246 if (usei
->op
== OP_PHI
|| usei
->op
== OP_UNION
) {
247 // need a barrier before WAW cases
248 for (int s
= 0; usei
->srcExists(s
); ++s
) {
249 Instruction
*defi
= usei
->getSrc(s
)->getUniqueInsn();
250 if (defi
&& &usei
->src(s
) != *u
)
251 findOverwritingDefs(texi
, defi
, usei
->bb
, uses
);
255 if (usei
->op
== OP_SPLIT
||
256 usei
->op
== OP_MERGE
||
257 usei
->op
== OP_PHI
||
258 usei
->op
== OP_UNION
) {
259 // these uses don't manifest in the machine code
260 findFirstUses(texi
, usei
, uses
, visited
);
262 if (usei
->op
== OP_MOV
&& usei
->getDef(0)->equals(usei
->getSrc(0)) &&
263 usei
->subOp
!= NV50_IR_SUBOP_MOV_FINAL
) {
264 findFirstUses(texi
, usei
, uses
, visited
);
266 addTexUse(uses
, usei
, insn
);
273 // This pass is a bit long and ugly and can probably be optimized.
275 // 1. obtain a list of TEXes and their outputs' first use(s)
276 // 2. calculate the barrier level of each first use (minimal number of TEXes,
277 // over all paths, between the TEX and the use in question)
278 // 3. for each barrier, if all paths from the source TEX to that barrier
279 // contain a barrier of lesser level, it can be culled
281 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
283 std::list
<TexUse
> *uses
;
284 std::vector
<Instruction
*> texes
;
285 std::vector
<int> bbFirstTex
;
286 std::vector
<int> bbFirstUse
;
287 std::vector
<int> texCounts
;
288 std::vector
<TexUse
> useVec
;
291 fn
->orderInstructions(insns
);
293 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
294 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
295 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
297 // tag BB CFG nodes by their id for later
298 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
299 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
301 bb
->cfg
.tag
= bb
->getId();
304 // gather the first uses for each TEX
305 for (int i
= 0; i
< insns
.getSize(); ++i
) {
306 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
307 if (isTextureOp(tex
->op
)) {
308 texes
.push_back(tex
);
309 if (!texCounts
.at(tex
->bb
->getId()))
310 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
311 texCounts
[tex
->bb
->getId()]++;
317 uses
= new std::list
<TexUse
>[texes
.size()];
320 for (size_t i
= 0; i
< texes
.size(); ++i
) {
321 std::tr1::unordered_set
<const Instruction
*> visited
;
322 findFirstUses(texes
[i
], texes
[i
], uses
[i
], visited
);
325 // determine the barrier level at each use
326 for (size_t i
= 0; i
< texes
.size(); ++i
) {
327 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
329 BasicBlock
*tb
= texes
[i
]->bb
;
330 BasicBlock
*ub
= u
->insn
->bb
;
333 for (size_t j
= i
+ 1; j
< texes
.size() &&
334 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
338 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
339 &ub
->cfg
, texCounts
);
341 WARN("Failed to find path TEX -> TEXBAR\n");
345 // this counted all TEXes in the origin block, correct that
346 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
347 // and did not count the TEXes in the destination block, add those
348 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
349 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
353 assert(u
->level
>= 0);
354 useVec
.push_back(*u
);
359 // insert the barriers
360 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
361 Instruction
*prev
= useVec
[i
].insn
->prev
;
362 if (useVec
[i
].level
< 0)
364 if (prev
&& prev
->op
== OP_TEXBAR
) {
365 if (prev
->subOp
> useVec
[i
].level
)
366 prev
->subOp
= useVec
[i
].level
;
367 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
369 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
371 bar
->subOp
= useVec
[i
].level
;
372 // make use explicit to ease latency calculation
373 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
374 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
378 if (fn
->getProgram()->optLevel
< 3)
381 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
383 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
384 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
385 limitS
.resize(fn
->allBBlocks
.getSize());
387 // cull unneeded barriers (should do that earlier, but for simplicity)
388 IteratorRef bi
= fn
->cfg
.iteratorCFG();
389 // first calculate min/max outstanding TEXes for each BB
390 for (bi
->reset(); !bi
->end(); bi
->next()) {
391 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
392 BasicBlock
*bb
= BasicBlock::get(n
);
394 int max
= std::numeric_limits
<int>::max();
395 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
396 if (isTextureOp(i
->op
)) {
398 if (max
< std::numeric_limits
<int>::max())
401 if (i
->op
== OP_TEXBAR
) {
402 min
= MIN2(min
, i
->subOp
);
403 max
= MIN2(max
, i
->subOp
);
406 // limits when looking at an isolated block
407 limitS
[bb
->getId()].min
= min
;
408 limitS
[bb
->getId()].max
= max
;
410 // propagate the min/max values
411 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
412 for (bi
->reset(); !bi
->end(); bi
->next()) {
413 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
414 BasicBlock
*bb
= BasicBlock::get(n
);
415 const int bbId
= bb
->getId();
416 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
417 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
418 const int inId
= in
->getId();
419 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
420 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
422 // I just hope this is correct ...
423 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
425 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
426 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
428 // block contained a barrier
429 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
430 limitT
[bbId
].min
+ limitS
[bbId
].min
);
431 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
432 limitT
[bbId
].max
+ limitS
[bbId
].min
);
436 // finally delete unnecessary barriers
437 for (bi
->reset(); !bi
->end(); bi
->next()) {
438 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
439 BasicBlock
*bb
= BasicBlock::get(n
);
440 Instruction
*prev
= NULL
;
442 int max
= limitT
[bb
->getId()].max
;
443 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
445 if (i
->op
== OP_TEXBAR
) {
446 if (i
->subOp
>= max
) {
447 delete_Instruction(prog
, i
);
451 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
452 delete_Instruction(prog
, prev
);
457 if (isTextureOp(i
->op
)) {
460 if (i
&& !i
->isNop())
468 NVC0LegalizePostRA::visit(Function
*fn
)
471 insertTextureBarriers(fn
);
473 rZero
= new_LValue(fn
, FILE_GPR
);
474 carry
= new_LValue(fn
, FILE_FLAGS
);
476 rZero
->reg
.data
.id
= prog
->getTarget()->getFileSize(FILE_GPR
);
477 carry
->reg
.data
.id
= 0;
483 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
485 for (int s
= 0; i
->srcExists(s
); ++s
) {
486 if (s
== 2 && i
->op
== OP_SUCLAMP
)
488 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
489 if (imm
&& imm
->reg
.data
.u64
== 0)
494 // replace CONT with BRA for single unconditional continue
496 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
498 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
500 Graph::EdgeIterator ei
= bb
->cfg
.incident();
501 if (ei
.getType() != Graph::Edge::BACK
)
503 if (ei
.getType() != Graph::Edge::BACK
)
505 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
507 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
508 contBB
->getExit()->getPredicate())
510 contBB
->getExit()->op
= OP_BRA
;
511 bb
->remove(bb
->getEntry()); // delete PRECONT
514 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
518 // replace branches to join blocks with join ops
520 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
522 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
524 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
525 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
526 Instruction
*exit
= in
->getExit();
528 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
529 // there should always be a terminator instruction
530 WARN("inserted missing terminator in BB:%i\n", in
->getId());
532 if (exit
->op
== OP_BRA
) {
534 exit
->asFlow()->limit
= 1; // must-not-propagate marker
537 bb
->remove(bb
->getEntry());
541 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
543 Instruction
*i
, *next
;
545 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
546 for (i
= bb
->getFirst(); i
; i
= next
) {
548 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
549 if (!i
->getDef(0)->refCount())
551 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
552 i
->setSrc(0, rZero
); // initial value must be 0
558 // TODO: Move this to before register allocation for operations that
559 // need the $c register !
560 if (typeSizeof(i
->dType
) == 8) {
562 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
567 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
574 if (!tryReplaceContWithBra(bb
))
580 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
582 bld
.setProgram(prog
);
587 NVC0LoweringPass::visit(Function
*fn
)
589 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
590 assert(!strncmp(fn
->getName(), "MAIN", 4));
591 // TODO: when we generate actual functions pass this value along somehow
592 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
593 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
595 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
596 bld
.mkMovToReg(0, gpEmitAddress
);
603 NVC0LoweringPass::visit(BasicBlock
*bb
)
609 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
611 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
612 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
614 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
617 // move array source to first slot, convert to u16, add indirections
619 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
621 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
622 const int arg
= i
->tex
.target
.getArgCount();
623 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
624 const int chipset
= prog
->getTarget()->getChipset();
626 // Arguments to the TEX instruction are a little insane. Even though the
627 // encoding is identical between SM20 and SM30, the arguments mean
628 // different things between Fermi and Kepler+. A lot of arguments are
629 // optional based on flags passed to the instruction. This summarizes the
639 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
640 // - other: 4 bits each, single reg
644 // array (+ offsets for txd in upper 16 bits)
649 // offsets (same as fermi, except txd which takes it with array)
666 if (chipset
>= NVISA_GK104_CHIPSET
) {
667 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
668 // XXX this ignores tsc, and assumes a 1:1 mapping
669 assert(i
->tex
.rIndirectSrc
>= 0);
670 Value
*hnd
= loadTexHandle(
671 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
672 i
->getIndirectR(), bld
.mkImm(2)),
676 i
->setIndirectR(hnd
);
677 i
->setIndirectS(NULL
);
678 } else if (i
->tex
.r
== i
->tex
.s
) {
679 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
680 i
->tex
.s
= 0; // only a single cX[] value possible here
682 Value
*hnd
= bld
.getScratch();
683 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
684 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
686 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
688 i
->tex
.r
= 0; // not used for indirect tex
690 i
->setIndirectR(hnd
);
692 if (i
->tex
.target
.isArray()) {
693 LValue
*layer
= new_LValue(func
, FILE_GPR
);
694 Value
*src
= i
->getSrc(lyr
);
695 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
696 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
697 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
698 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
699 for (int s
= dim
; s
>= 1; --s
)
700 i
->setSrc(s
, i
->getSrc(s
- 1));
703 i
->setSrc(dim
, layer
);
706 // Move the indirect reference to the first place
707 if (i
->tex
.rIndirectSrc
>= 0 && (
708 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
709 Value
*hnd
= i
->getIndirectR();
711 i
->setIndirectR(NULL
);
712 i
->moveSources(0, 1);
714 i
->tex
.rIndirectSrc
= 0;
715 i
->tex
.sIndirectSrc
= -1;
718 // (nvc0) generate and move the tsc/tic/array source to the front
719 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
720 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
722 Value
*ticRel
= i
->getIndirectR();
723 Value
*tscRel
= i
->getIndirectS();
726 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
728 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
729 ticRel
, bld
.mkImm(i
->tex
.r
));
732 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
734 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
735 tscRel
, bld
.mkImm(i
->tex
.s
));
738 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
739 for (int s
= dim
; s
>= 1; --s
)
740 i
->setSrc(s
, i
->getSrc(s
- 1));
741 i
->setSrc(0, arrayIndex
);
744 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
745 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
746 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
752 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
754 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
759 // For nvc0, the sample id has to be in the second operand, as the offset
760 // does. Right now we don't know how to pass both in, and this case can't
761 // happen with OpenGL. On nve0, the sample id is part of the texture
762 // coordinate argument.
763 assert(chipset
>= NVISA_GK104_CHIPSET
||
764 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
766 // offset is between lod and dc
767 if (i
->tex
.useOffsets
) {
769 int s
= i
->srcCount(0xff, true);
770 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
771 if (i
->tex
.target
.isShadow())
773 if (i
->srcExists(s
)) // move potential predicate out of the way
774 i
->moveSources(s
, 1);
775 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
776 i
->moveSources(s
+ 1, 1);
778 if (i
->op
== OP_TXG
) {
779 // Either there is 1 offset, which goes into the 2 low bytes of the
780 // first source, or there are 4 offsets, which go into 2 sources (8
781 // values, 1 byte each).
782 Value
*offs
[2] = {NULL
, NULL
};
783 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
784 for (c
= 0; c
< 2; ++c
) {
785 if ((n
% 2) == 0 && c
== 0)
786 offs
[n
/ 2] = i
->offset
[n
][c
].get();
788 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
790 i
->offset
[n
][c
].get(),
791 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
795 i
->setSrc(s
, offs
[0]);
797 i
->setSrc(s
+ 1, offs
[1]);
800 assert(i
->tex
.useOffsets
== 1);
801 for (c
= 0; c
< 3; ++c
) {
803 if (!i
->offset
[0][c
].getImmediate(val
))
804 assert(!"non-immediate offset passed to non-TXG");
805 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
807 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
808 // The offset goes into the upper 16 bits of the array index. So
809 // create it if it's not already there, and INSBF it if it already
811 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
812 if (chipset
>= NVISA_GM107_CHIPSET
)
814 if (i
->tex
.target
.isArray()) {
815 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
816 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
819 i
->moveSources(s
, 1);
820 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
823 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
828 if (chipset
>= NVISA_GK104_CHIPSET
) {
830 // If TEX requires more than 4 sources, the 2nd register tuple must be
831 // aligned to 4, even if it consists of just a single 4-byte register.
833 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
835 int s
= i
->srcCount(0xff, true);
836 if (s
> 4 && s
< 7) {
837 if (i
->srcExists(s
)) // move potential predicate out of the way
838 i
->moveSources(s
, 7 - s
);
840 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
848 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
850 static const uint8_t qOps
[4][2] =
852 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
853 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
854 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
855 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
860 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
862 const int dim
= i
->tex
.target
.getDim();
863 const int array
= i
->tex
.target
.isArray();
865 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
867 for (c
= 0; c
< dim
; ++c
)
868 crd
[c
] = bld
.getScratch();
870 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
871 for (l
= 0; l
< 4; ++l
) {
872 // mov coordinates from lane l to all lanes
873 for (c
= 0; c
< dim
; ++c
)
874 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
875 // add dPdx from lane l to lanes dx
876 for (c
= 0; c
< dim
; ++c
)
877 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
878 // add dPdy from lane l to lanes dy
879 for (c
= 0; c
< dim
; ++c
)
880 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
882 bld
.insert(tex
= cloneForward(func
, i
));
883 for (c
= 0; c
< dim
; ++c
)
884 tex
->setSrc(c
+ array
, crd
[c
]);
886 for (c
= 0; i
->defExists(c
); ++c
) {
888 def
[c
][l
] = bld
.getSSA();
889 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
894 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
896 for (c
= 0; i
->defExists(c
); ++c
) {
897 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
898 for (l
= 0; l
< 4; ++l
)
899 u
->setSrc(l
, def
[c
][l
]);
907 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
909 int dim
= txd
->tex
.target
.getDim();
910 unsigned arg
= txd
->tex
.target
.getArgCount();
911 unsigned expected_args
= arg
;
912 const int chipset
= prog
->getTarget()->getChipset();
914 if (chipset
>= NVISA_GK104_CHIPSET
) {
915 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
917 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
920 if (txd
->tex
.useOffsets
)
922 if (!txd
->tex
.target
.isArray() && (
923 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
927 if (expected_args
> 4 ||
929 txd
->tex
.target
.isShadow() ||
930 txd
->tex
.target
.isCube())
934 while (txd
->srcExists(arg
))
937 txd
->tex
.derivAll
= true;
938 if (txd
->op
== OP_TEX
)
939 return handleManualTXD(txd
);
941 assert(arg
== expected_args
);
942 for (int c
= 0; c
< dim
; ++c
) {
943 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
944 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
945 txd
->dPdx
[c
].set(NULL
);
946 txd
->dPdy
[c
].set(NULL
);
952 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
954 // TODO: indirect resource/sampler index
959 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
961 /* The outputs are inverted compared to what the TGSI instruction
962 * expects. Take that into account in the mask.
964 assert((i
->tex
.mask
& ~3) == 0);
965 if (i
->tex
.mask
== 1)
967 else if (i
->tex
.mask
== 2)
970 bld
.setPosition(i
, true);
972 /* The returned values are not quite what we want:
973 * (a) convert from s16/u16 to f32
974 * (b) multiply by 1/256
976 for (int def
= 0; def
< 2; ++def
) {
977 if (!i
->defExists(def
))
979 enum DataType type
= TYPE_S16
;
980 if (i
->tex
.mask
== 2 || def
> 0)
982 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
983 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
984 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
986 if (i
->tex
.mask
== 3) {
987 LValue
*t
= new_LValue(func
, FILE_GPR
);
988 bld
.mkMov(t
, i
->getDef(0));
989 bld
.mkMov(i
->getDef(0), i
->getDef(1));
990 bld
.mkMov(i
->getDef(1), t
);
997 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1001 switch (atom
->src(0).getFile()) {
1002 case FILE_MEMORY_LOCAL
:
1005 case FILE_MEMORY_SHARED
:
1009 assert(atom
->src(0).getFile() == FILE_MEMORY_GLOBAL
);
1013 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1014 Value
*ptr
= atom
->getIndirect(0, 0);
1016 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1017 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1019 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1020 atom
->setIndirect(0, 0, base
);
1026 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1028 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1029 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1031 bld
.setPosition(cas
, true);
1034 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1035 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1037 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1038 if (cas
->isPredicated())
1039 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1042 if (cas
->defExists(0) && cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1043 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1044 // should be set to the high part of the double reg or bad things will
1045 // happen elsewhere in the universe.
1046 // Also, it sometimes returns the new value instead of the old one
1047 // under mysterious circumstances.
1048 Value
*dreg
= bld
.getSSA(8);
1049 bld
.setPosition(cas
, false);
1050 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1051 cas
->setSrc(1, dreg
);
1058 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
)
1060 uint8_t b
= prog
->driver
->io
.resInfoCBSlot
;
1061 off
+= prog
->driver
->io
.suInfoBase
;
1063 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1067 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1069 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1070 off
+= prog
->driver
->io
.msInfoBase
;
1072 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1075 /* On nvc0, surface info is obtained via the surface binding points passed
1076 * to the SULD/SUST instructions.
1077 * On nve4, surface info is stored in c[] and is used by various special
1078 * instructions, e.g. for clamping coordiantes or generating an address.
1079 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1081 #define NVE4_SU_INFO_ADDR 0x00
1082 #define NVE4_SU_INFO_FMT 0x04
1083 #define NVE4_SU_INFO_DIM_X 0x08
1084 #define NVE4_SU_INFO_PITCH 0x0c
1085 #define NVE4_SU_INFO_DIM_Y 0x10
1086 #define NVE4_SU_INFO_ARRAY 0x14
1087 #define NVE4_SU_INFO_DIM_Z 0x18
1088 #define NVE4_SU_INFO_UNK1C 0x1c
1089 #define NVE4_SU_INFO_WIDTH 0x20
1090 #define NVE4_SU_INFO_HEIGHT 0x24
1091 #define NVE4_SU_INFO_DEPTH 0x28
1092 #define NVE4_SU_INFO_TARGET 0x2c
1093 #define NVE4_SU_INFO_CALL 0x30
1094 #define NVE4_SU_INFO_RAW_X 0x34
1095 #define NVE4_SU_INFO_MS_X 0x38
1096 #define NVE4_SU_INFO_MS_Y 0x3c
1098 #define NVE4_SU_INFO__STRIDE 0x40
1100 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
1101 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1102 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
1104 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1106 switch (su
->tex
.target
.getEnum()) {
1107 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1108 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1109 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1110 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1111 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1112 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1113 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1114 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1115 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1116 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1117 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1118 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1119 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1127 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1129 const uint16_t base
= tex
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1130 const int arg
= tex
->tex
.target
.getArgCount();
1132 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1133 tex
->tex
.target
= TEX_TARGET_2D
;
1135 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1136 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1140 Value
*x
= tex
->getSrc(0);
1141 Value
*y
= tex
->getSrc(1);
1142 Value
*s
= tex
->getSrc(arg
- 1);
1144 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1146 Value
*ms_x
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(0));
1147 Value
*ms_y
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_MS(1));
1149 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1150 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1152 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1153 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1155 Value
*dx
= loadMsInfo32(ts
, 0x0);
1156 Value
*dy
= loadMsInfo32(ts
, 0x4);
1158 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1159 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1163 tex
->moveSources(arg
, -1);
1166 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1167 // They're computed from the coordinates using the surface info in c[] space.
1169 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1172 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1174 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1175 const int idx
= su
->tex
.r
;
1176 const int dim
= su
->tex
.target
.getDim();
1177 const int arg
= dim
+ (su
->tex
.target
.isArray() ? 1 : 0);
1178 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
1180 Value
*zero
= bld
.mkImm(0);
1184 Value
*bf
, *eau
, *off
;
1187 off
= bld
.getScratch(4);
1188 bf
= bld
.getScratch(4);
1189 addr
= bld
.getSSA(8);
1190 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1192 bld
.setPosition(su
, false);
1194 adjustCoordinatesMS(su
);
1196 // calculate clamped coordinates
1197 for (c
= 0; c
< arg
; ++c
) {
1198 src
[c
] = bld
.getScratch();
1200 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_RAW_X
);
1202 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_DIM(c
));
1203 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1204 ->subOp
= getSuClampSubOp(su
, c
);
1209 // set predicate output
1210 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1211 src
[0]->getInsn()->setFlagsDef(1, pred
);
1213 if (su
->tex
.target
.isArray()) {
1214 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1215 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1218 // calculate pixel offset
1220 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1221 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1224 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1225 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1226 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1228 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1229 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1230 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1233 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_PITCH
);
1234 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1235 ->subOp
= su
->tex
.target
.isArray() ?
1236 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1239 // calculate effective address part 1
1240 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1244 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1245 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1246 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1260 if (!su
->tex
.target
.isArray()) {
1261 z
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_UNK1C
);
1262 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1266 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1270 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1271 insn
->subOp
= subOp
;
1272 insn
->setFlagsDef(1, pred
);
1276 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ADDR
);
1278 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1281 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1283 // add array layer offset
1284 if (su
->tex
.target
.isArray()) {
1285 v
= loadResInfo32(NULL
, base
+ NVE4_SU_INFO_ARRAY
);
1287 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1288 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1290 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1291 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1292 // combine predicates
1294 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1299 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1303 // bf == g[] address & 0xff
1304 // eau == g[] address >> 8
1305 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1306 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1308 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1309 // Convert from u32 to u8 address format, which is what the library code
1310 // doing SULDP currently uses.
1311 // XXX: can SUEAU do this ?
1312 // XXX: does it matter that we don't mask high bytes in bf ?
1314 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1315 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1318 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1320 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1321 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1323 // let's just set it 0 for raw access and hope it works
1325 bld
.mkImm(0) : loadResInfo32(NULL
, base
+ NVE4_SU_INFO_FMT
);
1327 // get rid of old coordinate sources, make space for fmt info and predicate
1328 su
->moveSources(arg
, 3 - arg
);
1329 // set 64 bit address and 32-bit format sources
1330 su
->setSrc(0, addr
);
1332 su
->setSrc(2, pred
);
1336 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1338 processSurfaceCoordsNVE4(su
);
1340 // Who do we hate more ? The person who decided that nvc0's SULD doesn't
1341 // have to support conversion or the person who decided that, in OpenCL,
1342 // you don't have to specify the format here like you do in OpenGL ?
1344 if (su
->op
== OP_SULDP
) {
1345 // We don't patch shaders. Ever.
1346 // You get an indirect call to our library blob here.
1347 // But at least it's uniform.
1348 FlowInstruction
*call
;
1351 uint16_t base
= su
->tex
.r
* NVE4_SU_INFO__STRIDE
+ NVE4_SU_INFO_CALL
;
1353 for (int i
= 0; i
< 4; ++i
)
1354 (r
[i
] = bld
.getScratch(4, FILE_GPR
))->reg
.data
.id
= i
;
1355 for (int i
= 0; i
< 3; ++i
)
1356 (p
[i
] = bld
.getScratch(1, FILE_PREDICATE
))->reg
.data
.id
= i
;
1357 (r
[4] = bld
.getScratch(8, FILE_GPR
))->reg
.data
.id
= 4;
1359 bld
.mkMov(p
[1], bld
.mkImm((su
->cache
== CACHE_CA
) ? 1 : 0), TYPE_U8
);
1360 bld
.mkMov(p
[2], bld
.mkImm((su
->cache
== CACHE_CG
) ? 1 : 0), TYPE_U8
);
1361 bld
.mkMov(p
[0], su
->getSrc(2), TYPE_U8
);
1362 bld
.mkMov(r
[4], su
->getSrc(0), TYPE_U64
);
1363 bld
.mkMov(r
[2], su
->getSrc(1), TYPE_U32
);
1365 call
= bld
.mkFlow(OP_CALL
, NULL
, su
->cc
, su
->getPredicate());
1369 call
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_CONST
,
1370 prog
->driver
->io
.resInfoCBSlot
, TYPE_U32
,
1371 prog
->driver
->io
.suInfoBase
+ base
));
1372 call
->setSrc(1, r
[2]);
1373 call
->setSrc(2, r
[4]);
1374 for (int i
= 0; i
< 3; ++i
)
1375 call
->setSrc(3 + i
, p
[i
]);
1376 for (int i
= 0; i
< 4; ++i
) {
1377 call
->setDef(i
, r
[i
]);
1378 bld
.mkMov(su
->getDef(i
), r
[i
]);
1380 call
->setDef(4, p
[1]);
1381 delete_Instruction(bld
.getProgram(), su
);
1384 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
1385 // FIXME: for out of bounds access, destination value will be undefined !
1386 Value
*pred
= su
->getSrc(2);
1387 CondCode cc
= CC_NOT_P
;
1388 if (su
->getPredicate()) {
1389 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1391 if (cc
== CC_NOT_P
) {
1392 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1394 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
1395 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
1398 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, su
->getDef(0));
1399 red
->subOp
= su
->subOp
;
1401 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
1402 red
->setSrc(0, gMemBase
);
1403 red
->setSrc(1, su
->getSrc(3));
1404 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1405 red
->setSrc(2, su
->getSrc(4));
1406 red
->setIndirect(0, 0, su
->getSrc(0));
1407 red
->setPredicate(cc
, pred
);
1408 delete_Instruction(bld
.getProgram(), su
);
1409 handleCasExch(red
, true);
1411 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
1416 NVC0LoweringPass::handleWRSV(Instruction
*i
)
1422 // must replace, $sreg are not writeable
1423 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
1426 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
1428 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
1430 st
->perPatch
= i
->perPatch
;
1432 bld
.getBB()->remove(i
);
1437 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
1439 Value
*laneid
= bld
.getSSA();
1442 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
1457 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
1459 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
1462 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
1463 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
1468 NVC0LoweringPass::handleRDSV(Instruction
*i
)
1470 Symbol
*sym
= i
->getSrc(0)->asSym();
1471 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
1474 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
1476 if (addr
>= 0x400) {
1478 if (sym
->reg
.data
.sv
.index
== 3) {
1479 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
1481 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
1488 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
1489 if (i
->srcExists(1)) {
1490 // Pass offset through to the interpolation logic
1491 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
1492 i
->getDef(0), addr
, NULL
);
1493 ld
->setSrc(1, i
->getSrc(1));
1495 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
1500 Value
*face
= i
->getDef(0);
1501 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
1502 if (i
->dType
== TYPE_F32
) {
1503 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
1504 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
1505 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
1510 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
1511 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
1516 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
1517 if (sym
->reg
.data
.sv
.index
== 3) {
1519 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
1522 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
1523 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
1524 bld
.mkSymbol(FILE_MEMORY_CONST
, 0, TYPE_U32
, addr
), NULL
);
1526 case SV_SAMPLE_INDEX
:
1527 // TODO: Properly pass source as an address in the PIX address space
1528 // (which can be of the form [r0+offset]). But this is currently
1530 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1531 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1533 case SV_SAMPLE_POS
: {
1534 Value
*off
= new_LValue(func
, FILE_GPR
);
1535 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1536 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
1537 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
1538 bld
.mkLoad(TYPE_F32
,
1541 FILE_MEMORY_CONST
, prog
->driver
->io
.resInfoCBSlot
,
1542 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
1543 4 * sym
->reg
.data
.sv
.index
),
1547 case SV_SAMPLE_MASK
:
1548 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
1549 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
1552 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
)
1553 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
1554 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
1555 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
1556 ld
->perPatch
= i
->perPatch
;
1559 bld
.getBB()->remove(i
);
1564 NVC0LoweringPass::handleDIV(Instruction
*i
)
1566 if (!isFloatType(i
->dType
))
1568 bld
.setPosition(i
, false);
1569 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
1571 i
->setSrc(1, rcp
->getDef(0));
1576 NVC0LoweringPass::handleMOD(Instruction
*i
)
1578 if (!isFloatType(i
->dType
))
1580 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
1581 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
1582 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
1583 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
1584 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
1586 i
->setSrc(1, value
);
1591 NVC0LoweringPass::handleSQRT(Instruction
*i
)
1593 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
1594 Value
*zero
= bld
.getSSA();
1597 bld
.mkOp1(OP_MOV
, TYPE_U32
, zero
, bld
.mkImm(0));
1598 if (i
->dType
== TYPE_F64
)
1599 zero
= bld
.mkOp2v(OP_MERGE
, TYPE_U64
, bld
.getSSA(8), zero
, zero
);
1600 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
1601 bld
.mkOp1(OP_MOV
, i
->dType
, i
->getDef(0), zero
)->setPredicate(CC_P
, pred
);
1602 rsq
= bld
.mkOp1(OP_RSQ
, i
->dType
,
1603 bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(0));
1604 rsq
->setPredicate(CC_NOT_P
, pred
);
1606 i
->setSrc(1, rsq
->getDef(0));
1607 i
->setPredicate(CC_NOT_P
, pred
);
1614 NVC0LoweringPass::handlePOW(Instruction
*i
)
1616 LValue
*val
= bld
.getScratch();
1618 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
1619 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
1620 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
1630 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
1632 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1633 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
1635 if (i
->src(0).isIndirect(0)) // TODO, ugly
1638 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
1639 i
->src(0).set(i
->src(1));
1641 i
->setDef(0, new_LValue(func
, FILE_GPR
));
1642 i
->getDef(0)->reg
.data
.id
= id
;
1644 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
1646 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
1647 i
->setIndirect(0, 1, gpEmitAddress
);
1653 NVC0LoweringPass::handleOUT(Instruction
*i
)
1655 Instruction
*prev
= i
->prev
;
1656 ImmediateValue stream
, prevStream
;
1658 // Only merge if the stream ids match. Also, note that the previous
1659 // instruction would have already been lowered, so we take arg1 from it.
1660 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
1661 i
->src(0).getImmediate(stream
) &&
1662 prev
->src(1).getImmediate(prevStream
) &&
1663 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
1664 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
1665 delete_Instruction(prog
, i
);
1667 assert(gpEmitAddress
);
1668 i
->setDef(0, gpEmitAddress
);
1669 i
->setSrc(1, i
->getSrc(0));
1670 i
->setSrc(0, gpEmitAddress
);
1675 // Generate a binary predicate if an instruction is predicated by
1676 // e.g. an f32 value.
1678 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
1680 Value
*pred
= insn
->getPredicate();
1683 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
1685 pdst
= new_LValue(func
, FILE_PREDICATE
);
1687 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
1688 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
1690 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
1692 insn
->setPredicate(insn
->cc
, pdst
);
1696 // - add quadop dance for texturing
1697 // - put FP outputs in GPRs
1698 // - convert instruction sequences
1701 NVC0LoweringPass::visit(Instruction
*i
)
1703 bld
.setPosition(i
, false);
1705 if (i
->cc
!= CC_ALWAYS
)
1714 return handleTEX(i
->asTex());
1716 return handleTXD(i
->asTex());
1718 return handleTXLQ(i
->asTex());
1720 return handleTXQ(i
->asTex());
1722 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
1723 i
->setSrc(0, i
->getDef(0));
1726 return handlePOW(i
);
1728 return handleDIV(i
);
1730 return handleMOD(i
);
1732 return handleSQRT(i
);
1734 return handleEXPORT(i
);
1737 return handleOUT(i
);
1739 return handleRDSV(i
);
1741 return handleWRSV(i
);
1743 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
1744 if (prog
->getType() == Program::TYPE_COMPUTE
) {
1745 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
1746 i
->getSrc(0)->reg
.fileIndex
= 0;
1748 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
1749 i
->src(0).isIndirect(0)) {
1750 // XXX: this assumes vec4 units
1751 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1752 i
->getIndirect(0, 0), bld
.mkImm(4));
1753 i
->setIndirect(0, 0, ptr
);
1756 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
1758 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
1759 if (i
->src(0).isIndirect(1)) {
1761 if (i
->src(0).isIndirect(0))
1762 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
1763 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
1764 i
->getIndirect(0, 0));
1766 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1767 i
->getIndirect(0, 1), bld
.mkImm(16));
1768 i
->setIndirect(0, 1, NULL
);
1769 i
->setIndirect(0, 0, ptr
);
1770 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
1776 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_GLOBAL
;
1778 handleCasExch(i
, cctl
);
1787 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1788 handleSurfaceOpNVE4(i
->asTex());
1797 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
1799 if (stage
== CG_STAGE_PRE_SSA
) {
1800 NVC0LoweringPass
pass(prog
);
1801 return pass
.run(prog
, false, true);
1803 if (stage
== CG_STAGE_POST_RA
) {
1804 NVC0LegalizePostRA
pass(prog
);
1805 return pass
.run(prog
, false, true);
1807 if (stage
== CG_STAGE_SSA
) {
1808 NVC0LegalizeSSA pass
;
1809 return pass
.run(prog
, false, true);
1814 } // namespace nv50_ir