2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir.h"
24 #include "codegen/nv50_ir_build_util.h"
26 #include "codegen/nv50_ir_target_nvc0.h"
27 #include "codegen/nv50_ir_lowering_nvc0.h"
39 #define QUADOP(q, r, s, t) \
40 ((QOP_##q << 6) | (QOP_##r << 4) | \
41 (QOP_##s << 2) | (QOP_##t << 0))
44 NVC0LegalizeSSA::handleDIV(Instruction
*i
)
46 FlowInstruction
*call
;
50 bld
.setPosition(i
, false);
51 def
[0] = bld
.mkMovToReg(0, i
->getSrc(0))->getDef(0);
52 def
[1] = bld
.mkMovToReg(1, i
->getSrc(1))->getDef(0);
54 case TYPE_U32
: builtin
= NVC0_BUILTIN_DIV_U32
; break;
55 case TYPE_S32
: builtin
= NVC0_BUILTIN_DIV_S32
; break;
59 call
= bld
.mkFlow(OP_CALL
, NULL
, CC_ALWAYS
, NULL
);
60 bld
.mkMov(i
->getDef(0), def
[(i
->op
== OP_DIV
) ? 0 : 1]);
61 bld
.mkClobber(FILE_GPR
, (i
->op
== OP_DIV
) ? 0xe : 0xd, 2);
62 bld
.mkClobber(FILE_PREDICATE
, (i
->dType
== TYPE_S32
) ? 0xf : 0x3, 0);
65 call
->absolute
= call
->builtin
= 1;
66 call
->target
.builtin
= builtin
;
67 delete_Instruction(prog
, i
);
71 NVC0LegalizeSSA::handleRCPRSQ(Instruction
*i
)
73 assert(i
->dType
== TYPE_F64
);
74 // There are instructions that will compute the high 32 bits of the 64-bit
75 // float. We will just stick 0 in the bottom 32 bits.
77 bld
.setPosition(i
, false);
79 // 1. Take the source and it up.
80 Value
*src
[2], *dst
[2], *def
= i
->getDef(0);
81 bld
.mkSplit(src
, 4, i
->getSrc(0));
83 // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
84 dst
[0] = bld
.loadImm(NULL
, 0);
85 dst
[1] = bld
.getSSA();
87 // 3. The new version of the instruction takes the high 32 bits of the
88 // source and outputs the high 32 bits of the destination.
92 i
->subOp
= NV50_IR_SUBOP_RCPRSQ_64H
;
94 // 4. Recombine the two dst pieces back into the original destination.
95 bld
.setPosition(i
, true);
96 bld
.mkOp2(OP_MERGE
, TYPE_U64
, def
, dst
[0], dst
[1]);
100 NVC0LegalizeSSA::handleFTZ(Instruction
*i
)
102 // Only want to flush float inputs
103 assert(i
->sType
== TYPE_F32
);
105 // If we're already flushing denorms (and NaN's) to zero, no need for this.
109 // Only certain classes of operations can flush
110 OpClass cls
= prog
->getTarget()->getOpClass(i
->op
);
111 if (cls
!= OPCLASS_ARITH
&& cls
!= OPCLASS_COMPARE
&&
112 cls
!= OPCLASS_CONVERT
)
119 NVC0LegalizeSSA::visit(Function
*fn
)
121 bld
.setProgram(fn
->getProgram());
126 NVC0LegalizeSSA::visit(BasicBlock
*bb
)
129 for (Instruction
*i
= bb
->getEntry(); i
; i
= next
) {
131 if (i
->sType
== TYPE_F32
) {
132 if (prog
->getType() != Program::TYPE_COMPUTE
)
143 if (i
->dType
== TYPE_F64
)
153 NVC0LegalizePostRA::NVC0LegalizePostRA(const Program
*prog
)
157 needTexBar(prog
->getTarget()->getChipset() >= 0xe0)
162 NVC0LegalizePostRA::insnDominatedBy(const Instruction
*later
,
163 const Instruction
*early
) const
165 if (early
->bb
== later
->bb
)
166 return early
->serial
< later
->serial
;
167 return later
->bb
->dominatedBy(early
->bb
);
171 NVC0LegalizePostRA::addTexUse(std::list
<TexUse
> &uses
,
172 Instruction
*usei
, const Instruction
*texi
)
175 bool dominated
= insnDominatedBy(usei
, texi
);
176 // Uses before the tex have to all be included. Just because an earlier
177 // instruction dominates another instruction doesn't mean that there's no
178 // way to get from the tex to the later instruction. For example you could
179 // have nested loops, with the tex in the inner loop, and uses before it in
180 // both loops - even though the outer loop's instruction would dominate the
181 // inner's, we still want a texbar before the inner loop's instruction.
183 // However we can still use the eliding logic between uses dominated by the
184 // tex instruction, as that is unambiguously correct.
186 for (std::list
<TexUse
>::iterator it
= uses
.begin(); it
!= uses
.end();) {
188 if (insnDominatedBy(usei
, it
->insn
)) {
192 if (insnDominatedBy(it
->insn
, usei
)) {
201 uses
.push_back(TexUse(usei
, texi
, dominated
));
204 // While it might be tempting to use the an algorithm that just looks at tex
205 // uses, not all texture results are guaranteed to be used on all paths. In
206 // the case where along some control flow path a texture result is never used,
207 // we might reuse that register for something else, creating a
208 // write-after-write hazard. So we have to manually look through all
209 // instructions looking for ones that reference the registers in question.
211 NVC0LegalizePostRA::findFirstUses(
212 Instruction
*texi
, std::list
<TexUse
> &uses
)
214 int minGPR
= texi
->def(0).rep()->reg
.data
.id
;
215 int maxGPR
= minGPR
+ texi
->def(0).rep()->reg
.size
/ 4 - 1;
217 unordered_set
<const BasicBlock
*> visited
;
218 findFirstUsesBB(minGPR
, maxGPR
, texi
->next
, texi
, uses
, visited
);
222 NVC0LegalizePostRA::findFirstUsesBB(
223 int minGPR
, int maxGPR
, Instruction
*start
,
224 const Instruction
*texi
, std::list
<TexUse
> &uses
,
225 unordered_set
<const BasicBlock
*> &visited
)
227 const BasicBlock
*bb
= start
->bb
;
229 // We don't process the whole bb the first time around. This is correct,
230 // however we might be in a loop and hit this BB again, and need to process
231 // the full thing. So only mark a bb as visited if we processed it from the
233 if (start
== bb
->getEntry()) {
234 if (visited
.find(bb
) != visited
.end())
239 for (Instruction
*insn
= start
; insn
!= bb
->getExit(); insn
= insn
->next
) {
243 for (int d
= 0; insn
->defExists(d
); ++d
) {
244 const Value
*def
= insn
->def(d
).rep();
245 if (insn
->def(d
).getFile() != FILE_GPR
||
246 def
->reg
.data
.id
+ def
->reg
.size
/ 4 - 1 < minGPR
||
247 def
->reg
.data
.id
> maxGPR
)
249 addTexUse(uses
, insn
, texi
);
253 for (int s
= 0; insn
->srcExists(s
); ++s
) {
254 const Value
*src
= insn
->src(s
).rep();
255 if (insn
->src(s
).getFile() != FILE_GPR
||
256 src
->reg
.data
.id
+ src
->reg
.size
/ 4 - 1 < minGPR
||
257 src
->reg
.data
.id
> maxGPR
)
259 addTexUse(uses
, insn
, texi
);
264 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
265 findFirstUsesBB(minGPR
, maxGPR
, BasicBlock::get(ei
.getNode())->getEntry(),
266 texi
, uses
, visited
);
271 // This pass is a bit long and ugly and can probably be optimized.
273 // 1. obtain a list of TEXes and their outputs' first use(s)
274 // 2. calculate the barrier level of each first use (minimal number of TEXes,
275 // over all paths, between the TEX and the use in question)
276 // 3. for each barrier, if all paths from the source TEX to that barrier
277 // contain a barrier of lesser level, it can be culled
279 NVC0LegalizePostRA::insertTextureBarriers(Function
*fn
)
281 std::list
<TexUse
> *uses
;
282 std::vector
<Instruction
*> texes
;
283 std::vector
<int> bbFirstTex
;
284 std::vector
<int> bbFirstUse
;
285 std::vector
<int> texCounts
;
286 std::vector
<TexUse
> useVec
;
289 fn
->orderInstructions(insns
);
291 texCounts
.resize(fn
->allBBlocks
.getSize(), 0);
292 bbFirstTex
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
293 bbFirstUse
.resize(fn
->allBBlocks
.getSize(), insns
.getSize());
295 // tag BB CFG nodes by their id for later
296 for (ArrayList::Iterator i
= fn
->allBBlocks
.iterator(); !i
.end(); i
.next()) {
297 BasicBlock
*bb
= reinterpret_cast<BasicBlock
*>(i
.get());
299 bb
->cfg
.tag
= bb
->getId();
302 // gather the first uses for each TEX
303 for (int i
= 0; i
< insns
.getSize(); ++i
) {
304 Instruction
*tex
= reinterpret_cast<Instruction
*>(insns
.get(i
));
305 if (isTextureOp(tex
->op
)) {
306 texes
.push_back(tex
);
307 if (!texCounts
.at(tex
->bb
->getId()))
308 bbFirstTex
[tex
->bb
->getId()] = texes
.size() - 1;
309 texCounts
[tex
->bb
->getId()]++;
315 uses
= new std::list
<TexUse
>[texes
.size()];
318 for (size_t i
= 0; i
< texes
.size(); ++i
) {
319 findFirstUses(texes
[i
], uses
[i
]);
322 // determine the barrier level at each use
323 for (size_t i
= 0; i
< texes
.size(); ++i
) {
324 for (std::list
<TexUse
>::iterator u
= uses
[i
].begin(); u
!= uses
[i
].end();
326 BasicBlock
*tb
= texes
[i
]->bb
;
327 BasicBlock
*ub
= u
->insn
->bb
;
330 for (size_t j
= i
+ 1; j
< texes
.size() &&
331 texes
[j
]->bb
== tb
&& texes
[j
]->serial
< u
->insn
->serial
;
335 u
->level
= fn
->cfg
.findLightestPathWeight(&tb
->cfg
,
336 &ub
->cfg
, texCounts
);
338 WARN("Failed to find path TEX -> TEXBAR\n");
342 // this counted all TEXes in the origin block, correct that
343 u
->level
-= i
- bbFirstTex
.at(tb
->getId()) + 1 /* this TEX */;
344 // and did not count the TEXes in the destination block, add those
345 for (size_t j
= bbFirstTex
.at(ub
->getId()); j
< texes
.size() &&
346 texes
[j
]->bb
== ub
&& texes
[j
]->serial
< u
->insn
->serial
;
350 assert(u
->level
>= 0);
351 useVec
.push_back(*u
);
356 // insert the barriers
357 for (size_t i
= 0; i
< useVec
.size(); ++i
) {
358 Instruction
*prev
= useVec
[i
].insn
->prev
;
359 if (useVec
[i
].level
< 0)
361 if (prev
&& prev
->op
== OP_TEXBAR
) {
362 if (prev
->subOp
> useVec
[i
].level
)
363 prev
->subOp
= useVec
[i
].level
;
364 prev
->setSrc(prev
->srcCount(), useVec
[i
].tex
->getDef(0));
366 Instruction
*bar
= new_Instruction(func
, OP_TEXBAR
, TYPE_NONE
);
368 bar
->subOp
= useVec
[i
].level
;
369 // make use explicit to ease latency calculation
370 bar
->setSrc(bar
->srcCount(), useVec
[i
].tex
->getDef(0));
371 useVec
[i
].insn
->bb
->insertBefore(useVec
[i
].insn
, bar
);
375 if (fn
->getProgram()->optLevel
< 3)
378 std::vector
<Limits
> limitT
, limitB
, limitS
; // entry, exit, single
380 limitT
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
381 limitB
.resize(fn
->allBBlocks
.getSize(), Limits(0, 0));
382 limitS
.resize(fn
->allBBlocks
.getSize());
384 // cull unneeded barriers (should do that earlier, but for simplicity)
385 IteratorRef bi
= fn
->cfg
.iteratorCFG();
386 // first calculate min/max outstanding TEXes for each BB
387 for (bi
->reset(); !bi
->end(); bi
->next()) {
388 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
389 BasicBlock
*bb
= BasicBlock::get(n
);
391 int max
= std::numeric_limits
<int>::max();
392 for (Instruction
*i
= bb
->getFirst(); i
; i
= i
->next
) {
393 if (isTextureOp(i
->op
)) {
395 if (max
< std::numeric_limits
<int>::max())
398 if (i
->op
== OP_TEXBAR
) {
399 min
= MIN2(min
, i
->subOp
);
400 max
= MIN2(max
, i
->subOp
);
403 // limits when looking at an isolated block
404 limitS
[bb
->getId()].min
= min
;
405 limitS
[bb
->getId()].max
= max
;
407 // propagate the min/max values
408 for (unsigned int l
= 0; l
<= fn
->loopNestingBound
; ++l
) {
409 for (bi
->reset(); !bi
->end(); bi
->next()) {
410 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
411 BasicBlock
*bb
= BasicBlock::get(n
);
412 const int bbId
= bb
->getId();
413 for (Graph::EdgeIterator ei
= n
->incident(); !ei
.end(); ei
.next()) {
414 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
415 const int inId
= in
->getId();
416 limitT
[bbId
].min
= MAX2(limitT
[bbId
].min
, limitB
[inId
].min
);
417 limitT
[bbId
].max
= MAX2(limitT
[bbId
].max
, limitB
[inId
].max
);
419 // I just hope this is correct ...
420 if (limitS
[bbId
].max
== std::numeric_limits
<int>::max()) {
422 limitB
[bbId
].min
= limitT
[bbId
].min
+ limitS
[bbId
].min
;
423 limitB
[bbId
].max
= limitT
[bbId
].max
+ limitS
[bbId
].min
;
425 // block contained a barrier
426 limitB
[bbId
].min
= MIN2(limitS
[bbId
].max
,
427 limitT
[bbId
].min
+ limitS
[bbId
].min
);
428 limitB
[bbId
].max
= MIN2(limitS
[bbId
].max
,
429 limitT
[bbId
].max
+ limitS
[bbId
].min
);
433 // finally delete unnecessary barriers
434 for (bi
->reset(); !bi
->end(); bi
->next()) {
435 Graph::Node
*n
= reinterpret_cast<Graph::Node
*>(bi
->get());
436 BasicBlock
*bb
= BasicBlock::get(n
);
437 Instruction
*prev
= NULL
;
439 int max
= limitT
[bb
->getId()].max
;
440 for (Instruction
*i
= bb
->getFirst(); i
; i
= next
) {
442 if (i
->op
== OP_TEXBAR
) {
443 if (i
->subOp
>= max
) {
444 delete_Instruction(prog
, i
);
448 if (prev
&& prev
->op
== OP_TEXBAR
&& prev
->subOp
>= max
) {
449 delete_Instruction(prog
, prev
);
454 if (isTextureOp(i
->op
)) {
457 if (i
&& !i
->isNop())
465 NVC0LegalizePostRA::visit(Function
*fn
)
468 insertTextureBarriers(fn
);
470 rZero
= new_LValue(fn
, FILE_GPR
);
471 pOne
= new_LValue(fn
, FILE_PREDICATE
);
472 carry
= new_LValue(fn
, FILE_FLAGS
);
474 rZero
->reg
.data
.id
= (prog
->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET
) ? 255 : 63;
475 carry
->reg
.data
.id
= 0;
476 pOne
->reg
.data
.id
= 7;
482 NVC0LegalizePostRA::replaceZero(Instruction
*i
)
484 for (int s
= 0; i
->srcExists(s
); ++s
) {
485 if (s
== 2 && i
->op
== OP_SUCLAMP
)
487 ImmediateValue
*imm
= i
->getSrc(s
)->asImm();
489 if (i
->op
== OP_SELP
&& s
== 2) {
491 if (imm
->reg
.data
.u64
== 0)
492 i
->src(s
).mod
= i
->src(s
).mod
^ Modifier(NV50_IR_MOD_NOT
);
493 } else if (imm
->reg
.data
.u64
== 0) {
500 // replace CONT with BRA for single unconditional continue
502 NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock
*bb
)
504 if (bb
->cfg
.incidentCount() != 2 || bb
->getEntry()->op
!= OP_PRECONT
)
506 Graph::EdgeIterator ei
= bb
->cfg
.incident();
507 if (ei
.getType() != Graph::Edge::BACK
)
509 if (ei
.getType() != Graph::Edge::BACK
)
511 BasicBlock
*contBB
= BasicBlock::get(ei
.getNode());
513 if (!contBB
->getExit() || contBB
->getExit()->op
!= OP_CONT
||
514 contBB
->getExit()->getPredicate())
516 contBB
->getExit()->op
= OP_BRA
;
517 bb
->remove(bb
->getEntry()); // delete PRECONT
520 assert(ei
.end() || ei
.getType() != Graph::Edge::BACK
);
524 // replace branches to join blocks with join ops
526 NVC0LegalizePostRA::propagateJoin(BasicBlock
*bb
)
528 if (bb
->getEntry()->op
!= OP_JOIN
|| bb
->getEntry()->asFlow()->limit
)
530 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
531 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
532 Instruction
*exit
= in
->getExit();
534 in
->insertTail(new FlowInstruction(func
, OP_JOIN
, bb
));
535 // there should always be a terminator instruction
536 WARN("inserted missing terminator in BB:%i\n", in
->getId());
538 if (exit
->op
== OP_BRA
) {
540 exit
->asFlow()->limit
= 1; // must-not-propagate marker
543 bb
->remove(bb
->getEntry());
547 NVC0LegalizePostRA::visit(BasicBlock
*bb
)
549 Instruction
*i
, *next
;
551 // remove pseudo operations and non-fixed no-ops, split 64 bit operations
552 for (i
= bb
->getFirst(); i
; i
= next
) {
554 if (i
->op
== OP_EMIT
|| i
->op
== OP_RESTART
) {
555 if (!i
->getDef(0)->refCount())
557 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
558 i
->setSrc(0, rZero
); // initial value must be 0
564 if (i
->op
== OP_BAR
&& i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
&&
565 prog
->getType() != Program::TYPE_COMPUTE
) {
566 // It seems like barriers are never required for tessellation since
567 // the warp size is 32, and there are always at most 32 tcs threads.
570 if (i
->op
== OP_LOAD
&& i
->subOp
== NV50_IR_SUBOP_LDC_IS
) {
571 int offset
= i
->src(0).get()->reg
.data
.offset
;
572 if (abs(offset
) > 0x10000)
573 i
->src(0).get()->reg
.fileIndex
+= offset
>> 16;
574 i
->src(0).get()->reg
.data
.offset
= (int)(short)offset
;
576 // TODO: Move this to before register allocation for operations that
577 // need the $c register !
578 if (typeSizeof(i
->dType
) == 8) {
580 hi
= BuildUtil::split64BitOpPostRA(func
, i
, rZero
, carry
);
585 if (i
->op
!= OP_MOV
&& i
->op
!= OP_PFETCH
)
592 if (!tryReplaceContWithBra(bb
))
598 NVC0LoweringPass::NVC0LoweringPass(Program
*prog
) : targ(prog
->getTarget())
600 bld
.setProgram(prog
);
605 NVC0LoweringPass::visit(Function
*fn
)
607 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
608 assert(!strncmp(fn
->getName(), "MAIN", 4));
609 // TODO: when we generate actual functions pass this value along somehow
610 bld
.setPosition(BasicBlock::get(fn
->cfg
.getRoot()), false);
611 gpEmitAddress
= bld
.loadImm(NULL
, 0)->asLValue();
613 bld
.setPosition(BasicBlock::get(fn
->cfgExit
)->getExit(), false);
614 bld
.mkMovToReg(0, gpEmitAddress
);
621 NVC0LoweringPass::visit(BasicBlock
*bb
)
627 NVC0LoweringPass::loadTexHandle(Value
*ptr
, unsigned int slot
)
629 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
630 uint32_t off
= prog
->driver
->io
.texBindBase
+ slot
* 4;
632 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
635 // move array source to first slot, convert to u16, add indirections
637 NVC0LoweringPass::handleTEX(TexInstruction
*i
)
639 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
640 const int arg
= i
->tex
.target
.getArgCount();
641 const int lyr
= arg
- (i
->tex
.target
.isMS() ? 2 : 1);
642 const int chipset
= prog
->getTarget()->getChipset();
644 /* Only normalize in the non-explicit derivatives case. For explicit
645 * derivatives, this is handled in handleManualTXD.
647 if (i
->tex
.target
.isCube() && i
->dPdx
[0].get() == NULL
) {
650 for (c
= 0; c
< 3; ++c
)
651 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), i
->getSrc(c
));
652 val
= bld
.getScratch();
653 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
654 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
655 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
656 for (c
= 0; c
< 3; ++c
) {
657 i
->setSrc(c
, bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(),
662 // Arguments to the TEX instruction are a little insane. Even though the
663 // encoding is identical between SM20 and SM30, the arguments mean
664 // different things between Fermi and Kepler+. A lot of arguments are
665 // optional based on flags passed to the instruction. This summarizes the
675 // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
676 // - other: 4 bits each, single reg
680 // array (+ offsets for txd in upper 16 bits)
685 // offsets (same as fermi, except txd which takes it with array)
702 if (chipset
>= NVISA_GK104_CHIPSET
) {
703 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
704 // XXX this ignores tsc, and assumes a 1:1 mapping
705 assert(i
->tex
.rIndirectSrc
>= 0);
706 Value
*hnd
= loadTexHandle(
707 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
708 i
->getIndirectR(), bld
.mkImm(2)),
712 i
->setIndirectR(hnd
);
713 i
->setIndirectS(NULL
);
714 } else if (i
->tex
.r
== i
->tex
.s
|| i
->op
== OP_TXF
) {
715 i
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
716 i
->tex
.s
= 0; // only a single cX[] value possible here
718 Value
*hnd
= bld
.getScratch();
719 Value
*rHnd
= loadTexHandle(NULL
, i
->tex
.r
);
720 Value
*sHnd
= loadTexHandle(NULL
, i
->tex
.s
);
722 bld
.mkOp3(OP_INSBF
, TYPE_U32
, hnd
, rHnd
, bld
.mkImm(0x1400), sHnd
);
724 i
->tex
.r
= 0; // not used for indirect tex
726 i
->setIndirectR(hnd
);
728 if (i
->tex
.target
.isArray()) {
729 LValue
*layer
= new_LValue(func
, FILE_GPR
);
730 Value
*src
= i
->getSrc(lyr
);
731 const int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
732 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
733 bld
.mkCvt(OP_CVT
, TYPE_U16
, layer
, sTy
, src
)->saturate
= sat
;
734 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
) {
735 for (int s
= dim
; s
>= 1; --s
)
736 i
->setSrc(s
, i
->getSrc(s
- 1));
739 i
->setSrc(dim
, layer
);
742 // Move the indirect reference to the first place
743 if (i
->tex
.rIndirectSrc
>= 0 && (
744 i
->op
== OP_TXD
|| chipset
< NVISA_GM107_CHIPSET
)) {
745 Value
*hnd
= i
->getIndirectR();
747 i
->setIndirectR(NULL
);
748 i
->moveSources(0, 1);
750 i
->tex
.rIndirectSrc
= 0;
751 i
->tex
.sIndirectSrc
= -1;
754 // (nvc0) generate and move the tsc/tic/array source to the front
755 if (i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0) {
756 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
758 Value
*ticRel
= i
->getIndirectR();
759 Value
*tscRel
= i
->getIndirectS();
762 i
->setSrc(i
->tex
.rIndirectSrc
, NULL
);
764 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
765 ticRel
, bld
.mkImm(i
->tex
.r
));
768 i
->setSrc(i
->tex
.sIndirectSrc
, NULL
);
770 tscRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
771 tscRel
, bld
.mkImm(i
->tex
.s
));
774 Value
*arrayIndex
= i
->tex
.target
.isArray() ? i
->getSrc(lyr
) : NULL
;
776 for (int s
= dim
; s
>= 1; --s
)
777 i
->setSrc(s
, i
->getSrc(s
- 1));
778 i
->setSrc(0, arrayIndex
);
780 i
->moveSources(0, 1);
784 int sat
= (i
->op
== OP_TXF
) ? 1 : 0;
785 DataType sTy
= (i
->op
== OP_TXF
) ? TYPE_U32
: TYPE_F32
;
786 bld
.mkCvt(OP_CVT
, TYPE_U16
, src
, sTy
, arrayIndex
)->saturate
= sat
;
792 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x0917), src
);
794 bld
.mkOp3(OP_INSBF
, TYPE_U32
, src
, tscRel
, bld
.mkImm(0x0710), src
);
799 // For nvc0, the sample id has to be in the second operand, as the offset
800 // does. Right now we don't know how to pass both in, and this case can't
801 // happen with OpenGL. On nve0, the sample id is part of the texture
802 // coordinate argument.
803 assert(chipset
>= NVISA_GK104_CHIPSET
||
804 !i
->tex
.useOffsets
|| !i
->tex
.target
.isMS());
806 // offset is between lod and dc
807 if (i
->tex
.useOffsets
) {
809 int s
= i
->srcCount(0xff, true);
810 if (i
->op
!= OP_TXD
|| chipset
< NVISA_GK104_CHIPSET
) {
811 if (i
->tex
.target
.isShadow())
813 if (i
->srcExists(s
)) // move potential predicate out of the way
814 i
->moveSources(s
, 1);
815 if (i
->tex
.useOffsets
== 4 && i
->srcExists(s
+ 1))
816 i
->moveSources(s
+ 1, 1);
818 if (i
->op
== OP_TXG
) {
819 // Either there is 1 offset, which goes into the 2 low bytes of the
820 // first source, or there are 4 offsets, which go into 2 sources (8
821 // values, 1 byte each).
822 Value
*offs
[2] = {NULL
, NULL
};
823 for (n
= 0; n
< i
->tex
.useOffsets
; n
++) {
824 for (c
= 0; c
< 2; ++c
) {
825 if ((n
% 2) == 0 && c
== 0)
826 offs
[n
/ 2] = i
->offset
[n
][c
].get();
828 bld
.mkOp3(OP_INSBF
, TYPE_U32
,
830 i
->offset
[n
][c
].get(),
831 bld
.mkImm(0x800 | ((n
* 16 + c
* 8) % 32)),
835 i
->setSrc(s
, offs
[0]);
837 i
->setSrc(s
+ 1, offs
[1]);
840 assert(i
->tex
.useOffsets
== 1);
841 for (c
= 0; c
< 3; ++c
) {
843 if (!i
->offset
[0][c
].getImmediate(val
))
844 assert(!"non-immediate offset passed to non-TXG");
845 imm
|= (val
.reg
.data
.u32
& 0xf) << (c
* 4);
847 if (i
->op
== OP_TXD
&& chipset
>= NVISA_GK104_CHIPSET
) {
848 // The offset goes into the upper 16 bits of the array index. So
849 // create it if it's not already there, and INSBF it if it already
851 s
= (i
->tex
.rIndirectSrc
>= 0) ? 1 : 0;
852 if (chipset
>= NVISA_GM107_CHIPSET
)
854 if (i
->tex
.target
.isArray()) {
855 bld
.mkOp3(OP_INSBF
, TYPE_U32
, i
->getSrc(s
),
856 bld
.loadImm(NULL
, imm
), bld
.mkImm(0xc10),
859 i
->moveSources(s
, 1);
860 i
->setSrc(s
, bld
.loadImm(NULL
, imm
<< 16));
863 i
->setSrc(s
, bld
.loadImm(NULL
, imm
));
868 if (chipset
>= NVISA_GK104_CHIPSET
) {
870 // If TEX requires more than 4 sources, the 2nd register tuple must be
871 // aligned to 4, even if it consists of just a single 4-byte register.
873 // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
875 int s
= i
->srcCount(0xff, true);
876 if (s
> 4 && s
< 7) {
877 if (i
->srcExists(s
)) // move potential predicate out of the way
878 i
->moveSources(s
, 7 - s
);
880 i
->setSrc(s
++, bld
.loadImm(NULL
, 0));
888 NVC0LoweringPass::handleManualTXD(TexInstruction
*i
)
890 static const uint8_t qOps
[4][2] =
892 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l0
893 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(MOV2
, MOV2
, ADD
, ADD
) }, // l1
894 { QUADOP(MOV2
, ADD
, MOV2
, ADD
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l2
895 { QUADOP(SUBR
, MOV2
, SUBR
, MOV2
), QUADOP(SUBR
, SUBR
, MOV2
, MOV2
) }, // l3
900 Value
*zero
= bld
.loadImm(bld
.getSSA(), 0);
902 const int dim
= i
->tex
.target
.getDim() + i
->tex
.target
.isCube();
904 // This function is invoked after handleTEX lowering, so we have to expect
905 // the arguments in the order that the hw wants them. For Fermi, array and
906 // indirect are both in the leading arg, while for Kepler, array and
907 // indirect are separate (and both precede the coordinates). Maxwell is
908 // handled in a separate function.
910 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
911 array
= i
->tex
.target
.isArray() || i
->tex
.rIndirectSrc
>= 0;
913 array
= i
->tex
.target
.isArray() + (i
->tex
.rIndirectSrc
>= 0);
915 i
->op
= OP_TEX
; // no need to clone dPdx/dPdy later
917 for (c
= 0; c
< dim
; ++c
)
918 crd
[c
] = bld
.getScratch();
920 bld
.mkOp(OP_QUADON
, TYPE_NONE
, NULL
);
921 for (l
= 0; l
< 4; ++l
) {
923 // mov coordinates from lane l to all lanes
924 for (c
= 0; c
< dim
; ++c
)
925 bld
.mkQuadop(0x00, crd
[c
], l
, i
->getSrc(c
+ array
), zero
);
926 // add dPdx from lane l to lanes dx
927 for (c
= 0; c
< dim
; ++c
)
928 bld
.mkQuadop(qOps
[l
][0], crd
[c
], l
, i
->dPdx
[c
].get(), crd
[c
]);
929 // add dPdy from lane l to lanes dy
930 for (c
= 0; c
< dim
; ++c
)
931 bld
.mkQuadop(qOps
[l
][1], crd
[c
], l
, i
->dPdy
[c
].get(), crd
[c
]);
932 // normalize cube coordinates
933 if (i
->tex
.target
.isCube()) {
934 for (c
= 0; c
< 3; ++c
)
935 src
[c
] = bld
.mkOp1v(OP_ABS
, TYPE_F32
, bld
.getSSA(), crd
[c
]);
936 val
= bld
.getScratch();
937 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[0], src
[1]);
938 bld
.mkOp2(OP_MAX
, TYPE_F32
, val
, src
[2], val
);
939 bld
.mkOp1(OP_RCP
, TYPE_F32
, val
, val
);
940 for (c
= 0; c
< 3; ++c
)
941 src
[c
] = bld
.mkOp2v(OP_MUL
, TYPE_F32
, bld
.getSSA(), crd
[c
], val
);
943 for (c
= 0; c
< dim
; ++c
)
947 bld
.insert(tex
= cloneForward(func
, i
));
948 for (c
= 0; c
< dim
; ++c
)
949 tex
->setSrc(c
+ array
, src
[c
]);
951 for (c
= 0; i
->defExists(c
); ++c
) {
953 def
[c
][l
] = bld
.getSSA();
954 mov
= bld
.mkMov(def
[c
][l
], tex
->getDef(c
));
959 bld
.mkOp(OP_QUADPOP
, TYPE_NONE
, NULL
);
961 for (c
= 0; i
->defExists(c
); ++c
) {
962 Instruction
*u
= bld
.mkOp(OP_UNION
, TYPE_U32
, i
->getDef(c
));
963 for (l
= 0; l
< 4; ++l
)
964 u
->setSrc(l
, def
[c
][l
]);
972 NVC0LoweringPass::handleTXD(TexInstruction
*txd
)
974 int dim
= txd
->tex
.target
.getDim() + txd
->tex
.target
.isCube();
975 unsigned arg
= txd
->tex
.target
.getArgCount();
976 unsigned expected_args
= arg
;
977 const int chipset
= prog
->getTarget()->getChipset();
979 if (chipset
>= NVISA_GK104_CHIPSET
) {
980 if (!txd
->tex
.target
.isArray() && txd
->tex
.useOffsets
)
982 if (txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0)
985 if (txd
->tex
.useOffsets
)
987 if (!txd
->tex
.target
.isArray() && (
988 txd
->tex
.rIndirectSrc
>= 0 || txd
->tex
.sIndirectSrc
>= 0))
992 if (expected_args
> 4 ||
994 txd
->tex
.target
.isShadow())
998 while (txd
->srcExists(arg
))
1001 txd
->tex
.derivAll
= true;
1002 if (txd
->op
== OP_TEX
)
1003 return handleManualTXD(txd
);
1005 assert(arg
== expected_args
);
1006 for (int c
= 0; c
< dim
; ++c
) {
1007 txd
->setSrc(arg
+ c
* 2 + 0, txd
->dPdx
[c
]);
1008 txd
->setSrc(arg
+ c
* 2 + 1, txd
->dPdy
[c
]);
1009 txd
->dPdx
[c
].set(NULL
);
1010 txd
->dPdy
[c
].set(NULL
);
1013 // In this case we have fewer than 4 "real" arguments, which means that
1014 // handleTEX didn't apply any padding. However we have to make sure that
1015 // the second "group" of arguments still gets padded up to 4.
1016 if (chipset
>= NVISA_GK104_CHIPSET
) {
1017 int s
= arg
+ 2 * dim
;
1018 if (s
>= 4 && s
< 7) {
1019 if (txd
->srcExists(s
)) // move potential predicate out of the way
1020 txd
->moveSources(s
, 7 - s
);
1022 txd
->setSrc(s
++, bld
.loadImm(NULL
, 0));
1030 NVC0LoweringPass::handleTXQ(TexInstruction
*txq
)
1032 const int chipset
= prog
->getTarget()->getChipset();
1033 if (chipset
>= NVISA_GK104_CHIPSET
&& txq
->tex
.rIndirectSrc
< 0)
1034 txq
->tex
.r
+= prog
->driver
->io
.texBindBase
/ 4;
1036 if (txq
->tex
.rIndirectSrc
< 0)
1039 Value
*ticRel
= txq
->getIndirectR();
1041 txq
->setIndirectS(NULL
);
1042 txq
->tex
.sIndirectSrc
= -1;
1046 if (chipset
< NVISA_GK104_CHIPSET
) {
1047 LValue
*src
= new_LValue(func
, FILE_GPR
); // 0xttxsaaaa
1049 txq
->setSrc(txq
->tex
.rIndirectSrc
, NULL
);
1051 ticRel
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(),
1052 ticRel
, bld
.mkImm(txq
->tex
.r
));
1054 bld
.mkOp2(OP_SHL
, TYPE_U32
, src
, ticRel
, bld
.mkImm(0x17));
1056 txq
->moveSources(0, 1);
1057 txq
->setSrc(0, src
);
1059 Value
*hnd
= loadTexHandle(
1060 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1061 txq
->getIndirectR(), bld
.mkImm(2)),
1066 txq
->setIndirectR(NULL
);
1067 txq
->moveSources(0, 1);
1068 txq
->setSrc(0, hnd
);
1069 txq
->tex
.rIndirectSrc
= 0;
1076 NVC0LoweringPass::handleTXLQ(TexInstruction
*i
)
1078 /* The outputs are inverted compared to what the TGSI instruction
1079 * expects. Take that into account in the mask.
1081 assert((i
->tex
.mask
& ~3) == 0);
1082 if (i
->tex
.mask
== 1)
1084 else if (i
->tex
.mask
== 2)
1087 bld
.setPosition(i
, true);
1089 /* The returned values are not quite what we want:
1090 * (a) convert from s16/u16 to f32
1091 * (b) multiply by 1/256
1093 for (int def
= 0; def
< 2; ++def
) {
1094 if (!i
->defExists(def
))
1096 enum DataType type
= TYPE_S16
;
1097 if (i
->tex
.mask
== 2 || def
> 0)
1099 bld
.mkCvt(OP_CVT
, TYPE_F32
, i
->getDef(def
), type
, i
->getDef(def
));
1100 bld
.mkOp2(OP_MUL
, TYPE_F32
, i
->getDef(def
),
1101 i
->getDef(def
), bld
.loadImm(NULL
, 1.0f
/ 256));
1103 if (i
->tex
.mask
== 3) {
1104 LValue
*t
= new_LValue(func
, FILE_GPR
);
1105 bld
.mkMov(t
, i
->getDef(0));
1106 bld
.mkMov(i
->getDef(0), i
->getDef(1));
1107 bld
.mkMov(i
->getDef(1), t
);
1113 NVC0LoweringPass::handleBUFQ(Instruction
*bufq
)
1116 bufq
->setSrc(0, loadBufLength32(bufq
->getIndirect(0, 1),
1117 bufq
->getSrc(0)->reg
.fileIndex
* 16));
1118 bufq
->setIndirect(0, 0, NULL
);
1119 bufq
->setIndirect(0, 1, NULL
);
1124 NVC0LoweringPass::handleSharedATOMNVE4(Instruction
*atom
)
1126 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1128 BasicBlock
*currBB
= atom
->bb
;
1129 BasicBlock
*tryLockBB
= atom
->bb
->splitBefore(atom
, false);
1130 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1131 BasicBlock
*setAndUnlockBB
= new BasicBlock(func
);
1132 BasicBlock
*failLockBB
= new BasicBlock(func
);
1134 bld
.setPosition(currBB
, true);
1135 assert(!currBB
->joinAt
);
1136 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1138 CmpInstruction
*pred
=
1139 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1140 TYPE_U32
, bld
.mkImm(0), bld
.mkImm(1));
1142 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_ALWAYS
, NULL
);
1143 currBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::TREE
);
1145 bld
.setPosition(tryLockBB
, true);
1148 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1149 atom
->getIndirect(0, 0));
1150 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1151 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1153 bld
.mkFlow(OP_BRA
, setAndUnlockBB
, CC_P
, ld
->getDef(1));
1154 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1155 tryLockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::CROSS
);
1156 tryLockBB
->cfg
.attach(&setAndUnlockBB
->cfg
, Graph::Edge::TREE
);
1158 tryLockBB
->cfg
.detach(&joinBB
->cfg
);
1161 bld
.setPosition(setAndUnlockBB
, true);
1163 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1164 // Read the old value, and write the new one.
1165 stVal
= atom
->getSrc(1);
1166 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1167 CmpInstruction
*set
=
1168 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(),
1169 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1171 bld
.mkCmp(OP_SLCT
, CC_NE
, TYPE_U32
, (stVal
= bld
.getSSA()),
1172 TYPE_U32
, atom
->getSrc(2), ld
->getDef(0), set
->getDef(0));
1176 switch (atom
->subOp
) {
1177 case NV50_IR_SUBOP_ATOM_ADD
:
1180 case NV50_IR_SUBOP_ATOM_AND
:
1183 case NV50_IR_SUBOP_ATOM_OR
:
1186 case NV50_IR_SUBOP_ATOM_XOR
:
1189 case NV50_IR_SUBOP_ATOM_MIN
:
1192 case NV50_IR_SUBOP_ATOM_MAX
:
1200 stVal
= bld
.mkOp2v(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1205 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1206 atom
->getIndirect(0, 0), stVal
);
1207 st
->setDef(0, pred
->getDef(0));
1208 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1210 bld
.mkFlow(OP_BRA
, failLockBB
, CC_ALWAYS
, NULL
);
1211 setAndUnlockBB
->cfg
.attach(&failLockBB
->cfg
, Graph::Edge::TREE
);
1213 // Lock until the store has not been performed.
1214 bld
.setPosition(failLockBB
, true);
1215 bld
.mkFlow(OP_BRA
, tryLockBB
, CC_NOT_P
, pred
->getDef(0));
1216 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1217 failLockBB
->cfg
.attach(&tryLockBB
->cfg
, Graph::Edge::BACK
);
1218 failLockBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::TREE
);
1220 bld
.setPosition(joinBB
, false);
1221 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1225 NVC0LoweringPass::handleSharedATOM(Instruction
*atom
)
1227 assert(atom
->src(0).getFile() == FILE_MEMORY_SHARED
);
1229 BasicBlock
*currBB
= atom
->bb
;
1230 BasicBlock
*tryLockAndSetBB
= atom
->bb
->splitBefore(atom
, false);
1231 BasicBlock
*joinBB
= atom
->bb
->splitAfter(atom
);
1233 bld
.setPosition(currBB
, true);
1234 assert(!currBB
->joinAt
);
1235 currBB
->joinAt
= bld
.mkFlow(OP_JOINAT
, joinBB
, CC_ALWAYS
, NULL
);
1237 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_ALWAYS
, NULL
);
1238 currBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::TREE
);
1240 bld
.setPosition(tryLockAndSetBB
, true);
1243 bld
.mkLoad(TYPE_U32
, atom
->getDef(0), atom
->getSrc(0)->asSym(),
1244 atom
->getIndirect(0, 0));
1245 ld
->setDef(1, bld
.getSSA(1, FILE_PREDICATE
));
1246 ld
->subOp
= NV50_IR_SUBOP_LOAD_LOCKED
;
1249 if (atom
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
) {
1250 // Read the old value, and write the new one.
1251 stVal
= atom
->getSrc(1);
1252 } else if (atom
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1253 CmpInstruction
*set
=
1254 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1255 TYPE_U32
, ld
->getDef(0), atom
->getSrc(1));
1256 set
->setPredicate(CC_P
, ld
->getDef(1));
1259 bld
.mkOp3(OP_SELP
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
1260 atom
->getSrc(2), set
->getDef(0));
1261 selp
->src(2).mod
= Modifier(NV50_IR_MOD_NOT
);
1262 selp
->setPredicate(CC_P
, ld
->getDef(1));
1264 stVal
= selp
->getDef(0);
1268 switch (atom
->subOp
) {
1269 case NV50_IR_SUBOP_ATOM_ADD
:
1272 case NV50_IR_SUBOP_ATOM_AND
:
1275 case NV50_IR_SUBOP_ATOM_OR
:
1278 case NV50_IR_SUBOP_ATOM_XOR
:
1281 case NV50_IR_SUBOP_ATOM_MIN
:
1284 case NV50_IR_SUBOP_ATOM_MAX
:
1293 bld
.mkOp2(op
, atom
->dType
, bld
.getSSA(), ld
->getDef(0),
1295 i
->setPredicate(CC_P
, ld
->getDef(1));
1297 stVal
= i
->getDef(0);
1301 bld
.mkStore(OP_STORE
, TYPE_U32
, atom
->getSrc(0)->asSym(),
1302 atom
->getIndirect(0, 0), stVal
);
1303 st
->setPredicate(CC_P
, ld
->getDef(1));
1304 st
->subOp
= NV50_IR_SUBOP_STORE_UNLOCKED
;
1306 // Loop until the lock is acquired.
1307 bld
.mkFlow(OP_BRA
, tryLockAndSetBB
, CC_NOT_P
, ld
->getDef(1));
1308 tryLockAndSetBB
->cfg
.attach(&tryLockAndSetBB
->cfg
, Graph::Edge::BACK
);
1309 tryLockAndSetBB
->cfg
.attach(&joinBB
->cfg
, Graph::Edge::CROSS
);
1310 bld
.mkFlow(OP_BRA
, joinBB
, CC_ALWAYS
, NULL
);
1314 bld
.setPosition(joinBB
, false);
1315 bld
.mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1319 NVC0LoweringPass::handleATOM(Instruction
*atom
)
1322 Value
*ptr
= atom
->getIndirect(0, 0), *ind
= atom
->getIndirect(0, 1), *base
;
1324 switch (atom
->src(0).getFile()) {
1325 case FILE_MEMORY_LOCAL
:
1328 case FILE_MEMORY_SHARED
:
1329 // For Fermi/Kepler, we have to use ld lock/st unlock to perform atomic
1330 // operations on shared memory. For Maxwell, ATOMS is enough.
1331 if (targ
->getChipset() < NVISA_GK104_CHIPSET
)
1332 handleSharedATOM(atom
);
1333 else if (targ
->getChipset() < NVISA_GM107_CHIPSET
)
1334 handleSharedATOMNVE4(atom
);
1337 assert(atom
->src(0).getFile() == FILE_MEMORY_BUFFER
);
1338 base
= loadBufInfo64(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1339 assert(base
->reg
.size
== 8);
1341 base
= bld
.mkOp2v(OP_ADD
, TYPE_U64
, base
, base
, ptr
);
1342 assert(base
->reg
.size
== 8);
1343 atom
->setIndirect(0, 0, base
);
1344 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1346 // Harden against out-of-bounds accesses
1347 Value
*offset
= bld
.loadImm(NULL
, atom
->getSrc(0)->reg
.data
.offset
+ typeSizeof(atom
->sType
));
1348 Value
*length
= loadBufLength32(ind
, atom
->getSrc(0)->reg
.fileIndex
* 16);
1349 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
1351 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, ptr
);
1352 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
1353 atom
->setPredicate(CC_NOT_P
, pred
);
1354 if (atom
->defExists(0)) {
1355 Value
*zero
, *dst
= atom
->getDef(0);
1356 atom
->setDef(0, bld
.getSSA());
1358 bld
.setPosition(atom
, true);
1359 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
1360 ->setPredicate(CC_P
, pred
);
1361 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, atom
->getDef(0), zero
);
1367 bld
.mkOp1v(OP_RDSV
, TYPE_U32
, bld
.getScratch(), bld
.mkSysVal(sv
, 0));
1369 atom
->setSrc(0, cloneShallow(func
, atom
->getSrc(0)));
1370 atom
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
1372 base
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, base
, base
, ptr
);
1373 atom
->setIndirect(0, 1, NULL
);
1374 atom
->setIndirect(0, 0, base
);
1380 NVC0LoweringPass::handleCasExch(Instruction
*cas
, bool needCctl
)
1382 if (targ
->getChipset() < NVISA_GM107_CHIPSET
) {
1383 if (cas
->src(0).getFile() == FILE_MEMORY_SHARED
) {
1384 // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
1389 if (cas
->subOp
!= NV50_IR_SUBOP_ATOM_CAS
&&
1390 cas
->subOp
!= NV50_IR_SUBOP_ATOM_EXCH
)
1392 bld
.setPosition(cas
, true);
1395 Instruction
*cctl
= bld
.mkOp1(OP_CCTL
, TYPE_NONE
, NULL
, cas
->getSrc(0));
1396 cctl
->setIndirect(0, 0, cas
->getIndirect(0, 0));
1398 cctl
->subOp
= NV50_IR_SUBOP_CCTL_IV
;
1399 if (cas
->isPredicated())
1400 cctl
->setPredicate(cas
->cc
, cas
->getPredicate());
1403 if (cas
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
1404 // CAS is crazy. It's 2nd source is a double reg, and the 3rd source
1405 // should be set to the high part of the double reg or bad things will
1406 // happen elsewhere in the universe.
1407 // Also, it sometimes returns the new value instead of the old one
1408 // under mysterious circumstances.
1409 Value
*dreg
= bld
.getSSA(8);
1410 bld
.setPosition(cas
, false);
1411 bld
.mkOp2(OP_MERGE
, TYPE_U64
, dreg
, cas
->getSrc(1), cas
->getSrc(2));
1412 cas
->setSrc(1, dreg
);
1413 cas
->setSrc(2, dreg
);
1420 NVC0LoweringPass::loadResInfo32(Value
*ptr
, uint32_t off
, uint16_t base
)
1422 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1426 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1430 NVC0LoweringPass::loadResInfo64(Value
*ptr
, uint32_t off
, uint16_t base
)
1432 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1436 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1439 mkLoadv(TYPE_U64
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
), ptr
);
1443 NVC0LoweringPass::loadResLength32(Value
*ptr
, uint32_t off
, uint16_t base
)
1445 uint8_t b
= prog
->driver
->io
.auxCBSlot
;
1449 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getScratch(), ptr
, bld
.mkImm(4));
1452 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U64
, off
+ 8), ptr
);
1456 NVC0LoweringPass::loadSuInfo32(Value
*ptr
, uint32_t off
)
1458 return loadResInfo32(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1462 NVC0LoweringPass::loadSuInfo64(Value
*ptr
, uint32_t off
)
1464 return loadResInfo64(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1468 NVC0LoweringPass::loadSuLength32(Value
*ptr
, uint32_t off
)
1470 return loadResLength32(ptr
, off
, prog
->driver
->io
.suInfoBase
);
1474 NVC0LoweringPass::loadBufInfo32(Value
*ptr
, uint32_t off
)
1476 return loadResInfo32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1480 NVC0LoweringPass::loadBufInfo64(Value
*ptr
, uint32_t off
)
1482 return loadResInfo64(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1486 NVC0LoweringPass::loadBufLength32(Value
*ptr
, uint32_t off
)
1488 return loadResLength32(ptr
, off
, prog
->driver
->io
.bufInfoBase
);
1492 NVC0LoweringPass::loadUboInfo32(Value
*ptr
, uint32_t off
)
1494 return loadResInfo32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1498 NVC0LoweringPass::loadUboInfo64(Value
*ptr
, uint32_t off
)
1500 return loadResInfo64(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1504 NVC0LoweringPass::loadUboLength32(Value
*ptr
, uint32_t off
)
1506 return loadResLength32(ptr
, off
, prog
->driver
->io
.uboInfoBase
);
1510 NVC0LoweringPass::loadMsInfo32(Value
*ptr
, uint32_t off
)
1512 uint8_t b
= prog
->driver
->io
.msInfoCBSlot
;
1513 off
+= prog
->driver
->io
.msInfoBase
;
1515 mkLoadv(TYPE_U32
, bld
.mkSymbol(FILE_MEMORY_CONST
, b
, TYPE_U32
, off
), ptr
);
1518 /* On nvc0, surface info is obtained via the surface binding points passed
1519 * to the SULD/SUST instructions.
1520 * On nve4, surface info is stored in c[] and is used by various special
1521 * instructions, e.g. for clamping coordiantes or generating an address.
1522 * They couldn't just have added an equivalent to TIC now, couldn't they ?
1524 #define NVE4_SU_INFO_ADDR 0x00
1525 #define NVE4_SU_INFO_FMT 0x04
1526 #define NVE4_SU_INFO_DIM_X 0x08
1527 #define NVE4_SU_INFO_PITCH 0x0c
1528 #define NVE4_SU_INFO_DIM_Y 0x10
1529 #define NVE4_SU_INFO_ARRAY 0x14
1530 #define NVE4_SU_INFO_DIM_Z 0x18
1531 #define NVE4_SU_INFO_UNK1C 0x1c
1532 #define NVE4_SU_INFO_WIDTH 0x20
1533 #define NVE4_SU_INFO_HEIGHT 0x24
1534 #define NVE4_SU_INFO_DEPTH 0x28
1535 #define NVE4_SU_INFO_TARGET 0x2c
1536 #define NVE4_SU_INFO_BSIZE 0x30
1537 #define NVE4_SU_INFO_RAW_X 0x34
1538 #define NVE4_SU_INFO_MS_X 0x38
1539 #define NVE4_SU_INFO_MS_Y 0x3c
1541 #define NVE4_SU_INFO__STRIDE 0x40
1543 #define NVE4_SU_INFO_DIM(i) (0x08 + (i) * 8)
1544 #define NVE4_SU_INFO_SIZE(i) (0x20 + (i) * 4)
1545 #define NVE4_SU_INFO_MS(i) (0x38 + (i) * 4)
1547 static inline uint16_t getSuClampSubOp(const TexInstruction
*su
, int c
)
1549 switch (su
->tex
.target
.getEnum()) {
1550 case TEX_TARGET_BUFFER
: return NV50_IR_SUBOP_SUCLAMP_PL(0, 1);
1551 case TEX_TARGET_RECT
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1552 case TEX_TARGET_1D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1553 case TEX_TARGET_1D_ARRAY
: return (c
== 1) ?
1554 NV50_IR_SUBOP_SUCLAMP_PL(0, 2) :
1555 NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1556 case TEX_TARGET_2D
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1557 case TEX_TARGET_2D_MS
: return NV50_IR_SUBOP_SUCLAMP_BL(0, 2);
1558 case TEX_TARGET_2D_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1559 case TEX_TARGET_2D_MS_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1560 case TEX_TARGET_3D
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1561 case TEX_TARGET_CUBE
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1562 case TEX_TARGET_CUBE_ARRAY
: return NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
1570 NVC0LoweringPass::handleSUQ(TexInstruction
*suq
)
1572 int mask
= suq
->tex
.mask
;
1573 int dim
= suq
->tex
.target
.getDim();
1574 int arg
= dim
+ (suq
->tex
.target
.isArray() || suq
->tex
.target
.isCube());
1575 Value
*ind
= suq
->getIndirectR();
1580 ind
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(),
1581 ind
, bld
.mkImm(suq
->tex
.r
));
1582 ind
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(),
1584 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1588 base
= suq
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1591 for (c
= 0, d
= 0; c
< 3; ++c
, mask
>>= 1) {
1592 if (c
>= arg
|| !(mask
& 1))
1597 if (c
== 1 && suq
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1598 offset
= NVE4_SU_INFO_SIZE(2);
1600 offset
= NVE4_SU_INFO_SIZE(c
);
1602 bld
.mkMov(suq
->getDef(d
++), loadSuInfo32(ind
, base
+ offset
));
1603 if (c
== 2 && suq
->tex
.target
.isCube())
1604 bld
.mkOp2(OP_DIV
, TYPE_U32
, suq
->getDef(d
- 1), suq
->getDef(d
- 1),
1605 bld
.loadImm(NULL
, 6));
1609 if (suq
->tex
.target
.isMS()) {
1610 Value
*ms_x
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(0));
1611 Value
*ms_y
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(1));
1612 Value
*ms
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getScratch(), ms_x
, ms_y
);
1613 bld
.mkOp2(OP_SHL
, TYPE_U32
, suq
->getDef(d
++), bld
.loadImm(NULL
, 1), ms
);
1615 bld
.mkMov(suq
->getDef(d
++), bld
.loadImm(NULL
, 1));
1624 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction
*tex
)
1627 const int arg
= tex
->tex
.target
.getArgCount();
1629 if (tex
->tex
.target
== TEX_TARGET_2D_MS
)
1630 tex
->tex
.target
= TEX_TARGET_2D
;
1632 if (tex
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1633 tex
->tex
.target
= TEX_TARGET_2D_ARRAY
;
1637 Value
*x
= tex
->getSrc(0);
1638 Value
*y
= tex
->getSrc(1);
1639 Value
*s
= tex
->getSrc(arg
- 1);
1641 Value
*tx
= bld
.getSSA(), *ty
= bld
.getSSA(), *ts
= bld
.getSSA();
1642 Value
*ind
= tex
->getIndirectR();
1645 ind
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(),
1646 ind
, bld
.mkImm(tex
->tex
.r
));
1647 ind
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(),
1649 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
1653 base
= tex
->tex
.r
* NVE4_SU_INFO__STRIDE
;
1656 Value
*ms_x
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(0));
1657 Value
*ms_y
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_MS(1));
1659 bld
.mkOp2(OP_SHL
, TYPE_U32
, tx
, x
, ms_x
);
1660 bld
.mkOp2(OP_SHL
, TYPE_U32
, ty
, y
, ms_y
);
1662 s
= bld
.mkOp2v(OP_AND
, TYPE_U32
, ts
, s
, bld
.loadImm(NULL
, 0x7));
1663 s
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, ts
, ts
, bld
.mkImm(3));
1665 Value
*dx
= loadMsInfo32(ts
, 0x0);
1666 Value
*dy
= loadMsInfo32(ts
, 0x4);
1668 bld
.mkOp2(OP_ADD
, TYPE_U32
, tx
, tx
, dx
);
1669 bld
.mkOp2(OP_ADD
, TYPE_U32
, ty
, ty
, dy
);
1673 tex
->moveSources(arg
, -1);
1676 // Sets 64-bit "generic address", predicate and format sources for SULD/SUST.
1677 // They're computed from the coordinates using the surface info in c[] space.
1679 NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction
*su
)
1682 const bool atom
= su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
;
1684 su
->op
== OP_SULDB
|| su
->op
== OP_SUSTB
|| su
->op
== OP_SUREDB
;
1685 const int idx
= su
->tex
.r
;
1686 const int dim
= su
->tex
.target
.getDim();
1687 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
1688 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
1690 Value
*zero
= bld
.mkImm(0);
1694 Value
*bf
, *eau
, *off
;
1698 off
= bld
.getScratch(4);
1699 bf
= bld
.getScratch(4);
1700 addr
= bld
.getSSA(8);
1701 pred
= bld
.getScratch(1, FILE_PREDICATE
);
1703 bld
.setPosition(su
, false);
1705 adjustCoordinatesMS(su
);
1707 if (su
->tex
.rIndirectSrc
>= 0) {
1708 ind
= su
->getIndirectR();
1709 if (su
->tex
.r
> 0) {
1710 ind
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ind
,
1711 bld
.loadImm(NULL
, su
->tex
.r
));
1713 ind
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(7));
1714 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(6));
1717 // calculate clamped coordinates
1718 for (c
= 0; c
< arg
; ++c
) {
1721 if (c
== 1 && su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
1722 // The array index is stored in the Z component for 1D arrays.
1726 src
[c
] = bld
.getScratch();
1728 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_RAW_X
);
1730 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_DIM(dimc
));
1731 bld
.mkOp3(OP_SUCLAMP
, TYPE_S32
, src
[c
], su
->getSrc(c
), v
, zero
)
1732 ->subOp
= getSuClampSubOp(su
, dimc
);
1737 // set predicate output
1738 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1739 src
[0]->getInsn()->setFlagsDef(1, pred
);
1741 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1742 p1
= bld
.getSSA(1, FILE_PREDICATE
);
1743 src
[dim
]->getInsn()->setFlagsDef(1, p1
);
1746 // calculate pixel offset
1748 if (su
->tex
.target
!= TEX_TARGET_BUFFER
)
1749 bld
.mkOp2(OP_AND
, TYPE_U32
, off
, src
[0], bld
.loadImm(NULL
, 0xffff));
1752 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_UNK1C
);
1753 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[2], v
, src
[1])
1754 ->subOp
= NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1756 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_PITCH
);
1757 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, off
, v
, src
[0])
1758 ->subOp
= NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
1761 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_PITCH
);
1762 bld
.mkOp3(OP_MADSP
, TYPE_U32
, off
, src
[1], v
, src
[0])
1763 ->subOp
= (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) ?
1764 NV50_IR_SUBOP_MADSP_SD
: NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
1767 // calculate effective address part 1
1768 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1772 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_FMT
);
1773 bld
.mkOp3(OP_VSHL
, TYPE_U32
, bf
, src
[0], v
, zero
)
1774 ->subOp
= NV50_IR_SUBOP_V1(7,6,8|2);
1788 if (!su
->tex
.target
.isArray() && !su
->tex
.target
.isCube()) {
1789 z
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_UNK1C
);
1790 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1794 subOp
= NV50_IR_SUBOP_SUBFM_3D
;
1798 insn
= bld
.mkOp3(OP_SUBFM
, TYPE_U32
, bf
, src
[0], y
, z
);
1799 insn
->subOp
= subOp
;
1800 insn
->setFlagsDef(1, pred
);
1804 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ADDR
);
1806 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1809 eau
= bld
.mkOp3v(OP_SUEAU
, TYPE_U32
, bld
.getScratch(4), off
, bf
, v
);
1811 // add array layer offset
1812 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
1813 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ARRAY
);
1815 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, src
[1], v
, eau
)
1816 ->subOp
= NV50_IR_SUBOP_MADSP(4,0,0); // u16 u24 u32
1818 bld
.mkOp3(OP_MADSP
, TYPE_U32
, eau
, v
, src
[2], eau
)
1819 ->subOp
= NV50_IR_SUBOP_MADSP(0,0,0); // u32 u24 u32
1820 // combine predicates
1822 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, pred
, p1
);
1827 if (su
->tex
.target
== TEX_TARGET_BUFFER
) {
1831 // bf == g[] address & 0xff
1832 // eau == g[] address >> 8
1833 bld
.mkOp3(OP_PERMT
, TYPE_U32
, bf
, lo
, bld
.loadImm(NULL
, 0x6540), eau
);
1834 bld
.mkOp3(OP_PERMT
, TYPE_U32
, eau
, zero
, bld
.loadImm(NULL
, 0x0007), eau
);
1836 if (su
->op
== OP_SULDP
&& su
->tex
.target
== TEX_TARGET_BUFFER
) {
1837 // Convert from u32 to u8 address format, which is what the library code
1838 // doing SULDP currently uses.
1839 // XXX: can SUEAU do this ?
1840 // XXX: does it matter that we don't mask high bytes in bf ?
1842 bld
.mkOp2(OP_SHR
, TYPE_U32
, off
, bf
, bld
.mkImm(8));
1843 bld
.mkOp2(OP_ADD
, TYPE_U32
, eau
, eau
, off
);
1846 bld
.mkOp2(OP_MERGE
, TYPE_U64
, addr
, bf
, eau
);
1848 if (atom
&& su
->tex
.target
== TEX_TARGET_BUFFER
)
1849 bld
.mkOp2(OP_ADD
, TYPE_U64
, addr
, addr
, off
);
1851 // let's just set it 0 for raw access and hope it works
1853 bld
.mkImm(0) : loadSuInfo32(ind
, base
+ NVE4_SU_INFO_FMT
);
1855 // get rid of old coordinate sources, make space for fmt info and predicate
1856 su
->moveSources(arg
, 3 - arg
);
1857 // set 64 bit address and 32-bit format sources
1858 su
->setSrc(0, addr
);
1860 su
->setSrc(2, pred
);
1862 // prevent read fault when the image is not actually bound
1863 CmpInstruction
*pred1
=
1864 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
1865 TYPE_U32
, bld
.mkImm(0),
1866 loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ADDR
));
1868 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
1869 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
1870 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
1871 format
->bits
[2] + format
->bits
[3];
1873 // make sure that the format doesn't mismatch
1874 assert(format
->components
!= 0);
1875 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred1
->getDef(0),
1876 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
1877 loadSuInfo32(ind
, base
+ NVE4_SU_INFO_BSIZE
),
1880 su
->setPredicate(CC_NOT_P
, pred1
->getDef(0));
1882 // TODO: initialize def values to 0 when the surface operation is not
1883 // performed (not needed for stores). Also, fix the "address bounds test"
1884 // subtests from arb_shader_image_load_store-invalid for buffers, because it
1885 // seems like that the predicate is not correctly set by suclamp.
1889 getSrcType(const TexInstruction::ImgFormatDesc
*t
, int c
)
1892 case FLOAT
: return t
->bits
[c
] == 16 ? TYPE_F16
: TYPE_F32
;
1893 case UNORM
: return t
->bits
[c
] == 8 ? TYPE_U8
: TYPE_U16
;
1894 case SNORM
: return t
->bits
[c
] == 8 ? TYPE_S8
: TYPE_S16
;
1896 return (t
->bits
[c
] == 8 ? TYPE_U8
:
1897 (t
->bits
[c
] == 16 ? TYPE_U16
: TYPE_U32
));
1899 return (t
->bits
[c
] == 8 ? TYPE_S8
:
1900 (t
->bits
[c
] == 16 ? TYPE_S16
: TYPE_S32
));
1906 getDestType(const ImgType type
) {
1917 assert(!"Impossible type");
1923 NVC0LoweringPass::convertSurfaceFormat(TexInstruction
*su
)
1925 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
1926 int width
= format
->bits
[0] + format
->bits
[1] +
1927 format
->bits
[2] + format
->bits
[3];
1928 Value
*untypedDst
[4] = {};
1929 Value
*typedDst
[4] = {};
1931 // We must convert this to a generic load.
1934 su
->dType
= typeOfSize(width
/ 8);
1935 su
->sType
= TYPE_U8
;
1937 for (int i
= 0; i
< width
/ 32; i
++)
1938 untypedDst
[i
] = bld
.getSSA();
1940 untypedDst
[0] = bld
.getSSA();
1942 for (int i
= 0; i
< 4; i
++) {
1943 typedDst
[i
] = su
->getDef(i
);
1946 // Set the untyped dsts as the su's destinations
1947 for (int i
= 0; i
< 4; i
++)
1948 su
->setDef(i
, untypedDst
[i
]);
1950 bld
.setPosition(su
, true);
1952 // Unpack each component into the typed dsts
1954 for (int i
= 0; i
< 4; bits
+= format
->bits
[i
], i
++) {
1957 if (i
>= format
->components
) {
1958 if (format
->type
== FLOAT
||
1959 format
->type
== UNORM
||
1960 format
->type
== SNORM
)
1961 bld
.loadImm(typedDst
[i
], i
== 3 ? 1.0f
: 0.0f
);
1963 bld
.loadImm(typedDst
[i
], i
== 3 ? 1 : 0);
1967 // Get just that component's data into the relevant place
1968 if (format
->bits
[i
] == 32)
1969 bld
.mkMov(typedDst
[i
], untypedDst
[i
]);
1970 else if (format
->bits
[i
] == 16)
1971 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1972 getSrcType(format
, i
), untypedDst
[i
/ 2])
1973 ->subOp
= (i
& 1) << (format
->type
== FLOAT
? 0 : 1);
1974 else if (format
->bits
[i
] == 8)
1975 bld
.mkCvt(OP_CVT
, getDestType(format
->type
), typedDst
[i
],
1976 getSrcType(format
, i
), untypedDst
[0])->subOp
= i
;
1978 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, typedDst
[i
], untypedDst
[bits
/ 32],
1979 bld
.mkImm((bits
% 32) | (format
->bits
[i
] << 8)));
1980 if (format
->type
== UNORM
|| format
->type
== SNORM
)
1981 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], getSrcType(format
, i
), typedDst
[i
]);
1984 // Normalize / convert as necessary
1985 if (format
->type
== UNORM
)
1986 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << format
->bits
[i
]) - 1)));
1987 else if (format
->type
== SNORM
)
1988 bld
.mkOp2(OP_MUL
, TYPE_F32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 1.0f
/ ((1 << (format
->bits
[i
] - 1)) - 1)));
1989 else if (format
->type
== FLOAT
&& format
->bits
[i
] < 16) {
1990 bld
.mkOp2(OP_SHL
, TYPE_U32
, typedDst
[i
], typedDst
[i
], bld
.loadImm(NULL
, 15 - format
->bits
[i
]));
1991 bld
.mkCvt(OP_CVT
, TYPE_F32
, typedDst
[i
], TYPE_F16
, typedDst
[i
]);
1997 NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
*su
)
1999 processSurfaceCoordsNVE4(su
);
2001 if (su
->op
== OP_SULDP
)
2002 convertSurfaceFormat(su
);
2004 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
2005 Value
*pred
= su
->getSrc(2);
2006 CondCode cc
= CC_NOT_P
;
2007 if (su
->getPredicate()) {
2008 pred
= bld
.getScratch(1, FILE_PREDICATE
);
2010 if (cc
== CC_NOT_P
) {
2011 bld
.mkOp2(OP_OR
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
2013 bld
.mkOp2(OP_AND
, TYPE_U8
, pred
, su
->getPredicate(), su
->getSrc(2));
2014 pred
->getInsn()->src(1).mod
= Modifier(NV50_IR_MOD_NOT
);
2017 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->dType
, bld
.getSSA());
2018 red
->subOp
= su
->subOp
;
2020 gMemBase
= bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, 0);
2021 red
->setSrc(0, gMemBase
);
2022 red
->setSrc(1, su
->getSrc(3));
2023 if (su
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2024 red
->setSrc(2, su
->getSrc(4));
2025 red
->setIndirect(0, 0, su
->getSrc(0));
2027 // make sure to initialize dst value when the atomic operation is not
2029 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2031 assert(cc
== CC_NOT_P
);
2032 red
->setPredicate(cc
, pred
);
2033 mov
->setPredicate(CC_P
, pred
);
2035 bld
.mkOp2(OP_UNION
, TYPE_U32
, su
->getDef(0),
2036 red
->getDef(0), mov
->getDef(0));
2038 delete_Instruction(bld
.getProgram(), su
);
2039 handleCasExch(red
, true);
2042 if (su
->op
== OP_SUSTB
|| su
->op
== OP_SUSTP
)
2043 su
->sType
= (su
->tex
.target
== TEX_TARGET_BUFFER
) ? TYPE_U32
: TYPE_U8
;
2047 NVC0LoweringPass::processSurfaceCoordsNVC0(TexInstruction
*su
)
2049 const int idx
= su
->tex
.r
;
2050 const int dim
= su
->tex
.target
.getDim();
2051 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2052 const uint16_t base
= idx
* NVE4_SU_INFO__STRIDE
;
2054 Value
*zero
= bld
.mkImm(0);
2059 bld
.setPosition(su
, false);
2061 adjustCoordinatesMS(su
);
2063 if (su
->tex
.rIndirectSrc
>= 0) {
2064 ind
= su
->getIndirectR();
2065 if (su
->tex
.r
> 0) {
2066 ind
= bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(), ind
,
2067 bld
.loadImm(NULL
, su
->tex
.r
));
2069 ind
= bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(7));
2070 ind
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(), ind
, bld
.mkImm(6));
2073 // get surface coordinates
2074 for (c
= 0; c
< arg
; ++c
)
2075 src
[c
] = su
->getSrc(c
);
2079 // calculate pixel offset
2080 if (su
->op
== OP_SULDP
|| su
->op
== OP_SUREDP
) {
2081 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_BSIZE
);
2082 su
->setSrc(0, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[0], v
));
2085 // add array layer offset
2086 if (su
->tex
.target
.isArray() || su
->tex
.target
.isCube()) {
2087 v
= loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ARRAY
);
2089 su
->setSrc(2, bld
.mkOp2v(OP_MUL
, TYPE_U32
, bld
.getSSA(), src
[2], v
));
2092 // prevent read fault when the image is not actually bound
2093 CmpInstruction
*pred
=
2094 bld
.mkCmp(OP_SET
, CC_EQ
, TYPE_U32
, bld
.getSSA(1, FILE_PREDICATE
),
2095 TYPE_U32
, bld
.mkImm(0),
2096 loadSuInfo32(ind
, base
+ NVE4_SU_INFO_ADDR
));
2097 if (su
->op
!= OP_SUSTP
&& su
->tex
.format
) {
2098 const TexInstruction::ImgFormatDesc
*format
= su
->tex
.format
;
2099 int blockwidth
= format
->bits
[0] + format
->bits
[1] +
2100 format
->bits
[2] + format
->bits
[3];
2102 assert(format
->components
!= 0);
2103 // make sure that the format doesn't mismatch when it's not FMT_NONE
2104 bld
.mkCmp(OP_SET_OR
, CC_NE
, TYPE_U32
, pred
->getDef(0),
2105 TYPE_U32
, bld
.loadImm(NULL
, blockwidth
/ 8),
2106 loadSuInfo32(ind
, base
+ NVE4_SU_INFO_BSIZE
),
2109 su
->setPredicate(CC_NOT_P
, pred
->getDef(0));
2113 NVC0LoweringPass::handleSurfaceOpNVC0(TexInstruction
*su
)
2115 if (su
->tex
.target
== TEX_TARGET_1D_ARRAY
) {
2116 /* As 1d arrays also need 3 coordinates, switching to TEX_TARGET_2D_ARRAY
2117 * will simplify the lowering pass and the texture constraints. */
2118 su
->moveSources(1, 1);
2119 su
->setSrc(1, bld
.loadImm(NULL
, 0));
2120 su
->tex
.target
= TEX_TARGET_2D_ARRAY
;
2123 processSurfaceCoordsNVC0(su
);
2125 if (su
->op
== OP_SULDP
)
2126 convertSurfaceFormat(su
);
2128 if (su
->op
== OP_SUREDB
|| su
->op
== OP_SUREDP
) {
2129 const int dim
= su
->tex
.target
.getDim();
2130 const int arg
= dim
+ (su
->tex
.target
.isArray() || su
->tex
.target
.isCube());
2131 LValue
*addr
= bld
.getSSA(8);
2132 Value
*def
= su
->getDef(0);
2136 // Set the destination to the address
2137 su
->dType
= TYPE_U64
;
2138 su
->setDef(0, addr
);
2139 su
->setDef(1, su
->getPredicate());
2141 bld
.setPosition(su
, true);
2143 // Perform the atomic op
2144 Instruction
*red
= bld
.mkOp(OP_ATOM
, su
->sType
, bld
.getSSA());
2145 red
->subOp
= su
->subOp
;
2146 red
->setSrc(0, bld
.mkSymbol(FILE_MEMORY_GLOBAL
, 0, su
->sType
, 0));
2147 red
->setSrc(1, su
->getSrc(arg
));
2148 if (red
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2149 red
->setSrc(2, su
->getSrc(arg
+ 1));
2150 red
->setIndirect(0, 0, addr
);
2152 // make sure to initialize dst value when the atomic operation is not
2154 Instruction
*mov
= bld
.mkMov(bld
.getSSA(), bld
.loadImm(NULL
, 0));
2156 assert(su
->cc
== CC_NOT_P
);
2157 red
->setPredicate(su
->cc
, su
->getPredicate());
2158 mov
->setPredicate(CC_P
, su
->getPredicate());
2160 bld
.mkOp2(OP_UNION
, TYPE_U32
, def
, red
->getDef(0), mov
->getDef(0));
2162 handleCasExch(red
, false);
2167 NVC0LoweringPass::handleWRSV(Instruction
*i
)
2173 // must replace, $sreg are not writeable
2174 addr
= targ
->getSVAddress(FILE_SHADER_OUTPUT
, i
->getSrc(0)->asSym());
2177 sym
= bld
.mkSymbol(FILE_SHADER_OUTPUT
, 0, i
->sType
, addr
);
2179 st
= bld
.mkStore(OP_EXPORT
, i
->dType
, sym
, i
->getIndirect(0, 0),
2181 st
->perPatch
= i
->perPatch
;
2183 bld
.getBB()->remove(i
);
2188 NVC0LoweringPass::handleLDST(Instruction
*i
)
2190 if (i
->src(0).getFile() == FILE_SHADER_INPUT
) {
2191 if (prog
->getType() == Program::TYPE_COMPUTE
) {
2192 i
->getSrc(0)->reg
.file
= FILE_MEMORY_CONST
;
2193 i
->getSrc(0)->reg
.fileIndex
= 0;
2195 if (prog
->getType() == Program::TYPE_GEOMETRY
&&
2196 i
->src(0).isIndirect(0)) {
2197 // XXX: this assumes vec4 units
2198 Value
*ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2199 i
->getIndirect(0, 0), bld
.mkImm(4));
2200 i
->setIndirect(0, 0, ptr
);
2204 assert(prog
->getType() != Program::TYPE_FRAGMENT
); // INTERP
2206 } else if (i
->src(0).getFile() == FILE_MEMORY_CONST
) {
2207 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&&
2208 prog
->getType() == Program::TYPE_COMPUTE
) {
2209 // The launch descriptor only allows to set up 8 CBs, but OpenGL
2210 // requires at least 12 UBOs. To bypass this limitation, we store the
2211 // addrs into the driver constbuf and we directly load from the global
2213 int8_t fileIndex
= i
->getSrc(0)->reg
.fileIndex
- 1;
2214 Value
*ind
= i
->getIndirect(0, 1);
2217 // Clamp the UBO index when an indirect access is used to avoid
2218 // loading information from the wrong place in the driver cb.
2219 ind
= bld
.mkOp2v(OP_MIN
, TYPE_U32
, ind
,
2220 bld
.mkOp2v(OP_ADD
, TYPE_U32
, bld
.getSSA(),
2221 ind
, bld
.loadImm(NULL
, fileIndex
)),
2222 bld
.loadImm(NULL
, 12));
2225 if (i
->src(0).isIndirect(1)) {
2226 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2227 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
2228 Value
*length
= loadUboLength32(ind
, fileIndex
* 16);
2229 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2230 if (i
->src(0).isIndirect(0)) {
2231 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2232 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2234 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2235 i
->setIndirect(0, 1, NULL
);
2236 i
->setIndirect(0, 0, ptr
);
2237 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2238 i
->setPredicate(CC_NOT_P
, pred
);
2239 if (i
->defExists(0)) {
2240 bld
.mkMov(i
->getDef(0), bld
.mkImm(0));
2242 } else if (fileIndex
>= 0) {
2243 Value
*ptr
= loadUboInfo64(ind
, fileIndex
* 16);
2244 if (i
->src(0).isIndirect(0)) {
2245 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2247 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2248 i
->setIndirect(0, 1, NULL
);
2249 i
->setIndirect(0, 0, ptr
);
2251 } else if (i
->src(0).isIndirect(1)) {
2253 if (i
->src(0).isIndirect(0))
2254 ptr
= bld
.mkOp3v(OP_INSBF
, TYPE_U32
, bld
.getSSA(),
2255 i
->getIndirect(0, 1), bld
.mkImm(0x1010),
2256 i
->getIndirect(0, 0));
2258 ptr
= bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2259 i
->getIndirect(0, 1), bld
.mkImm(16));
2260 i
->setIndirect(0, 1, NULL
);
2261 i
->setIndirect(0, 0, ptr
);
2262 i
->subOp
= NV50_IR_SUBOP_LDC_IS
;
2264 } else if (i
->src(0).getFile() == FILE_SHADER_OUTPUT
) {
2265 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
2267 } else if (i
->src(0).getFile() == FILE_MEMORY_BUFFER
) {
2268 Value
*ind
= i
->getIndirect(0, 1);
2269 Value
*ptr
= loadBufInfo64(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2270 // XXX come up with a way not to do this for EVERY little access but
2271 // rather to batch these up somehow. Unfortunately we've lost the
2272 // information about the field width by the time we get here.
2273 Value
*offset
= bld
.loadImm(NULL
, i
->getSrc(0)->reg
.data
.offset
+ typeSizeof(i
->sType
));
2274 Value
*length
= loadBufLength32(ind
, i
->getSrc(0)->reg
.fileIndex
* 16);
2275 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
2276 if (i
->src(0).isIndirect(0)) {
2277 bld
.mkOp2(OP_ADD
, TYPE_U64
, ptr
, ptr
, i
->getIndirect(0, 0));
2278 bld
.mkOp2(OP_ADD
, TYPE_U32
, offset
, offset
, i
->getIndirect(0, 0));
2280 i
->setIndirect(0, 1, NULL
);
2281 i
->setIndirect(0, 0, ptr
);
2282 i
->getSrc(0)->reg
.file
= FILE_MEMORY_GLOBAL
;
2283 bld
.mkCmp(OP_SET
, CC_GT
, TYPE_U32
, pred
, TYPE_U32
, offset
, length
);
2284 i
->setPredicate(CC_NOT_P
, pred
);
2285 if (i
->defExists(0)) {
2286 Value
*zero
, *dst
= i
->getDef(0);
2287 i
->setDef(0, bld
.getSSA());
2289 bld
.setPosition(i
, true);
2290 bld
.mkMov((zero
= bld
.getSSA()), bld
.mkImm(0))
2291 ->setPredicate(CC_P
, pred
);
2292 bld
.mkOp2(OP_UNION
, TYPE_U32
, dst
, i
->getDef(0), zero
);
2298 NVC0LoweringPass::readTessCoord(LValue
*dst
, int c
)
2300 Value
*laneid
= bld
.getSSA();
2303 bld
.mkOp1(OP_RDSV
, TYPE_U32
, laneid
, bld
.mkSysVal(SV_LANEID
, 0));
2314 if (prog
->driver
->prop
.tp
.domain
!= PIPE_PRIM_TRIANGLES
) {
2315 bld
.mkMov(dst
, bld
.loadImm(NULL
, 0));
2322 bld
.mkFetch(x
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f0, NULL
, laneid
);
2324 bld
.mkFetch(y
, TYPE_F32
, FILE_SHADER_OUTPUT
, 0x2f4, NULL
, laneid
);
2327 bld
.mkOp2(OP_ADD
, TYPE_F32
, dst
, x
, y
);
2328 bld
.mkOp2(OP_SUB
, TYPE_F32
, dst
, bld
.loadImm(NULL
, 1.0f
), dst
);
2333 NVC0LoweringPass::handleRDSV(Instruction
*i
)
2335 Symbol
*sym
= i
->getSrc(0)->asSym();
2336 const SVSemantic sv
= sym
->reg
.data
.sv
.sv
;
2339 uint32_t addr
= targ
->getSVAddress(FILE_SHADER_INPUT
, sym
);
2341 if (addr
>= 0x400) {
2343 if (sym
->reg
.data
.sv
.index
== 3) {
2344 // TGSI backend may use 4th component of TID,NTID,CTAID,NCTAID
2346 i
->setSrc(0, bld
.mkImm((sv
== SV_NTID
|| sv
== SV_NCTAID
) ? 1 : 0));
2348 if (sv
== SV_VERTEX_COUNT
) {
2349 bld
.setPosition(i
, true);
2350 bld
.mkOp2(OP_EXTBF
, TYPE_U32
, i
->getDef(0), i
->getDef(0), bld
.mkImm(0x808));
2357 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
2358 if (i
->srcExists(1)) {
2359 // Pass offset through to the interpolation logic
2360 ld
= bld
.mkInterp(NV50_IR_INTERP_LINEAR
| NV50_IR_INTERP_OFFSET
,
2361 i
->getDef(0), addr
, NULL
);
2362 ld
->setSrc(1, i
->getSrc(1));
2364 bld
.mkInterp(NV50_IR_INTERP_LINEAR
, i
->getDef(0), addr
, NULL
);
2369 Value
*face
= i
->getDef(0);
2370 bld
.mkInterp(NV50_IR_INTERP_FLAT
, face
, addr
, NULL
);
2371 if (i
->dType
== TYPE_F32
) {
2372 bld
.mkOp2(OP_OR
, TYPE_U32
, face
, face
, bld
.mkImm(0x00000001));
2373 bld
.mkOp1(OP_NEG
, TYPE_S32
, face
, face
);
2374 bld
.mkCvt(OP_CVT
, TYPE_F32
, face
, TYPE_S32
, face
);
2379 assert(prog
->getType() == Program::TYPE_TESSELLATION_EVAL
);
2380 readTessCoord(i
->getDef(0)->asLValue(), i
->getSrc(0)->reg
.data
.sv
.index
);
2385 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
); // mov $sreg otherwise
2386 if (sym
->reg
.data
.sv
.index
== 3) {
2388 i
->setSrc(0, bld
.mkImm(sv
== SV_GRIDID
? 0 : 1));
2391 addr
+= prog
->driver
->prop
.cp
.gridInfoBase
;
2392 bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2393 bld
.mkSymbol(FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2394 TYPE_U32
, addr
), NULL
);
2396 case SV_SAMPLE_INDEX
:
2397 // TODO: Properly pass source as an address in the PIX address space
2398 // (which can be of the form [r0+offset]). But this is currently
2400 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2401 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2403 case SV_SAMPLE_POS
: {
2404 Value
*off
= new_LValue(func
, FILE_GPR
);
2405 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2406 ld
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2407 bld
.mkOp2(OP_SHL
, TYPE_U32
, off
, i
->getDef(0), bld
.mkImm(3));
2408 bld
.mkLoad(TYPE_F32
,
2411 FILE_MEMORY_CONST
, prog
->driver
->io
.auxCBSlot
,
2412 TYPE_U32
, prog
->driver
->io
.sampleInfoBase
+
2413 4 * sym
->reg
.data
.sv
.index
),
2417 case SV_SAMPLE_MASK
: {
2418 ld
= bld
.mkOp1(OP_PIXLD
, TYPE_U32
, i
->getDef(0), bld
.mkImm(0));
2419 ld
->subOp
= NV50_IR_SUBOP_PIXLD_COVMASK
;
2420 Instruction
*sampleid
=
2421 bld
.mkOp1(OP_PIXLD
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2422 sampleid
->subOp
= NV50_IR_SUBOP_PIXLD_SAMPLEID
;
2424 bld
.mkOp2v(OP_AND
, TYPE_U32
, bld
.getSSA(), ld
->getDef(0),
2425 bld
.mkOp2v(OP_SHL
, TYPE_U32
, bld
.getSSA(),
2426 bld
.loadImm(NULL
, 1), sampleid
->getDef(0)));
2427 if (prog
->driver
->prop
.fp
.persampleInvocation
) {
2428 bld
.mkMov(i
->getDef(0), masked
);
2430 bld
.mkOp3(OP_SELP
, TYPE_U32
, i
->getDef(0), ld
->getDef(0), masked
,
2437 case SV_BASEINSTANCE
:
2439 ld
= bld
.mkLoad(TYPE_U32
, i
->getDef(0),
2440 bld
.mkSymbol(FILE_MEMORY_CONST
,
2441 prog
->driver
->io
.auxCBSlot
,
2443 prog
->driver
->io
.drawInfoBase
+
2444 4 * (sv
- SV_BASEVERTEX
)),
2448 if (prog
->getType() == Program::TYPE_TESSELLATION_EVAL
&& !i
->perPatch
)
2449 vtx
= bld
.mkOp1v(OP_PFETCH
, TYPE_U32
, bld
.getSSA(), bld
.mkImm(0));
2450 ld
= bld
.mkFetch(i
->getDef(0), i
->dType
,
2451 FILE_SHADER_INPUT
, addr
, i
->getIndirect(0, 0), vtx
);
2452 ld
->perPatch
= i
->perPatch
;
2455 bld
.getBB()->remove(i
);
2460 NVC0LoweringPass::handleDIV(Instruction
*i
)
2462 if (!isFloatType(i
->dType
))
2464 bld
.setPosition(i
, false);
2465 Instruction
*rcp
= bld
.mkOp1(OP_RCP
, i
->dType
, bld
.getSSA(typeSizeof(i
->dType
)), i
->getSrc(1));
2467 i
->setSrc(1, rcp
->getDef(0));
2472 NVC0LoweringPass::handleMOD(Instruction
*i
)
2474 if (!isFloatType(i
->dType
))
2476 LValue
*value
= bld
.getScratch(typeSizeof(i
->dType
));
2477 bld
.mkOp1(OP_RCP
, i
->dType
, value
, i
->getSrc(1));
2478 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(0), value
);
2479 bld
.mkOp1(OP_TRUNC
, i
->dType
, value
, value
);
2480 bld
.mkOp2(OP_MUL
, i
->dType
, value
, i
->getSrc(1), value
);
2482 i
->setSrc(1, value
);
2487 NVC0LoweringPass::handleSQRT(Instruction
*i
)
2489 if (i
->dType
== TYPE_F64
) {
2490 Value
*pred
= bld
.getSSA(1, FILE_PREDICATE
);
2491 Value
*zero
= bld
.loadImm(NULL
, 0.0);
2492 Value
*dst
= bld
.getSSA(8);
2493 bld
.mkOp1(OP_RSQ
, i
->dType
, dst
, i
->getSrc(0));
2494 bld
.mkCmp(OP_SET
, CC_LE
, i
->dType
, pred
, i
->dType
, i
->getSrc(0), zero
);
2495 bld
.mkOp3(OP_SELP
, TYPE_U64
, dst
, zero
, dst
, pred
);
2498 // TODO: Handle this properly with a library function
2500 bld
.setPosition(i
, true);
2502 bld
.mkOp1(OP_RCP
, i
->dType
, i
->getDef(0), i
->getDef(0));
2509 NVC0LoweringPass::handlePOW(Instruction
*i
)
2511 LValue
*val
= bld
.getScratch();
2513 bld
.mkOp1(OP_LG2
, TYPE_F32
, val
, i
->getSrc(0));
2514 bld
.mkOp2(OP_MUL
, TYPE_F32
, val
, i
->getSrc(1), val
)->dnz
= 1;
2515 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, val
, val
);
2525 NVC0LoweringPass::handleEXPORT(Instruction
*i
)
2527 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2528 int id
= i
->getSrc(0)->reg
.data
.offset
/ 4;
2530 if (i
->src(0).isIndirect(0)) // TODO, ugly
2533 i
->subOp
= NV50_IR_SUBOP_MOV_FINAL
;
2534 i
->src(0).set(i
->src(1));
2536 i
->setDef(0, new_LValue(func
, FILE_GPR
));
2537 i
->getDef(0)->reg
.data
.id
= id
;
2539 prog
->maxGPR
= MAX2(prog
->maxGPR
, id
);
2541 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
2542 i
->setIndirect(0, 1, gpEmitAddress
);
2548 NVC0LoweringPass::handleOUT(Instruction
*i
)
2550 Instruction
*prev
= i
->prev
;
2551 ImmediateValue stream
, prevStream
;
2553 // Only merge if the stream ids match. Also, note that the previous
2554 // instruction would have already been lowered, so we take arg1 from it.
2555 if (i
->op
== OP_RESTART
&& prev
&& prev
->op
== OP_EMIT
&&
2556 i
->src(0).getImmediate(stream
) &&
2557 prev
->src(1).getImmediate(prevStream
) &&
2558 stream
.reg
.data
.u32
== prevStream
.reg
.data
.u32
) {
2559 i
->prev
->subOp
= NV50_IR_SUBOP_EMIT_RESTART
;
2560 delete_Instruction(prog
, i
);
2562 assert(gpEmitAddress
);
2563 i
->setDef(0, gpEmitAddress
);
2564 i
->setSrc(1, i
->getSrc(0));
2565 i
->setSrc(0, gpEmitAddress
);
2570 // Generate a binary predicate if an instruction is predicated by
2571 // e.g. an f32 value.
2573 NVC0LoweringPass::checkPredicate(Instruction
*insn
)
2575 Value
*pred
= insn
->getPredicate();
2578 if (!pred
|| pred
->reg
.file
== FILE_PREDICATE
)
2580 pdst
= new_LValue(func
, FILE_PREDICATE
);
2582 // CAUTION: don't use pdst->getInsn, the definition might not be unique,
2583 // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
2585 bld
.mkCmp(OP_SET
, CC_NEU
, insn
->dType
, pdst
, insn
->dType
, bld
.mkImm(0), pred
);
2587 insn
->setPredicate(insn
->cc
, pdst
);
2591 // - add quadop dance for texturing
2592 // - put FP outputs in GPRs
2593 // - convert instruction sequences
2596 NVC0LoweringPass::visit(Instruction
*i
)
2599 bld
.setPosition(i
, false);
2601 if (i
->cc
!= CC_ALWAYS
)
2610 return handleTEX(i
->asTex());
2612 return handleTXD(i
->asTex());
2614 return handleTXLQ(i
->asTex());
2616 return handleTXQ(i
->asTex());
2618 bld
.mkOp1(OP_PREEX2
, TYPE_F32
, i
->getDef(0), i
->getSrc(0));
2619 i
->setSrc(0, i
->getDef(0));
2622 return handlePOW(i
);
2624 return handleDIV(i
);
2626 return handleMOD(i
);
2628 return handleSQRT(i
);
2630 ret
= handleEXPORT(i
);
2634 return handleOUT(i
);
2636 return handleRDSV(i
);
2638 return handleWRSV(i
);
2645 const bool cctl
= i
->src(0).getFile() == FILE_MEMORY_BUFFER
;
2647 handleCasExch(i
, cctl
);
2656 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2657 handleSurfaceOpNVE4(i
->asTex());
2659 handleSurfaceOpNVC0(i
->asTex());
2662 handleSUQ(i
->asTex());
2671 /* Kepler+ has a special opcode to compute a new base address to be used
2672 * for indirect loads.
2674 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
&& !i
->perPatch
&&
2675 (i
->op
== OP_VFETCH
|| i
->op
== OP_EXPORT
) && i
->src(0).isIndirect(0)) {
2676 Instruction
*afetch
= bld
.mkOp1(OP_AFETCH
, TYPE_U32
, bld
.getSSA(),
2677 cloneShallow(func
, i
->getSrc(0)));
2678 afetch
->setIndirect(0, 0, i
->getIndirect(0, 0));
2679 i
->src(0).get()->reg
.data
.offset
= 0;
2680 i
->setIndirect(0, 0, afetch
->getDef(0));
2687 TargetNVC0::runLegalizePass(Program
*prog
, CGStage stage
) const
2689 if (stage
== CG_STAGE_PRE_SSA
) {
2690 NVC0LoweringPass
pass(prog
);
2691 return pass
.run(prog
, false, true);
2693 if (stage
== CG_STAGE_POST_RA
) {
2694 NVC0LegalizePostRA
pass(prog
);
2695 return pass
.run(prog
, false, true);
2697 if (stage
== CG_STAGE_SSA
) {
2698 NVC0LegalizeSSA pass
;
2699 return pass
.run(prog
, false, true);
2704 } // namespace nv50_ir