radeon: enable Hyper-Z on r600g and radeonsi by default
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_lowering_nvc0.h
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <tr1/unordered_set>
24
25 #include "codegen/nv50_ir.h"
26 #include "codegen/nv50_ir_build_util.h"
27
28 namespace nv50_ir {
29
30 class NVC0LegalizeSSA : public Pass
31 {
32 private:
33 virtual bool visit(BasicBlock *);
34 virtual bool visit(Function *);
35
36 // we want to insert calls to the builtin library only after optimization
37 void handleDIV(Instruction *); // integer division, modulus
38 void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
39
40 private:
41 BuildUtil bld;
42 };
43
44 class NVC0LegalizePostRA : public Pass
45 {
46 public:
47 NVC0LegalizePostRA(const Program *);
48
49 private:
50 virtual bool visit(Function *);
51 virtual bool visit(BasicBlock *);
52
53 void replaceZero(Instruction *);
54 bool tryReplaceContWithBra(BasicBlock *);
55 void propagateJoin(BasicBlock *);
56
57 struct TexUse
58 {
59 TexUse(Instruction *use, const Instruction *tex)
60 : insn(use), tex(tex), level(-1) { }
61 Instruction *insn;
62 const Instruction *tex; // or split / mov
63 int level;
64 };
65 struct Limits
66 {
67 Limits() { }
68 Limits(int min, int max) : min(min), max(max) { }
69 int min, max;
70 };
71 bool insertTextureBarriers(Function *);
72 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
73 void findFirstUses(const Instruction *tex, const Instruction *def,
74 std::list<TexUse>&,
75 std::tr1::unordered_set<const Instruction *>&);
76 void findOverwritingDefs(const Instruction *tex, Instruction *insn,
77 const BasicBlock *term,
78 std::list<TexUse>&);
79 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
80 const Instruction *recurseDef(const Instruction *);
81
82 private:
83 LValue *rZero;
84 LValue *carry;
85 const bool needTexBar;
86 };
87
88 class NVC0LoweringPass : public Pass
89 {
90 public:
91 NVC0LoweringPass(Program *);
92
93 protected:
94 bool handleRDSV(Instruction *);
95 bool handleWRSV(Instruction *);
96 bool handleEXPORT(Instruction *);
97 bool handleOUT(Instruction *);
98 bool handleDIV(Instruction *);
99 bool handleMOD(Instruction *);
100 bool handleSQRT(Instruction *);
101 bool handlePOW(Instruction *);
102 bool handleTEX(TexInstruction *);
103 bool handleTXD(TexInstruction *);
104 bool handleTXQ(TexInstruction *);
105 virtual bool handleManualTXD(TexInstruction *);
106 bool handleTXLQ(TexInstruction *);
107 bool handleATOM(Instruction *);
108 bool handleCasExch(Instruction *, bool needCctl);
109 void handleSurfaceOpNVE4(TexInstruction *);
110
111 void checkPredicate(Instruction *);
112
113 private:
114 virtual bool visit(Function *);
115 virtual bool visit(BasicBlock *);
116 virtual bool visit(Instruction *);
117
118 void readTessCoord(LValue *dst, int c);
119
120 Value *loadResInfo32(Value *ptr, uint32_t off);
121 Value *loadMsInfo32(Value *ptr, uint32_t off);
122 Value *loadTexHandle(Value *ptr, unsigned int slot);
123
124 void adjustCoordinatesMS(TexInstruction *);
125 void processSurfaceCoordsNVE4(TexInstruction *);
126
127 protected:
128 BuildUtil bld;
129
130 private:
131 const Target *const targ;
132
133 Symbol *gMemBase;
134 LValue *gpEmitAddress;
135 };
136
137 } // namespace nv50_ir