src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir.h"
  24 #include "codegen/nv50_ir_target.h"
  25
  26 #include <algorithm>
  27 #include <stack>
  28 #include <limits>
  29 #if __cplusplus >= 201103L
  30 #include <unordered_map>
  31 #else
  32 #include <tr1/unordered_map>
  33 #endif
  34
  35 namespace nv50_ir {
  36
  37 #if __cplusplus >= 201103L
  38 using std::hash;
  39 using std::unordered_map;
  40 #elif !defined(ANDROID)
  41 using std::tr1::hash;
  42 using std::tr1::unordered_map;
  43 #else
  44 #error Android release before Lollipop is not supported!
  45 #endif
  46
  47 #define MAX_REGISTER_FILE_SIZE 256
  48
  49 class RegisterSet
  50 {
  51 public:
  52    RegisterSet(const Target *);
  53
  54    void init(const Target *);
  55    void reset(DataFile, bool resetMax = false);
  56
  57    void periodicMask(DataFile f, uint32_t lock, uint32_t unlock);
  58    void intersect(DataFile f, const RegisterSet *);
  59
  60    bool assign(int32_t& reg, DataFile f, unsigned int size);
  61    void release(DataFile f, int32_t reg, unsigned int size);
  62    void occupy(DataFile f, int32_t reg, unsigned int size);
  63    void occupy(const Value *);
  64    void occupyMask(DataFile f, int32_t reg, uint8_t mask);
  65    bool isOccupied(DataFile f, int32_t reg, unsigned int size) const;
  66    bool testOccupy(const Value *);
  67    bool testOccupy(DataFile f, int32_t reg, unsigned int size);
  68
  69    inline int getMaxAssigned(DataFile f) const { return fill[f]; }
  70
  71    inline unsigned int getFileSize(DataFile f, uint8_t regSize) const
  72    {
  73       if (restrictedGPR16Range && f == FILE_GPR && regSize == 2)
  74          return (last[f] + 1) / 2;
  75       return last[f] + 1;
  76    }
  77
  78    inline unsigned int units(DataFile f, unsigned int size) const
  79    {
  80       return size >> unit[f];
  81    }
  82    // for regs of size >= 4, id is counted in 4-byte words (like nv50/c0 binary)
  83    inline unsigned int idToBytes(const Value *v) const
  84    {
  85       return v->reg.data.id * MIN2(v->reg.size, 4);
  86    }
  87    inline unsigned int idToUnits(const Value *v) const
  88    {
  89       return units(v->reg.file, idToBytes(v));
  90    }
  91    inline int bytesToId(Value *v, unsigned int bytes) const
  92    {
  93       if (v->reg.size < 4)
  94          return units(v->reg.file, bytes);
  95       return bytes / 4;
  96    }
  97    inline int unitsToId(DataFile f, int u, uint8_t size) const
  98    {
  99       if (u < 0)
 100          return -1;
 101       return (size < 4) ? u : ((u << unit[f]) / 4);
 102    }
 103
 104    void print() const;
 105
 106    const bool restrictedGPR16Range;
 107
 108 private:
 109    BitSet bits[LAST_REGISTER_FILE + 1];
 110
 111    int unit[LAST_REGISTER_FILE + 1]; // log2 of allocation granularity
 112
 113    int last[LAST_REGISTER_FILE + 1];
 114    int fill[LAST_REGISTER_FILE + 1];
 115 };
 116
 117 void
 118 RegisterSet::reset(DataFile f, bool resetMax)
 119 {
 120    bits[f].fill(0);
 121    if (resetMax)
 122       fill[f] = -1;
 123 }
 124
 125 void
 126 RegisterSet::init(const Target *targ)
 127 {
 128    for (unsigned int rf = 0; rf <= FILE_ADDRESS; ++rf) {
 129       DataFile f = static_cast<DataFile>(rf);
 130       last[rf] = targ->getFileSize(f) - 1;
 131       unit[rf] = targ->getFileUnit(f);
 132       fill[rf] = -1;
 133       assert(last[rf] < MAX_REGISTER_FILE_SIZE);
 134       bits[rf].allocate(last[rf] + 1, true);
 135    }
 136 }
 137
 138 RegisterSet::RegisterSet(const Target *targ)
 139   : restrictedGPR16Range(targ->getChipset() < 0xc0)
 140 {
 141    init(targ);
 142    for (unsigned int i = 0; i <= LAST_REGISTER_FILE; ++i)
 143       reset(static_cast<DataFile>(i));
 144 }
 145
 146 void
 147 RegisterSet::periodicMask(DataFile f, uint32_t lock, uint32_t unlock)
 148 {
 149    bits[f].periodicMask32(lock, unlock);
 150 }
 151
 152 void
 153 RegisterSet::intersect(DataFile f, const RegisterSet *set)
 154 {
 155    bits[f] |= set->bits[f];
 156 }
 157
 158 void
 159 RegisterSet::print() const
 160 {
 161    INFO("GPR:");
 162    bits[FILE_GPR].print();
 163    INFO("\n");
 164 }
 165
 166 bool
 167 RegisterSet::assign(int32_t& reg, DataFile f, unsigned int size)
 168 {
 169    reg = bits[f].findFreeRange(size);
 170    if (reg < 0)
 171       return false;
 172    fill[f] = MAX2(fill[f], (int32_t)(reg + size - 1));
 173    return true;
 174 }
 175
 176 bool
 177 RegisterSet::isOccupied(DataFile f, int32_t reg, unsigned int size) const
 178 {
 179    return bits[f].testRange(reg, size);
 180 }
 181
 182 void
 183 RegisterSet::occupy(const Value *v)
 184 {
 185    occupy(v->reg.file, idToUnits(v), v->reg.size >> unit[v->reg.file]);
 186 }
 187
 188 void
 189 RegisterSet::occupyMask(DataFile f, int32_t reg, uint8_t mask)
 190 {
 191    bits[f].setMask(reg & ~31, static_cast<uint32_t>(mask) << (reg % 32));
 192 }
 193
 194 void
 195 RegisterSet::occupy(DataFile f, int32_t reg, unsigned int size)
 196 {
 197    bits[f].setRange(reg, size);
 198
 199    INFO_DBG(0, REG_ALLOC, "reg occupy: %u[%i] %u\n", f, reg, size);
 200
 201    fill[f] = MAX2(fill[f], (int32_t)(reg + size - 1));
 202 }
 203
 204 bool
 205 RegisterSet::testOccupy(const Value *v)
 206 {
 207    return testOccupy(v->reg.file,
 208                      idToUnits(v), v->reg.size >> unit[v->reg.file]);
 209 }
 210
 211 bool
 212 RegisterSet::testOccupy(DataFile f, int32_t reg, unsigned int size)
 213 {
 214    if (isOccupied(f, reg, size))
 215       return false;
 216    occupy(f, reg, size);
 217    return true;
 218 }
 219
 220 void
 221 RegisterSet::release(DataFile f, int32_t reg, unsigned int size)
 222 {
 223    bits[f].clrRange(reg, size);
 224
 225    INFO_DBG(0, REG_ALLOC, "reg release: %u[%i] %u\n", f, reg, size);
 226 }
 227
 228 class RegAlloc
 229 {
 230 public:
 231    RegAlloc(Program *program) : prog(program), sequence(0) { }
 232
 233    bool exec();
 234    bool execFunc();
 235
 236 private:
 237    class PhiMovesPass : public Pass {
 238    private:
 239       virtual bool visit(BasicBlock *);
 240       inline bool needNewElseBlock(BasicBlock *b, BasicBlock *p);
 241       inline void splitEdges(BasicBlock *b);
 242    };
 243
 244    class ArgumentMovesPass : public Pass {
 245    private:
 246       virtual bool visit(BasicBlock *);
 247    };
 248
 249    class BuildIntervalsPass : public Pass {
 250    private:
 251       virtual bool visit(BasicBlock *);
 252       void collectLiveValues(BasicBlock *);
 253       void addLiveRange(Value *, const BasicBlock *, int end);
 254    };
 255
 256    class InsertConstraintsPass : public Pass {
 257    public:
 258       bool exec(Function *func);
 259    private:
 260       virtual bool visit(BasicBlock *);
 261
 262       bool insertConstraintMoves();
 263
 264       void condenseDefs(Instruction *);
 265       void condenseSrcs(Instruction *, const int first, const int last);
 266
 267       void addHazard(Instruction *i, const ValueRef *src);
 268       void textureMask(TexInstruction *);
 269       void addConstraint(Instruction *, int s, int n);
 270       bool detectConflict(Instruction *, int s);
 271
 272       // target specific functions, TODO: put in subclass or Target
 273       void texConstraintNV50(TexInstruction *);
 274       void texConstraintNVC0(TexInstruction *);
 275       void texConstraintNVE0(TexInstruction *);
 276       void texConstraintGM107(TexInstruction *);
 277
 278       std::list<Instruction *> constrList;
 279
 280       const Target *targ;
 281    };
 282
 283    bool buildLiveSets(BasicBlock *);
 284
 285 private:
 286    Program *prog;
 287    Function *func;
 288
 289    // instructions in control flow / chronological order
 290    ArrayList insns;
 291
 292    int sequence; // for manual passes through CFG
 293 };
 294
 295 typedef std::pair<Value *, Value *> ValuePair;
 296
 297 class SpillCodeInserter
 298 {
 299 public:
 300    SpillCodeInserter(Function *fn) : func(fn), stackSize(0), stackBase(0) { }
 301
 302    bool run(const std::list<ValuePair>&);
 303
 304    Symbol *assignSlot(const Interval&, const unsigned int size);
 305    Value *offsetSlot(Value *, const LValue *);
 306    inline int32_t getStackSize() const { return stackSize; }
 307
 308 private:
 309    Function *func;
 310
 311    struct SpillSlot
 312    {
 313       Interval occup;
 314       std::list<Value *> residents; // needed to recalculate occup
 315       Symbol *sym;
 316       int32_t offset;
 317       inline uint8_t size() const { return sym->reg.size; }
 318    };
 319    std::list<SpillSlot> slots;
 320    int32_t stackSize;
 321    int32_t stackBase;
 322
 323    LValue *unspill(Instruction *usei, LValue *, Value *slot);
 324    void spill(Instruction *defi, Value *slot, LValue *);
 325 };
 326
 327 void
 328 RegAlloc::BuildIntervalsPass::addLiveRange(Value *val,
 329                                            const BasicBlock *bb,
 330                                            int end)
 331 {
 332    Instruction *insn = val->getUniqueInsn();
 333
 334    if (!insn)
 335       insn = bb->getFirst();
 336
 337    assert(bb->getFirst()->serial <= bb->getExit()->serial);
 338    assert(bb->getExit()->serial + 1 >= end);
 339
 340    int begin = insn->serial;
 341    if (begin < bb->getEntry()->serial || begin > bb->getExit()->serial)
 342       begin = bb->getEntry()->serial;
 343
 344    INFO_DBG(prog->dbgFlags, REG_ALLOC, "%%%i <- live range [%i(%i), %i)\n",
 345             val->id, begin, insn->serial, end);
 346
 347    if (begin != end) // empty ranges are only added as hazards for fixed regs
 348       val->livei.extend(begin, end);
 349 }
 350
 351 bool
 352 RegAlloc::PhiMovesPass::needNewElseBlock(BasicBlock *b, BasicBlock *p)
 353 {
 354    if (b->cfg.incidentCount() <= 1)
 355       return false;
 356
 357    int n = 0;
 358    for (Graph::EdgeIterator ei = p->cfg.outgoing(); !ei.end(); ei.next())
 359       if (ei.getType() == Graph::Edge::TREE ||
 360           ei.getType() == Graph::Edge::FORWARD)
 361          ++n;
 362    return (n == 2);
 363 }
 364
 365 struct PhiMapHash {
 366    size_t operator()(const std::pair<Instruction *, BasicBlock *>& val) const {
 367       return hash<Instruction*>()(val.first) * 31 +
 368          hash<BasicBlock*>()(val.second);
 369    }
 370 };
 371
 372 typedef unordered_map<
 373    std::pair<Instruction *, BasicBlock *>, Value *, PhiMapHash> PhiMap;
 374
 375 // Critical edges need to be split up so that work can be inserted along
 376 // specific edge transitions. Unfortunately manipulating incident edges into a
 377 // BB invalidates all the PHI nodes since their sources are implicitly ordered
 378 // by incident edge order.
 379 //
 380 // TODO: Make it so that that is not the case, and PHI nodes store pointers to
 381 // the original BBs.
 382 void
 383 RegAlloc::PhiMovesPass::splitEdges(BasicBlock *bb)
 384 {
 385    BasicBlock *pb, *pn;
 386    Instruction *phi;
 387    Graph::EdgeIterator ei;
 388    std::stack<BasicBlock *> stack;
 389    int j = 0;
 390
 391    for (ei = bb->cfg.incident(); !ei.end(); ei.next()) {
 392       pb = BasicBlock::get(ei.getNode());
 393       assert(pb);
 394       if (needNewElseBlock(bb, pb))
 395          stack.push(pb);
 396    }
 397
 398    // No critical edges were found, no need to perform any work.
 399    if (stack.empty())
 400       return;
 401
 402    // We're about to, potentially, reorder the inbound edges. This means that
 403    // we need to hold on to the (phi, bb) -> src mapping, and fix up the phi
 404    // nodes after the graph has been modified.
 405    PhiMap phis;
 406
 407    j = 0;
 408    for (ei = bb->cfg.incident(); !ei.end(); ei.next(), j++) {
 409       pb = BasicBlock::get(ei.getNode());
 410       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next)
 411          phis.insert(std::make_pair(std::make_pair(phi, pb), phi->getSrc(j)));
 412    }
 413
 414    while (!stack.empty()) {
 415       pb = stack.top();
 416       pn = new BasicBlock(func);
 417       stack.pop();
 418
 419       pb->cfg.detach(&bb->cfg);
 420       pb->cfg.attach(&pn->cfg, Graph::Edge::TREE);
 421       pn->cfg.attach(&bb->cfg, Graph::Edge::FORWARD);
 422
 423       assert(pb->getExit()->op != OP_CALL);
 424       if (pb->getExit()->asFlow()->target.bb == bb)
 425          pb->getExit()->asFlow()->target.bb = pn;
 426
 427       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 428          PhiMap::iterator it = phis.find(std::make_pair(phi, pb));
 429          assert(it != phis.end());
 430          phis.insert(std::make_pair(std::make_pair(phi, pn), it->second));
 431          phis.erase(it);
 432       }
 433    }
 434
 435    // Now go through and fix up all of the phi node sources.
 436    j = 0;
 437    for (ei = bb->cfg.incident(); !ei.end(); ei.next(), j++) {
 438       pb = BasicBlock::get(ei.getNode());
 439       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 440          PhiMap::const_iterator it = phis.find(std::make_pair(phi, pb));
 441          assert(it != phis.end());
 442
 443          phi->setSrc(j, it->second);
 444       }
 445    }
 446 }
 447
 448 // For each operand of each PHI in b, generate a new value by inserting a MOV
 449 // at the end of the block it is coming from and replace the operand with its
 450 // result. This eliminates liveness conflicts and enables us to let values be
 451 // copied to the right register if such a conflict exists nonetheless.
 452 //
 453 // These MOVs are also crucial in making sure the live intervals of phi srces
 454 // are extended until the end of the loop, since they are not included in the
 455 // live-in sets.
 456 bool
 457 RegAlloc::PhiMovesPass::visit(BasicBlock *bb)
 458 {
 459    Instruction *phi, *mov;
 460
 461    splitEdges(bb);
 462
 463    // insert MOVs (phi->src(j) should stem from j-th in-BB)
 464    int j = 0;
 465    for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
 466       BasicBlock *pb = BasicBlock::get(ei.getNode());
 467       if (!pb->isTerminated())
 468          pb->insertTail(new_FlowInstruction(func, OP_BRA, bb));
 469
 470       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 471          LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue());
 472          mov = new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 473
 474          mov->setSrc(0, phi->getSrc(j));
 475          mov->setDef(0, tmp);
 476          phi->setSrc(j, tmp);
 477
 478          pb->insertBefore(pb->getExit(), mov);
 479       }
 480       ++j;
 481    }
 482
 483    return true;
 484 }
 485
 486 bool
 487 RegAlloc::ArgumentMovesPass::visit(BasicBlock *bb)
 488 {
 489    // Bind function call inputs/outputs to the same physical register
 490    // the callee uses, inserting moves as appropriate for the case a
 491    // conflict arises.
 492    for (Instruction *i = bb->getEntry(); i; i = i->next) {
 493       FlowInstruction *cal = i->asFlow();
 494       // TODO: Handle indirect calls.
 495       // Right now they should only be generated for builtins.
 496       if (!cal || cal->op != OP_CALL || cal->builtin || cal->indirect)
 497          continue;
 498       RegisterSet clobberSet(prog->getTarget());
 499
 500       // Bind input values.
 501       for (int s = cal->indirect ? 1 : 0; cal->srcExists(s); ++s) {
 502          const int t = cal->indirect ? (s - 1) : s;
 503          LValue *tmp = new_LValue(func, cal->getSrc(s)->asLValue());
 504          tmp->reg.data.id = cal->target.fn->ins[t].rep()->reg.data.id;
 505
 506          Instruction *mov =
 507             new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 508          mov->setDef(0, tmp);
 509          mov->setSrc(0, cal->getSrc(s));
 510          cal->setSrc(s, tmp);
 511
 512          bb->insertBefore(cal, mov);
 513       }
 514
 515       // Bind output values.
 516       for (int d = 0; cal->defExists(d); ++d) {
 517          LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue());
 518          tmp->reg.data.id = cal->target.fn->outs[d].rep()->reg.data.id;
 519
 520          Instruction *mov =
 521             new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 522          mov->setSrc(0, tmp);
 523          mov->setDef(0, cal->getDef(d));
 524          cal->setDef(d, tmp);
 525
 526          bb->insertAfter(cal, mov);
 527          clobberSet.occupy(tmp);
 528       }
 529
 530       // Bind clobbered values.
 531       for (std::deque<Value *>::iterator it = cal->target.fn->clobbers.begin();
 532            it != cal->target.fn->clobbers.end();
 533            ++it) {
 534          if (clobberSet.testOccupy(*it)) {
 535             Value *tmp = new_LValue(func, (*it)->asLValue());
 536             tmp->reg.data.id = (*it)->reg.data.id;
 537             cal->setDef(cal->defCount(), tmp);
 538          }
 539       }
 540    }
 541
 542    // Update the clobber set of the function.
 543    if (BasicBlock::get(func->cfgExit) == bb) {
 544       func->buildDefSets();
 545       for (unsigned int i = 0; i < bb->defSet.getSize(); ++i)
 546          if (bb->defSet.test(i))
 547             func->clobbers.push_back(func->getLValue(i));
 548    }
 549
 550    return true;
 551 }
 552
 553 // Build the set of live-in variables of bb.
 554 bool
 555 RegAlloc::buildLiveSets(BasicBlock *bb)
 556 {
 557    Function *f = bb->getFunction();
 558    BasicBlock *bn;
 559    Instruction *i;
 560    unsigned int s, d;
 561
 562    INFO_DBG(prog->dbgFlags, REG_ALLOC, "buildLiveSets(BB:%i)\n", bb->getId());
 563
 564    bb->liveSet.allocate(func->allLValues.getSize(), false);
 565
 566    int n = 0;
 567    for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 568       bn = BasicBlock::get(ei.getNode());
 569       if (bn == bb)
 570          continue;
 571       if (bn->cfg.visit(sequence))
 572          if (!buildLiveSets(bn))
 573             return false;
 574       if (n++ || bb->liveSet.marker)
 575          bb->liveSet |= bn->liveSet;
 576       else
 577          bb->liveSet = bn->liveSet;
 578    }
 579    if (!n && !bb->liveSet.marker)
 580       bb->liveSet.fill(0);
 581    bb->liveSet.marker = true;
 582
 583    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
 584       INFO("BB:%i live set of out blocks:\n", bb->getId());
 585       bb->liveSet.print();
 586    }
 587
 588    // if (!bb->getEntry())
 589    //   return true;
 590
 591    if (bb == BasicBlock::get(f->cfgExit)) {
 592       for (std::deque<ValueRef>::iterator it = f->outs.begin();
 593            it != f->outs.end(); ++it) {
 594          assert(it->get()->asLValue());
 595          bb->liveSet.set(it->get()->id);
 596       }
 597    }
 598
 599    for (i = bb->getExit(); i && i != bb->getEntry()->prev; i = i->prev) {
 600       for (d = 0; i->defExists(d); ++d)
 601          bb->liveSet.clr(i->getDef(d)->id);
 602       for (s = 0; i->srcExists(s); ++s)
 603          if (i->getSrc(s)->asLValue())
 604             bb->liveSet.set(i->getSrc(s)->id);
 605    }
 606    for (i = bb->getPhi(); i && i->op == OP_PHI; i = i->next)
 607       bb->liveSet.clr(i->getDef(0)->id);
 608
 609    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
 610       INFO("BB:%i live set after propagation:\n", bb->getId());
 611       bb->liveSet.print();
 612    }
 613
 614    return true;
 615 }
 616
 617 void
 618 RegAlloc::BuildIntervalsPass::collectLiveValues(BasicBlock *bb)
 619 {
 620    BasicBlock *bbA = NULL, *bbB = NULL;
 621
 622    if (bb->cfg.outgoingCount()) {
 623       // trickery to save a loop of OR'ing liveSets
 624       // aliasing works fine with BitSet::setOr
 625       for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 626          if (ei.getType() == Graph::Edge::DUMMY)
 627             continue;
 628          if (bbA) {
 629             bb->liveSet.setOr(&bbA->liveSet, &bbB->liveSet);
 630             bbA = bb;
 631          } else {
 632             bbA = bbB;
 633          }
 634          bbB = BasicBlock::get(ei.getNode());
 635       }
 636       bb->liveSet.setOr(&bbB->liveSet, bbA ? &bbA->liveSet : NULL);
 637    } else
 638    if (bb->cfg.incidentCount()) {
 639       bb->liveSet.fill(0);
 640    }
 641 }
 642
 643 bool
 644 RegAlloc::BuildIntervalsPass::visit(BasicBlock *bb)
 645 {
 646    collectLiveValues(bb);
 647
 648    INFO_DBG(prog->dbgFlags, REG_ALLOC, "BuildIntervals(BB:%i)\n", bb->getId());
 649
 650    // go through out blocks and delete phi sources that do not originate from
 651    // the current block from the live set
 652    for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 653       BasicBlock *out = BasicBlock::get(ei.getNode());
 654
 655       for (Instruction *i = out->getPhi(); i && i->op == OP_PHI; i = i->next) {
 656          bb->liveSet.clr(i->getDef(0)->id);
 657
 658          for (int s = 0; i->srcExists(s); ++s) {
 659             assert(i->src(s).getInsn());
 660             if (i->getSrc(s)->getUniqueInsn()->bb == bb) // XXX: reachableBy ?
 661                bb->liveSet.set(i->getSrc(s)->id);
 662             else
 663                bb->liveSet.clr(i->getSrc(s)->id);
 664          }
 665       }
 666    }
 667
 668    // remaining live-outs are live until end
 669    if (bb->getExit()) {
 670       for (unsigned int j = 0; j < bb->liveSet.getSize(); ++j)
 671          if (bb->liveSet.test(j))
 672             addLiveRange(func->getLValue(j), bb, bb->getExit()->serial + 1);
 673    }
 674
 675    for (Instruction *i = bb->getExit(); i && i->op != OP_PHI; i = i->prev) {
 676       for (int d = 0; i->defExists(d); ++d) {
 677          bb->liveSet.clr(i->getDef(d)->id);
 678          if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs
 679             i->getDef(d)->livei.extend(i->serial, i->serial);
 680       }
 681
 682       for (int s = 0; i->srcExists(s); ++s) {
 683          if (!i->getSrc(s)->asLValue())
 684             continue;
 685          if (!bb->liveSet.test(i->getSrc(s)->id)) {
 686             bb->liveSet.set(i->getSrc(s)->id);
 687             addLiveRange(i->getSrc(s), bb, i->serial);
 688          }
 689       }
 690    }
 691
 692    if (bb == BasicBlock::get(func->cfg.getRoot())) {
 693       for (std::deque<ValueDef>::iterator it = func->ins.begin();
 694            it != func->ins.end(); ++it) {
 695          if (it->get()->reg.data.id >= 0) // add hazard for fixed regs
 696             it->get()->livei.extend(0, 1);
 697       }
 698    }
 699
 700    return true;
 701 }
 702
 703
 704 #define JOIN_MASK_PHI        (1 << 0)
 705 #define JOIN_MASK_UNION      (1 << 1)
 706 #define JOIN_MASK_MOV        (1 << 2)
 707 #define JOIN_MASK_TEX        (1 << 3)
 708
 709 class GCRA
 710 {
 711 public:
 712    GCRA(Function *, SpillCodeInserter&);
 713    ~GCRA();
 714
 715    bool allocateRegisters(ArrayList& insns);
 716
 717    void printNodeInfo() const;
 718
 719 private:
 720    class RIG_Node : public Graph::Node
 721    {
 722    public:
 723       RIG_Node();
 724
 725       void init(const RegisterSet&, LValue *);
 726
 727       void addInterference(RIG_Node *);
 728       void addRegPreference(RIG_Node *);
 729
 730       inline LValue *getValue() const
 731       {
 732          return reinterpret_cast<LValue *>(data);
 733       }
 734       inline void setValue(LValue *lval) { data = lval; }
 735
 736       inline uint8_t getCompMask() const
 737       {
 738          return ((1 << colors) - 1) << (reg & 7);
 739       }
 740
 741       static inline RIG_Node *get(const Graph::EdgeIterator& ei)
 742       {
 743          return static_cast<RIG_Node *>(ei.getNode());
 744       }
 745
 746    public:
 747       uint32_t degree;
 748       uint16_t degreeLimit; // if deg < degLimit, node is trivially colourable
 749       uint16_t colors;
 750
 751       DataFile f;
 752       int32_t reg;
 753
 754       float weight;
 755
 756       // list pointers for simplify() phase
 757       RIG_Node *next;
 758       RIG_Node *prev;
 759
 760       // union of the live intervals of all coalesced values (we want to retain
 761       //  the separate intervals for testing interference of compound values)
 762       Interval livei;
 763
 764       std::list<RIG_Node *> prefRegs;
 765    };
 766
 767 private:
 768    inline RIG_Node *getNode(const LValue *v) const { return &nodes[v->id]; }
 769
 770    void buildRIG(ArrayList&);
 771    bool coalesce(ArrayList&);
 772    bool doCoalesce(ArrayList&, unsigned int mask);
 773    void calculateSpillWeights();
 774    void simplify();
 775    bool selectRegisters();
 776    void cleanup(const bool success);
 777
 778    void simplifyEdge(RIG_Node *, RIG_Node *);
 779    void simplifyNode(RIG_Node *);
 780
 781    bool coalesceValues(Value *, Value *, bool force);
 782    void resolveSplitsAndMerges();
 783    void makeCompound(Instruction *, bool isSplit);
 784
 785    inline void checkInterference(const RIG_Node *, Graph::EdgeIterator&);
 786
 787    inline void insertOrderedTail(std::list<RIG_Node *>&, RIG_Node *);
 788    void checkList(std::list<RIG_Node *>&);
 789
 790 private:
 791    std::stack<uint32_t> stack;
 792
 793    // list headers for simplify() phase
 794    RIG_Node lo[2];
 795    RIG_Node hi;
 796
 797    Graph RIG;
 798    RIG_Node *nodes;
 799    unsigned int nodeCount;
 800
 801    Function *func;
 802    Program *prog;
 803
 804    static uint8_t relDegree[17][17];
 805
 806    RegisterSet regs;
 807
 808    // need to fixup register id for participants of OP_MERGE/SPLIT
 809    std::list<Instruction *> merges;
 810    std::list<Instruction *> splits;
 811
 812    SpillCodeInserter& spill;
 813    std::list<ValuePair> mustSpill;
 814 };
 815
 816 uint8_t GCRA::relDegree[17][17];
 817
 818 GCRA::RIG_Node::RIG_Node() : Node(NULL), next(this), prev(this)
 819 {
 820    colors = 0;
 821 }
 822
 823 void
 824 GCRA::printNodeInfo() const
 825 {
 826    for (unsigned int i = 0; i < nodeCount; ++i) {
 827       if (!nodes[i].colors)
 828          continue;
 829       INFO("RIG_Node[%%%i]($[%u]%i): %u colors, weight %f, deg %u/%u\n X",
 830            i,
 831            nodes[i].f,nodes[i].reg,nodes[i].colors,
 832            nodes[i].weight,
 833            nodes[i].degree, nodes[i].degreeLimit);
 834
 835       for (Graph::EdgeIterator ei = nodes[i].outgoing(); !ei.end(); ei.next())
 836          INFO(" %%%i", RIG_Node::get(ei)->getValue()->id);
 837       for (Graph::EdgeIterator ei = nodes[i].incident(); !ei.end(); ei.next())
 838          INFO(" %%%i", RIG_Node::get(ei)->getValue()->id);
 839       INFO("\n");
 840    }
 841 }
 842
 843 static bool
 844 isShortRegOp(Instruction *insn)
 845 {
 846    // Immediates are always in src1. Every other situation can be resolved by
 847    // using a long encoding.
 848    return insn->srcExists(1) && insn->src(1).getFile() == FILE_IMMEDIATE;
 849 }
 850
 851 // Check if this LValue is ever used in an instruction that can't be encoded
 852 // with long registers (i.e. > r63)
 853 static bool
 854 isShortRegVal(LValue *lval)
 855 {
 856    if (lval->getInsn() == NULL)
 857       return false;
 858    for (Value::DefCIterator def = lval->defs.begin();
 859         def != lval->defs.end(); ++def)
 860       if (isShortRegOp((*def)->getInsn()))
 861          return true;
 862    for (Value::UseCIterator use = lval->uses.begin();
 863         use != lval->uses.end(); ++use)
 864       if (isShortRegOp((*use)->getInsn()))
 865          return true;
 866    return false;
 867 }
 868
 869 void
 870 GCRA::RIG_Node::init(const RegisterSet& regs, LValue *lval)
 871 {
 872    setValue(lval);
 873    if (lval->reg.data.id >= 0)
 874       lval->noSpill = lval->fixedReg = 1;
 875
 876    colors = regs.units(lval->reg.file, lval->reg.size);
 877    f = lval->reg.file;
 878    reg = -1;
 879    if (lval->reg.data.id >= 0)
 880       reg = regs.idToUnits(lval);
 881
 882    weight = std::numeric_limits<float>::infinity();
 883    degree = 0;
 884    int size = regs.getFileSize(f, lval->reg.size);
 885    // On nv50, we lose a bit of gpr encoding when there's an embedded
 886    // immediate.
 887    if (regs.restrictedGPR16Range && f == FILE_GPR && isShortRegVal(lval))
 888       size /= 2;
 889    degreeLimit = size;
 890    degreeLimit -= relDegree[1][colors] - 1;
 891
 892    livei.insert(lval->livei);
 893 }
 894
 895 bool
 896 GCRA::coalesceValues(Value *dst, Value *src, bool force)
 897 {
 898    LValue *rep = dst->join->asLValue();
 899    LValue *val = src->join->asLValue();
 900
 901    if (!force && val->reg.data.id >= 0) {
 902       rep = src->join->asLValue();
 903       val = dst->join->asLValue();
 904    }
 905    RIG_Node *nRep = &nodes[rep->id];
 906    RIG_Node *nVal = &nodes[val->id];
 907
 908    if (src->reg.file != dst->reg.file) {
 909       if (!force)
 910          return false;
 911       WARN("forced coalescing of values in different files !\n");
 912    }
 913    if (!force && dst->reg.size != src->reg.size)
 914       return false;
 915
 916    if ((rep->reg.data.id >= 0) && (rep->reg.data.id != val->reg.data.id)) {
 917       if (force) {
 918          if (val->reg.data.id >= 0)
 919             WARN("forced coalescing of values in different fixed regs !\n");
 920       } else {
 921          if (val->reg.data.id >= 0)
 922             return false;
 923          // make sure that there is no overlap with the fixed register of rep
 924          for (ArrayList::Iterator it = func->allLValues.iterator();
 925               !it.end(); it.next()) {
 926             Value *reg = reinterpret_cast<Value *>(it.get())->asLValue();
 927             assert(reg);
 928             if (reg->interfers(rep) && reg->livei.overlaps(nVal->livei))
 929                return false;
 930          }
 931       }
 932    }
 933
 934    if (!force && nRep->livei.overlaps(nVal->livei))
 935       return false;
 936
 937    INFO_DBG(prog->dbgFlags, REG_ALLOC, "joining %%%i($%i) <- %%%i\n",
 938             rep->id, rep->reg.data.id, val->id);
 939
 940    // set join pointer of all values joined with val
 941    for (Value::DefIterator def = val->defs.begin(); def != val->defs.end();
 942         ++def)
 943       (*def)->get()->join = rep;
 944    assert(rep->join == rep && val->join == rep);
 945
 946    // add val's definitions to rep and extend the live interval of its RIG node
 947    rep->defs.insert(rep->defs.end(), val->defs.begin(), val->defs.end());
 948    nRep->livei.unify(nVal->livei);
 949    return true;
 950 }
 951
 952 bool
 953 GCRA::coalesce(ArrayList& insns)
 954 {
 955    bool ret = doCoalesce(insns, JOIN_MASK_PHI);
 956    if (!ret)
 957       return false;
 958    switch (func->getProgram()->getTarget()->getChipset() & ~0xf) {
 959    case 0x50:
 960    case 0x80:
 961    case 0x90:
 962    case 0xa0:
 963       ret = doCoalesce(insns, JOIN_MASK_UNION | JOIN_MASK_TEX);
 964       break;
 965    case 0xc0:
 966    case 0xd0:
 967    case 0xe0:
 968    case 0xf0:
 969    case 0x100:
 970    case 0x110:
 971    case 0x120:
 972       ret = doCoalesce(insns, JOIN_MASK_UNION);
 973       break;
 974    default:
 975       break;
 976    }
 977    if (!ret)
 978       return false;
 979    return doCoalesce(insns, JOIN_MASK_MOV);
 980 }
 981
 982 static inline uint8_t makeCompMask(int compSize, int base, int size)
 983 {
 984    uint8_t m = ((1 << size) - 1) << base;
 985
 986    switch (compSize) {
 987    case 1:
 988       return 0xff;
 989    case 2:
 990       m |= (m << 2);
 991       return (m << 4) | m;
 992    case 3:
 993    case 4:
 994       return (m << 4) | m;
 995    default:
 996       assert(compSize <= 8);
 997       return m;
 998    }
 999 }
1000
1001 // Used when coalescing moves. The non-compound value will become one, e.g.:
1002 // mov b32 $r0 $r2            / merge b64 $r0d { $r0 $r1 }
1003 // split b64 { $r0 $r1 } $r0d / mov b64 $r0d f64 $r2d
1004 static inline void copyCompound(Value *dst, Value *src)
1005 {
1006    LValue *ldst = dst->asLValue();
1007    LValue *lsrc = src->asLValue();
1008
1009    if (ldst->compound && !lsrc->compound) {
1010       LValue *swap = lsrc;
1011       lsrc = ldst;
1012       ldst = swap;
1013    }
1014
1015    ldst->compound = lsrc->compound;
1016    ldst->compMask = lsrc->compMask;
1017 }
1018
1019 void
1020 GCRA::makeCompound(Instruction *insn, bool split)
1021 {
1022    LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue();
1023
1024    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
1025       INFO("makeCompound(split = %i): ", split);
1026       insn->print();
1027    }
1028
1029    const unsigned int size = getNode(rep)->colors;
1030    unsigned int base = 0;
1031
1032    if (!rep->compound)
1033       rep->compMask = 0xff;
1034    rep->compound = 1;
1035
1036    for (int c = 0; split ? insn->defExists(c) : insn->srcExists(c); ++c) {
1037       LValue *val = (split ? insn->getDef(c) : insn->getSrc(c))->asLValue();
1038
1039       val->compound = 1;
1040       if (!val->compMask)
1041          val->compMask = 0xff;
1042       val->compMask &= makeCompMask(size, base, getNode(val)->colors);
1043       assert(val->compMask);
1044
1045       INFO_DBG(prog->dbgFlags, REG_ALLOC, "compound: %%%i:%02x <- %%%i:%02x\n",
1046            rep->id, rep->compMask, val->id, val->compMask);
1047
1048       base += getNode(val)->colors;
1049    }
1050    assert(base == size);
1051 }
1052
1053 bool
1054 GCRA::doCoalesce(ArrayList& insns, unsigned int mask)
1055 {
1056    int c, n;
1057
1058    for (n = 0; n < insns.getSize(); ++n) {
1059       Instruction *i;
1060       Instruction *insn = reinterpret_cast<Instruction *>(insns.get(n));
1061
1062       switch (insn->op) {
1063       case OP_PHI:
1064          if (!(mask & JOIN_MASK_PHI))
1065             break;
1066          for (c = 0; insn->srcExists(c); ++c)
1067             if (!coalesceValues(insn->getDef(0), insn->getSrc(c), false)) {
1068                // this is bad
1069                ERROR("failed to coalesce phi operands\n");
1070                return false;
1071             }
1072          break;
1073       case OP_UNION:
1074       case OP_MERGE:
1075          if (!(mask & JOIN_MASK_UNION))
1076             break;
1077          for (c = 0; insn->srcExists(c); ++c)
1078             coalesceValues(insn->getDef(0), insn->getSrc(c), true);
1079          if (insn->op == OP_MERGE) {
1080             merges.push_back(insn);
1081             if (insn->srcExists(1))
1082                makeCompound(insn, false);
1083          }
1084          break;
1085       case OP_SPLIT:
1086          if (!(mask & JOIN_MASK_UNION))
1087             break;
1088          splits.push_back(insn);
1089          for (c = 0; insn->defExists(c); ++c)
1090             coalesceValues(insn->getSrc(0), insn->getDef(c), true);
1091          makeCompound(insn, true);
1092          break;
1093       case OP_MOV:
1094          if (!(mask & JOIN_MASK_MOV))
1095             break;
1096          i = NULL;
1097          if (!insn->getDef(0)->uses.empty())
1098             i = (*insn->getDef(0)->uses.begin())->getInsn();
1099          // if this is a contraint-move there will only be a single use
1100          if (i && i->op == OP_MERGE) // do we really still need this ?
1101             break;
1102          i = insn->getSrc(0)->getUniqueInsn();
1103          if (i && !i->constrainedDefs()) {
1104             if (coalesceValues(insn->getDef(0), insn->getSrc(0), false))
1105                copyCompound(insn->getSrc(0), insn->getDef(0));
1106          }
1107          break;
1108       case OP_TEX:
1109       case OP_TXB:
1110       case OP_TXL:
1111       case OP_TXF:
1112       case OP_TXQ:
1113       case OP_TXD:
1114       case OP_TXG:
1115       case OP_TXLQ:
1116       case OP_TEXCSAA:
1117       case OP_TEXPREP:
1118          if (!(mask & JOIN_MASK_TEX))
1119             break;
1120          for (c = 0; insn->srcExists(c) && c != insn->predSrc; ++c)
1121             coalesceValues(insn->getDef(c), insn->getSrc(c), true);
1122          break;
1123       default:
1124          break;
1125       }
1126    }
1127    return true;
1128 }
1129
1130 void
1131 GCRA::RIG_Node::addInterference(RIG_Node *node)
1132 {
1133    this->degree += relDegree[node->colors][colors];
1134    node->degree += relDegree[colors][node->colors];
1135
1136    this->attach(node, Graph::Edge::CROSS);
1137 }
1138
1139 void
1140 GCRA::RIG_Node::addRegPreference(RIG_Node *node)
1141 {
1142    prefRegs.push_back(node);
1143 }
1144
1145 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) :
1146    func(fn),
1147    regs(fn->getProgram()->getTarget()),
1148    spill(spill)
1149 {
1150    prog = func->getProgram();
1151
1152    // initialize relative degrees array - i takes away from j
1153    for (int i = 1; i <= 16; ++i)
1154       for (int j = 1; j <= 16; ++j)
1155          relDegree[i][j] = j * ((i + j - 1) / j);
1156 }
1157
1158 GCRA::~GCRA()
1159 {
1160    if (nodes)
1161       delete[] nodes;
1162 }
1163
1164 void
1165 GCRA::checkList(std::list<RIG_Node *>& lst)
1166 {
1167    GCRA::RIG_Node *prev = NULL;
1168
1169    for (std::list<RIG_Node *>::iterator it = lst.begin();
1170         it != lst.end();
1171         ++it) {
1172       assert((*it)->getValue()->join == (*it)->getValue());
1173       if (prev)
1174          assert(prev->livei.begin() <= (*it)->livei.begin());
1175       prev = *it;
1176    }
1177 }
1178
1179 void
1180 GCRA::insertOrderedTail(std::list<RIG_Node *>& list, RIG_Node *node)
1181 {
1182    if (node->livei.isEmpty())
1183       return;
1184    // only the intervals of joined values don't necessarily arrive in order
1185    std::list<RIG_Node *>::iterator prev, it;
1186    for (it = list.end(); it != list.begin(); it = prev) {
1187       prev = it;
1188       --prev;
1189       if ((*prev)->livei.begin() <= node->livei.begin())
1190          break;
1191    }
1192    list.insert(it, node);
1193 }
1194
1195 void
1196 GCRA::buildRIG(ArrayList& insns)
1197 {
1198    std::list<RIG_Node *> values, active;
1199
1200    for (std::deque<ValueDef>::iterator it = func->ins.begin();
1201         it != func->ins.end(); ++it)
1202       insertOrderedTail(values, getNode(it->get()->asLValue()));
1203
1204    for (int i = 0; i < insns.getSize(); ++i) {
1205       Instruction *insn = reinterpret_cast<Instruction *>(insns.get(i));
1206       for (int d = 0; insn->defExists(d); ++d)
1207          if (insn->getDef(d)->rep() == insn->getDef(d))
1208             insertOrderedTail(values, getNode(insn->getDef(d)->asLValue()));
1209    }
1210    checkList(values);
1211
1212    while (!values.empty()) {
1213       RIG_Node *cur = values.front();
1214
1215       for (std::list<RIG_Node *>::iterator it = active.begin();
1216            it != active.end();) {
1217          RIG_Node *node = *it;
1218
1219          if (node->livei.end() <= cur->livei.begin()) {
1220             it = active.erase(it);
1221          } else {
1222             if (node->f == cur->f && node->livei.overlaps(cur->livei))
1223                cur->addInterference(node);
1224             ++it;
1225          }
1226       }
1227       values.pop_front();
1228       active.push_back(cur);
1229    }
1230 }
1231
1232 void
1233 GCRA::calculateSpillWeights()
1234 {
1235    for (unsigned int i = 0; i < nodeCount; ++i) {
1236       RIG_Node *const n = &nodes[i];
1237       if (!nodes[i].colors || nodes[i].livei.isEmpty())
1238          continue;
1239       if (nodes[i].reg >= 0) {
1240          // update max reg
1241          regs.occupy(n->f, n->reg, n->colors);
1242          continue;
1243       }
1244       LValue *val = nodes[i].getValue();
1245
1246       if (!val->noSpill) {
1247          int rc = 0;
1248          for (Value::DefIterator it = val->defs.begin();
1249               it != val->defs.end();
1250               ++it)
1251             rc += (*it)->get()->refCount();
1252
1253          nodes[i].weight =
1254             (float)rc * (float)rc / (float)nodes[i].livei.extent();
1255       }
1256
1257       if (nodes[i].degree < nodes[i].degreeLimit) {
1258          int l = 0;
1259          if (val->reg.size > 4)
1260             l = 1;
1261          DLLIST_ADDHEAD(&lo[l], &nodes[i]);
1262       } else {
1263          DLLIST_ADDHEAD(&hi, &nodes[i]);
1264       }
1265    }
1266    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1267       printNodeInfo();
1268 }
1269
1270 void
1271 GCRA::simplifyEdge(RIG_Node *a, RIG_Node *b)
1272 {
1273    bool move = b->degree >= b->degreeLimit;
1274
1275    INFO_DBG(prog->dbgFlags, REG_ALLOC,
1276             "edge: (%%%i, deg %u/%u) >-< (%%%i, deg %u/%u)\n",
1277             a->getValue()->id, a->degree, a->degreeLimit,
1278             b->getValue()->id, b->degree, b->degreeLimit);
1279
1280    b->degree -= relDegree[a->colors][b->colors];
1281
1282    move = move && b->degree < b->degreeLimit;
1283    if (move && !DLLIST_EMPTY(b)) {
1284       int l = (b->getValue()->reg.size > 4) ? 1 : 0;
1285       DLLIST_DEL(b);
1286       DLLIST_ADDTAIL(&lo[l], b);
1287    }
1288 }
1289
1290 void
1291 GCRA::simplifyNode(RIG_Node *node)
1292 {
1293    for (Graph::EdgeIterator ei = node->outgoing(); !ei.end(); ei.next())
1294       simplifyEdge(node, RIG_Node::get(ei));
1295
1296    for (Graph::EdgeIterator ei = node->incident(); !ei.end(); ei.next())
1297       simplifyEdge(node, RIG_Node::get(ei));
1298
1299    DLLIST_DEL(node);
1300    stack.push(node->getValue()->id);
1301
1302    INFO_DBG(prog->dbgFlags, REG_ALLOC, "SIMPLIFY: pushed %%%i%s\n",
1303             node->getValue()->id,
1304             (node->degree < node->degreeLimit) ? "" : "(spill)");
1305 }
1306
1307 void
1308 GCRA::simplify()
1309 {
1310    for (;;) {
1311       if (!DLLIST_EMPTY(&lo[0])) {
1312          do {
1313             simplifyNode(lo[0].next);
1314          } while (!DLLIST_EMPTY(&lo[0]));
1315       } else
1316       if (!DLLIST_EMPTY(&lo[1])) {
1317          simplifyNode(lo[1].next);
1318       } else
1319       if (!DLLIST_EMPTY(&hi)) {
1320          RIG_Node *best = hi.next;
1321          float bestScore = best->weight / (float)best->degree;
1322          // spill candidate
1323          for (RIG_Node *it = best->next; it != &hi; it = it->next) {
1324             float score = it->weight / (float)it->degree;
1325             if (score < bestScore) {
1326                best = it;
1327                bestScore = score;
1328             }
1329          }
1330          if (isinf(bestScore)) {
1331             ERROR("no viable spill candidates left\n");
1332             break;
1333          }
1334          simplifyNode(best);
1335       } else {
1336          break;
1337       }
1338    }
1339 }
1340
1341 void
1342 GCRA::checkInterference(const RIG_Node *node, Graph::EdgeIterator& ei)
1343 {
1344    const RIG_Node *intf = RIG_Node::get(ei);
1345
1346    if (intf->reg < 0)
1347       return;
1348    const LValue *vA = node->getValue();
1349    const LValue *vB = intf->getValue();
1350
1351    const uint8_t intfMask = ((1 << intf->colors) - 1) << (intf->reg & 7);
1352
1353    if (vA->compound | vB->compound) {
1354       // NOTE: this only works for >aligned< register tuples !
1355       for (Value::DefCIterator D = vA->defs.begin(); D != vA->defs.end(); ++D) {
1356       for (Value::DefCIterator d = vB->defs.begin(); d != vB->defs.end(); ++d) {
1357          const LValue *vD = (*D)->get()->asLValue();
1358          const LValue *vd = (*d)->get()->asLValue();
1359
1360          if (!vD->livei.overlaps(vd->livei)) {
1361             INFO_DBG(prog->dbgFlags, REG_ALLOC, "(%%%i) X (%%%i): no overlap\n",
1362                      vD->id, vd->id);
1363             continue;
1364          }
1365
1366          uint8_t mask = vD->compound ? vD->compMask : ~0;
1367          if (vd->compound) {
1368             assert(vB->compound);
1369             mask &= vd->compMask & vB->compMask;
1370          } else {
1371             mask &= intfMask;
1372          }
1373
1374          INFO_DBG(prog->dbgFlags, REG_ALLOC,
1375                   "(%%%i)%02x X (%%%i)%02x & %02x: $r%i.%02x\n",
1376                   vD->id,
1377                   vD->compound ? vD->compMask : 0xff,
1378                   vd->id,
1379                   vd->compound ? vd->compMask : intfMask,
1380                   vB->compMask, intf->reg & ~7, mask);
1381          if (mask)
1382             regs.occupyMask(node->f, intf->reg & ~7, mask);
1383       }
1384       }
1385    } else {
1386       INFO_DBG(prog->dbgFlags, REG_ALLOC,
1387                "(%%%i) X (%%%i): $r%i + %u\n",
1388                vA->id, vB->id, intf->reg, intf->colors);
1389       regs.occupy(node->f, intf->reg, intf->colors);
1390    }
1391 }
1392
1393 bool
1394 GCRA::selectRegisters()
1395 {
1396    INFO_DBG(prog->dbgFlags, REG_ALLOC, "\nSELECT phase\n");
1397
1398    while (!stack.empty()) {
1399       RIG_Node *node = &nodes[stack.top()];
1400       stack.pop();
1401
1402       regs.reset(node->f);
1403
1404       INFO_DBG(prog->dbgFlags, REG_ALLOC, "\nNODE[%%%i, %u colors]\n",
1405                node->getValue()->id, node->colors);
1406
1407       for (Graph::EdgeIterator ei = node->outgoing(); !ei.end(); ei.next())
1408          checkInterference(node, ei);
1409       for (Graph::EdgeIterator ei = node->incident(); !ei.end(); ei.next())
1410          checkInterference(node, ei);
1411
1412       if (!node->prefRegs.empty()) {
1413          for (std::list<RIG_Node *>::const_iterator it = node->prefRegs.begin();
1414               it != node->prefRegs.end();
1415               ++it) {
1416             if ((*it)->reg >= 0 &&
1417                 regs.testOccupy(node->f, (*it)->reg, node->colors)) {
1418                node->reg = (*it)->reg;
1419                break;
1420             }
1421          }
1422       }
1423       if (node->reg >= 0)
1424          continue;
1425       LValue *lval = node->getValue();
1426       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1427          regs.print();
1428       bool ret = regs.assign(node->reg, node->f, node->colors);
1429       if (ret) {
1430          INFO_DBG(prog->dbgFlags, REG_ALLOC, "assigned reg %i\n", node->reg);
1431          lval->compMask = node->getCompMask();
1432       } else {
1433          INFO_DBG(prog->dbgFlags, REG_ALLOC, "must spill: %%%i (size %u)\n",
1434                   lval->id, lval->reg.size);
1435          Symbol *slot = NULL;
1436          if (lval->reg.file == FILE_GPR)
1437             slot = spill.assignSlot(node->livei, lval->reg.size);
1438          mustSpill.push_back(ValuePair(lval, slot));
1439       }
1440    }
1441    if (!mustSpill.empty())
1442       return false;
1443    for (unsigned int i = 0; i < nodeCount; ++i) {
1444       LValue *lval = nodes[i].getValue();
1445       if (nodes[i].reg >= 0 && nodes[i].colors > 0)
1446          lval->reg.data.id =
1447             regs.unitsToId(nodes[i].f, nodes[i].reg, lval->reg.size);
1448    }
1449    return true;
1450 }
1451
1452 bool
1453 GCRA::allocateRegisters(ArrayList& insns)
1454 {
1455    bool ret;
1456
1457    INFO_DBG(prog->dbgFlags, REG_ALLOC,
1458             "allocateRegisters to %u instructions\n", insns.getSize());
1459
1460    nodeCount = func->allLValues.getSize();
1461    nodes = new RIG_Node[nodeCount];
1462    if (!nodes)
1463       return false;
1464    for (unsigned int i = 0; i < nodeCount; ++i) {
1465       LValue *lval = reinterpret_cast<LValue *>(func->allLValues.get(i));
1466       if (lval) {
1467          nodes[i].init(regs, lval);
1468          RIG.insert(&nodes[i]);
1469
1470          if (lval->inFile(FILE_GPR) && lval->getInsn() != NULL &&
1471              prog->getTarget()->getChipset() < 0xc0) {
1472             Instruction *insn = lval->getInsn();
1473             if (insn->op == OP_MAD || insn->op == OP_SAD)
1474                // Short encoding only possible if they're all GPRs, no need to
1475                // affect them otherwise.
1476                if (insn->flagsDef < 0 &&
1477                    insn->src(0).getFile() == FILE_GPR &&
1478                    insn->src(1).getFile() == FILE_GPR &&
1479                    insn->src(2).getFile() == FILE_GPR)
1480                   nodes[i].addRegPreference(getNode(insn->getSrc(2)->asLValue()));
1481          }
1482       }
1483    }
1484
1485    // coalesce first, we use only 1 RIG node for a group of joined values
1486    ret = coalesce(insns);
1487    if (!ret)
1488       goto out;
1489
1490    if (func->getProgram()->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1491       func->printLiveIntervals();
1492
1493    buildRIG(insns);
1494    calculateSpillWeights();
1495    simplify();
1496
1497    ret = selectRegisters();
1498    if (!ret) {
1499       INFO_DBG(prog->dbgFlags, REG_ALLOC,
1500                "selectRegisters failed, inserting spill code ...\n");
1501       regs.reset(FILE_GPR, true);
1502       spill.run(mustSpill);
1503       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1504          func->print();
1505    } else {
1506       prog->maxGPR = std::max(prog->maxGPR, regs.getMaxAssigned(FILE_GPR));
1507    }
1508
1509 out:
1510    cleanup(ret);
1511    return ret;
1512 }
1513
1514 void
1515 GCRA::cleanup(const bool success)
1516 {
1517    mustSpill.clear();
1518
1519    for (ArrayList::Iterator it = func->allLValues.iterator();
1520         !it.end(); it.next()) {
1521       LValue *lval =  reinterpret_cast<LValue *>(it.get());
1522
1523       lval->livei.clear();
1524
1525       lval->compound = 0;
1526       lval->compMask = 0;
1527
1528       if (lval->join == lval)
1529          continue;
1530
1531       if (success) {
1532          lval->reg.data.id = lval->join->reg.data.id;
1533       } else {
1534          for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
1535               ++d)
1536             lval->join->defs.remove(*d);
1537          lval->join = lval;
1538       }
1539    }
1540
1541    if (success)
1542       resolveSplitsAndMerges();
1543    splits.clear(); // avoid duplicate entries on next coalesce pass
1544    merges.clear();
1545
1546    delete[] nodes;
1547    nodes = NULL;
1548    hi.next = hi.prev = &hi;
1549    lo[0].next = lo[0].prev = &lo[0];
1550    lo[1].next = lo[1].prev = &lo[1];
1551 }
1552
1553 Symbol *
1554 SpillCodeInserter::assignSlot(const Interval &livei, const unsigned int size)
1555 {
1556    SpillSlot slot;
1557    int32_t offsetBase = stackSize;
1558    int32_t offset;
1559    std::list<SpillSlot>::iterator pos = slots.end(), it = slots.begin();
1560
1561    if (offsetBase % size)
1562       offsetBase += size - (offsetBase % size);
1563
1564    slot.sym = NULL;
1565
1566    for (offset = offsetBase; offset < stackSize; offset += size) {
1567       const int32_t entryEnd = offset + size;
1568       while (it != slots.end() && it->offset < offset)
1569          ++it;
1570       if (it == slots.end()) // no slots left
1571          break;
1572       std::list<SpillSlot>::iterator bgn = it;
1573
1574       while (it != slots.end() && it->offset < entryEnd) {
1575          it->occup.print();
1576          if (it->occup.overlaps(livei))
1577             break;
1578          ++it;
1579       }
1580       if (it == slots.end() || it->offset >= entryEnd) {
1581          // fits
1582          for (; bgn != slots.end() && bgn->offset < entryEnd; ++bgn) {
1583             bgn->occup.insert(livei);
1584             if (bgn->size() == size)
1585                slot.sym = bgn->sym;
1586          }
1587          break;
1588       }
1589    }
1590    if (!slot.sym) {
1591       stackSize = offset + size;
1592       slot.offset = offset;
1593       slot.sym = new_Symbol(func->getProgram(), FILE_MEMORY_LOCAL);
1594       if (!func->stackPtr)
1595          offset += func->tlsBase;
1596       slot.sym->setAddress(NULL, offset);
1597       slot.sym->reg.size = size;
1598       slots.insert(pos, slot)->occup.insert(livei);
1599    }
1600    return slot.sym;
1601 }
1602
1603 Value *
1604 SpillCodeInserter::offsetSlot(Value *base, const LValue *lval)
1605 {
1606    if (!lval->compound || (lval->compMask & 0x1))
1607       return base;
1608    Value *slot = cloneShallow(func, base);
1609
1610    slot->reg.data.offset += (ffs(lval->compMask) - 1) * lval->reg.size;
1611    slot->reg.size = lval->reg.size;
1612
1613    return slot;
1614 }
1615
1616 void
1617 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval)
1618 {
1619    const DataType ty = typeOfSize(lval->reg.size);
1620
1621    slot = offsetSlot(slot, lval);
1622
1623    Instruction *st;
1624    if (slot->reg.file == FILE_MEMORY_LOCAL) {
1625       lval->noSpill = 1;
1626       if (ty != TYPE_B96) {
1627          st = new_Instruction(func, OP_STORE, ty);
1628          st->setSrc(0, slot);
1629          st->setSrc(1, lval);
1630       } else {
1631          st = new_Instruction(func, OP_SPLIT, ty);
1632          st->setSrc(0, lval);
1633          for (int d = 0; d < lval->reg.size / 4; ++d)
1634             st->setDef(d, new_LValue(func, FILE_GPR));
1635
1636          for (int d = lval->reg.size / 4 - 1; d >= 0; --d) {
1637             Value *tmp = cloneShallow(func, slot);
1638             tmp->reg.size = 4;
1639             tmp->reg.data.offset += 4 * d;
1640
1641             Instruction *s = new_Instruction(func, OP_STORE, TYPE_U32);
1642             s->setSrc(0, tmp);
1643             s->setSrc(1, st->getDef(d));
1644             defi->bb->insertAfter(defi, s);
1645          }
1646       }
1647    } else {
1648       st = new_Instruction(func, OP_CVT, ty);
1649       st->setDef(0, slot);
1650       st->setSrc(0, lval);
1651       if (lval->reg.file == FILE_FLAGS)
1652          st->flagsSrc = 0;
1653    }
1654    defi->bb->insertAfter(defi, st);
1655 }
1656
1657 LValue *
1658 SpillCodeInserter::unspill(Instruction *usei, LValue *lval, Value *slot)
1659 {
1660    const DataType ty = typeOfSize(lval->reg.size);
1661
1662    slot = offsetSlot(slot, lval);
1663    lval = cloneShallow(func, lval);
1664
1665    Instruction *ld;
1666    if (slot->reg.file == FILE_MEMORY_LOCAL) {
1667       lval->noSpill = 1;
1668       if (ty != TYPE_B96) {
1669          ld = new_Instruction(func, OP_LOAD, ty);
1670       } else {
1671          ld = new_Instruction(func, OP_MERGE, ty);
1672          for (int d = 0; d < lval->reg.size / 4; ++d) {
1673             Value *tmp = cloneShallow(func, slot);
1674             LValue *val;
1675             tmp->reg.size = 4;
1676             tmp->reg.data.offset += 4 * d;
1677
1678             Instruction *l = new_Instruction(func, OP_LOAD, TYPE_U32);
1679             l->setDef(0, (val = new_LValue(func, FILE_GPR)));
1680             l->setSrc(0, tmp);
1681             usei->bb->insertBefore(usei, l);
1682             ld->setSrc(d, val);
1683             val->noSpill = 1;
1684          }
1685          ld->setDef(0, lval);
1686          usei->bb->insertBefore(usei, ld);
1687          return lval;
1688       }
1689    } else {
1690       ld = new_Instruction(func, OP_CVT, ty);
1691    }
1692    ld->setDef(0, lval);
1693    ld->setSrc(0, slot);
1694    if (lval->reg.file == FILE_FLAGS)
1695       ld->flagsDef = 0;
1696
1697    usei->bb->insertBefore(usei, ld);
1698    return lval;
1699 }
1700
1701 static bool
1702 value_cmp(ValueRef *a, ValueRef *b) {
1703    Instruction *ai = a->getInsn(), *bi = b->getInsn();
1704    if (ai->bb != bi->bb)
1705       return ai->bb->getId() < bi->bb->getId();
1706    return ai->serial < bi->serial;
1707 }
1708
1709 // For each value that is to be spilled, go through all its definitions.
1710 // A value can have multiple definitions if it has been coalesced before.
1711 // For each definition, first go through all its uses and insert an unspill
1712 // instruction before it, then replace the use with the temporary register.
1713 // Unspill can be either a load from memory or simply a move to another
1714 // register file.
1715 // For "Pseudo" instructions (like PHI, SPLIT, MERGE) we can erase the use
1716 // if we have spilled to a memory location, or simply with the new register.
1717 // No load or conversion instruction should be needed.
1718 bool
1719 SpillCodeInserter::run(const std::list<ValuePair>& lst)
1720 {
1721    for (std::list<ValuePair>::const_iterator it = lst.begin(); it != lst.end();
1722         ++it) {
1723       LValue *lval = it->first->asLValue();
1724       Symbol *mem = it->second ? it->second->asSym() : NULL;
1725
1726       // Keep track of which instructions to delete later. Deleting them
1727       // inside the loop is unsafe since a single instruction may have
1728       // multiple destinations that all need to be spilled (like OP_SPLIT).
1729       unordered_set<Instruction *> to_del;
1730
1731       for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
1732            ++d) {
1733          Value *slot = mem ?
1734             static_cast<Value *>(mem) : new_LValue(func, FILE_GPR);
1735          Value *tmp = NULL;
1736          Instruction *last = NULL;
1737
1738          LValue *dval = (*d)->get()->asLValue();
1739          Instruction *defi = (*d)->getInsn();
1740
1741          // Sort all the uses by BB/instruction so that we don't unspill
1742          // multiple times in a row, and also remove a source of
1743          // non-determinism.
1744          std::vector<ValueRef *> refs(dval->uses.begin(), dval->uses.end());
1745          std::sort(refs.begin(), refs.end(), value_cmp);
1746
1747          // Unspill at each use *before* inserting spill instructions,
1748          // we don't want to have the spill instructions in the use list here.
1749          for (std::vector<ValueRef*>::const_iterator it = refs.begin();
1750               it != refs.end(); ++it) {
1751             ValueRef *u = *it;
1752             Instruction *usei = u->getInsn();
1753             assert(usei);
1754             if (usei->isPseudo()) {
1755                tmp = (slot->reg.file == FILE_MEMORY_LOCAL) ? NULL : slot;
1756                last = NULL;
1757             } else {
1758                if (!last || (usei != last->next && usei != last))
1759                   tmp = unspill(usei, dval, slot);
1760                last = usei;
1761             }
1762             u->set(tmp);
1763          }
1764
1765          assert(defi);
1766          if (defi->isPseudo()) {
1767             d = lval->defs.erase(d);
1768             --d;
1769             if (slot->reg.file == FILE_MEMORY_LOCAL)
1770                to_del.insert(defi);
1771             else
1772                defi->setDef(0, slot);
1773          } else {
1774             spill(defi, slot, dval);
1775          }
1776       }
1777
1778       for (unordered_set<Instruction *>::const_iterator it = to_del.begin();
1779            it != to_del.end(); ++it)
1780          delete_Instruction(func->getProgram(), *it);
1781    }
1782
1783    // TODO: We're not trying to reuse old slots in a potential next iteration.
1784    //  We have to update the slots' livei intervals to be able to do that.
1785    stackBase = stackSize;
1786    slots.clear();
1787    return true;
1788 }
1789
1790 bool
1791 RegAlloc::exec()
1792 {
1793    for (IteratorRef it = prog->calls.iteratorDFS(false);
1794         !it->end(); it->next()) {
1795       func = Function::get(reinterpret_cast<Graph::Node *>(it->get()));
1796
1797       func->tlsBase = prog->tlsSize;
1798       if (!execFunc())
1799          return false;
1800       prog->tlsSize += func->tlsSize;
1801    }
1802    return true;
1803 }
1804
1805 bool
1806 RegAlloc::execFunc()
1807 {
1808    InsertConstraintsPass insertConstr;
1809    PhiMovesPass insertPhiMoves;
1810    ArgumentMovesPass insertArgMoves;
1811    BuildIntervalsPass buildIntervals;
1812    SpillCodeInserter insertSpills(func);
1813
1814    GCRA gcra(func, insertSpills);
1815
1816    unsigned int i, retries;
1817    bool ret;
1818
1819    if (!func->ins.empty()) {
1820       // Insert a nop at the entry so inputs only used by the first instruction
1821       // don't count as having an empty live range.
1822       Instruction *nop = new_Instruction(func, OP_NOP, TYPE_NONE);
1823       BasicBlock::get(func->cfg.getRoot())->insertHead(nop);
1824    }
1825
1826    ret = insertConstr.exec(func);
1827    if (!ret)
1828       goto out;
1829
1830    ret = insertPhiMoves.run(func);
1831    if (!ret)
1832       goto out;
1833
1834    ret = insertArgMoves.run(func);
1835    if (!ret)
1836       goto out;
1837
1838    // TODO: need to fix up spill slot usage ranges to support > 1 retry
1839    for (retries = 0; retries < 3; ++retries) {
1840       if (retries && (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC))
1841          INFO("Retry: %i\n", retries);
1842       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1843          func->print();
1844
1845       // spilling to registers may add live ranges, need to rebuild everything
1846       ret = true;
1847       for (sequence = func->cfg.nextSequence(), i = 0;
1848            ret && i <= func->loopNestingBound;
1849            sequence = func->cfg.nextSequence(), ++i)
1850          ret = buildLiveSets(BasicBlock::get(func->cfg.getRoot()));
1851       // reset marker
1852       for (ArrayList::Iterator bi = func->allBBlocks.iterator();
1853            !bi.end(); bi.next())
1854          BasicBlock::get(bi)->liveSet.marker = false;
1855       if (!ret)
1856          break;
1857       func->orderInstructions(this->insns);
1858
1859       ret = buildIntervals.run(func);
1860       if (!ret)
1861          break;
1862       ret = gcra.allocateRegisters(insns);
1863       if (ret)
1864          break; // success
1865    }
1866    INFO_DBG(prog->dbgFlags, REG_ALLOC, "RegAlloc done: %i\n", ret);
1867
1868    func->tlsSize = insertSpills.getStackSize();
1869 out:
1870    return ret;
1871 }
1872
1873 // TODO: check if modifying Instruction::join here breaks anything
1874 void
1875 GCRA::resolveSplitsAndMerges()
1876 {
1877    for (std::list<Instruction *>::iterator it = splits.begin();
1878         it != splits.end();
1879         ++it) {
1880       Instruction *split = *it;
1881       unsigned int reg = regs.idToBytes(split->getSrc(0));
1882       for (int d = 0; split->defExists(d); ++d) {
1883          Value *v = split->getDef(d);
1884          v->reg.data.id = regs.bytesToId(v, reg);
1885          v->join = v;
1886          reg += v->reg.size;
1887       }
1888    }
1889    splits.clear();
1890
1891    for (std::list<Instruction *>::iterator it = merges.begin();
1892         it != merges.end();
1893         ++it) {
1894       Instruction *merge = *it;
1895       unsigned int reg = regs.idToBytes(merge->getDef(0));
1896       for (int s = 0; merge->srcExists(s); ++s) {
1897          Value *v = merge->getSrc(s);
1898          v->reg.data.id = regs.bytesToId(v, reg);
1899          v->join = v;
1900          // If the value is defined by a phi/union node, we also need to
1901          // perform the same fixup on that node's sources, since after RA
1902          // their registers should be identical.
1903          if (v->getInsn()->op == OP_PHI || v->getInsn()->op == OP_UNION) {
1904             Instruction *phi = v->getInsn();
1905             for (int phis = 0; phi->srcExists(phis); ++phis)
1906                phi->getSrc(phis)->join = v;
1907          }
1908          reg += v->reg.size;
1909       }
1910    }
1911    merges.clear();
1912 }
1913
1914 bool Program::registerAllocation()
1915 {
1916    RegAlloc ra(this);
1917    return ra.exec();
1918 }
1919
1920 bool
1921 RegAlloc::InsertConstraintsPass::exec(Function *ir)
1922 {
1923    constrList.clear();
1924
1925    bool ret = run(ir, true, true);
1926    if (ret)
1927       ret = insertConstraintMoves();
1928    return ret;
1929 }
1930
1931 // TODO: make part of texture insn
1932 void
1933 RegAlloc::InsertConstraintsPass::textureMask(TexInstruction *tex)
1934 {
1935    Value *def[4];
1936    int c, k, d;
1937    uint8_t mask = 0;
1938
1939    for (d = 0, k = 0, c = 0; c < 4; ++c) {
1940       if (!(tex->tex.mask & (1 << c)))
1941          continue;
1942       if (tex->getDef(k)->refCount()) {
1943          mask |= 1 << c;
1944          def[d++] = tex->getDef(k);
1945       }
1946       ++k;
1947    }
1948    tex->tex.mask = mask;
1949
1950    for (c = 0; c < d; ++c)
1951       tex->setDef(c, def[c]);
1952    for (; c < 4; ++c)
1953       tex->setDef(c, NULL);
1954 }
1955
1956 bool
1957 RegAlloc::InsertConstraintsPass::detectConflict(Instruction *cst, int s)
1958 {
1959    Value *v = cst->getSrc(s);
1960
1961    // current register allocation can't handle it if a value participates in
1962    // multiple constraints
1963    for (Value::UseIterator it = v->uses.begin(); it != v->uses.end(); ++it) {
1964       if (cst != (*it)->getInsn())
1965          return true;
1966    }
1967
1968    // can start at s + 1 because detectConflict is called on all sources
1969    for (int c = s + 1; cst->srcExists(c); ++c)
1970       if (v == cst->getSrc(c))
1971          return true;
1972
1973    Instruction *defi = v->getInsn();
1974
1975    return (!defi || defi->constrainedDefs());
1976 }
1977
1978 void
1979 RegAlloc::InsertConstraintsPass::addConstraint(Instruction *i, int s, int n)
1980 {
1981    Instruction *cst;
1982    int d;
1983
1984    // first, look for an existing identical constraint op
1985    for (std::list<Instruction *>::iterator it = constrList.begin();
1986         it != constrList.end();
1987         ++it) {
1988       cst = (*it);
1989       if (!i->bb->dominatedBy(cst->bb))
1990          break;
1991       for (d = 0; d < n; ++d)
1992          if (cst->getSrc(d) != i->getSrc(d + s))
1993             break;
1994       if (d >= n) {
1995          for (d = 0; d < n; ++d, ++s)
1996             i->setSrc(s, cst->getDef(d));
1997          return;
1998       }
1999    }
2000    cst = new_Instruction(func, OP_CONSTRAINT, i->dType);
2001
2002    for (d = 0; d < n; ++s, ++d) {
2003       cst->setDef(d, new_LValue(func, FILE_GPR));
2004       cst->setSrc(d, i->getSrc(s));
2005       i->setSrc(s, cst->getDef(d));
2006    }
2007    i->bb->insertBefore(i, cst);
2008
2009    constrList.push_back(cst);
2010 }
2011
2012 // Add a dummy use of the pointer source of >= 8 byte loads after the load
2013 // to prevent it from being assigned a register which overlapping the load's
2014 // destination, which would produce random corruptions.
2015 void
2016 RegAlloc::InsertConstraintsPass::addHazard(Instruction *i, const ValueRef *src)
2017 {
2018    Instruction *hzd = new_Instruction(func, OP_NOP, TYPE_NONE);
2019    hzd->setSrc(0, src->get());
2020    i->bb->insertAfter(i, hzd);
2021
2022 }
2023
2024 // b32 { %r0 %r1 %r2 %r3 } -> b128 %r0q
2025 void
2026 RegAlloc::InsertConstraintsPass::condenseDefs(Instruction *insn)
2027 {
2028    uint8_t size = 0;
2029    int n;
2030    for (n = 0; insn->defExists(n) && insn->def(n).getFile() == FILE_GPR; ++n)
2031       size += insn->getDef(n)->reg.size;
2032    if (n < 2)
2033       return;
2034    LValue *lval = new_LValue(func, FILE_GPR);
2035    lval->reg.size = size;
2036
2037    Instruction *split = new_Instruction(func, OP_SPLIT, typeOfSize(size));
2038    split->setSrc(0, lval);
2039    for (int d = 0; d < n; ++d) {
2040       split->setDef(d, insn->getDef(d));
2041       insn->setDef(d, NULL);
2042    }
2043    insn->setDef(0, lval);
2044
2045    for (int k = 1, d = n; insn->defExists(d); ++d, ++k) {
2046       insn->setDef(k, insn->getDef(d));
2047       insn->setDef(d, NULL);
2048    }
2049    // carry over predicate if any (mainly for OP_UNION uses)
2050    split->setPredicate(insn->cc, insn->getPredicate());
2051
2052    insn->bb->insertAfter(insn, split);
2053    constrList.push_back(split);
2054 }
2055 void
2056 RegAlloc::InsertConstraintsPass::condenseSrcs(Instruction *insn,
2057                                               const int a, const int b)
2058 {
2059    uint8_t size = 0;
2060    if (a >= b)
2061       return;
2062    for (int s = a; s <= b; ++s)
2063       size += insn->getSrc(s)->reg.size;
2064    if (!size)
2065       return;
2066    LValue *lval = new_LValue(func, FILE_GPR);
2067    lval->reg.size = size;
2068
2069    Value *save[3];
2070    insn->takeExtraSources(0, save);
2071
2072    Instruction *merge = new_Instruction(func, OP_MERGE, typeOfSize(size));
2073    merge->setDef(0, lval);
2074    for (int s = a, i = 0; s <= b; ++s, ++i) {
2075       merge->setSrc(i, insn->getSrc(s));
2076    }
2077    insn->moveSources(b + 1, a - b);
2078    insn->setSrc(a, lval);
2079    insn->bb->insertBefore(insn, merge);
2080
2081    insn->putExtraSources(0, save);
2082
2083    constrList.push_back(merge);
2084 }
2085
2086 void
2087 RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex)
2088 {
2089    int n, s;
2090
2091    if (isTextureOp(tex->op))
2092       textureMask(tex);
2093    condenseDefs(tex);
2094
2095    if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2096       condenseSrcs(tex, 3, (3 + typeSizeof(tex->dType) / 4) - 1);
2097    } else
2098    if (isTextureOp(tex->op)) {
2099       if (tex->op != OP_TXQ) {
2100          s = tex->tex.target.getArgCount() - tex->tex.target.isMS();
2101          if (tex->op == OP_TXD) {
2102             // Indirect handle belongs in the first arg
2103             if (tex->tex.rIndirectSrc >= 0)
2104                s++;
2105             if (!tex->tex.target.isArray() && tex->tex.useOffsets)
2106                s++;
2107          }
2108          n = tex->srcCount(0xff) - s;
2109       } else {
2110          s = tex->srcCount(0xff);
2111          n = 0;
2112       }
2113
2114       if (s > 1)
2115          condenseSrcs(tex, 0, s - 1);
2116       if (n > 1) // NOTE: first call modified positions already
2117          condenseSrcs(tex, 1, n);
2118    }
2119 }
2120
2121 void
2122 RegAlloc::InsertConstraintsPass::texConstraintNVE0(TexInstruction *tex)
2123 {
2124    if (isTextureOp(tex->op))
2125       textureMask(tex);
2126    condenseDefs(tex);
2127
2128    if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2129       condenseSrcs(tex, 3, 6);
2130    } else
2131    if (isTextureOp(tex->op)) {
2132       int n = tex->srcCount(0xff, true);
2133       if (n > 4) {
2134          condenseSrcs(tex, 0, 3);
2135          if (n > 5) // NOTE: first call modified positions already
2136             condenseSrcs(tex, 4 - (4 - 1), n - 1 - (4 - 1));
2137       } else
2138       if (n > 1) {
2139          condenseSrcs(tex, 0, n - 1);
2140       }
2141    }
2142 }
2143
2144 void
2145 RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex)
2146 {
2147    int n, s;
2148
2149    if (isTextureOp(tex->op))
2150       textureMask(tex);
2151
2152    if (tex->op == OP_TXQ) {
2153       s = tex->srcCount(0xff);
2154       n = 0;
2155    } else if (isSurfaceOp(tex->op)) {
2156       s = tex->tex.target.getDim() + (tex->tex.target.isArray() || tex->tex.target.isCube());
2157       if (tex->op == OP_SUSTB || tex->op == OP_SUSTP)
2158          n = 4;
2159       else
2160          n = 0;
2161    } else {
2162       s = tex->tex.target.getArgCount() - tex->tex.target.isMS();
2163       if (!tex->tex.target.isArray() &&
2164           (tex->tex.rIndirectSrc >= 0 || tex->tex.sIndirectSrc >= 0))
2165          ++s;
2166       if (tex->op == OP_TXD && tex->tex.useOffsets)
2167          ++s;
2168       n = tex->srcCount(0xff) - s;
2169       assert(n <= 4);
2170    }
2171
2172    if (s > 1)
2173       condenseSrcs(tex, 0, s - 1);
2174    if (n > 1) // NOTE: first call modified positions already
2175       condenseSrcs(tex, 1, n);
2176
2177    condenseDefs(tex);
2178 }
2179
2180 void
2181 RegAlloc::InsertConstraintsPass::texConstraintNV50(TexInstruction *tex)
2182 {
2183    Value *pred = tex->getPredicate();
2184    if (pred)
2185       tex->setPredicate(tex->cc, NULL);
2186
2187    textureMask(tex);
2188
2189    assert(tex->defExists(0) && tex->srcExists(0));
2190    // make src and def count match
2191    int c;
2192    for (c = 0; tex->srcExists(c) || tex->defExists(c); ++c) {
2193       if (!tex->srcExists(c))
2194          tex->setSrc(c, new_LValue(func, tex->getSrc(0)->asLValue()));
2195       if (!tex->defExists(c))
2196          tex->setDef(c, new_LValue(func, tex->getDef(0)->asLValue()));
2197    }
2198    if (pred)
2199       tex->setPredicate(tex->cc, pred);
2200    condenseDefs(tex);
2201    condenseSrcs(tex, 0, c - 1);
2202 }
2203
2204 // Insert constraint markers for instructions whose multiple sources must be
2205 // located in consecutive registers.
2206 bool
2207 RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
2208 {
2209    TexInstruction *tex;
2210    Instruction *next;
2211    int s, size;
2212
2213    targ = bb->getProgram()->getTarget();
2214
2215    for (Instruction *i = bb->getEntry(); i; i = next) {
2216       next = i->next;
2217
2218       if ((tex = i->asTex())) {
2219          switch (targ->getChipset() & ~0xf) {
2220          case 0x50:
2221          case 0x80:
2222          case 0x90:
2223          case 0xa0:
2224             texConstraintNV50(tex);
2225             break;
2226          case 0xc0:
2227          case 0xd0:
2228             texConstraintNVC0(tex);
2229             break;
2230          case 0xe0:
2231          case 0xf0:
2232          case 0x100:
2233             texConstraintNVE0(tex);
2234             break;
2235          case 0x110:
2236          case 0x120:
2237             texConstraintGM107(tex);
2238             break;
2239          default:
2240             break;
2241          }
2242       } else
2243       if (i->op == OP_EXPORT || i->op == OP_STORE) {
2244          for (size = typeSizeof(i->dType), s = 1; size > 0; ++s) {
2245             assert(i->srcExists(s));
2246             size -= i->getSrc(s)->reg.size;
2247          }
2248          condenseSrcs(i, 1, s - 1);
2249       } else
2250       if (i->op == OP_LOAD || i->op == OP_VFETCH) {
2251          condenseDefs(i);
2252          if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
2253             addHazard(i, i->src(0).getIndirect(0));
2254          if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8)
2255             addHazard(i, i->src(0).getIndirect(1));
2256       } else
2257       if (i->op == OP_UNION ||
2258           i->op == OP_MERGE ||
2259           i->op == OP_SPLIT) {
2260          constrList.push_back(i);
2261       }
2262    }
2263    return true;
2264 }
2265
2266 // Insert extra moves so that, if multiple register constraints on a value are
2267 // in conflict, these conflicts can be resolved.
2268 bool
2269 RegAlloc::InsertConstraintsPass::insertConstraintMoves()
2270 {
2271    for (std::list<Instruction *>::iterator it = constrList.begin();
2272         it != constrList.end();
2273         ++it) {
2274       Instruction *cst = *it;
2275       Instruction *mov;
2276
2277       if (cst->op == OP_SPLIT && 0) {
2278          // spilling splits is annoying, just make sure they're separate
2279          for (int d = 0; cst->defExists(d); ++d) {
2280             if (!cst->getDef(d)->refCount())
2281                continue;
2282             LValue *lval = new_LValue(func, cst->def(d).getFile());
2283             const uint8_t size = cst->def(d).getSize();
2284             lval->reg.size = size;
2285
2286             mov = new_Instruction(func, OP_MOV, typeOfSize(size));
2287             mov->setSrc(0, lval);
2288             mov->setDef(0, cst->getDef(d));
2289             cst->setDef(d, mov->getSrc(0));
2290             cst->bb->insertAfter(cst, mov);
2291
2292             cst->getSrc(0)->asLValue()->noSpill = 1;
2293             mov->getSrc(0)->asLValue()->noSpill = 1;
2294          }
2295       } else
2296       if (cst->op == OP_MERGE || cst->op == OP_UNION) {
2297          for (int s = 0; cst->srcExists(s); ++s) {
2298             const uint8_t size = cst->src(s).getSize();
2299
2300             if (!cst->getSrc(s)->defs.size()) {
2301                mov = new_Instruction(func, OP_NOP, typeOfSize(size));
2302                mov->setDef(0, cst->getSrc(s));
2303                cst->bb->insertBefore(cst, mov);
2304                continue;
2305             }
2306             assert(cst->getSrc(s)->defs.size() == 1); // still SSA
2307
2308             Instruction *defi = cst->getSrc(s)->defs.front()->getInsn();
2309             // catch some cases where don't really need MOVs
2310             if (cst->getSrc(s)->refCount() == 1 && !defi->constrainedDefs())
2311                continue;
2312
2313             LValue *lval = new_LValue(func, cst->src(s).getFile());
2314             lval->reg.size = size;
2315
2316             mov = new_Instruction(func, OP_MOV, typeOfSize(size));
2317             mov->setDef(0, lval);
2318             mov->setSrc(0, cst->getSrc(s));
2319             cst->setSrc(s, mov->getDef(0));
2320             cst->bb->insertBefore(cst, mov);
2321
2322             cst->getDef(0)->asLValue()->noSpill = 1; // doesn't help
2323
2324             if (cst->op == OP_UNION)
2325                mov->setPredicate(defi->cc, defi->getPredicate());
2326          }
2327       }
2328    }
2329
2330    return true;
2331 }
2332
2333 } // namespace nv50_ir