src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir.h"
  24 #include "codegen/nv50_ir_target.h"
  25
  26 #include <algorithm>
  27 #include <stack>
  28 #include <limits>
  29 #if __cplusplus >= 201103L
  30 #include <unordered_map>
  31 #else
  32 #include <tr1/unordered_map>
  33 #endif
  34
  35 namespace nv50_ir {
  36
  37 #if __cplusplus >= 201103L
  38 using std::hash;
  39 using std::unordered_map;
  40 #elif !defined(ANDROID)
  41 using std::tr1::hash;
  42 using std::tr1::unordered_map;
  43 #else
  44 #error Android release before Lollipop is not supported!
  45 #endif
  46
  47 #define MAX_REGISTER_FILE_SIZE 256
  48
  49 class RegisterSet
  50 {
  51 public:
  52    RegisterSet(const Target *);
  53
  54    void init(const Target *);
  55    void reset(DataFile, bool resetMax = false);
  56
  57    void periodicMask(DataFile f, uint32_t lock, uint32_t unlock);
  58    void intersect(DataFile f, const RegisterSet *);
  59
  60    bool assign(int32_t& reg, DataFile f, unsigned int size);
  61    void release(DataFile f, int32_t reg, unsigned int size);
  62    void occupy(DataFile f, int32_t reg, unsigned int size);
  63    void occupy(const Value *);
  64    void occupyMask(DataFile f, int32_t reg, uint8_t mask);
  65    bool isOccupied(DataFile f, int32_t reg, unsigned int size) const;
  66    bool testOccupy(const Value *);
  67    bool testOccupy(DataFile f, int32_t reg, unsigned int size);
  68
  69    inline int getMaxAssigned(DataFile f) const { return fill[f]; }
  70
  71    inline unsigned int getFileSize(DataFile f, uint8_t regSize) const
  72    {
  73       if (restrictedGPR16Range && f == FILE_GPR && regSize == 2)
  74          return (last[f] + 1) / 2;
  75       return last[f] + 1;
  76    }
  77
  78    inline unsigned int units(DataFile f, unsigned int size) const
  79    {
  80       return size >> unit[f];
  81    }
  82    // for regs of size >= 4, id is counted in 4-byte words (like nv50/c0 binary)
  83    inline unsigned int idToBytes(const Value *v) const
  84    {
  85       return v->reg.data.id * MIN2(v->reg.size, 4);
  86    }
  87    inline unsigned int idToUnits(const Value *v) const
  88    {
  89       return units(v->reg.file, idToBytes(v));
  90    }
  91    inline int bytesToId(Value *v, unsigned int bytes) const
  92    {
  93       if (v->reg.size < 4)
  94          return units(v->reg.file, bytes);
  95       return bytes / 4;
  96    }
  97    inline int unitsToId(DataFile f, int u, uint8_t size) const
  98    {
  99       if (u < 0)
 100          return -1;
 101       return (size < 4) ? u : ((u << unit[f]) / 4);
 102    }
 103
 104    void print() const;
 105
 106    const bool restrictedGPR16Range;
 107
 108 private:
 109    BitSet bits[LAST_REGISTER_FILE + 1];
 110
 111    int unit[LAST_REGISTER_FILE + 1]; // log2 of allocation granularity
 112
 113    int last[LAST_REGISTER_FILE + 1];
 114    int fill[LAST_REGISTER_FILE + 1];
 115 };
 116
 117 void
 118 RegisterSet::reset(DataFile f, bool resetMax)
 119 {
 120    bits[f].fill(0);
 121    if (resetMax)
 122       fill[f] = -1;
 123 }
 124
 125 void
 126 RegisterSet::init(const Target *targ)
 127 {
 128    for (unsigned int rf = 0; rf <= FILE_ADDRESS; ++rf) {
 129       DataFile f = static_cast<DataFile>(rf);
 130       last[rf] = targ->getFileSize(f) - 1;
 131       unit[rf] = targ->getFileUnit(f);
 132       fill[rf] = -1;
 133       assert(last[rf] < MAX_REGISTER_FILE_SIZE);
 134       bits[rf].allocate(last[rf] + 1, true);
 135    }
 136 }
 137
 138 RegisterSet::RegisterSet(const Target *targ)
 139   : restrictedGPR16Range(targ->getChipset() < 0xc0)
 140 {
 141    init(targ);
 142    for (unsigned int i = 0; i <= LAST_REGISTER_FILE; ++i)
 143       reset(static_cast<DataFile>(i));
 144 }
 145
 146 void
 147 RegisterSet::periodicMask(DataFile f, uint32_t lock, uint32_t unlock)
 148 {
 149    bits[f].periodicMask32(lock, unlock);
 150 }
 151
 152 void
 153 RegisterSet::intersect(DataFile f, const RegisterSet *set)
 154 {
 155    bits[f] |= set->bits[f];
 156 }
 157
 158 void
 159 RegisterSet::print() const
 160 {
 161    INFO("GPR:");
 162    bits[FILE_GPR].print();
 163    INFO("\n");
 164 }
 165
 166 bool
 167 RegisterSet::assign(int32_t& reg, DataFile f, unsigned int size)
 168 {
 169    reg = bits[f].findFreeRange(size);
 170    if (reg < 0)
 171       return false;
 172    fill[f] = MAX2(fill[f], (int32_t)(reg + size - 1));
 173    return true;
 174 }
 175
 176 bool
 177 RegisterSet::isOccupied(DataFile f, int32_t reg, unsigned int size) const
 178 {
 179    return bits[f].testRange(reg, size);
 180 }
 181
 182 void
 183 RegisterSet::occupy(const Value *v)
 184 {
 185    occupy(v->reg.file, idToUnits(v), v->reg.size >> unit[v->reg.file]);
 186 }
 187
 188 void
 189 RegisterSet::occupyMask(DataFile f, int32_t reg, uint8_t mask)
 190 {
 191    bits[f].setMask(reg & ~31, static_cast<uint32_t>(mask) << (reg % 32));
 192 }
 193
 194 void
 195 RegisterSet::occupy(DataFile f, int32_t reg, unsigned int size)
 196 {
 197    bits[f].setRange(reg, size);
 198
 199    INFO_DBG(0, REG_ALLOC, "reg occupy: %u[%i] %u\n", f, reg, size);
 200
 201    fill[f] = MAX2(fill[f], (int32_t)(reg + size - 1));
 202 }
 203
 204 bool
 205 RegisterSet::testOccupy(const Value *v)
 206 {
 207    return testOccupy(v->reg.file,
 208                      idToUnits(v), v->reg.size >> unit[v->reg.file]);
 209 }
 210
 211 bool
 212 RegisterSet::testOccupy(DataFile f, int32_t reg, unsigned int size)
 213 {
 214    if (isOccupied(f, reg, size))
 215       return false;
 216    occupy(f, reg, size);
 217    return true;
 218 }
 219
 220 void
 221 RegisterSet::release(DataFile f, int32_t reg, unsigned int size)
 222 {
 223    bits[f].clrRange(reg, size);
 224
 225    INFO_DBG(0, REG_ALLOC, "reg release: %u[%i] %u\n", f, reg, size);
 226 }
 227
 228 class RegAlloc
 229 {
 230 public:
 231    RegAlloc(Program *program) : prog(program), sequence(0) { }
 232
 233    bool exec();
 234    bool execFunc();
 235
 236 private:
 237    class PhiMovesPass : public Pass {
 238    private:
 239       virtual bool visit(BasicBlock *);
 240       inline bool needNewElseBlock(BasicBlock *b, BasicBlock *p);
 241       inline void splitEdges(BasicBlock *b);
 242    };
 243
 244    class ArgumentMovesPass : public Pass {
 245    private:
 246       virtual bool visit(BasicBlock *);
 247    };
 248
 249    class BuildIntervalsPass : public Pass {
 250    private:
 251       virtual bool visit(BasicBlock *);
 252       void collectLiveValues(BasicBlock *);
 253       void addLiveRange(Value *, const BasicBlock *, int end);
 254    };
 255
 256    class InsertConstraintsPass : public Pass {
 257    public:
 258       bool exec(Function *func);
 259    private:
 260       virtual bool visit(BasicBlock *);
 261
 262       bool insertConstraintMoves();
 263
 264       void condenseDefs(Instruction *);
 265       void condenseSrcs(Instruction *, const int first, const int last);
 266
 267       void addHazard(Instruction *i, const ValueRef *src);
 268       void textureMask(TexInstruction *);
 269       void addConstraint(Instruction *, int s, int n);
 270       bool detectConflict(Instruction *, int s);
 271
 272       // target specific functions, TODO: put in subclass or Target
 273       void texConstraintNV50(TexInstruction *);
 274       void texConstraintNVC0(TexInstruction *);
 275       void texConstraintNVE0(TexInstruction *);
 276       void texConstraintGM107(TexInstruction *);
 277
 278       std::list<Instruction *> constrList;
 279
 280       const Target *targ;
 281    };
 282
 283    bool buildLiveSets(BasicBlock *);
 284
 285 private:
 286    Program *prog;
 287    Function *func;
 288
 289    // instructions in control flow / chronological order
 290    ArrayList insns;
 291
 292    int sequence; // for manual passes through CFG
 293 };
 294
 295 typedef std::pair<Value *, Value *> ValuePair;
 296
 297 class SpillCodeInserter
 298 {
 299 public:
 300    SpillCodeInserter(Function *fn) : func(fn), stackSize(0), stackBase(0) { }
 301
 302    bool run(const std::list<ValuePair>&);
 303
 304    Symbol *assignSlot(const Interval&, const unsigned int size);
 305    Value *offsetSlot(Value *, const LValue *);
 306    inline int32_t getStackSize() const { return stackSize; }
 307
 308 private:
 309    Function *func;
 310
 311    struct SpillSlot
 312    {
 313       Interval occup;
 314       std::list<Value *> residents; // needed to recalculate occup
 315       Symbol *sym;
 316       int32_t offset;
 317       inline uint8_t size() const { return sym->reg.size; }
 318    };
 319    std::list<SpillSlot> slots;
 320    int32_t stackSize;
 321    int32_t stackBase;
 322
 323    LValue *unspill(Instruction *usei, LValue *, Value *slot);
 324    void spill(Instruction *defi, Value *slot, LValue *);
 325 };
 326
 327 void
 328 RegAlloc::BuildIntervalsPass::addLiveRange(Value *val,
 329                                            const BasicBlock *bb,
 330                                            int end)
 331 {
 332    Instruction *insn = val->getUniqueInsn();
 333
 334    if (!insn)
 335       insn = bb->getFirst();
 336
 337    assert(bb->getFirst()->serial <= bb->getExit()->serial);
 338    assert(bb->getExit()->serial + 1 >= end);
 339
 340    int begin = insn->serial;
 341    if (begin < bb->getEntry()->serial || begin > bb->getExit()->serial)
 342       begin = bb->getEntry()->serial;
 343
 344    INFO_DBG(prog->dbgFlags, REG_ALLOC, "%%%i <- live range [%i(%i), %i)\n",
 345             val->id, begin, insn->serial, end);
 346
 347    if (begin != end) // empty ranges are only added as hazards for fixed regs
 348       val->livei.extend(begin, end);
 349 }
 350
 351 bool
 352 RegAlloc::PhiMovesPass::needNewElseBlock(BasicBlock *b, BasicBlock *p)
 353 {
 354    if (b->cfg.incidentCount() <= 1)
 355       return false;
 356
 357    int n = 0;
 358    for (Graph::EdgeIterator ei = p->cfg.outgoing(); !ei.end(); ei.next())
 359       if (ei.getType() == Graph::Edge::TREE ||
 360           ei.getType() == Graph::Edge::FORWARD)
 361          ++n;
 362    return (n == 2);
 363 }
 364
 365 struct PhiMapHash {
 366    size_t operator()(const std::pair<Instruction *, BasicBlock *>& val) const {
 367       return hash<Instruction*>()(val.first) * 31 +
 368          hash<BasicBlock*>()(val.second);
 369    }
 370 };
 371
 372 typedef unordered_map<
 373    std::pair<Instruction *, BasicBlock *>, Value *, PhiMapHash> PhiMap;
 374
 375 // Critical edges need to be split up so that work can be inserted along
 376 // specific edge transitions. Unfortunately manipulating incident edges into a
 377 // BB invalidates all the PHI nodes since their sources are implicitly ordered
 378 // by incident edge order.
 379 //
 380 // TODO: Make it so that that is not the case, and PHI nodes store pointers to
 381 // the original BBs.
 382 void
 383 RegAlloc::PhiMovesPass::splitEdges(BasicBlock *bb)
 384 {
 385    BasicBlock *pb, *pn;
 386    Instruction *phi;
 387    Graph::EdgeIterator ei;
 388    std::stack<BasicBlock *> stack;
 389    int j = 0;
 390
 391    for (ei = bb->cfg.incident(); !ei.end(); ei.next()) {
 392       pb = BasicBlock::get(ei.getNode());
 393       assert(pb);
 394       if (needNewElseBlock(bb, pb))
 395          stack.push(pb);
 396    }
 397
 398    // No critical edges were found, no need to perform any work.
 399    if (stack.empty())
 400       return;
 401
 402    // We're about to, potentially, reorder the inbound edges. This means that
 403    // we need to hold on to the (phi, bb) -> src mapping, and fix up the phi
 404    // nodes after the graph has been modified.
 405    PhiMap phis;
 406
 407    j = 0;
 408    for (ei = bb->cfg.incident(); !ei.end(); ei.next(), j++) {
 409       pb = BasicBlock::get(ei.getNode());
 410       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next)
 411          phis.insert(std::make_pair(std::make_pair(phi, pb), phi->getSrc(j)));
 412    }
 413
 414    while (!stack.empty()) {
 415       pb = stack.top();
 416       pn = new BasicBlock(func);
 417       stack.pop();
 418
 419       pb->cfg.detach(&bb->cfg);
 420       pb->cfg.attach(&pn->cfg, Graph::Edge::TREE);
 421       pn->cfg.attach(&bb->cfg, Graph::Edge::FORWARD);
 422
 423       assert(pb->getExit()->op != OP_CALL);
 424       if (pb->getExit()->asFlow()->target.bb == bb)
 425          pb->getExit()->asFlow()->target.bb = pn;
 426
 427       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 428          PhiMap::iterator it = phis.find(std::make_pair(phi, pb));
 429          assert(it != phis.end());
 430          phis.insert(std::make_pair(std::make_pair(phi, pn), it->second));
 431          phis.erase(it);
 432       }
 433    }
 434
 435    // Now go through and fix up all of the phi node sources.
 436    j = 0;
 437    for (ei = bb->cfg.incident(); !ei.end(); ei.next(), j++) {
 438       pb = BasicBlock::get(ei.getNode());
 439       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 440          PhiMap::const_iterator it = phis.find(std::make_pair(phi, pb));
 441          assert(it != phis.end());
 442
 443          phi->setSrc(j, it->second);
 444       }
 445    }
 446 }
 447
 448 // For each operand of each PHI in b, generate a new value by inserting a MOV
 449 // at the end of the block it is coming from and replace the operand with its
 450 // result. This eliminates liveness conflicts and enables us to let values be
 451 // copied to the right register if such a conflict exists nonetheless.
 452 //
 453 // These MOVs are also crucial in making sure the live intervals of phi srces
 454 // are extended until the end of the loop, since they are not included in the
 455 // live-in sets.
 456 bool
 457 RegAlloc::PhiMovesPass::visit(BasicBlock *bb)
 458 {
 459    Instruction *phi, *mov;
 460
 461    splitEdges(bb);
 462
 463    // insert MOVs (phi->src(j) should stem from j-th in-BB)
 464    int j = 0;
 465    for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
 466       BasicBlock *pb = BasicBlock::get(ei.getNode());
 467       if (!pb->isTerminated())
 468          pb->insertTail(new_FlowInstruction(func, OP_BRA, bb));
 469
 470       for (phi = bb->getPhi(); phi && phi->op == OP_PHI; phi = phi->next) {
 471          LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue());
 472          mov = new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 473
 474          mov->setSrc(0, phi->getSrc(j));
 475          mov->setDef(0, tmp);
 476          phi->setSrc(j, tmp);
 477
 478          pb->insertBefore(pb->getExit(), mov);
 479       }
 480       ++j;
 481    }
 482
 483    return true;
 484 }
 485
 486 bool
 487 RegAlloc::ArgumentMovesPass::visit(BasicBlock *bb)
 488 {
 489    // Bind function call inputs/outputs to the same physical register
 490    // the callee uses, inserting moves as appropriate for the case a
 491    // conflict arises.
 492    for (Instruction *i = bb->getEntry(); i; i = i->next) {
 493       FlowInstruction *cal = i->asFlow();
 494       // TODO: Handle indirect calls.
 495       // Right now they should only be generated for builtins.
 496       if (!cal || cal->op != OP_CALL || cal->builtin || cal->indirect)
 497          continue;
 498       RegisterSet clobberSet(prog->getTarget());
 499
 500       // Bind input values.
 501       for (int s = cal->indirect ? 1 : 0; cal->srcExists(s); ++s) {
 502          const int t = cal->indirect ? (s - 1) : s;
 503          LValue *tmp = new_LValue(func, cal->getSrc(s)->asLValue());
 504          tmp->reg.data.id = cal->target.fn->ins[t].rep()->reg.data.id;
 505
 506          Instruction *mov =
 507             new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 508          mov->setDef(0, tmp);
 509          mov->setSrc(0, cal->getSrc(s));
 510          cal->setSrc(s, tmp);
 511
 512          bb->insertBefore(cal, mov);
 513       }
 514
 515       // Bind output values.
 516       for (int d = 0; cal->defExists(d); ++d) {
 517          LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue());
 518          tmp->reg.data.id = cal->target.fn->outs[d].rep()->reg.data.id;
 519
 520          Instruction *mov =
 521             new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size));
 522          mov->setSrc(0, tmp);
 523          mov->setDef(0, cal->getDef(d));
 524          cal->setDef(d, tmp);
 525
 526          bb->insertAfter(cal, mov);
 527          clobberSet.occupy(tmp);
 528       }
 529
 530       // Bind clobbered values.
 531       for (std::deque<Value *>::iterator it = cal->target.fn->clobbers.begin();
 532            it != cal->target.fn->clobbers.end();
 533            ++it) {
 534          if (clobberSet.testOccupy(*it)) {
 535             Value *tmp = new_LValue(func, (*it)->asLValue());
 536             tmp->reg.data.id = (*it)->reg.data.id;
 537             cal->setDef(cal->defCount(), tmp);
 538          }
 539       }
 540    }
 541
 542    // Update the clobber set of the function.
 543    if (BasicBlock::get(func->cfgExit) == bb) {
 544       func->buildDefSets();
 545       for (unsigned int i = 0; i < bb->defSet.getSize(); ++i)
 546          if (bb->defSet.test(i))
 547             func->clobbers.push_back(func->getLValue(i));
 548    }
 549
 550    return true;
 551 }
 552
 553 // Build the set of live-in variables of bb.
 554 bool
 555 RegAlloc::buildLiveSets(BasicBlock *bb)
 556 {
 557    Function *f = bb->getFunction();
 558    BasicBlock *bn;
 559    Instruction *i;
 560    unsigned int s, d;
 561
 562    INFO_DBG(prog->dbgFlags, REG_ALLOC, "buildLiveSets(BB:%i)\n", bb->getId());
 563
 564    bb->liveSet.allocate(func->allLValues.getSize(), false);
 565
 566    int n = 0;
 567    for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 568       bn = BasicBlock::get(ei.getNode());
 569       if (bn == bb)
 570          continue;
 571       if (bn->cfg.visit(sequence))
 572          if (!buildLiveSets(bn))
 573             return false;
 574       if (n++ || bb->liveSet.marker)
 575          bb->liveSet |= bn->liveSet;
 576       else
 577          bb->liveSet = bn->liveSet;
 578    }
 579    if (!n && !bb->liveSet.marker)
 580       bb->liveSet.fill(0);
 581    bb->liveSet.marker = true;
 582
 583    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
 584       INFO("BB:%i live set of out blocks:\n", bb->getId());
 585       bb->liveSet.print();
 586    }
 587
 588    // if (!bb->getEntry())
 589    //   return true;
 590
 591    if (bb == BasicBlock::get(f->cfgExit)) {
 592       for (std::deque<ValueRef>::iterator it = f->outs.begin();
 593            it != f->outs.end(); ++it) {
 594          assert(it->get()->asLValue());
 595          bb->liveSet.set(it->get()->id);
 596       }
 597    }
 598
 599    for (i = bb->getExit(); i && i != bb->getEntry()->prev; i = i->prev) {
 600       for (d = 0; i->defExists(d); ++d)
 601          bb->liveSet.clr(i->getDef(d)->id);
 602       for (s = 0; i->srcExists(s); ++s)
 603          if (i->getSrc(s)->asLValue())
 604             bb->liveSet.set(i->getSrc(s)->id);
 605    }
 606    for (i = bb->getPhi(); i && i->op == OP_PHI; i = i->next)
 607       bb->liveSet.clr(i->getDef(0)->id);
 608
 609    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
 610       INFO("BB:%i live set after propagation:\n", bb->getId());
 611       bb->liveSet.print();
 612    }
 613
 614    return true;
 615 }
 616
 617 void
 618 RegAlloc::BuildIntervalsPass::collectLiveValues(BasicBlock *bb)
 619 {
 620    BasicBlock *bbA = NULL, *bbB = NULL;
 621
 622    if (bb->cfg.outgoingCount()) {
 623       // trickery to save a loop of OR'ing liveSets
 624       // aliasing works fine with BitSet::setOr
 625       for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 626          if (ei.getType() == Graph::Edge::DUMMY)
 627             continue;
 628          if (bbA) {
 629             bb->liveSet.setOr(&bbA->liveSet, &bbB->liveSet);
 630             bbA = bb;
 631          } else {
 632             bbA = bbB;
 633          }
 634          bbB = BasicBlock::get(ei.getNode());
 635       }
 636       bb->liveSet.setOr(&bbB->liveSet, bbA ? &bbA->liveSet : NULL);
 637    } else
 638    if (bb->cfg.incidentCount()) {
 639       bb->liveSet.fill(0);
 640    }
 641 }
 642
 643 bool
 644 RegAlloc::BuildIntervalsPass::visit(BasicBlock *bb)
 645 {
 646    collectLiveValues(bb);
 647
 648    INFO_DBG(prog->dbgFlags, REG_ALLOC, "BuildIntervals(BB:%i)\n", bb->getId());
 649
 650    // go through out blocks and delete phi sources that do not originate from
 651    // the current block from the live set
 652    for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
 653       BasicBlock *out = BasicBlock::get(ei.getNode());
 654
 655       for (Instruction *i = out->getPhi(); i && i->op == OP_PHI; i = i->next) {
 656          bb->liveSet.clr(i->getDef(0)->id);
 657
 658          for (int s = 0; i->srcExists(s); ++s) {
 659             assert(i->src(s).getInsn());
 660             if (i->getSrc(s)->getUniqueInsn()->bb == bb) // XXX: reachableBy ?
 661                bb->liveSet.set(i->getSrc(s)->id);
 662             else
 663                bb->liveSet.clr(i->getSrc(s)->id);
 664          }
 665       }
 666    }
 667
 668    // remaining live-outs are live until end
 669    if (bb->getExit()) {
 670       for (unsigned int j = 0; j < bb->liveSet.getSize(); ++j)
 671          if (bb->liveSet.test(j))
 672             addLiveRange(func->getLValue(j), bb, bb->getExit()->serial + 1);
 673    }
 674
 675    for (Instruction *i = bb->getExit(); i && i->op != OP_PHI; i = i->prev) {
 676       for (int d = 0; i->defExists(d); ++d) {
 677          bb->liveSet.clr(i->getDef(d)->id);
 678          if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs
 679             i->getDef(d)->livei.extend(i->serial, i->serial);
 680       }
 681
 682       for (int s = 0; i->srcExists(s); ++s) {
 683          if (!i->getSrc(s)->asLValue())
 684             continue;
 685          if (!bb->liveSet.test(i->getSrc(s)->id)) {
 686             bb->liveSet.set(i->getSrc(s)->id);
 687             addLiveRange(i->getSrc(s), bb, i->serial);
 688          }
 689       }
 690    }
 691
 692    if (bb == BasicBlock::get(func->cfg.getRoot())) {
 693       for (std::deque<ValueDef>::iterator it = func->ins.begin();
 694            it != func->ins.end(); ++it) {
 695          if (it->get()->reg.data.id >= 0) // add hazard for fixed regs
 696             it->get()->livei.extend(0, 1);
 697       }
 698    }
 699
 700    return true;
 701 }
 702
 703
 704 #define JOIN_MASK_PHI        (1 << 0)
 705 #define JOIN_MASK_UNION      (1 << 1)
 706 #define JOIN_MASK_MOV        (1 << 2)
 707 #define JOIN_MASK_TEX        (1 << 3)
 708
 709 class GCRA
 710 {
 711 public:
 712    GCRA(Function *, SpillCodeInserter&);
 713    ~GCRA();
 714
 715    bool allocateRegisters(ArrayList& insns);
 716
 717    void printNodeInfo() const;
 718
 719 private:
 720    class RIG_Node : public Graph::Node
 721    {
 722    public:
 723       RIG_Node();
 724
 725       void init(const RegisterSet&, LValue *);
 726
 727       void addInterference(RIG_Node *);
 728       void addRegPreference(RIG_Node *);
 729
 730       inline LValue *getValue() const
 731       {
 732          return reinterpret_cast<LValue *>(data);
 733       }
 734       inline void setValue(LValue *lval) { data = lval; }
 735
 736       inline uint8_t getCompMask() const
 737       {
 738          return ((1 << colors) - 1) << (reg & 7);
 739       }
 740
 741       static inline RIG_Node *get(const Graph::EdgeIterator& ei)
 742       {
 743          return static_cast<RIG_Node *>(ei.getNode());
 744       }
 745
 746    public:
 747       uint32_t degree;
 748       uint16_t degreeLimit; // if deg < degLimit, node is trivially colourable
 749       uint16_t colors;
 750
 751       DataFile f;
 752       int32_t reg;
 753
 754       float weight;
 755
 756       // list pointers for simplify() phase
 757       RIG_Node *next;
 758       RIG_Node *prev;
 759
 760       // union of the live intervals of all coalesced values (we want to retain
 761       //  the separate intervals for testing interference of compound values)
 762       Interval livei;
 763
 764       std::list<RIG_Node *> prefRegs;
 765    };
 766
 767 private:
 768    inline RIG_Node *getNode(const LValue *v) const { return &nodes[v->id]; }
 769
 770    void buildRIG(ArrayList&);
 771    bool coalesce(ArrayList&);
 772    bool doCoalesce(ArrayList&, unsigned int mask);
 773    void calculateSpillWeights();
 774    void simplify();
 775    bool selectRegisters();
 776    void cleanup(const bool success);
 777
 778    void simplifyEdge(RIG_Node *, RIG_Node *);
 779    void simplifyNode(RIG_Node *);
 780
 781    bool coalesceValues(Value *, Value *, bool force);
 782    void resolveSplitsAndMerges();
 783    void makeCompound(Instruction *, bool isSplit);
 784
 785    inline void checkInterference(const RIG_Node *, Graph::EdgeIterator&);
 786
 787    inline void insertOrderedTail(std::list<RIG_Node *>&, RIG_Node *);
 788    void checkList(std::list<RIG_Node *>&);
 789
 790 private:
 791    std::stack<uint32_t> stack;
 792
 793    // list headers for simplify() phase
 794    RIG_Node lo[2];
 795    RIG_Node hi;
 796
 797    Graph RIG;
 798    RIG_Node *nodes;
 799    unsigned int nodeCount;
 800
 801    Function *func;
 802    Program *prog;
 803
 804    static uint8_t relDegree[17][17];
 805
 806    RegisterSet regs;
 807
 808    // need to fixup register id for participants of OP_MERGE/SPLIT
 809    std::list<Instruction *> merges;
 810    std::list<Instruction *> splits;
 811
 812    SpillCodeInserter& spill;
 813    std::list<ValuePair> mustSpill;
 814 };
 815
 816 uint8_t GCRA::relDegree[17][17];
 817
 818 GCRA::RIG_Node::RIG_Node() : Node(NULL), next(this), prev(this)
 819 {
 820    colors = 0;
 821 }
 822
 823 void
 824 GCRA::printNodeInfo() const
 825 {
 826    for (unsigned int i = 0; i < nodeCount; ++i) {
 827       if (!nodes[i].colors)
 828          continue;
 829       INFO("RIG_Node[%%%i]($[%u]%i): %u colors, weight %f, deg %u/%u\n X",
 830            i,
 831            nodes[i].f,nodes[i].reg,nodes[i].colors,
 832            nodes[i].weight,
 833            nodes[i].degree, nodes[i].degreeLimit);
 834
 835       for (Graph::EdgeIterator ei = nodes[i].outgoing(); !ei.end(); ei.next())
 836          INFO(" %%%i", RIG_Node::get(ei)->getValue()->id);
 837       for (Graph::EdgeIterator ei = nodes[i].incident(); !ei.end(); ei.next())
 838          INFO(" %%%i", RIG_Node::get(ei)->getValue()->id);
 839       INFO("\n");
 840    }
 841 }
 842
 843 static bool
 844 isShortRegOp(Instruction *insn)
 845 {
 846    // Immediates are always in src1. Every other situation can be resolved by
 847    // using a long encoding.
 848    return insn->srcExists(1) && insn->src(1).getFile() == FILE_IMMEDIATE;
 849 }
 850
 851 // Check if this LValue is ever used in an instruction that can't be encoded
 852 // with long registers (i.e. > r63)
 853 static bool
 854 isShortRegVal(LValue *lval)
 855 {
 856    if (lval->defs.size() == 0)
 857       return false;
 858    for (Value::DefCIterator def = lval->defs.begin();
 859         def != lval->defs.end(); ++def)
 860       if (isShortRegOp((*def)->getInsn()))
 861          return true;
 862    for (Value::UseCIterator use = lval->uses.begin();
 863         use != lval->uses.end(); ++use)
 864       if (isShortRegOp((*use)->getInsn()))
 865          return true;
 866    return false;
 867 }
 868
 869 void
 870 GCRA::RIG_Node::init(const RegisterSet& regs, LValue *lval)
 871 {
 872    setValue(lval);
 873    if (lval->reg.data.id >= 0)
 874       lval->noSpill = lval->fixedReg = 1;
 875
 876    colors = regs.units(lval->reg.file, lval->reg.size);
 877    f = lval->reg.file;
 878    reg = -1;
 879    if (lval->reg.data.id >= 0)
 880       reg = regs.idToUnits(lval);
 881
 882    weight = std::numeric_limits<float>::infinity();
 883    degree = 0;
 884    int size = regs.getFileSize(f, lval->reg.size);
 885    // On nv50, we lose a bit of gpr encoding when there's an embedded
 886    // immediate.
 887    if (regs.restrictedGPR16Range && f == FILE_GPR && isShortRegVal(lval))
 888       size /= 2;
 889    degreeLimit = size;
 890    degreeLimit -= relDegree[1][colors] - 1;
 891
 892    livei.insert(lval->livei);
 893 }
 894
 895 bool
 896 GCRA::coalesceValues(Value *dst, Value *src, bool force)
 897 {
 898    LValue *rep = dst->join->asLValue();
 899    LValue *val = src->join->asLValue();
 900
 901    if (!force && val->reg.data.id >= 0) {
 902       rep = src->join->asLValue();
 903       val = dst->join->asLValue();
 904    }
 905    RIG_Node *nRep = &nodes[rep->id];
 906    RIG_Node *nVal = &nodes[val->id];
 907
 908    if (src->reg.file != dst->reg.file) {
 909       if (!force)
 910          return false;
 911       WARN("forced coalescing of values in different files !\n");
 912    }
 913    if (!force && dst->reg.size != src->reg.size)
 914       return false;
 915
 916    if ((rep->reg.data.id >= 0) && (rep->reg.data.id != val->reg.data.id)) {
 917       if (force) {
 918          if (val->reg.data.id >= 0)
 919             WARN("forced coalescing of values in different fixed regs !\n");
 920       } else {
 921          if (val->reg.data.id >= 0)
 922             return false;
 923          // make sure that there is no overlap with the fixed register of rep
 924          for (ArrayList::Iterator it = func->allLValues.iterator();
 925               !it.end(); it.next()) {
 926             Value *reg = reinterpret_cast<Value *>(it.get())->asLValue();
 927             assert(reg);
 928             if (reg->interfers(rep) && reg->livei.overlaps(nVal->livei))
 929                return false;
 930          }
 931       }
 932    }
 933
 934    if (!force && nRep->livei.overlaps(nVal->livei))
 935       return false;
 936
 937    INFO_DBG(prog->dbgFlags, REG_ALLOC, "joining %%%i($%i) <- %%%i\n",
 938             rep->id, rep->reg.data.id, val->id);
 939
 940    // set join pointer of all values joined with val
 941    for (Value::DefIterator def = val->defs.begin(); def != val->defs.end();
 942         ++def)
 943       (*def)->get()->join = rep;
 944    assert(rep->join == rep && val->join == rep);
 945
 946    // add val's definitions to rep and extend the live interval of its RIG node
 947    rep->defs.insert(rep->defs.end(), val->defs.begin(), val->defs.end());
 948    nRep->livei.unify(nVal->livei);
 949    return true;
 950 }
 951
 952 bool
 953 GCRA::coalesce(ArrayList& insns)
 954 {
 955    bool ret = doCoalesce(insns, JOIN_MASK_PHI);
 956    if (!ret)
 957       return false;
 958    switch (func->getProgram()->getTarget()->getChipset() & ~0xf) {
 959    case 0x50:
 960    case 0x80:
 961    case 0x90:
 962    case 0xa0:
 963       ret = doCoalesce(insns, JOIN_MASK_UNION | JOIN_MASK_TEX);
 964       break;
 965    case 0xc0:
 966    case 0xd0:
 967    case 0xe0:
 968    case 0xf0:
 969    case 0x100:
 970    case 0x110:
 971       ret = doCoalesce(insns, JOIN_MASK_UNION);
 972       break;
 973    default:
 974       break;
 975    }
 976    if (!ret)
 977       return false;
 978    return doCoalesce(insns, JOIN_MASK_MOV);
 979 }
 980
 981 static inline uint8_t makeCompMask(int compSize, int base, int size)
 982 {
 983    uint8_t m = ((1 << size) - 1) << base;
 984
 985    switch (compSize) {
 986    case 1:
 987       return 0xff;
 988    case 2:
 989       m |= (m << 2);
 990       return (m << 4) | m;
 991    case 3:
 992    case 4:
 993       return (m << 4) | m;
 994    default:
 995       assert(compSize <= 8);
 996       return m;
 997    }
 998 }
 999
1000 // Used when coalescing moves. The non-compound value will become one, e.g.:
1001 // mov b32 $r0 $r2            / merge b64 $r0d { $r0 $r1 }
1002 // split b64 { $r0 $r1 } $r0d / mov b64 $r0d f64 $r2d
1003 static inline void copyCompound(Value *dst, Value *src)
1004 {
1005    LValue *ldst = dst->asLValue();
1006    LValue *lsrc = src->asLValue();
1007
1008    if (ldst->compound && !lsrc->compound) {
1009       LValue *swap = lsrc;
1010       lsrc = ldst;
1011       ldst = swap;
1012    }
1013
1014    ldst->compound = lsrc->compound;
1015    ldst->compMask = lsrc->compMask;
1016 }
1017
1018 void
1019 GCRA::makeCompound(Instruction *insn, bool split)
1020 {
1021    LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue();
1022
1023    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC) {
1024       INFO("makeCompound(split = %i): ", split);
1025       insn->print();
1026    }
1027
1028    const unsigned int size = getNode(rep)->colors;
1029    unsigned int base = 0;
1030
1031    if (!rep->compound)
1032       rep->compMask = 0xff;
1033    rep->compound = 1;
1034
1035    for (int c = 0; split ? insn->defExists(c) : insn->srcExists(c); ++c) {
1036       LValue *val = (split ? insn->getDef(c) : insn->getSrc(c))->asLValue();
1037
1038       val->compound = 1;
1039       if (!val->compMask)
1040          val->compMask = 0xff;
1041       val->compMask &= makeCompMask(size, base, getNode(val)->colors);
1042       assert(val->compMask);
1043
1044       INFO_DBG(prog->dbgFlags, REG_ALLOC, "compound: %%%i:%02x <- %%%i:%02x\n",
1045            rep->id, rep->compMask, val->id, val->compMask);
1046
1047       base += getNode(val)->colors;
1048    }
1049    assert(base == size);
1050 }
1051
1052 bool
1053 GCRA::doCoalesce(ArrayList& insns, unsigned int mask)
1054 {
1055    int c, n;
1056
1057    for (n = 0; n < insns.getSize(); ++n) {
1058       Instruction *i;
1059       Instruction *insn = reinterpret_cast<Instruction *>(insns.get(n));
1060
1061       switch (insn->op) {
1062       case OP_PHI:
1063          if (!(mask & JOIN_MASK_PHI))
1064             break;
1065          for (c = 0; insn->srcExists(c); ++c)
1066             if (!coalesceValues(insn->getDef(0), insn->getSrc(c), false)) {
1067                // this is bad
1068                ERROR("failed to coalesce phi operands\n");
1069                return false;
1070             }
1071          break;
1072       case OP_UNION:
1073       case OP_MERGE:
1074          if (!(mask & JOIN_MASK_UNION))
1075             break;
1076          for (c = 0; insn->srcExists(c); ++c)
1077             coalesceValues(insn->getDef(0), insn->getSrc(c), true);
1078          if (insn->op == OP_MERGE) {
1079             merges.push_back(insn);
1080             if (insn->srcExists(1))
1081                makeCompound(insn, false);
1082          }
1083          break;
1084       case OP_SPLIT:
1085          if (!(mask & JOIN_MASK_UNION))
1086             break;
1087          splits.push_back(insn);
1088          for (c = 0; insn->defExists(c); ++c)
1089             coalesceValues(insn->getSrc(0), insn->getDef(c), true);
1090          makeCompound(insn, true);
1091          break;
1092       case OP_MOV:
1093          if (!(mask & JOIN_MASK_MOV))
1094             break;
1095          i = NULL;
1096          if (!insn->getDef(0)->uses.empty())
1097             i = (*insn->getDef(0)->uses.begin())->getInsn();
1098          // if this is a contraint-move there will only be a single use
1099          if (i && i->op == OP_MERGE) // do we really still need this ?
1100             break;
1101          i = insn->getSrc(0)->getUniqueInsn();
1102          if (i && !i->constrainedDefs()) {
1103             if (coalesceValues(insn->getDef(0), insn->getSrc(0), false))
1104                copyCompound(insn->getSrc(0), insn->getDef(0));
1105          }
1106          break;
1107       case OP_TEX:
1108       case OP_TXB:
1109       case OP_TXL:
1110       case OP_TXF:
1111       case OP_TXQ:
1112       case OP_TXD:
1113       case OP_TXG:
1114       case OP_TXLQ:
1115       case OP_TEXCSAA:
1116       case OP_TEXPREP:
1117          if (!(mask & JOIN_MASK_TEX))
1118             break;
1119          for (c = 0; insn->srcExists(c) && c != insn->predSrc; ++c)
1120             coalesceValues(insn->getDef(c), insn->getSrc(c), true);
1121          break;
1122       default:
1123          break;
1124       }
1125    }
1126    return true;
1127 }
1128
1129 void
1130 GCRA::RIG_Node::addInterference(RIG_Node *node)
1131 {
1132    this->degree += relDegree[node->colors][colors];
1133    node->degree += relDegree[colors][node->colors];
1134
1135    this->attach(node, Graph::Edge::CROSS);
1136 }
1137
1138 void
1139 GCRA::RIG_Node::addRegPreference(RIG_Node *node)
1140 {
1141    prefRegs.push_back(node);
1142 }
1143
1144 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) :
1145    func(fn),
1146    regs(fn->getProgram()->getTarget()),
1147    spill(spill)
1148 {
1149    prog = func->getProgram();
1150
1151    // initialize relative degrees array - i takes away from j
1152    for (int i = 1; i <= 16; ++i)
1153       for (int j = 1; j <= 16; ++j)
1154          relDegree[i][j] = j * ((i + j - 1) / j);
1155 }
1156
1157 GCRA::~GCRA()
1158 {
1159    if (nodes)
1160       delete[] nodes;
1161 }
1162
1163 void
1164 GCRA::checkList(std::list<RIG_Node *>& lst)
1165 {
1166    GCRA::RIG_Node *prev = NULL;
1167
1168    for (std::list<RIG_Node *>::iterator it = lst.begin();
1169         it != lst.end();
1170         ++it) {
1171       assert((*it)->getValue()->join == (*it)->getValue());
1172       if (prev)
1173          assert(prev->livei.begin() <= (*it)->livei.begin());
1174       prev = *it;
1175    }
1176 }
1177
1178 void
1179 GCRA::insertOrderedTail(std::list<RIG_Node *>& list, RIG_Node *node)
1180 {
1181    if (node->livei.isEmpty())
1182       return;
1183    // only the intervals of joined values don't necessarily arrive in order
1184    std::list<RIG_Node *>::iterator prev, it;
1185    for (it = list.end(); it != list.begin(); it = prev) {
1186       prev = it;
1187       --prev;
1188       if ((*prev)->livei.begin() <= node->livei.begin())
1189          break;
1190    }
1191    list.insert(it, node);
1192 }
1193
1194 void
1195 GCRA::buildRIG(ArrayList& insns)
1196 {
1197    std::list<RIG_Node *> values, active;
1198
1199    for (std::deque<ValueDef>::iterator it = func->ins.begin();
1200         it != func->ins.end(); ++it)
1201       insertOrderedTail(values, getNode(it->get()->asLValue()));
1202
1203    for (int i = 0; i < insns.getSize(); ++i) {
1204       Instruction *insn = reinterpret_cast<Instruction *>(insns.get(i));
1205       for (int d = 0; insn->defExists(d); ++d)
1206          if (insn->getDef(d)->rep() == insn->getDef(d))
1207             insertOrderedTail(values, getNode(insn->getDef(d)->asLValue()));
1208    }
1209    checkList(values);
1210
1211    while (!values.empty()) {
1212       RIG_Node *cur = values.front();
1213
1214       for (std::list<RIG_Node *>::iterator it = active.begin();
1215            it != active.end();) {
1216          RIG_Node *node = *it;
1217
1218          if (node->livei.end() <= cur->livei.begin()) {
1219             it = active.erase(it);
1220          } else {
1221             if (node->f == cur->f && node->livei.overlaps(cur->livei))
1222                cur->addInterference(node);
1223             ++it;
1224          }
1225       }
1226       values.pop_front();
1227       active.push_back(cur);
1228    }
1229 }
1230
1231 void
1232 GCRA::calculateSpillWeights()
1233 {
1234    for (unsigned int i = 0; i < nodeCount; ++i) {
1235       RIG_Node *const n = &nodes[i];
1236       if (!nodes[i].colors || nodes[i].livei.isEmpty())
1237          continue;
1238       if (nodes[i].reg >= 0) {
1239          // update max reg
1240          regs.occupy(n->f, n->reg, n->colors);
1241          continue;
1242       }
1243       LValue *val = nodes[i].getValue();
1244
1245       if (!val->noSpill) {
1246          int rc = 0;
1247          for (Value::DefIterator it = val->defs.begin();
1248               it != val->defs.end();
1249               ++it)
1250             rc += (*it)->get()->refCount();
1251
1252          nodes[i].weight =
1253             (float)rc * (float)rc / (float)nodes[i].livei.extent();
1254       }
1255
1256       if (nodes[i].degree < nodes[i].degreeLimit) {
1257          int l = 0;
1258          if (val->reg.size > 4)
1259             l = 1;
1260          DLLIST_ADDHEAD(&lo[l], &nodes[i]);
1261       } else {
1262          DLLIST_ADDHEAD(&hi, &nodes[i]);
1263       }
1264    }
1265    if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1266       printNodeInfo();
1267 }
1268
1269 void
1270 GCRA::simplifyEdge(RIG_Node *a, RIG_Node *b)
1271 {
1272    bool move = b->degree >= b->degreeLimit;
1273
1274    INFO_DBG(prog->dbgFlags, REG_ALLOC,
1275             "edge: (%%%i, deg %u/%u) >-< (%%%i, deg %u/%u)\n",
1276             a->getValue()->id, a->degree, a->degreeLimit,
1277             b->getValue()->id, b->degree, b->degreeLimit);
1278
1279    b->degree -= relDegree[a->colors][b->colors];
1280
1281    move = move && b->degree < b->degreeLimit;
1282    if (move && !DLLIST_EMPTY(b)) {
1283       int l = (b->getValue()->reg.size > 4) ? 1 : 0;
1284       DLLIST_DEL(b);
1285       DLLIST_ADDTAIL(&lo[l], b);
1286    }
1287 }
1288
1289 void
1290 GCRA::simplifyNode(RIG_Node *node)
1291 {
1292    for (Graph::EdgeIterator ei = node->outgoing(); !ei.end(); ei.next())
1293       simplifyEdge(node, RIG_Node::get(ei));
1294
1295    for (Graph::EdgeIterator ei = node->incident(); !ei.end(); ei.next())
1296       simplifyEdge(node, RIG_Node::get(ei));
1297
1298    DLLIST_DEL(node);
1299    stack.push(node->getValue()->id);
1300
1301    INFO_DBG(prog->dbgFlags, REG_ALLOC, "SIMPLIFY: pushed %%%i%s\n",
1302             node->getValue()->id,
1303             (node->degree < node->degreeLimit) ? "" : "(spill)");
1304 }
1305
1306 void
1307 GCRA::simplify()
1308 {
1309    for (;;) {
1310       if (!DLLIST_EMPTY(&lo[0])) {
1311          do {
1312             simplifyNode(lo[0].next);
1313          } while (!DLLIST_EMPTY(&lo[0]));
1314       } else
1315       if (!DLLIST_EMPTY(&lo[1])) {
1316          simplifyNode(lo[1].next);
1317       } else
1318       if (!DLLIST_EMPTY(&hi)) {
1319          RIG_Node *best = hi.next;
1320          float bestScore = best->weight / (float)best->degree;
1321          // spill candidate
1322          for (RIG_Node *it = best->next; it != &hi; it = it->next) {
1323             float score = it->weight / (float)it->degree;
1324             if (score < bestScore) {
1325                best = it;
1326                bestScore = score;
1327             }
1328          }
1329          if (isinf(bestScore)) {
1330             ERROR("no viable spill candidates left\n");
1331             break;
1332          }
1333          simplifyNode(best);
1334       } else {
1335          break;
1336       }
1337    }
1338 }
1339
1340 void
1341 GCRA::checkInterference(const RIG_Node *node, Graph::EdgeIterator& ei)
1342 {
1343    const RIG_Node *intf = RIG_Node::get(ei);
1344
1345    if (intf->reg < 0)
1346       return;
1347    const LValue *vA = node->getValue();
1348    const LValue *vB = intf->getValue();
1349
1350    const uint8_t intfMask = ((1 << intf->colors) - 1) << (intf->reg & 7);
1351
1352    if (vA->compound | vB->compound) {
1353       // NOTE: this only works for >aligned< register tuples !
1354       for (Value::DefCIterator D = vA->defs.begin(); D != vA->defs.end(); ++D) {
1355       for (Value::DefCIterator d = vB->defs.begin(); d != vB->defs.end(); ++d) {
1356          const LValue *vD = (*D)->get()->asLValue();
1357          const LValue *vd = (*d)->get()->asLValue();
1358
1359          if (!vD->livei.overlaps(vd->livei)) {
1360             INFO_DBG(prog->dbgFlags, REG_ALLOC, "(%%%i) X (%%%i): no overlap\n",
1361                      vD->id, vd->id);
1362             continue;
1363          }
1364
1365          uint8_t mask = vD->compound ? vD->compMask : ~0;
1366          if (vd->compound) {
1367             assert(vB->compound);
1368             mask &= vd->compMask & vB->compMask;
1369          } else {
1370             mask &= intfMask;
1371          }
1372
1373          INFO_DBG(prog->dbgFlags, REG_ALLOC,
1374                   "(%%%i)%02x X (%%%i)%02x & %02x: $r%i.%02x\n",
1375                   vD->id,
1376                   vD->compound ? vD->compMask : 0xff,
1377                   vd->id,
1378                   vd->compound ? vd->compMask : intfMask,
1379                   vB->compMask, intf->reg & ~7, mask);
1380          if (mask)
1381             regs.occupyMask(node->f, intf->reg & ~7, mask);
1382       }
1383       }
1384    } else {
1385       INFO_DBG(prog->dbgFlags, REG_ALLOC,
1386                "(%%%i) X (%%%i): $r%i + %u\n",
1387                vA->id, vB->id, intf->reg, intf->colors);
1388       regs.occupy(node->f, intf->reg, intf->colors);
1389    }
1390 }
1391
1392 bool
1393 GCRA::selectRegisters()
1394 {
1395    INFO_DBG(prog->dbgFlags, REG_ALLOC, "\nSELECT phase\n");
1396
1397    while (!stack.empty()) {
1398       RIG_Node *node = &nodes[stack.top()];
1399       stack.pop();
1400
1401       regs.reset(node->f);
1402
1403       INFO_DBG(prog->dbgFlags, REG_ALLOC, "\nNODE[%%%i, %u colors]\n",
1404                node->getValue()->id, node->colors);
1405
1406       for (Graph::EdgeIterator ei = node->outgoing(); !ei.end(); ei.next())
1407          checkInterference(node, ei);
1408       for (Graph::EdgeIterator ei = node->incident(); !ei.end(); ei.next())
1409          checkInterference(node, ei);
1410
1411       if (!node->prefRegs.empty()) {
1412          for (std::list<RIG_Node *>::const_iterator it = node->prefRegs.begin();
1413               it != node->prefRegs.end();
1414               ++it) {
1415             if ((*it)->reg >= 0 &&
1416                 regs.testOccupy(node->f, (*it)->reg, node->colors)) {
1417                node->reg = (*it)->reg;
1418                break;
1419             }
1420          }
1421       }
1422       if (node->reg >= 0)
1423          continue;
1424       LValue *lval = node->getValue();
1425       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1426          regs.print();
1427       bool ret = regs.assign(node->reg, node->f, node->colors);
1428       if (ret) {
1429          INFO_DBG(prog->dbgFlags, REG_ALLOC, "assigned reg %i\n", node->reg);
1430          lval->compMask = node->getCompMask();
1431       } else {
1432          INFO_DBG(prog->dbgFlags, REG_ALLOC, "must spill: %%%i (size %u)\n",
1433                   lval->id, lval->reg.size);
1434          Symbol *slot = NULL;
1435          if (lval->reg.file == FILE_GPR)
1436             slot = spill.assignSlot(node->livei, lval->reg.size);
1437          mustSpill.push_back(ValuePair(lval, slot));
1438       }
1439    }
1440    if (!mustSpill.empty())
1441       return false;
1442    for (unsigned int i = 0; i < nodeCount; ++i) {
1443       LValue *lval = nodes[i].getValue();
1444       if (nodes[i].reg >= 0 && nodes[i].colors > 0)
1445          lval->reg.data.id =
1446             regs.unitsToId(nodes[i].f, nodes[i].reg, lval->reg.size);
1447    }
1448    return true;
1449 }
1450
1451 bool
1452 GCRA::allocateRegisters(ArrayList& insns)
1453 {
1454    bool ret;
1455
1456    INFO_DBG(prog->dbgFlags, REG_ALLOC,
1457             "allocateRegisters to %u instructions\n", insns.getSize());
1458
1459    nodeCount = func->allLValues.getSize();
1460    nodes = new RIG_Node[nodeCount];
1461    if (!nodes)
1462       return false;
1463    for (unsigned int i = 0; i < nodeCount; ++i) {
1464       LValue *lval = reinterpret_cast<LValue *>(func->allLValues.get(i));
1465       if (lval) {
1466          nodes[i].init(regs, lval);
1467          RIG.insert(&nodes[i]);
1468
1469          if (lval->inFile(FILE_GPR) && lval->defs.size() > 0 &&
1470              prog->getTarget()->getChipset() < 0xc0) {
1471             Instruction *insn = lval->getInsn();
1472             if (insn->op == OP_MAD || insn->op == OP_SAD)
1473                // Short encoding only possible if they're all GPRs, no need to
1474                // affect them otherwise.
1475                if (insn->flagsDef < 0 &&
1476                    insn->src(0).getFile() == FILE_GPR &&
1477                    insn->src(1).getFile() == FILE_GPR &&
1478                    insn->src(2).getFile() == FILE_GPR)
1479                   nodes[i].addRegPreference(getNode(insn->getSrc(2)->asLValue()));
1480          }
1481       }
1482    }
1483
1484    // coalesce first, we use only 1 RIG node for a group of joined values
1485    ret = coalesce(insns);
1486    if (!ret)
1487       goto out;
1488
1489    if (func->getProgram()->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1490       func->printLiveIntervals();
1491
1492    buildRIG(insns);
1493    calculateSpillWeights();
1494    simplify();
1495
1496    ret = selectRegisters();
1497    if (!ret) {
1498       INFO_DBG(prog->dbgFlags, REG_ALLOC,
1499                "selectRegisters failed, inserting spill code ...\n");
1500       regs.reset(FILE_GPR, true);
1501       spill.run(mustSpill);
1502       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1503          func->print();
1504    } else {
1505       prog->maxGPR = std::max(prog->maxGPR, regs.getMaxAssigned(FILE_GPR));
1506    }
1507
1508 out:
1509    cleanup(ret);
1510    return ret;
1511 }
1512
1513 void
1514 GCRA::cleanup(const bool success)
1515 {
1516    mustSpill.clear();
1517
1518    for (ArrayList::Iterator it = func->allLValues.iterator();
1519         !it.end(); it.next()) {
1520       LValue *lval =  reinterpret_cast<LValue *>(it.get());
1521
1522       lval->livei.clear();
1523
1524       lval->compound = 0;
1525       lval->compMask = 0;
1526
1527       if (lval->join == lval)
1528          continue;
1529
1530       if (success) {
1531          lval->reg.data.id = lval->join->reg.data.id;
1532       } else {
1533          for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
1534               ++d)
1535             lval->join->defs.remove(*d);
1536          lval->join = lval;
1537       }
1538    }
1539
1540    if (success)
1541       resolveSplitsAndMerges();
1542    splits.clear(); // avoid duplicate entries on next coalesce pass
1543    merges.clear();
1544
1545    delete[] nodes;
1546    nodes = NULL;
1547 }
1548
1549 Symbol *
1550 SpillCodeInserter::assignSlot(const Interval &livei, const unsigned int size)
1551 {
1552    SpillSlot slot;
1553    int32_t offsetBase = stackSize;
1554    int32_t offset;
1555    std::list<SpillSlot>::iterator pos = slots.end(), it = slots.begin();
1556
1557    if (offsetBase % size)
1558       offsetBase += size - (offsetBase % size);
1559
1560    slot.sym = NULL;
1561
1562    for (offset = offsetBase; offset < stackSize; offset += size) {
1563       const int32_t entryEnd = offset + size;
1564       while (it != slots.end() && it->offset < offset)
1565          ++it;
1566       if (it == slots.end()) // no slots left
1567          break;
1568       std::list<SpillSlot>::iterator bgn = it;
1569
1570       while (it != slots.end() && it->offset < entryEnd) {
1571          it->occup.print();
1572          if (it->occup.overlaps(livei))
1573             break;
1574          ++it;
1575       }
1576       if (it == slots.end() || it->offset >= entryEnd) {
1577          // fits
1578          for (; bgn != slots.end() && bgn->offset < entryEnd; ++bgn) {
1579             bgn->occup.insert(livei);
1580             if (bgn->size() == size)
1581                slot.sym = bgn->sym;
1582          }
1583          break;
1584       }
1585    }
1586    if (!slot.sym) {
1587       stackSize = offset + size;
1588       slot.offset = offset;
1589       slot.sym = new_Symbol(func->getProgram(), FILE_MEMORY_LOCAL);
1590       if (!func->stackPtr)
1591          offset += func->tlsBase;
1592       slot.sym->setAddress(NULL, offset);
1593       slot.sym->reg.size = size;
1594       slots.insert(pos, slot)->occup.insert(livei);
1595    }
1596    return slot.sym;
1597 }
1598
1599 Value *
1600 SpillCodeInserter::offsetSlot(Value *base, const LValue *lval)
1601 {
1602    if (!lval->compound || (lval->compMask & 0x1))
1603       return base;
1604    Value *slot = cloneShallow(func, base);
1605
1606    slot->reg.data.offset += (ffs(lval->compMask) - 1) * lval->reg.size;
1607    slot->reg.size = lval->reg.size;
1608
1609    return slot;
1610 }
1611
1612 void
1613 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval)
1614 {
1615    const DataType ty = typeOfSize(lval->reg.size);
1616
1617    slot = offsetSlot(slot, lval);
1618
1619    Instruction *st;
1620    if (slot->reg.file == FILE_MEMORY_LOCAL) {
1621       lval->noSpill = 1;
1622       if (ty != TYPE_B96) {
1623          st = new_Instruction(func, OP_STORE, ty);
1624          st->setSrc(0, slot);
1625          st->setSrc(1, lval);
1626       } else {
1627          st = new_Instruction(func, OP_SPLIT, ty);
1628          st->setSrc(0, lval);
1629          for (int d = 0; d < lval->reg.size / 4; ++d)
1630             st->setDef(d, new_LValue(func, FILE_GPR));
1631
1632          for (int d = lval->reg.size / 4 - 1; d >= 0; --d) {
1633             Value *tmp = cloneShallow(func, slot);
1634             tmp->reg.size = 4;
1635             tmp->reg.data.offset += 4 * d;
1636
1637             Instruction *s = new_Instruction(func, OP_STORE, TYPE_U32);
1638             s->setSrc(0, tmp);
1639             s->setSrc(1, st->getDef(d));
1640             defi->bb->insertAfter(defi, s);
1641          }
1642       }
1643    } else {
1644       st = new_Instruction(func, OP_CVT, ty);
1645       st->setDef(0, slot);
1646       st->setSrc(0, lval);
1647       if (lval->reg.file == FILE_FLAGS)
1648          st->flagsSrc = 0;
1649    }
1650    defi->bb->insertAfter(defi, st);
1651 }
1652
1653 LValue *
1654 SpillCodeInserter::unspill(Instruction *usei, LValue *lval, Value *slot)
1655 {
1656    const DataType ty = typeOfSize(lval->reg.size);
1657
1658    slot = offsetSlot(slot, lval);
1659    lval = cloneShallow(func, lval);
1660
1661    Instruction *ld;
1662    if (slot->reg.file == FILE_MEMORY_LOCAL) {
1663       lval->noSpill = 1;
1664       if (ty != TYPE_B96) {
1665          ld = new_Instruction(func, OP_LOAD, ty);
1666       } else {
1667          ld = new_Instruction(func, OP_MERGE, ty);
1668          for (int d = 0; d < lval->reg.size / 4; ++d) {
1669             Value *tmp = cloneShallow(func, slot);
1670             LValue *val;
1671             tmp->reg.size = 4;
1672             tmp->reg.data.offset += 4 * d;
1673
1674             Instruction *l = new_Instruction(func, OP_LOAD, TYPE_U32);
1675             l->setDef(0, (val = new_LValue(func, FILE_GPR)));
1676             l->setSrc(0, tmp);
1677             usei->bb->insertBefore(usei, l);
1678             ld->setSrc(d, val);
1679             val->noSpill = 1;
1680          }
1681          ld->setDef(0, lval);
1682          usei->bb->insertBefore(usei, ld);
1683          return lval;
1684       }
1685    } else {
1686       ld = new_Instruction(func, OP_CVT, ty);
1687    }
1688    ld->setDef(0, lval);
1689    ld->setSrc(0, slot);
1690    if (lval->reg.file == FILE_FLAGS)
1691       ld->flagsDef = 0;
1692
1693    usei->bb->insertBefore(usei, ld);
1694    return lval;
1695 }
1696
1697 static bool
1698 value_cmp(ValueRef *a, ValueRef *b) {
1699    Instruction *ai = a->getInsn(), *bi = b->getInsn();
1700    if (ai->bb != bi->bb)
1701       return ai->bb->getId() < bi->bb->getId();
1702    return ai->serial < bi->serial;
1703 }
1704
1705 // For each value that is to be spilled, go through all its definitions.
1706 // A value can have multiple definitions if it has been coalesced before.
1707 // For each definition, first go through all its uses and insert an unspill
1708 // instruction before it, then replace the use with the temporary register.
1709 // Unspill can be either a load from memory or simply a move to another
1710 // register file.
1711 // For "Pseudo" instructions (like PHI, SPLIT, MERGE) we can erase the use
1712 // if we have spilled to a memory location, or simply with the new register.
1713 // No load or conversion instruction should be needed.
1714 bool
1715 SpillCodeInserter::run(const std::list<ValuePair>& lst)
1716 {
1717    for (std::list<ValuePair>::const_iterator it = lst.begin(); it != lst.end();
1718         ++it) {
1719       LValue *lval = it->first->asLValue();
1720       Symbol *mem = it->second ? it->second->asSym() : NULL;
1721
1722       // Keep track of which instructions to delete later. Deleting them
1723       // inside the loop is unsafe since a single instruction may have
1724       // multiple destinations that all need to be spilled (like OP_SPLIT).
1725       unordered_set<Instruction *> to_del;
1726
1727       for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
1728            ++d) {
1729          Value *slot = mem ?
1730             static_cast<Value *>(mem) : new_LValue(func, FILE_GPR);
1731          Value *tmp = NULL;
1732          Instruction *last = NULL;
1733
1734          LValue *dval = (*d)->get()->asLValue();
1735          Instruction *defi = (*d)->getInsn();
1736
1737          // Sort all the uses by BB/instruction so that we don't unspill
1738          // multiple times in a row, and also remove a source of
1739          // non-determinism.
1740          std::vector<ValueRef *> refs(dval->uses.begin(), dval->uses.end());
1741          std::sort(refs.begin(), refs.end(), value_cmp);
1742
1743          // Unspill at each use *before* inserting spill instructions,
1744          // we don't want to have the spill instructions in the use list here.
1745          for (std::vector<ValueRef*>::const_iterator it = refs.begin();
1746               it != refs.end(); ++it) {
1747             ValueRef *u = *it;
1748             Instruction *usei = u->getInsn();
1749             assert(usei);
1750             if (usei->isPseudo()) {
1751                tmp = (slot->reg.file == FILE_MEMORY_LOCAL) ? NULL : slot;
1752                last = NULL;
1753             } else {
1754                if (!last || (usei != last->next && usei != last))
1755                   tmp = unspill(usei, dval, slot);
1756                last = usei;
1757             }
1758             u->set(tmp);
1759          }
1760
1761          assert(defi);
1762          if (defi->isPseudo()) {
1763             d = lval->defs.erase(d);
1764             --d;
1765             if (slot->reg.file == FILE_MEMORY_LOCAL)
1766                to_del.insert(defi);
1767             else
1768                defi->setDef(0, slot);
1769          } else {
1770             spill(defi, slot, dval);
1771          }
1772       }
1773
1774       for (unordered_set<Instruction *>::const_iterator it = to_del.begin();
1775            it != to_del.end(); ++it)
1776          delete_Instruction(func->getProgram(), *it);
1777    }
1778
1779    // TODO: We're not trying to reuse old slots in a potential next iteration.
1780    //  We have to update the slots' livei intervals to be able to do that.
1781    stackBase = stackSize;
1782    slots.clear();
1783    return true;
1784 }
1785
1786 bool
1787 RegAlloc::exec()
1788 {
1789    for (IteratorRef it = prog->calls.iteratorDFS(false);
1790         !it->end(); it->next()) {
1791       func = Function::get(reinterpret_cast<Graph::Node *>(it->get()));
1792
1793       func->tlsBase = prog->tlsSize;
1794       if (!execFunc())
1795          return false;
1796       prog->tlsSize += func->tlsSize;
1797    }
1798    return true;
1799 }
1800
1801 bool
1802 RegAlloc::execFunc()
1803 {
1804    InsertConstraintsPass insertConstr;
1805    PhiMovesPass insertPhiMoves;
1806    ArgumentMovesPass insertArgMoves;
1807    BuildIntervalsPass buildIntervals;
1808    SpillCodeInserter insertSpills(func);
1809
1810    GCRA gcra(func, insertSpills);
1811
1812    unsigned int i, retries;
1813    bool ret;
1814
1815    if (!func->ins.empty()) {
1816       // Insert a nop at the entry so inputs only used by the first instruction
1817       // don't count as having an empty live range.
1818       Instruction *nop = new_Instruction(func, OP_NOP, TYPE_NONE);
1819       BasicBlock::get(func->cfg.getRoot())->insertHead(nop);
1820    }
1821
1822    ret = insertConstr.exec(func);
1823    if (!ret)
1824       goto out;
1825
1826    ret = insertPhiMoves.run(func);
1827    if (!ret)
1828       goto out;
1829
1830    ret = insertArgMoves.run(func);
1831    if (!ret)
1832       goto out;
1833
1834    // TODO: need to fix up spill slot usage ranges to support > 1 retry
1835    for (retries = 0; retries < 3; ++retries) {
1836       if (retries && (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC))
1837          INFO("Retry: %i\n", retries);
1838       if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
1839          func->print();
1840
1841       // spilling to registers may add live ranges, need to rebuild everything
1842       ret = true;
1843       for (sequence = func->cfg.nextSequence(), i = 0;
1844            ret && i <= func->loopNestingBound;
1845            sequence = func->cfg.nextSequence(), ++i)
1846          ret = buildLiveSets(BasicBlock::get(func->cfg.getRoot()));
1847       // reset marker
1848       for (ArrayList::Iterator bi = func->allBBlocks.iterator();
1849            !bi.end(); bi.next())
1850          BasicBlock::get(bi)->liveSet.marker = false;
1851       if (!ret)
1852          break;
1853       func->orderInstructions(this->insns);
1854
1855       ret = buildIntervals.run(func);
1856       if (!ret)
1857          break;
1858       ret = gcra.allocateRegisters(insns);
1859       if (ret)
1860          break; // success
1861    }
1862    INFO_DBG(prog->dbgFlags, REG_ALLOC, "RegAlloc done: %i\n", ret);
1863
1864    func->tlsSize = insertSpills.getStackSize();
1865 out:
1866    return ret;
1867 }
1868
1869 // TODO: check if modifying Instruction::join here breaks anything
1870 void
1871 GCRA::resolveSplitsAndMerges()
1872 {
1873    for (std::list<Instruction *>::iterator it = splits.begin();
1874         it != splits.end();
1875         ++it) {
1876       Instruction *split = *it;
1877       unsigned int reg = regs.idToBytes(split->getSrc(0));
1878       for (int d = 0; split->defExists(d); ++d) {
1879          Value *v = split->getDef(d);
1880          v->reg.data.id = regs.bytesToId(v, reg);
1881          v->join = v;
1882          reg += v->reg.size;
1883       }
1884    }
1885    splits.clear();
1886
1887    for (std::list<Instruction *>::iterator it = merges.begin();
1888         it != merges.end();
1889         ++it) {
1890       Instruction *merge = *it;
1891       unsigned int reg = regs.idToBytes(merge->getDef(0));
1892       for (int s = 0; merge->srcExists(s); ++s) {
1893          Value *v = merge->getSrc(s);
1894          v->reg.data.id = regs.bytesToId(v, reg);
1895          v->join = v;
1896          // If the value is defined by a phi/union node, we also need to
1897          // perform the same fixup on that node's sources, since after RA
1898          // their registers should be identical.
1899          if (v->getInsn()->op == OP_PHI || v->getInsn()->op == OP_UNION) {
1900             Instruction *phi = v->getInsn();
1901             for (int phis = 0; phi->srcExists(phis); ++phis)
1902                phi->getSrc(phis)->join = v;
1903          }
1904          reg += v->reg.size;
1905       }
1906    }
1907    merges.clear();
1908 }
1909
1910 bool Program::registerAllocation()
1911 {
1912    RegAlloc ra(this);
1913    return ra.exec();
1914 }
1915
1916 bool
1917 RegAlloc::InsertConstraintsPass::exec(Function *ir)
1918 {
1919    constrList.clear();
1920
1921    bool ret = run(ir, true, true);
1922    if (ret)
1923       ret = insertConstraintMoves();
1924    return ret;
1925 }
1926
1927 // TODO: make part of texture insn
1928 void
1929 RegAlloc::InsertConstraintsPass::textureMask(TexInstruction *tex)
1930 {
1931    Value *def[4];
1932    int c, k, d;
1933    uint8_t mask = 0;
1934
1935    for (d = 0, k = 0, c = 0; c < 4; ++c) {
1936       if (!(tex->tex.mask & (1 << c)))
1937          continue;
1938       if (tex->getDef(k)->refCount()) {
1939          mask |= 1 << c;
1940          def[d++] = tex->getDef(k);
1941       }
1942       ++k;
1943    }
1944    tex->tex.mask = mask;
1945
1946    for (c = 0; c < d; ++c)
1947       tex->setDef(c, def[c]);
1948    for (; c < 4; ++c)
1949       tex->setDef(c, NULL);
1950 }
1951
1952 bool
1953 RegAlloc::InsertConstraintsPass::detectConflict(Instruction *cst, int s)
1954 {
1955    Value *v = cst->getSrc(s);
1956
1957    // current register allocation can't handle it if a value participates in
1958    // multiple constraints
1959    for (Value::UseIterator it = v->uses.begin(); it != v->uses.end(); ++it) {
1960       if (cst != (*it)->getInsn())
1961          return true;
1962    }
1963
1964    // can start at s + 1 because detectConflict is called on all sources
1965    for (int c = s + 1; cst->srcExists(c); ++c)
1966       if (v == cst->getSrc(c))
1967          return true;
1968
1969    Instruction *defi = v->getInsn();
1970
1971    return (!defi || defi->constrainedDefs());
1972 }
1973
1974 void
1975 RegAlloc::InsertConstraintsPass::addConstraint(Instruction *i, int s, int n)
1976 {
1977    Instruction *cst;
1978    int d;
1979
1980    // first, look for an existing identical constraint op
1981    for (std::list<Instruction *>::iterator it = constrList.begin();
1982         it != constrList.end();
1983         ++it) {
1984       cst = (*it);
1985       if (!i->bb->dominatedBy(cst->bb))
1986          break;
1987       for (d = 0; d < n; ++d)
1988          if (cst->getSrc(d) != i->getSrc(d + s))
1989             break;
1990       if (d >= n) {
1991          for (d = 0; d < n; ++d, ++s)
1992             i->setSrc(s, cst->getDef(d));
1993          return;
1994       }
1995    }
1996    cst = new_Instruction(func, OP_CONSTRAINT, i->dType);
1997
1998    for (d = 0; d < n; ++s, ++d) {
1999       cst->setDef(d, new_LValue(func, FILE_GPR));
2000       cst->setSrc(d, i->getSrc(s));
2001       i->setSrc(s, cst->getDef(d));
2002    }
2003    i->bb->insertBefore(i, cst);
2004
2005    constrList.push_back(cst);
2006 }
2007
2008 // Add a dummy use of the pointer source of >= 8 byte loads after the load
2009 // to prevent it from being assigned a register which overlapping the load's
2010 // destination, which would produce random corruptions.
2011 void
2012 RegAlloc::InsertConstraintsPass::addHazard(Instruction *i, const ValueRef *src)
2013 {
2014    Instruction *hzd = new_Instruction(func, OP_NOP, TYPE_NONE);
2015    hzd->setSrc(0, src->get());
2016    i->bb->insertAfter(i, hzd);
2017
2018 }
2019
2020 // b32 { %r0 %r1 %r2 %r3 } -> b128 %r0q
2021 void
2022 RegAlloc::InsertConstraintsPass::condenseDefs(Instruction *insn)
2023 {
2024    uint8_t size = 0;
2025    int n;
2026    for (n = 0; insn->defExists(n) && insn->def(n).getFile() == FILE_GPR; ++n)
2027       size += insn->getDef(n)->reg.size;
2028    if (n < 2)
2029       return;
2030    LValue *lval = new_LValue(func, FILE_GPR);
2031    lval->reg.size = size;
2032
2033    Instruction *split = new_Instruction(func, OP_SPLIT, typeOfSize(size));
2034    split->setSrc(0, lval);
2035    for (int d = 0; d < n; ++d) {
2036       split->setDef(d, insn->getDef(d));
2037       insn->setDef(d, NULL);
2038    }
2039    insn->setDef(0, lval);
2040
2041    for (int k = 1, d = n; insn->defExists(d); ++d, ++k) {
2042       insn->setDef(k, insn->getDef(d));
2043       insn->setDef(d, NULL);
2044    }
2045    // carry over predicate if any (mainly for OP_UNION uses)
2046    split->setPredicate(insn->cc, insn->getPredicate());
2047
2048    insn->bb->insertAfter(insn, split);
2049    constrList.push_back(split);
2050 }
2051 void
2052 RegAlloc::InsertConstraintsPass::condenseSrcs(Instruction *insn,
2053                                               const int a, const int b)
2054 {
2055    uint8_t size = 0;
2056    if (a >= b)
2057       return;
2058    for (int s = a; s <= b; ++s)
2059       size += insn->getSrc(s)->reg.size;
2060    if (!size)
2061       return;
2062    LValue *lval = new_LValue(func, FILE_GPR);
2063    lval->reg.size = size;
2064
2065    Value *save[3];
2066    insn->takeExtraSources(0, save);
2067
2068    Instruction *merge = new_Instruction(func, OP_MERGE, typeOfSize(size));
2069    merge->setDef(0, lval);
2070    for (int s = a, i = 0; s <= b; ++s, ++i) {
2071       merge->setSrc(i, insn->getSrc(s));
2072       insn->setSrc(s, NULL);
2073    }
2074    insn->setSrc(a, lval);
2075
2076    for (int k = a + 1, s = b + 1; insn->srcExists(s); ++s, ++k) {
2077       insn->setSrc(k, insn->getSrc(s));
2078       insn->setSrc(s, NULL);
2079    }
2080    insn->bb->insertBefore(insn, merge);
2081
2082    insn->putExtraSources(0, save);
2083
2084    constrList.push_back(merge);
2085 }
2086
2087 void
2088 RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex)
2089 {
2090    int n, s;
2091
2092    if (isTextureOp(tex->op))
2093       textureMask(tex);
2094    condenseDefs(tex);
2095
2096    if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2097       condenseSrcs(tex, 3, (3 + typeSizeof(tex->dType) / 4) - 1);
2098    } else
2099    if (isTextureOp(tex->op)) {
2100       if (tex->op != OP_TXQ) {
2101          s = tex->tex.target.getArgCount() - tex->tex.target.isMS();
2102          if (tex->op == OP_TXD) {
2103             // Indirect handle belongs in the first arg
2104             if (tex->tex.rIndirectSrc >= 0)
2105                s++;
2106             if (!tex->tex.target.isArray() && tex->tex.useOffsets)
2107                s++;
2108          }
2109          n = tex->srcCount(0xff) - s;
2110       } else {
2111          s = tex->srcCount(0xff);
2112          n = 0;
2113       }
2114
2115       if (s > 1)
2116          condenseSrcs(tex, 0, s - 1);
2117       if (n > 1) // NOTE: first call modified positions already
2118          condenseSrcs(tex, 1, n);
2119    }
2120 }
2121
2122 void
2123 RegAlloc::InsertConstraintsPass::texConstraintNVE0(TexInstruction *tex)
2124 {
2125    if (isTextureOp(tex->op))
2126       textureMask(tex);
2127    condenseDefs(tex);
2128
2129    if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2130       condenseSrcs(tex, 3, (3 + typeSizeof(tex->dType) / 4) - 1);
2131    } else
2132    if (isTextureOp(tex->op)) {
2133       int n = tex->srcCount(0xff, true);
2134       if (n > 4) {
2135          condenseSrcs(tex, 0, 3);
2136          if (n > 5) // NOTE: first call modified positions already
2137             condenseSrcs(tex, 4 - (4 - 1), n - 1 - (4 - 1));
2138       } else
2139       if (n > 1) {
2140          condenseSrcs(tex, 0, n - 1);
2141       }
2142    }
2143 }
2144
2145 void
2146 RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex)
2147 {
2148    int n, s;
2149
2150    if (isTextureOp(tex->op))
2151       textureMask(tex);
2152
2153    if (tex->op == OP_TXQ) {
2154       s = tex->srcCount(0xff);
2155       n = 0;
2156    } else {
2157       s = tex->tex.target.getArgCount() - tex->tex.target.isMS();
2158       if (!tex->tex.target.isArray() &&
2159           (tex->tex.rIndirectSrc >= 0 || tex->tex.sIndirectSrc >= 0))
2160          ++s;
2161       if (tex->op == OP_TXD && tex->tex.useOffsets)
2162          ++s;
2163       n = tex->srcCount(0xff) - s;
2164       assert(n <= 4);
2165    }
2166
2167    if (s > 1)
2168       condenseSrcs(tex, 0, s - 1);
2169    if (n > 1) // NOTE: first call modified positions already
2170       condenseSrcs(tex, 1, n);
2171
2172    condenseDefs(tex);
2173 }
2174
2175 void
2176 RegAlloc::InsertConstraintsPass::texConstraintNV50(TexInstruction *tex)
2177 {
2178    Value *pred = tex->getPredicate();
2179    if (pred)
2180       tex->setPredicate(tex->cc, NULL);
2181
2182    textureMask(tex);
2183
2184    assert(tex->defExists(0) && tex->srcExists(0));
2185    // make src and def count match
2186    int c;
2187    for (c = 0; tex->srcExists(c) || tex->defExists(c); ++c) {
2188       if (!tex->srcExists(c))
2189          tex->setSrc(c, new_LValue(func, tex->getSrc(0)->asLValue()));
2190       if (!tex->defExists(c))
2191          tex->setDef(c, new_LValue(func, tex->getDef(0)->asLValue()));
2192    }
2193    if (pred)
2194       tex->setPredicate(tex->cc, pred);
2195    condenseDefs(tex);
2196    condenseSrcs(tex, 0, c - 1);
2197 }
2198
2199 // Insert constraint markers for instructions whose multiple sources must be
2200 // located in consecutive registers.
2201 bool
2202 RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
2203 {
2204    TexInstruction *tex;
2205    Instruction *next;
2206    int s, size;
2207
2208    targ = bb->getProgram()->getTarget();
2209
2210    for (Instruction *i = bb->getEntry(); i; i = next) {
2211       next = i->next;
2212
2213       if ((tex = i->asTex())) {
2214          switch (targ->getChipset() & ~0xf) {
2215          case 0x50:
2216          case 0x80:
2217          case 0x90:
2218          case 0xa0:
2219             texConstraintNV50(tex);
2220             break;
2221          case 0xc0:
2222          case 0xd0:
2223             texConstraintNVC0(tex);
2224             break;
2225          case 0xe0:
2226          case 0xf0:
2227          case 0x100:
2228             texConstraintNVE0(tex);
2229             break;
2230          case 0x110:
2231             texConstraintGM107(tex);
2232             break;
2233          default:
2234             break;
2235          }
2236       } else
2237       if (i->op == OP_EXPORT || i->op == OP_STORE) {
2238          for (size = typeSizeof(i->dType), s = 1; size > 0; ++s) {
2239             assert(i->srcExists(s));
2240             size -= i->getSrc(s)->reg.size;
2241          }
2242          condenseSrcs(i, 1, s - 1);
2243       } else
2244       if (i->op == OP_LOAD || i->op == OP_VFETCH) {
2245          condenseDefs(i);
2246          if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
2247             addHazard(i, i->src(0).getIndirect(0));
2248          if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8)
2249             addHazard(i, i->src(0).getIndirect(1));
2250       } else
2251       if (i->op == OP_UNION ||
2252           i->op == OP_MERGE ||
2253           i->op == OP_SPLIT) {
2254          constrList.push_back(i);
2255       }
2256    }
2257    return true;
2258 }
2259
2260 // Insert extra moves so that, if multiple register constraints on a value are
2261 // in conflict, these conflicts can be resolved.
2262 bool
2263 RegAlloc::InsertConstraintsPass::insertConstraintMoves()
2264 {
2265    for (std::list<Instruction *>::iterator it = constrList.begin();
2266         it != constrList.end();
2267         ++it) {
2268       Instruction *cst = *it;
2269       Instruction *mov;
2270
2271       if (cst->op == OP_SPLIT && 0) {
2272          // spilling splits is annoying, just make sure they're separate
2273          for (int d = 0; cst->defExists(d); ++d) {
2274             if (!cst->getDef(d)->refCount())
2275                continue;
2276             LValue *lval = new_LValue(func, cst->def(d).getFile());
2277             const uint8_t size = cst->def(d).getSize();
2278             lval->reg.size = size;
2279
2280             mov = new_Instruction(func, OP_MOV, typeOfSize(size));
2281             mov->setSrc(0, lval);
2282             mov->setDef(0, cst->getDef(d));
2283             cst->setDef(d, mov->getSrc(0));
2284             cst->bb->insertAfter(cst, mov);
2285
2286             cst->getSrc(0)->asLValue()->noSpill = 1;
2287             mov->getSrc(0)->asLValue()->noSpill = 1;
2288          }
2289       } else
2290       if (cst->op == OP_MERGE || cst->op == OP_UNION) {
2291          for (int s = 0; cst->srcExists(s); ++s) {
2292             const uint8_t size = cst->src(s).getSize();
2293
2294             if (!cst->getSrc(s)->defs.size()) {
2295                mov = new_Instruction(func, OP_NOP, typeOfSize(size));
2296                mov->setDef(0, cst->getSrc(s));
2297                cst->bb->insertBefore(cst, mov);
2298                continue;
2299             }
2300             assert(cst->getSrc(s)->defs.size() == 1); // still SSA
2301
2302             Instruction *defi = cst->getSrc(s)->defs.front()->getInsn();
2303             // catch some cases where don't really need MOVs
2304             if (cst->getSrc(s)->refCount() == 1 && !defi->constrainedDefs())
2305                continue;
2306
2307             LValue *lval = new_LValue(func, cst->src(s).getFile());
2308             lval->reg.size = size;
2309
2310             mov = new_Instruction(func, OP_MOV, typeOfSize(size));
2311             mov->setDef(0, lval);
2312             mov->setSrc(0, cst->getSrc(s));
2313             cst->setSrc(s, mov->getDef(0));
2314             cst->bb->insertBefore(cst, mov);
2315
2316             cst->getDef(0)->asLValue()->noSpill = 1; // doesn't help
2317
2318             if (cst->op == OP_UNION)
2319                mov->setPredicate(defi->cc, defi->getPredicate());
2320          }
2321       }
2322    }
2323
2324    return true;
2325 }
2326
2327 } // namespace nv50_ir