src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir.h"
  24 #include "codegen/nv50_ir_target.h"
  25
  26 namespace nv50_ir {
  27
  28 const uint8_t Target::operationSrcNr[OP_LAST + 1] =
  29 {
  30    0, 0,                   // NOP, PHI
  31    0, 0, 0, 0,             // UNION, SPLIT, MERGE, CONSTRAINT
  32    1, 1, 2,                // MOV, LOAD, STORE
  33    2, 2, 2, 2, 2, 3, 3, 3, // ADD, SUB, MUL, DIV, MOD, MAD, FMA, SAD
  34    1, 1, 1,                // ABS, NEG, NOT
  35    2, 2, 2, 2, 2,          // AND, OR, XOR, SHL, SHR
  36    2, 2, 1,                // MAX, MIN, SAT
  37    1, 1, 1, 1,             // CEIL, FLOOR, TRUNC, CVT
  38    3, 3, 3, 2, 3, 3,       // SET_AND,OR,XOR, SET, SELP, SLCT
  39    1, 1, 1, 1, 1, 1,       // RCP, RSQ, LG2, SIN, COS, EX2
  40    1, 1, 1, 1, 1, 2,       // EXP, LOG, PRESIN, PREEX2, SQRT, POW
  41    0, 0, 0, 0, 0,          // BRA, CALL, RET, CONT, BREAK,
  42    0, 0, 0,                // PRERET,CONT,BREAK
  43    0, 0, 0, 0, 0, 0,       // BRKPT, JOINAT, JOIN, DISCARD, EXIT, MEMBAR
  44    1, 1, 2, 1, 2,          // VFETCH, PFETCH, EXPORT, LINTERP, PINTERP
  45    1, 1,                   // EMIT, RESTART
  46    1, 1, 1,                // TEX, TXB, TXL,
  47    1, 1, 1, 1, 1, 2,       // TXF, TXQ, TXD, TXG, TEXCSAA, TEXPREP
  48    1, 1, 2, 2, 2, 2, 2,    // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA
  49    3, 3, 3, 3,             // SUBFM, SUCLAMP, SUEAU, MADSP
  50    0,                      // TEXBAR
  51    1, 1,                   // DFDX, DFDY
  52    1, 2, 2, 0, 0,          // RDSV, WRSV, QUADOP, QUADON, QUADPOP
  53    2, 3, 2, 3,             // POPCNT, INSBF, EXTBF, PERMT
  54    2, 2,                   // ATOM, BAR
  55    2, 2, 2, 2, 3, 2,       // VADD, VAVG, VMIN, VMAX, VSAD, VSET,
  56    2, 2, 2, 1,             // VSHR, VSHL, VSEL, CCTL
  57    0
  58 };
  59
  60 const OpClass Target::operationClass[OP_LAST + 1] =
  61 {
  62    // NOP; PHI; UNION, SPLIT, MERGE, CONSTRAINT
  63    OPCLASS_OTHER,
  64    OPCLASS_PSEUDO,
  65    OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO,
  66    // MOV; LOAD; STORE
  67    OPCLASS_MOVE,
  68    OPCLASS_LOAD,
  69    OPCLASS_STORE,
  70    // ADD, SUB, MUL; DIV, MOD; MAD, FMA, SAD
  71    OPCLASS_ARITH, OPCLASS_ARITH, OPCLASS_ARITH,
  72    OPCLASS_ARITH, OPCLASS_ARITH,
  73    OPCLASS_ARITH, OPCLASS_ARITH, OPCLASS_ARITH,
  74    // ABS, NEG; NOT, AND, OR, XOR; SHL, SHR
  75    OPCLASS_CONVERT, OPCLASS_CONVERT,
  76    OPCLASS_LOGIC, OPCLASS_LOGIC, OPCLASS_LOGIC, OPCLASS_LOGIC,
  77    OPCLASS_SHIFT, OPCLASS_SHIFT,
  78    // MAX, MIN
  79    OPCLASS_COMPARE, OPCLASS_COMPARE,
  80    // SAT, CEIL, FLOOR, TRUNC; CVT
  81    OPCLASS_CONVERT, OPCLASS_CONVERT, OPCLASS_CONVERT, OPCLASS_CONVERT,
  82    OPCLASS_CONVERT,
  83    // SET(AND,OR,XOR); SELP, SLCT
  84    OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE,
  85    OPCLASS_COMPARE, OPCLASS_COMPARE,
  86    // RCP, RSQ, LG2, SIN, COS; EX2, EXP, LOG, PRESIN, PREEX2; SQRT, POW
  87    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
  88    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
  89    OPCLASS_SFU, OPCLASS_SFU,
  90    // BRA, CALL, RET; CONT, BREAK, PRE(RET,CONT,BREAK); BRKPT, JOINAT, JOIN
  91    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  92    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  93    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  94    // DISCARD, EXIT
  95    OPCLASS_FLOW, OPCLASS_FLOW,
  96    // MEMBAR
  97    OPCLASS_CONTROL,
  98    // VFETCH, PFETCH, EXPORT
  99    OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_STORE,
 100    // LINTERP, PINTERP
 101    OPCLASS_SFU, OPCLASS_SFU,
 102    // EMIT, RESTART
 103    OPCLASS_CONTROL, OPCLASS_CONTROL,
 104    // TEX, TXB, TXL, TXF; TXQ, TXD, TXG, TEXCSAA; TEXPREP
 105    OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
 106    OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
 107    OPCLASS_TEXTURE,
 108    // SULDB, SULDP, SUSTB, SUSTP; SUREDB, SUREDP, SULEA
 109    OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_ATOMIC, OPCLASS_SURFACE,
 110    OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_SURFACE,
 111    // SUBFM, SUCLAMP, SUEAU, MADSP
 112    OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH,
 113    // TEXBAR
 114    OPCLASS_OTHER,
 115    // DFDX, DFDY, RDSV, WRSV; QUADOP, QUADON, QUADPOP
 116    OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER,
 117    OPCLASS_OTHER, OPCLASS_CONTROL, OPCLASS_CONTROL,
 118    // POPCNT, INSBF, EXTBF, PERMT
 119    OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD,
 120    // ATOM, BAR
 121    OPCLASS_ATOMIC, OPCLASS_CONTROL,
 122    // VADD, VAVG, VMIN, VMAX
 123    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
 124    // VSAD, VSET, VSHR, VSHL
 125    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
 126    // VSEL, CCTL
 127    OPCLASS_VECTOR, OPCLASS_CONTROL,
 128    OPCLASS_PSEUDO // LAST
 129 };
 130
 131
 132 extern Target *getTargetNVC0(unsigned int chipset);
 133 extern Target *getTargetNV50(unsigned int chipset);
 134
 135 Target *Target::create(unsigned int chipset)
 136 {
 137    switch (chipset & ~0xf) {
 138    case 0xc0:
 139    case 0xd0:
 140    case 0xe0:
 141    case 0xf0:
 142    case 0x100:
 143       return getTargetNVC0(chipset);
 144    case 0x50:
 145    case 0x80:
 146    case 0x90:
 147    case 0xa0:
 148       return getTargetNV50(chipset);
 149    default:
 150       ERROR("unsupported target: NV%x\n", chipset);
 151       return 0;
 152    }
 153 }
 154
 155 void Target::destroy(Target *targ)
 156 {
 157    delete targ;
 158 }
 159
 160 CodeEmitter::CodeEmitter(const Target *target) : targ(target)
 161 {
 162 }
 163
 164 void
 165 CodeEmitter::setCodeLocation(void *ptr, uint32_t size)
 166 {
 167    code = reinterpret_cast<uint32_t *>(ptr);
 168    codeSize = 0;
 169    codeSizeLimit = size;
 170 }
 171
 172 void
 173 CodeEmitter::printBinary() const
 174 {
 175    uint32_t *bin = code - codeSize / 4;
 176    INFO("program binary (%u bytes)", codeSize);
 177    for (unsigned int pos = 0; pos < codeSize / 4; ++pos) {
 178       if ((pos % 8) == 0)
 179          INFO("\n");
 180       INFO("%08x ", bin[pos]);
 181    }
 182    INFO("\n");
 183 }
 184
 185 static inline uint32_t sizeToBundlesNVE4(uint32_t size)
 186 {
 187    return (size + 55) / 56;
 188 }
 189
 190 void
 191 CodeEmitter::prepareEmission(Program *prog)
 192 {
 193    for (ArrayList::Iterator fi = prog->allFuncs.iterator();
 194         !fi.end(); fi.next()) {
 195       Function *func = reinterpret_cast<Function *>(fi.get());
 196       func->binPos = prog->binSize;
 197       prepareEmission(func);
 198
 199       // adjust sizes & positions for schedulding info:
 200       if (prog->getTarget()->hasSWSched) {
 201          uint32_t adjPos = func->binPos;
 202          BasicBlock *bb = NULL;
 203          for (int i = 0; i < func->bbCount; ++i) {
 204             bb = func->bbArray[i];
 205             int32_t adjSize = bb->binSize;
 206             if (adjPos % 64) {
 207                adjSize -= 64 - adjPos % 64;
 208                if (adjSize < 0)
 209                   adjSize = 0;
 210             }
 211             adjSize = bb->binSize + sizeToBundlesNVE4(adjSize) * 8;
 212             bb->binPos = adjPos;
 213             bb->binSize = adjSize;
 214             adjPos += adjSize;
 215          }
 216          if (bb)
 217             func->binSize = adjPos - func->binPos;
 218       }
 219
 220       prog->binSize += func->binSize;
 221    }
 222 }
 223
 224 void
 225 CodeEmitter::prepareEmission(Function *func)
 226 {
 227    func->bbCount = 0;
 228    func->bbArray = new BasicBlock * [func->cfg.getSize()];
 229
 230    BasicBlock::get(func->cfg.getRoot())->binPos = func->binPos;
 231
 232    for (IteratorRef it = func->cfg.iteratorCFG(); !it->end(); it->next())
 233       prepareEmission(BasicBlock::get(*it));
 234 }
 235
 236 void
 237 CodeEmitter::prepareEmission(BasicBlock *bb)
 238 {
 239    Instruction *i, *next;
 240    Function *func = bb->getFunction();
 241    int j;
 242    unsigned int nShort;
 243
 244    for (j = func->bbCount - 1; j >= 0 && !func->bbArray[j]->binSize; --j);
 245
 246    for (; j >= 0; --j) {
 247       BasicBlock *in = func->bbArray[j];
 248       Instruction *exit = in->getExit();
 249
 250       if (exit && exit->op == OP_BRA && exit->asFlow()->target.bb == bb) {
 251          in->binSize -= 8;
 252          func->binSize -= 8;
 253
 254          for (++j; j < func->bbCount; ++j)
 255             func->bbArray[j]->binPos -= 8;
 256
 257          in->remove(exit);
 258       }
 259       bb->binPos = in->binPos + in->binSize;
 260       if (in->binSize) // no more no-op branches to bb
 261          break;
 262    }
 263    func->bbArray[func->bbCount++] = bb;
 264
 265    if (!bb->getExit())
 266       return;
 267
 268    // determine encoding size, try to group short instructions
 269    nShort = 0;
 270    for (i = bb->getEntry(); i; i = next) {
 271       next = i->next;
 272
 273       if (i->op == OP_MEMBAR && !targ->isOpSupported(OP_MEMBAR, TYPE_NONE)) {
 274          bb->remove(i);
 275          continue;
 276       }
 277
 278       i->encSize = getMinEncodingSize(i);
 279       if (next && i->encSize < 8)
 280          ++nShort;
 281       else
 282       if ((nShort & 1) && next && getMinEncodingSize(next) == 4) {
 283          if (i->isCommutationLegal(i->next)) {
 284             bb->permuteAdjacent(i, next);
 285             next->encSize = 4;
 286             next = i;
 287             i = i->prev;
 288             ++nShort;
 289          } else
 290          if (i->isCommutationLegal(i->prev) && next->next) {
 291             bb->permuteAdjacent(i->prev, i);
 292             next->encSize = 4;
 293             next = next->next;
 294             bb->binSize += 4;
 295             ++nShort;
 296          } else {
 297             i->encSize = 8;
 298             i->prev->encSize = 8;
 299             bb->binSize += 4;
 300             nShort = 0;
 301          }
 302       } else {
 303          i->encSize = 8;
 304          if (nShort & 1) {
 305             i->prev->encSize = 8;
 306             bb->binSize += 4;
 307          }
 308          nShort = 0;
 309       }
 310       bb->binSize += i->encSize;
 311    }
 312
 313    if (bb->getExit()->encSize == 4) {
 314       assert(nShort);
 315       bb->getExit()->encSize = 8;
 316       bb->binSize += 4;
 317
 318       if ((bb->getExit()->prev->encSize == 4) && !(nShort & 1)) {
 319          bb->binSize += 8;
 320          bb->getExit()->prev->encSize = 8;
 321       }
 322    }
 323    assert(!bb->getEntry() || (bb->getExit() && bb->getExit()->encSize == 8));
 324
 325    func->binSize += bb->binSize;
 326 }
 327
 328 void
 329 Program::emitSymbolTable(struct nv50_ir_prog_info *info)
 330 {
 331    unsigned int n = 0, nMax = allFuncs.getSize();
 332
 333    info->bin.syms =
 334       (struct nv50_ir_prog_symbol *)MALLOC(nMax * sizeof(*info->bin.syms));
 335
 336    for (ArrayList::Iterator fi = allFuncs.iterator();
 337         !fi.end();
 338         fi.next(), ++n) {
 339       Function *f = (Function *)fi.get();
 340       assert(n < nMax);
 341
 342       info->bin.syms[n].label = f->getLabel();
 343       info->bin.syms[n].offset = f->binPos;
 344    }
 345
 346    info->bin.numSyms = n;
 347 }
 348
 349 bool
 350 Program::emitBinary(struct nv50_ir_prog_info *info)
 351 {
 352    CodeEmitter *emit = target->getCodeEmitter(progType);
 353
 354    emit->prepareEmission(this);
 355
 356    if (dbgFlags & NV50_IR_DEBUG_BASIC)
 357       this->print();
 358
 359    if (!binSize) {
 360       code = NULL;
 361       return false;
 362    }
 363    code = reinterpret_cast<uint32_t *>(MALLOC(binSize));
 364    if (!code)
 365       return false;
 366    emit->setCodeLocation(code, binSize);
 367
 368    for (ArrayList::Iterator fi = allFuncs.iterator(); !fi.end(); fi.next()) {
 369       Function *fn = reinterpret_cast<Function *>(fi.get());
 370
 371       assert(emit->getCodeSize() == fn->binPos);
 372
 373       for (int b = 0; b < fn->bbCount; ++b)
 374          for (Instruction *i = fn->bbArray[b]->getEntry(); i; i = i->next)
 375             emit->emitInstruction(i);
 376    }
 377    info->bin.relocData = emit->getRelocInfo();
 378
 379    emitSymbolTable(info);
 380
 381    // the nvc0 driver will print the binary iself together with the header
 382    if ((dbgFlags & NV50_IR_DEBUG_BASIC) && getTarget()->getChipset() < 0xc0)
 383       emit->printBinary();
 384
 385    delete emit;
 386    return true;
 387 }
 388
 389 #define RELOC_ALLOC_INCREMENT 8
 390
 391 bool
 392 CodeEmitter::addReloc(RelocEntry::Type ty, int w, uint32_t data, uint32_t m,
 393                       int s)
 394 {
 395    unsigned int n = relocInfo ? relocInfo->count : 0;
 396
 397    if (!(n % RELOC_ALLOC_INCREMENT)) {
 398       size_t size = sizeof(RelocInfo) + n * sizeof(RelocEntry);
 399       relocInfo = reinterpret_cast<RelocInfo *>(
 400          REALLOC(relocInfo, n ? size : 0,
 401                  size + RELOC_ALLOC_INCREMENT * sizeof(RelocEntry)));
 402       if (!relocInfo)
 403          return false;
 404       if (n == 0)
 405          memset(relocInfo, 0, sizeof(RelocInfo));
 406    }
 407    ++relocInfo->count;
 408
 409    relocInfo->entry[n].data = data;
 410    relocInfo->entry[n].mask = m;
 411    relocInfo->entry[n].offset = codeSize + w * 4;
 412    relocInfo->entry[n].bitPos = s;
 413    relocInfo->entry[n].type = ty;
 414
 415    return true;
 416 }
 417
 418 void
 419 RelocEntry::apply(uint32_t *binary, const RelocInfo *info) const
 420 {
 421    uint32_t value = 0;
 422
 423    switch (type) {
 424    case TYPE_CODE: value = info->codePos; break;
 425    case TYPE_BUILTIN: value = info->libPos; break;
 426    case TYPE_DATA: value = info->dataPos; break;
 427    default:
 428       assert(0);
 429       break;
 430    }
 431    value += data;
 432    value = (bitPos < 0) ? (value >> -bitPos) : (value << bitPos);
 433
 434    binary[offset / 4] &= ~mask;
 435    binary[offset / 4] |= value & mask;
 436 }
 437
 438 } // namespace nv50_ir
 439
 440
 441 #include "codegen/nv50_ir_driver.h"
 442
 443 extern "C" {
 444
 445 void
 446 nv50_ir_relocate_code(void *relocData, uint32_t *code,
 447                       uint32_t codePos,
 448                       uint32_t libPos,
 449                       uint32_t dataPos)
 450 {
 451    nv50_ir::RelocInfo *info = reinterpret_cast<nv50_ir::RelocInfo *>(relocData);
 452
 453    info->codePos = codePos;
 454    info->libPos = libPos;
 455    info->dataPos = dataPos;
 456
 457    for (unsigned int i = 0; i < info->count; ++i)
 458       info->entry[i].apply(code, info);
 459 }
 460
 461 void
 462 nv50_ir_get_target_library(uint32_t chipset,
 463                            const uint32_t **code, uint32_t *size)
 464 {
 465    nv50_ir::Target *targ = nv50_ir::Target::create(chipset);
 466    targ->getBuiltinCode(code, size);
 467    nv50_ir::Target::destroy(targ);
 468 }
 469
 470 }