src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir.h"
  24 #include "codegen/nv50_ir_target.h"
  25
  26 namespace nv50_ir {
  27
  28 const uint8_t Target::operationSrcNr[] =
  29 {
  30    0, 0,                   // NOP, PHI
  31    0, 0, 0, 0,             // UNION, SPLIT, MERGE, CONSTRAINT
  32    1, 1, 2,                // MOV, LOAD, STORE
  33    2, 2, 2, 2, 2, 3, 3, 3, // ADD, SUB, MUL, DIV, MOD, MAD, FMA, SAD
  34    1, 1, 1,                // ABS, NEG, NOT
  35    2, 2, 2, 2, 2,          // AND, OR, XOR, SHL, SHR
  36    2, 2, 1,                // MAX, MIN, SAT
  37    1, 1, 1, 1,             // CEIL, FLOOR, TRUNC, CVT
  38    3, 3, 3, 2, 3, 3,       // SET_AND,OR,XOR, SET, SELP, SLCT
  39    1, 1, 1, 1, 1, 1,       // RCP, RSQ, LG2, SIN, COS, EX2
  40    1, 1, 1, 1, 1, 2,       // EXP, LOG, PRESIN, PREEX2, SQRT, POW
  41    0, 0, 0, 0, 0,          // BRA, CALL, RET, CONT, BREAK,
  42    0, 0, 0,                // PRERET,CONT,BREAK
  43    0, 0, 0, 0, 0, 0,       // BRKPT, JOINAT, JOIN, DISCARD, EXIT, MEMBAR
  44    1, 1, 1, 2, 1, 2,       // VFETCH, PFETCH, AFETCH, EXPORT, LINTERP, PINTERP
  45    1, 1,                   // EMIT, RESTART
  46    1, 1, 1,                // TEX, TXB, TXL,
  47    1, 1, 1, 1, 1, 1, 2,    // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP
  48    1, 1, 2, 2, 2, 2, 2,    // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA
  49    3, 3, 3, 1, 3,          // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
  50    0,                      // TEXBAR
  51    1, 1,                   // DFDX, DFDY
  52    1, 2, 1, 2, 0, 0,       // RDSV, WRSV, PIXLD, QUADOP, QUADON, QUADPOP
  53    2, 3, 2, 1, 3,          // POPCNT, INSBF, EXTBF, BFIND, PERMT
  54    2, 2,                   // ATOM, BAR
  55    2, 2, 2, 2, 3, 2,       // VADD, VAVG, VMIN, VMAX, VSAD, VSET,
  56    2, 2, 2, 1,             // VSHR, VSHL, VSEL, CCTL
  57    3,                      // SHFL
  58    1,                      // VOTE
  59    1,                      // BUFQ
  60    0
  61 };
  62
  63 const OpClass Target::operationClass[] =
  64 {
  65    // NOP; PHI; UNION, SPLIT, MERGE, CONSTRAINT
  66    OPCLASS_OTHER,
  67    OPCLASS_PSEUDO,
  68    OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO,
  69    // MOV; LOAD; STORE
  70    OPCLASS_MOVE,
  71    OPCLASS_LOAD,
  72    OPCLASS_STORE,
  73    // ADD, SUB, MUL; DIV, MOD; MAD, FMA, SAD
  74    OPCLASS_ARITH, OPCLASS_ARITH, OPCLASS_ARITH,
  75    OPCLASS_ARITH, OPCLASS_ARITH,
  76    OPCLASS_ARITH, OPCLASS_ARITH, OPCLASS_ARITH,
  77    // ABS, NEG; NOT, AND, OR, XOR; SHL, SHR
  78    OPCLASS_CONVERT, OPCLASS_CONVERT,
  79    OPCLASS_LOGIC, OPCLASS_LOGIC, OPCLASS_LOGIC, OPCLASS_LOGIC,
  80    OPCLASS_SHIFT, OPCLASS_SHIFT,
  81    // MAX, MIN
  82    OPCLASS_COMPARE, OPCLASS_COMPARE,
  83    // SAT, CEIL, FLOOR, TRUNC; CVT
  84    OPCLASS_CONVERT, OPCLASS_CONVERT, OPCLASS_CONVERT, OPCLASS_CONVERT,
  85    OPCLASS_CONVERT,
  86    // SET(AND,OR,XOR); SELP, SLCT
  87    OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE,
  88    OPCLASS_COMPARE, OPCLASS_COMPARE,
  89    // RCP, RSQ, LG2, SIN, COS; EX2, EXP, LOG, PRESIN, PREEX2; SQRT, POW
  90    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
  91    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
  92    OPCLASS_SFU, OPCLASS_SFU,
  93    // BRA, CALL, RET; CONT, BREAK, PRE(RET,CONT,BREAK); BRKPT, JOINAT, JOIN
  94    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  95    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  96    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
  97    // DISCARD, EXIT
  98    OPCLASS_FLOW, OPCLASS_FLOW,
  99    // MEMBAR
 100    OPCLASS_CONTROL,
 101    // VFETCH, PFETCH, AFETCH, EXPORT
 102    OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_STORE,
 103    // LINTERP, PINTERP
 104    OPCLASS_SFU, OPCLASS_SFU,
 105    // EMIT, RESTART
 106    OPCLASS_CONTROL, OPCLASS_CONTROL,
 107    // TEX, TXB, TXL, TXF; TXQ, TXD, TXG, TXLQ; TEXCSAA, TEXPREP
 108    OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
 109    OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
 110    OPCLASS_TEXTURE, OPCLASS_TEXTURE,
 111    // SULDB, SULDP, SUSTB, SUSTP; SUREDB, SUREDP, SULEA
 112    OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_ATOMIC, OPCLASS_SURFACE,
 113    OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_SURFACE,
 114    // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
 115    OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH,
 116    // TEXBAR
 117    OPCLASS_OTHER,
 118    // DFDX, DFDY, RDSV, WRSV; PIXLD, QUADOP, QUADON, QUADPOP
 119    OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER,
 120    OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_CONTROL, OPCLASS_CONTROL,
 121    // POPCNT, INSBF, EXTBF, BFIND; PERMT
 122    OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD,
 123    OPCLASS_BITFIELD,
 124    // ATOM, BAR
 125    OPCLASS_ATOMIC, OPCLASS_CONTROL,
 126    // VADD, VAVG, VMIN, VMAX
 127    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
 128    // VSAD, VSET, VSHR, VSHL
 129    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
 130    // VSEL, CCTL
 131    OPCLASS_VECTOR, OPCLASS_CONTROL,
 132    // SHFL
 133    OPCLASS_OTHER,
 134    // VOTE
 135    OPCLASS_OTHER,
 136    // BUFQ
 137    OPCLASS_OTHER,
 138    OPCLASS_PSEUDO // LAST
 139 };
 140
 141
 142 extern Target *getTargetGM107(unsigned int chipset);
 143 extern Target *getTargetNVC0(unsigned int chipset);
 144 extern Target *getTargetNV50(unsigned int chipset);
 145
 146 Target *Target::create(unsigned int chipset)
 147 {
 148    STATIC_ASSERT(Elements(operationSrcNr) == OP_LAST + 1);
 149    STATIC_ASSERT(Elements(operationClass) == OP_LAST + 1);
 150    switch (chipset & ~0xf) {
 151    case 0x110:
 152    case 0x120:
 153       return getTargetGM107(chipset);
 154    case 0xc0:
 155    case 0xd0:
 156    case 0xe0:
 157    case 0xf0:
 158    case 0x100:
 159       return getTargetNVC0(chipset);
 160    case 0x50:
 161    case 0x80:
 162    case 0x90:
 163    case 0xa0:
 164       return getTargetNV50(chipset);
 165    default:
 166       ERROR("unsupported target: NV%x\n", chipset);
 167       return 0;
 168    }
 169 }
 170
 171 void Target::destroy(Target *targ)
 172 {
 173    delete targ;
 174 }
 175
 176 CodeEmitter::CodeEmitter(const Target *target) : targ(target), fixupInfo(NULL)
 177 {
 178 }
 179
 180 void
 181 CodeEmitter::setCodeLocation(void *ptr, uint32_t size)
 182 {
 183    code = reinterpret_cast<uint32_t *>(ptr);
 184    codeSize = 0;
 185    codeSizeLimit = size;
 186 }
 187
 188 void
 189 CodeEmitter::printBinary() const
 190 {
 191    uint32_t *bin = code - codeSize / 4;
 192    INFO("program binary (%u bytes)", codeSize);
 193    for (unsigned int pos = 0; pos < codeSize / 4; ++pos) {
 194       if ((pos % 8) == 0)
 195          INFO("\n");
 196       INFO("%08x ", bin[pos]);
 197    }
 198    INFO("\n");
 199 }
 200
 201 static inline uint32_t sizeToBundlesNVE4(uint32_t size)
 202 {
 203    return (size + 55) / 56;
 204 }
 205
 206 void
 207 CodeEmitter::prepareEmission(Program *prog)
 208 {
 209    for (ArrayList::Iterator fi = prog->allFuncs.iterator();
 210         !fi.end(); fi.next()) {
 211       Function *func = reinterpret_cast<Function *>(fi.get());
 212       func->binPos = prog->binSize;
 213       prepareEmission(func);
 214
 215       // adjust sizes & positions for schedulding info:
 216       if (prog->getTarget()->hasSWSched) {
 217          uint32_t adjPos = func->binPos;
 218          BasicBlock *bb = NULL;
 219          for (int i = 0; i < func->bbCount; ++i) {
 220             bb = func->bbArray[i];
 221             int32_t adjSize = bb->binSize;
 222             if (adjPos % 64) {
 223                adjSize -= 64 - adjPos % 64;
 224                if (adjSize < 0)
 225                   adjSize = 0;
 226             }
 227             adjSize = bb->binSize + sizeToBundlesNVE4(adjSize) * 8;
 228             bb->binPos = adjPos;
 229             bb->binSize = adjSize;
 230             adjPos += adjSize;
 231          }
 232          if (bb)
 233             func->binSize = adjPos - func->binPos;
 234       }
 235
 236       prog->binSize += func->binSize;
 237    }
 238 }
 239
 240 void
 241 CodeEmitter::prepareEmission(Function *func)
 242 {
 243    func->bbCount = 0;
 244    func->bbArray = new BasicBlock * [func->cfg.getSize()];
 245
 246    BasicBlock::get(func->cfg.getRoot())->binPos = func->binPos;
 247
 248    for (IteratorRef it = func->cfg.iteratorCFG(); !it->end(); it->next())
 249       prepareEmission(BasicBlock::get(*it));
 250 }
 251
 252 void
 253 CodeEmitter::prepareEmission(BasicBlock *bb)
 254 {
 255    Instruction *i, *next;
 256    Function *func = bb->getFunction();
 257    int j;
 258    unsigned int nShort;
 259
 260    for (j = func->bbCount - 1; j >= 0 && !func->bbArray[j]->binSize; --j);
 261
 262    for (; j >= 0; --j) {
 263       BasicBlock *in = func->bbArray[j];
 264       Instruction *exit = in->getExit();
 265
 266       if (exit && exit->op == OP_BRA && exit->asFlow()->target.bb == bb) {
 267          in->binSize -= 8;
 268          func->binSize -= 8;
 269
 270          for (++j; j < func->bbCount; ++j)
 271             func->bbArray[j]->binPos -= 8;
 272
 273          in->remove(exit);
 274       }
 275       bb->binPos = in->binPos + in->binSize;
 276       if (in->binSize) // no more no-op branches to bb
 277          break;
 278    }
 279    func->bbArray[func->bbCount++] = bb;
 280
 281    if (!bb->getExit())
 282       return;
 283
 284    // determine encoding size, try to group short instructions
 285    nShort = 0;
 286    for (i = bb->getEntry(); i; i = next) {
 287       next = i->next;
 288
 289       if (i->op == OP_MEMBAR && !targ->isOpSupported(OP_MEMBAR, TYPE_NONE)) {
 290          bb->remove(i);
 291          continue;
 292       }
 293
 294       i->encSize = getMinEncodingSize(i);
 295       if (next && i->encSize < 8)
 296          ++nShort;
 297       else
 298       if ((nShort & 1) && next && getMinEncodingSize(next) == 4) {
 299          if (i->isCommutationLegal(i->next)) {
 300             bb->permuteAdjacent(i, next);
 301             next->encSize = 4;
 302             next = i;
 303             i = i->prev;
 304             ++nShort;
 305          } else
 306          if (i->isCommutationLegal(i->prev) && next->next) {
 307             bb->permuteAdjacent(i->prev, i);
 308             next->encSize = 4;
 309             next = next->next;
 310             bb->binSize += 4;
 311             ++nShort;
 312          } else {
 313             i->encSize = 8;
 314             i->prev->encSize = 8;
 315             bb->binSize += 4;
 316             nShort = 0;
 317          }
 318       } else {
 319          i->encSize = 8;
 320          if (nShort & 1) {
 321             i->prev->encSize = 8;
 322             bb->binSize += 4;
 323          }
 324          nShort = 0;
 325       }
 326       bb->binSize += i->encSize;
 327    }
 328
 329    if (bb->getExit()->encSize == 4) {
 330       assert(nShort);
 331       bb->getExit()->encSize = 8;
 332       bb->binSize += 4;
 333
 334       if ((bb->getExit()->prev->encSize == 4) && !(nShort & 1)) {
 335          bb->binSize += 8;
 336          bb->getExit()->prev->encSize = 8;
 337       }
 338    }
 339    assert(!bb->getEntry() || (bb->getExit() && bb->getExit()->encSize == 8));
 340
 341    func->binSize += bb->binSize;
 342 }
 343
 344 void
 345 Program::emitSymbolTable(struct nv50_ir_prog_info *info)
 346 {
 347    unsigned int n = 0, nMax = allFuncs.getSize();
 348
 349    info->bin.syms =
 350       (struct nv50_ir_prog_symbol *)MALLOC(nMax * sizeof(*info->bin.syms));
 351
 352    for (ArrayList::Iterator fi = allFuncs.iterator();
 353         !fi.end();
 354         fi.next(), ++n) {
 355       Function *f = (Function *)fi.get();
 356       assert(n < nMax);
 357
 358       info->bin.syms[n].label = f->getLabel();
 359       info->bin.syms[n].offset = f->binPos;
 360    }
 361
 362    info->bin.numSyms = n;
 363 }
 364
 365 bool
 366 Program::emitBinary(struct nv50_ir_prog_info *info)
 367 {
 368    CodeEmitter *emit = target->getCodeEmitter(progType);
 369
 370    emit->prepareEmission(this);
 371
 372    if (dbgFlags & NV50_IR_DEBUG_BASIC)
 373       this->print();
 374
 375    if (!binSize) {
 376       code = NULL;
 377       return false;
 378    }
 379    code = reinterpret_cast<uint32_t *>(MALLOC(binSize));
 380    if (!code)
 381       return false;
 382    emit->setCodeLocation(code, binSize);
 383    info->bin.instructions = 0;
 384
 385    for (ArrayList::Iterator fi = allFuncs.iterator(); !fi.end(); fi.next()) {
 386       Function *fn = reinterpret_cast<Function *>(fi.get());
 387
 388       assert(emit->getCodeSize() == fn->binPos);
 389
 390       for (int b = 0; b < fn->bbCount; ++b) {
 391          for (Instruction *i = fn->bbArray[b]->getEntry(); i; i = i->next) {
 392             emit->emitInstruction(i);
 393             info->bin.instructions++;
 394             if (i->sType == TYPE_F64 || i->dType == TYPE_F64)
 395                info->io.fp64 = true;
 396          }
 397       }
 398    }
 399    info->bin.relocData = emit->getRelocInfo();
 400    info->bin.fixupData = emit->getFixupInfo();
 401
 402    emitSymbolTable(info);
 403
 404    // the nvc0 driver will print the binary iself together with the header
 405    if ((dbgFlags & NV50_IR_DEBUG_BASIC) && getTarget()->getChipset() < 0xc0)
 406       emit->printBinary();
 407
 408    delete emit;
 409    return true;
 410 }
 411
 412 #define RELOC_ALLOC_INCREMENT 8
 413
 414 bool
 415 CodeEmitter::addReloc(RelocEntry::Type ty, int w, uint32_t data, uint32_t m,
 416                       int s)
 417 {
 418    unsigned int n = relocInfo ? relocInfo->count : 0;
 419
 420    if (!(n % RELOC_ALLOC_INCREMENT)) {
 421       size_t size = sizeof(RelocInfo) + n * sizeof(RelocEntry);
 422       relocInfo = reinterpret_cast<RelocInfo *>(
 423          REALLOC(relocInfo, n ? size : 0,
 424                  size + RELOC_ALLOC_INCREMENT * sizeof(RelocEntry)));
 425       if (!relocInfo)
 426          return false;
 427       if (n == 0)
 428          memset(relocInfo, 0, sizeof(RelocInfo));
 429    }
 430    ++relocInfo->count;
 431
 432    relocInfo->entry[n].data = data;
 433    relocInfo->entry[n].mask = m;
 434    relocInfo->entry[n].offset = codeSize + w * 4;
 435    relocInfo->entry[n].bitPos = s;
 436    relocInfo->entry[n].type = ty;
 437
 438    return true;
 439 }
 440
 441 bool
 442 CodeEmitter::addInterp(int ipa, int reg, FixupApply apply)
 443 {
 444    unsigned int n = fixupInfo ? fixupInfo->count : 0;
 445
 446    if (!(n % RELOC_ALLOC_INCREMENT)) {
 447       size_t size = sizeof(FixupInfo) + n * sizeof(FixupEntry);
 448       fixupInfo = reinterpret_cast<FixupInfo *>(
 449          REALLOC(fixupInfo, n ? size : 0,
 450                  size + RELOC_ALLOC_INCREMENT * sizeof(FixupEntry)));
 451       if (!fixupInfo)
 452          return false;
 453       if (n == 0)
 454          memset(fixupInfo, 0, sizeof(FixupInfo));
 455    }
 456    ++fixupInfo->count;
 457
 458    fixupInfo->entry[n] = FixupEntry(apply, ipa, reg, codeSize >> 2);
 459
 460    return true;
 461 }
 462
 463 void
 464 RelocEntry::apply(uint32_t *binary, const RelocInfo *info) const
 465 {
 466    uint32_t value = 0;
 467
 468    switch (type) {
 469    case TYPE_CODE: value = info->codePos; break;
 470    case TYPE_BUILTIN: value = info->libPos; break;
 471    case TYPE_DATA: value = info->dataPos; break;
 472    default:
 473       assert(0);
 474       break;
 475    }
 476    value += data;
 477    value = (bitPos < 0) ? (value >> -bitPos) : (value << bitPos);
 478
 479    binary[offset / 4] &= ~mask;
 480    binary[offset / 4] |= value & mask;
 481 }
 482
 483 } // namespace nv50_ir
 484
 485
 486 #include "codegen/nv50_ir_driver.h"
 487
 488 extern "C" {
 489
 490 void
 491 nv50_ir_relocate_code(void *relocData, uint32_t *code,
 492                       uint32_t codePos,
 493                       uint32_t libPos,
 494                       uint32_t dataPos)
 495 {
 496    nv50_ir::RelocInfo *info = reinterpret_cast<nv50_ir::RelocInfo *>(relocData);
 497
 498    info->codePos = codePos;
 499    info->libPos = libPos;
 500    info->dataPos = dataPos;
 501
 502    for (unsigned int i = 0; i < info->count; ++i)
 503       info->entry[i].apply(code, info);
 504 }
 505
 506 void
 507 nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
 508                      bool force_persample_interp, bool flatshade)
 509 {
 510    nv50_ir::FixupInfo *info = reinterpret_cast<nv50_ir::FixupInfo *>(
 511       fixupData);
 512
 513    // force_persample_interp: all non-flat -> per-sample
 514    // flatshade: all color -> flat
 515    nv50_ir::FixupData data(force_persample_interp, flatshade);
 516    for (unsigned i = 0; i < info->count; ++i)
 517       info->entry[i].apply(&info->entry[i], code, data);
 518 }
 519
 520 void
 521 nv50_ir_get_target_library(uint32_t chipset,
 522                            const uint32_t **code, uint32_t *size)
 523 {
 524    nv50_ir::Target *targ = nv50_ir::Target::create(chipset);
 525    targ->getBuiltinCode(code, size);
 526    nv50_ir::Target::destroy(targ);
 527 }
 528
 529 }