nvc0/ir: avoid generating illegal instructions for compute constbuf loads
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_target.h
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #ifndef __NV50_IR_TARGET_H__
24 #define __NV50_IR_TARGET_H__
25
26 #include "codegen/nv50_ir.h"
27
28 namespace nv50_ir {
29
30 struct RelocInfo;
31
32 struct RelocEntry
33 {
34 enum Type
35 {
36 TYPE_CODE,
37 TYPE_BUILTIN,
38 TYPE_DATA
39 };
40
41 uint32_t data;
42 uint32_t mask;
43 uint32_t offset;
44 int8_t bitPos;
45 Type type;
46
47 inline void apply(uint32_t *binary, const RelocInfo *info) const;
48 };
49
50 struct RelocInfo
51 {
52 uint32_t codePos;
53 uint32_t libPos;
54 uint32_t dataPos;
55
56 uint32_t count;
57
58 RelocEntry entry[0];
59 };
60
61 struct FixupData {
62 FixupData(bool force, bool flat) :
63 force_persample_interp(force), flatshade(flat) {}
64 bool force_persample_interp;
65 bool flatshade;
66 };
67
68 struct FixupEntry;
69 typedef void (*FixupApply)(const FixupEntry*, uint32_t*, const FixupData&);
70
71 struct FixupEntry
72 {
73 FixupEntry(FixupApply apply, int ipa, int reg, int loc) :
74 apply(apply), ipa(ipa), reg(reg), loc(loc) {}
75
76 FixupApply apply;
77 union {
78 struct {
79 uint32_t ipa:4; // SC mode used to identify colors
80 uint32_t reg:8; // The reg used for perspective division
81 uint32_t loc:20; // Let's hope we don't have more than 1M-sized shaders
82 };
83 uint32_t val;
84 };
85 };
86
87 struct FixupInfo
88 {
89 uint32_t count;
90 FixupEntry entry[0];
91 };
92
93 class CodeEmitter
94 {
95 public:
96 CodeEmitter(const Target *);
97 virtual ~CodeEmitter() { }
98
99 // returns whether the instruction was encodable and written
100 virtual bool emitInstruction(Instruction *) = 0;
101
102 virtual uint32_t getMinEncodingSize(const Instruction *) const = 0;
103
104 void setCodeLocation(void *, uint32_t size);
105 inline void *getCodeLocation() const { return code; }
106 inline uint32_t getCodeSize() const { return codeSize; }
107
108 bool addReloc(RelocEntry::Type, int w, uint32_t data, uint32_t m,
109 int s);
110
111 inline void *getRelocInfo() const { return relocInfo; }
112
113 bool addInterp(int ipa, int reg, FixupApply apply);
114 inline void *getFixupInfo() const { return fixupInfo; }
115
116 virtual void prepareEmission(Program *);
117 virtual void prepareEmission(Function *);
118 virtual void prepareEmission(BasicBlock *);
119
120 void printBinary() const;
121
122 protected:
123 const Target *targ;
124
125 uint32_t *code;
126 uint32_t codeSize;
127 uint32_t codeSizeLimit;
128
129 RelocInfo *relocInfo;
130 FixupInfo *fixupInfo;
131 };
132
133
134 enum OpClass
135 {
136 OPCLASS_MOVE = 0,
137 OPCLASS_LOAD = 1,
138 OPCLASS_STORE = 2,
139 OPCLASS_ARITH = 3,
140 OPCLASS_SHIFT = 4,
141 OPCLASS_SFU = 5,
142 OPCLASS_LOGIC = 6,
143 OPCLASS_COMPARE = 7,
144 OPCLASS_CONVERT = 8,
145 OPCLASS_ATOMIC = 9,
146 OPCLASS_TEXTURE = 10,
147 OPCLASS_SURFACE = 11,
148 OPCLASS_FLOW = 12,
149 OPCLASS_PSEUDO = 14,
150 OPCLASS_VECTOR = 15,
151 OPCLASS_BITFIELD = 16,
152 OPCLASS_CONTROL = 17,
153 OPCLASS_OTHER = 18
154 };
155
156 class Target
157 {
158 public:
159 Target(bool m, bool j, bool s) : hasJoin(m), joinAnterior(j), hasSWSched(s) { }
160 virtual ~Target() { }
161
162 static Target *create(uint32_t chipset);
163 static void destroy(Target *);
164
165 // 0x50 and 0x84 to 0xaf for nv50
166 // 0xc0 to 0xdf for nvc0
167 inline uint32_t getChipset() const { return chipset; }
168
169 virtual CodeEmitter *getCodeEmitter(Program::Type) = 0;
170
171 // Drivers should upload this so we can use it from all programs.
172 // The address chosen is supplied to the relocation routine.
173 virtual void getBuiltinCode(const uint32_t **code, uint32_t *size) const = 0;
174
175 virtual void parseDriverInfo(const struct nv50_ir_prog_info *info) { }
176
177 virtual bool runLegalizePass(Program *, CGStage stage) const = 0;
178
179 public:
180 struct OpInfo
181 {
182 OpInfo *variants;
183 operation op;
184 uint16_t srcTypes;
185 uint16_t dstTypes;
186 uint32_t immdBits;
187 uint8_t srcNr;
188 uint8_t srcMods[3];
189 uint8_t dstMods;
190 uint16_t srcFiles[3];
191 uint16_t dstFiles;
192 unsigned int minEncSize : 4;
193 unsigned int vector : 1;
194 unsigned int predicate : 1;
195 unsigned int commutative : 1;
196 unsigned int pseudo : 1;
197 unsigned int flow : 1;
198 unsigned int hasDest : 1;
199 unsigned int terminator : 1;
200 };
201
202 inline const OpInfo& getOpInfo(const Instruction *) const;
203 inline const OpInfo& getOpInfo(const operation) const;
204
205 inline DataFile nativeFile(DataFile f) const;
206
207 virtual bool insnCanLoad(const Instruction *insn, int s,
208 const Instruction *ld) const = 0;
209 virtual bool insnCanLoadOffset(const Instruction *insn, int s,
210 int offset) const = 0;
211 virtual bool isOpSupported(operation, DataType) const = 0;
212 virtual bool isAccessSupported(DataFile, DataType) const = 0;
213 virtual bool isModSupported(const Instruction *,
214 int s, Modifier) const = 0;
215 virtual bool isSatSupported(const Instruction *) const = 0;
216 virtual bool isPostMultiplySupported(operation op, float f,
217 int& e) const { return false; }
218 virtual bool mayPredicate(const Instruction *,
219 const Value *) const = 0;
220
221 // whether @insn can be issued together with @next (order matters)
222 virtual bool canDualIssue(const Instruction *insn,
223 const Instruction *next) const { return false; }
224 virtual int getLatency(const Instruction *) const { return 1; }
225 virtual int getThroughput(const Instruction *) const { return 1; }
226
227 virtual unsigned int getFileSize(DataFile) const = 0;
228 virtual unsigned int getFileUnit(DataFile) const = 0;
229
230 virtual uint32_t getSVAddress(DataFile, const Symbol *) const = 0;
231
232 public:
233 const bool hasJoin; // true if instructions have a join modifier
234 const bool joinAnterior; // true if join is executed before the op
235 const bool hasSWSched; // true if code should provide scheduling data
236
237 static const uint8_t operationSrcNr[];
238 static const OpClass operationClass[];
239
240 static inline uint8_t getOpSrcNr(operation op)
241 {
242 return operationSrcNr[op];
243 }
244 static inline OpClass getOpClass(operation op)
245 {
246 return operationClass[op];
247 }
248
249 protected:
250 uint32_t chipset;
251
252 DataFile nativeFileMap[DATA_FILE_COUNT];
253
254 OpInfo opInfo[OP_LAST + 1];
255 };
256
257 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
258 {
259 return opInfo[MIN2(insn->op, OP_LAST)];
260 }
261
262 const Target::OpInfo& Target::getOpInfo(const operation op) const
263 {
264 return opInfo[op];
265 }
266
267 inline DataFile Target::nativeFile(DataFile f) const
268 {
269 return nativeFileMap[f];
270 }
271
272 } // namespace nv50_ir
273
274 #endif // __NV50_IR_TARGET_H__