Merge remote-tracking branch 'mattst88/nir-lower-pack-unpack' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_target_nv50.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nv50.h"
24
25 namespace nv50_ir {
26
27 Target *getTargetNV50(unsigned int chipset)
28 {
29 return new TargetNV50(chipset);
30 }
31
32 TargetNV50::TargetNV50(unsigned int card) : Target(true, true, false)
33 {
34 chipset = card;
35
36 wposMask = 0;
37 for (unsigned int i = 0; i <= SV_LAST; ++i)
38 sysvalLocation[i] = ~0;
39
40 initOpInfo();
41 }
42
43 #if 0
44 // BULTINS / LIBRARY FUNCTIONS:
45
46 // TODO
47 static const uint32_t nvc0_builtin_code[] =
48 {
49 };
50
51 static const uint16_t nvc0_builtin_offsets[NV50_BUILTIN_COUNT] =
52 {
53 };
54 #endif
55
56 void
57 TargetNV50::getBuiltinCode(const uint32_t **code, uint32_t *size) const
58 {
59 *code = NULL;
60 *size = 0;
61 }
62
63 uint32_t
64 TargetNV50::getBuiltinOffset(int builtin) const
65 {
66 return 0;
67 }
68
69 struct opProperties
70 {
71 operation op;
72 unsigned int mNeg : 4;
73 unsigned int mAbs : 4;
74 unsigned int mNot : 4;
75 unsigned int mSat : 4;
76 unsigned int fConst : 3;
77 unsigned int fShared : 3;
78 unsigned int fAttrib : 3;
79 unsigned int fImm : 3;
80 };
81
82 static const struct opProperties _initProps[] =
83 {
84 // neg abs not sat c[] s[], a[], imm
85 { OP_ADD, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
86 { OP_SUB, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
87 { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
88 { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
89 { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
90 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
91 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
92 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
93 { OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x0, 0x1, 0x1, 0x0 },
94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
95 { OP_OR, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
96 { OP_XOR, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
97 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
98 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
99 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
100 { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
101 { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
102 { OP_EX2, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0 },
103 { OP_LG2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
104 { OP_RCP, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
105 { OP_RSQ, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
106 { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
107 { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
108 };
109
110 void TargetNV50::initOpInfo()
111 {
112 unsigned int i, j;
113
114 static const uint32_t commutative[(OP_LAST + 31) / 32] =
115 {
116 // ADD,MAD,MUL,AND,OR,XOR,MAX,MIN
117 0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
118 };
119 static const uint32_t shortForm[(OP_LAST + 31) / 32] =
120 {
121 // MOV,ADD,SUB,MUL,MAD,SAD,L/PINTERP,RCP,TEX,TXF
122 0x00014e40, 0x00000040, 0x00000930, 0x00000000
123 };
124 static const operation noDestList[] =
125 {
126 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
127 OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
128 OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
130 OP_SUREDB, OP_BAR
131 };
132 static const operation noPredList[] =
133 {
134 OP_CALL, OP_PREBREAK, OP_PRERET, OP_QUADON, OP_QUADPOP, OP_JOINAT,
135 OP_EMIT, OP_RESTART
136 };
137
138 for (i = 0; i < DATA_FILE_COUNT; ++i)
139 nativeFileMap[i] = (DataFile)i;
140 nativeFileMap[FILE_PREDICATE] = FILE_FLAGS;
141
142 for (i = 0; i < OP_LAST; ++i) {
143 opInfo[i].variants = NULL;
144 opInfo[i].op = (operation)i;
145 opInfo[i].srcTypes = 1 << (int)TYPE_F32;
146 opInfo[i].dstTypes = 1 << (int)TYPE_F32;
147 opInfo[i].immdBits = 0xffffffff;
148 opInfo[i].srcNr = operationSrcNr[i];
149
150 for (j = 0; j < opInfo[i].srcNr; ++j) {
151 opInfo[i].srcMods[j] = 0;
152 opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
153 }
154 opInfo[i].dstMods = 0;
155 opInfo[i].dstFiles = 1 << (int)FILE_GPR;
156
157 opInfo[i].hasDest = 1;
158 opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
159 opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
160 opInfo[i].pseudo = (i < OP_MOV);
161 opInfo[i].predicate = !opInfo[i].pseudo;
162 opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
163 opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
164 }
165 for (i = 0; i < sizeof(noDestList) / sizeof(noDestList[0]); ++i)
166 opInfo[noDestList[i]].hasDest = 0;
167 for (i = 0; i < sizeof(noPredList) / sizeof(noPredList[0]); ++i)
168 opInfo[noPredList[i]].predicate = 0;
169
170 for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
171 const struct opProperties *prop = &_initProps[i];
172
173 for (int s = 0; s < 3; ++s) {
174 if (prop->mNeg & (1 << s))
175 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
176 if (prop->mAbs & (1 << s))
177 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
178 if (prop->mNot & (1 << s))
179 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
180 if (prop->fConst & (1 << s))
181 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
182 if (prop->fShared & (1 << s))
183 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_SHARED;
184 if (prop->fAttrib & (1 << s))
185 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_SHADER_INPUT;
186 if (prop->fImm & (1 << s))
187 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
188 }
189 if (prop->mSat & 8)
190 opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
191 }
192
193 if (chipset >= 0xa0)
194 opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
195 }
196
197 unsigned int
198 TargetNV50::getFileSize(DataFile file) const
199 {
200 switch (file) {
201 case FILE_NULL: return 0;
202 case FILE_GPR: return 256; // in 16-bit units **
203 case FILE_PREDICATE: return 0;
204 case FILE_FLAGS: return 4;
205 case FILE_ADDRESS: return 4;
206 case FILE_IMMEDIATE: return 0;
207 case FILE_MEMORY_CONST: return 65536;
208 case FILE_SHADER_INPUT: return 0x200;
209 case FILE_SHADER_OUTPUT: return 0x200;
210 case FILE_MEMORY_GLOBAL: return 0xffffffff;
211 case FILE_MEMORY_SHARED: return 16 << 10;
212 case FILE_MEMORY_LOCAL: return 48 << 10;
213 case FILE_SYSTEM_VALUE: return 16;
214 default:
215 assert(!"invalid file");
216 return 0;
217 }
218 // ** only first 128 units encodable for 16-bit regs
219 }
220
221 unsigned int
222 TargetNV50::getFileUnit(DataFile file) const
223 {
224 if (file == FILE_GPR || file == FILE_ADDRESS)
225 return 1;
226 if (file == FILE_SYSTEM_VALUE)
227 return 2;
228 return 0;
229 }
230
231 uint32_t
232 TargetNV50::getSVAddress(DataFile shaderFile, const Symbol *sym) const
233 {
234 switch (sym->reg.data.sv.sv) {
235 case SV_FACE:
236 return 0x3fc;
237 case SV_POSITION:
238 {
239 uint32_t addr = sysvalLocation[sym->reg.data.sv.sv];
240 for (int c = 0; c < sym->reg.data.sv.index; ++c)
241 if (wposMask & (1 << c))
242 addr += 4;
243 return addr;
244 }
245 case SV_PRIMITIVE_ID:
246 return shaderFile == FILE_SHADER_INPUT ? 0x18 :
247 sysvalLocation[sym->reg.data.sv.sv];
248 case SV_NCTAID:
249 return 0x8 + 2 * sym->reg.data.sv.index;
250 case SV_CTAID:
251 return 0xc + 2 * sym->reg.data.sv.index;
252 case SV_NTID:
253 return 0x2 + 2 * sym->reg.data.sv.index;
254 case SV_TID:
255 return 0;
256 case SV_SAMPLE_POS:
257 return 0; /* sample position is handled differently */
258 default:
259 return sysvalLocation[sym->reg.data.sv.sv];
260 }
261 }
262
263 // long: rrr, arr, rcr, acr, rrc, arc, gcr, grr
264 // short: rr, ar, rc, gr
265 // immd: ri, gi
266 bool
267 TargetNV50::insnCanLoad(const Instruction *i, int s,
268 const Instruction *ld) const
269 {
270 DataFile sf = ld->src(0).getFile();
271
272 // immediate 0 can be represented by GPR $r63/$r127
273 if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
274 return (!i->isPseudo() &&
275 !i->asTex() &&
276 i->op != OP_EXPORT && i->op != OP_STORE);
277
278 if (sf == FILE_IMMEDIATE && (i->predSrc >= 0 || i->flagsDef >= 0))
279 return false;
280 if (s >= opInfo[i->op].srcNr)
281 return false;
282 if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
283 return false;
284 if (s == 2 && i->src(1).getFile() != FILE_GPR)
285 return false;
286
287 // NOTE: don't rely on flagsDef
288 if (sf == FILE_IMMEDIATE)
289 for (int d = 0; i->defExists(d); ++d)
290 if (i->def(d).getFile() == FILE_FLAGS)
291 return false;
292
293 unsigned mode = 0;
294
295 for (int z = 0; z < Target::operationSrcNr[i->op]; ++z) {
296 DataFile zf = (z == s) ? sf : i->src(z).getFile();
297 switch (zf) {
298 case FILE_GPR:
299 break;
300 case FILE_MEMORY_SHARED:
301 case FILE_SHADER_INPUT:
302 mode |= 1 << (z * 2);
303 break;
304 case FILE_MEMORY_CONST:
305 mode |= 2 << (z * 2);
306 break;
307 case FILE_IMMEDIATE:
308 mode |= 3 << (z * 2);
309 default:
310 break;
311 }
312 }
313
314 switch (mode) {
315 case 0x00:
316 case 0x01:
317 case 0x03:
318 case 0x08:
319 case 0x0c:
320 case 0x20:
321 case 0x21:
322 break;
323 case 0x09:
324 // Shader inputs get transformed to p[] in geometry shaders, and those
325 // aren't allowed to be used at the same time as c[].
326 if (ld->bb->getProgram()->getType() == Program::TYPE_GEOMETRY)
327 return false;
328 break;
329 case 0x0d:
330 if (ld->bb->getProgram()->getType() != Program::TYPE_GEOMETRY)
331 return false;
332 break;
333 default:
334 return false;
335 }
336
337 uint8_t ldSize;
338
339 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) {
340 // 32-bit MUL will be split into 16-bit MULs
341 if (ld->src(0).isIndirect(0))
342 return false;
343 if (sf == FILE_IMMEDIATE)
344 return false;
345 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH && sf == FILE_MEMORY_CONST)
346 return false;
347 ldSize = 2;
348 } else {
349 ldSize = typeSizeof(ld->dType);
350 }
351
352 if (sf == FILE_IMMEDIATE)
353 return ldSize <= 4;
354
355
356 // Check if memory access is encodable:
357
358 if (ldSize < 4 && sf == FILE_SHADER_INPUT) // no < 4-byte aligned a[] access
359 return false;
360 if (ld->getSrc(0)->reg.data.offset > (int32_t)(127 * ldSize))
361 return false;
362
363 if (ld->src(0).isIndirect(0)) {
364 for (int z = 0; i->srcExists(z); ++z)
365 if (i->src(z).isIndirect(0))
366 return false;
367
368 // s[] access only possible in CP, $aX always applies
369 if (sf == FILE_MEMORY_SHARED)
370 return true;
371 if (!ld->bb) // can't check type ...
372 return false;
373 Program::Type pt = ld->bb->getProgram()->getType();
374
375 // $aX applies to c[] only in VP, FP, GP if p[] is not accessed
376 if (pt == Program::TYPE_COMPUTE)
377 return false;
378 if (pt == Program::TYPE_GEOMETRY) {
379 if (sf == FILE_MEMORY_CONST)
380 return i->src(s).getFile() != FILE_SHADER_INPUT;
381 return sf == FILE_SHADER_INPUT;
382 }
383 return sf == FILE_MEMORY_CONST;
384 }
385 return true;
386 }
387
388 bool
389 TargetNV50::insnCanLoadOffset(const Instruction *i, int s, int offset) const
390 {
391 if (!i->src(s).isIndirect(0))
392 return true;
393 offset += i->src(s).get()->reg.data.offset;
394 if (i->op == OP_LOAD || i->op == OP_STORE) {
395 // There are some restrictions in theory, but in practice they're never
396 // going to be hit. When we enable shared/global memory, this will
397 // become more important.
398 return true;
399 }
400 return offset >= 0 && offset <= (int32_t)(127 * i->src(s).get()->reg.size);
401 }
402
403 bool
404 TargetNV50::isAccessSupported(DataFile file, DataType ty) const
405 {
406 if (ty == TYPE_B96 || ty == TYPE_NONE)
407 return false;
408 if (typeSizeof(ty) > 4)
409 return (file == FILE_MEMORY_LOCAL) || (file == FILE_MEMORY_GLOBAL);
410 return true;
411 }
412
413 bool
414 TargetNV50::isOpSupported(operation op, DataType ty) const
415 {
416 if (ty == TYPE_F64 && chipset < 0xa0)
417 return false;
418
419 switch (op) {
420 case OP_PRERET:
421 return chipset >= 0xa0;
422 case OP_TXG:
423 return chipset >= 0xa3 && chipset != 0xaa && chipset != 0xac;
424 case OP_POW:
425 case OP_SQRT:
426 case OP_DIV:
427 case OP_MOD:
428 case OP_SET_AND:
429 case OP_SET_OR:
430 case OP_SET_XOR:
431 case OP_SLCT:
432 case OP_SELP:
433 case OP_POPCNT:
434 case OP_INSBF:
435 case OP_EXTBF:
436 case OP_EXIT: // want exit modifier instead (on NOP if required)
437 case OP_MEMBAR:
438 return false;
439 case OP_SAD:
440 return ty == TYPE_S32;
441 case OP_SET:
442 return !isFloatType(ty);
443 default:
444 return true;
445 }
446 }
447
448 bool
449 TargetNV50::isModSupported(const Instruction *insn, int s, Modifier mod) const
450 {
451 if (!isFloatType(insn->dType)) {
452 switch (insn->op) {
453 case OP_ABS:
454 case OP_NEG:
455 case OP_CVT:
456 case OP_CEIL:
457 case OP_FLOOR:
458 case OP_TRUNC:
459 case OP_AND:
460 case OP_OR:
461 case OP_XOR:
462 break;
463 case OP_ADD:
464 if (insn->src(s ? 0 : 1).mod.neg())
465 return false;
466 break;
467 case OP_SUB:
468 if (s == 0)
469 return insn->src(1).mod.neg() ? false : true;
470 break;
471 case OP_SET:
472 if (insn->sType != TYPE_F32)
473 return false;
474 break;
475 default:
476 return false;
477 }
478 }
479 if (s >= opInfo[insn->op].srcNr || s >= 3)
480 return false;
481 return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
482 }
483
484 bool
485 TargetNV50::mayPredicate(const Instruction *insn, const Value *pred) const
486 {
487 if (insn->getPredicate() || insn->flagsSrc >= 0)
488 return false;
489 for (int s = 0; insn->srcExists(s); ++s)
490 if (insn->src(s).getFile() == FILE_IMMEDIATE)
491 return false;
492 return opInfo[insn->op].predicate;
493 }
494
495 bool
496 TargetNV50::isSatSupported(const Instruction *insn) const
497 {
498 if (insn->op == OP_CVT)
499 return true;
500 if (insn->dType != TYPE_F32)
501 return false;
502 return opInfo[insn->op].dstMods & NV50_IR_MOD_SAT;
503 }
504
505 int TargetNV50::getLatency(const Instruction *i) const
506 {
507 // TODO: tune these values
508 if (i->op == OP_LOAD) {
509 switch (i->src(0).getFile()) {
510 case FILE_MEMORY_LOCAL:
511 case FILE_MEMORY_GLOBAL:
512 return 100; // really 400 to 800
513 default:
514 return 22;
515 }
516 }
517 return 22;
518 }
519
520 // These are "inverse" throughput values, i.e. the number of cycles required
521 // to issue a specific instruction for a full warp (32 threads).
522 //
523 // Assuming we have more than 1 warp in flight, a higher issue latency results
524 // in a lower result latency since the MP will have spent more time with other
525 // warps.
526 // This also helps to determine the number of cycles between instructions in
527 // a single warp.
528 //
529 int TargetNV50::getThroughput(const Instruction *i) const
530 {
531 // TODO: tune these values
532 if (i->dType == TYPE_F32) {
533 switch (i->op) {
534 case OP_RCP:
535 case OP_RSQ:
536 case OP_LG2:
537 case OP_SIN:
538 case OP_COS:
539 case OP_PRESIN:
540 case OP_PREEX2:
541 return 16;
542 default:
543 return 4;
544 }
545 } else
546 if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
547 return 4;
548 } else
549 if (i->dType == TYPE_F64) {
550 return 32;
551 } else {
552 return 1;
553 }
554 }
555
556 static void
557 recordLocation(uint16_t *locs, uint8_t *masks,
558 const struct nv50_ir_varying *var)
559 {
560 uint16_t addr = var->slot[0] * 4;
561
562 switch (var->sn) {
563 case TGSI_SEMANTIC_POSITION: locs[SV_POSITION] = addr; break;
564 case TGSI_SEMANTIC_INSTANCEID: locs[SV_INSTANCE_ID] = addr; break;
565 case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break;
566 case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break;
567 case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
568 case TGSI_SEMANTIC_VIEWPORT_INDEX: locs[SV_VIEWPORT_INDEX] = addr; break;
569 default:
570 break;
571 }
572 if (var->sn == TGSI_SEMANTIC_POSITION && masks)
573 masks[0] = var->mask;
574 }
575
576 void
577 TargetNV50::parseDriverInfo(const struct nv50_ir_prog_info *info)
578 {
579 unsigned int i;
580 for (i = 0; i < info->numOutputs; ++i)
581 recordLocation(sysvalLocation, NULL, &info->out[i]);
582 for (i = 0; i < info->numInputs; ++i)
583 recordLocation(sysvalLocation, &wposMask, &info->in[i]);
584 for (i = 0; i < info->numSysVals; ++i)
585 recordLocation(sysvalLocation, NULL, &info->sv[i]);
586
587 if (sysvalLocation[SV_POSITION] >= 0x200) {
588 // not assigned by driver, but we need it internally
589 wposMask = 0x8;
590 sysvalLocation[SV_POSITION] = 0;
591 }
592 }
593
594 } // namespace nv50_ir