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[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_target_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 Target *getTargetNVC0(unsigned int chipset)
28 {
29 return new TargetNVC0(chipset);
30 }
31
32 TargetNVC0::TargetNVC0(unsigned int card) :
33 Target(card < 0x110, false, card >= 0xe4)
34 {
35 chipset = card;
36 initOpInfo();
37 }
38
39 // BULTINS / LIBRARY FUNCTIONS:
40
41 // lazyness -> will just hardcode everything for the time being
42
43 #include "lib/gf100.asm.h"
44 #include "lib/gk104.asm.h"
45 #include "lib/gk110.asm.h"
46
47 void
48 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
49 {
50 switch (chipset & ~0xf) {
51 case 0xe0:
52 if (chipset < NVISA_GK20A_CHIPSET) {
53 *code = (const uint32_t *)&gk104_builtin_code[0];
54 *size = sizeof(gk104_builtin_code);
55 break;
56 }
57 /* fall-through for GK20A */
58 case 0xf0:
59 case 0x100:
60 *code = (const uint32_t *)&gk110_builtin_code[0];
61 *size = sizeof(gk110_builtin_code);
62 break;
63 default:
64 *code = (const uint32_t *)&gf100_builtin_code[0];
65 *size = sizeof(gf100_builtin_code);
66 break;
67 }
68 }
69
70 uint32_t
71 TargetNVC0::getBuiltinOffset(int builtin) const
72 {
73 assert(builtin < NVC0_BUILTIN_COUNT);
74
75 switch (chipset & ~0xf) {
76 case 0xe0:
77 if (chipset < NVISA_GK20A_CHIPSET)
78 return gk104_builtin_offsets[builtin];
79 /* fall-through for GK20A */
80 case 0xf0:
81 case 0x100:
82 return gk110_builtin_offsets[builtin];
83 default:
84 return gf100_builtin_offsets[builtin];
85 }
86 }
87
88 struct opProperties
89 {
90 operation op;
91 unsigned int mNeg : 4;
92 unsigned int mAbs : 4;
93 unsigned int mNot : 4;
94 unsigned int mSat : 4;
95 unsigned int fConst : 3;
96 unsigned int fImmd : 4; // last bit indicates if full immediate is suppoted
97 };
98
99 static const struct opProperties _initProps[] =
100 {
101 // neg abs not sat c[] imm
102 { OP_ADD, 0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
103 { OP_SUB, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
105 { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
106 { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
107 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // special c[] constraint
108 { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // keep the same as OP_MAD
109 { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 },
110 { OP_MADSP, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
112 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
113 { OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
114 { OP_CEIL, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
115 { OP_FLOOR, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
116 { OP_TRUNC, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
118 { OP_OR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
119 { OP_XOR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
120 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
122 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
123 { OP_SLCT, 0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
124 { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
125 { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
126 { OP_COS, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
129 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
130 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
131 { OP_RSQ, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
132 { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
133 { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
134 { OP_CALL, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
135 { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
136 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
137 { OP_EXTBF, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
138 { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
139 { OP_PERMT, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
140 { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
141 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
142 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
143 // saturate only:
144 { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
145 { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
146 };
147
148 static const struct opProperties _initPropsNVE4[] = {
149 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
150 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
151 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
152 { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
153 { OP_SUBFM, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
154 { OP_SUEAU, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
155 };
156
157 static const struct opProperties _initPropsGM107[] = {
158 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
159 { OP_SULDP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
160 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
161 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
162 { OP_SUREDB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
163 { OP_SUREDP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
164 };
165
166 void TargetNVC0::initProps(const struct opProperties *props, int size)
167 {
168 for (int i = 0; i < size; ++i) {
169 const struct opProperties *prop = &props[i];
170
171 for (int s = 0; s < 3; ++s) {
172 if (prop->mNeg & (1 << s))
173 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
174 if (prop->mAbs & (1 << s))
175 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
176 if (prop->mNot & (1 << s))
177 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
178 if (prop->fConst & (1 << s))
179 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
180 if (prop->fImmd & (1 << s))
181 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
182 if (prop->fImmd & 8)
183 opInfo[prop->op].immdBits = 0xffffffff;
184 }
185 if (prop->mSat & 8)
186 opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
187 }
188 }
189
190 void TargetNVC0::initOpInfo()
191 {
192 unsigned int i, j;
193
194 static const uint32_t commutative[(OP_LAST + 31) / 32] =
195 {
196 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN, SET_AND, SET_OR, SET_XOR,
197 // SET, SELP, SLCT
198 0x0ce0ca00, 0x0000007e, 0x00000000, 0x00000000
199 };
200
201 static const uint32_t shortForm[(OP_LAST + 31) / 32] =
202 {
203 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN
204 0x0ce0ca00, 0x00000000, 0x00000000, 0x00000000
205 };
206
207 static const operation noDest[] =
208 {
209 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
210 OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
211 OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
213 OP_SUREDB, OP_BAR
214 };
215
216 static const operation noPred[] =
217 {
218 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
219 OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
220 };
221
222 for (i = 0; i < DATA_FILE_COUNT; ++i)
223 nativeFileMap[i] = (DataFile)i;
224 nativeFileMap[FILE_ADDRESS] = FILE_GPR;
225
226 for (i = 0; i < OP_LAST; ++i) {
227 opInfo[i].variants = NULL;
228 opInfo[i].op = (operation)i;
229 opInfo[i].srcTypes = 1 << (int)TYPE_F32;
230 opInfo[i].dstTypes = 1 << (int)TYPE_F32;
231 opInfo[i].immdBits = 0;
232 opInfo[i].srcNr = operationSrcNr[i];
233
234 for (j = 0; j < opInfo[i].srcNr; ++j) {
235 opInfo[i].srcMods[j] = 0;
236 opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
237 }
238 opInfo[i].dstMods = 0;
239 opInfo[i].dstFiles = 1 << (int)FILE_GPR;
240
241 opInfo[i].hasDest = 1;
242 opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
243 opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
244 opInfo[i].pseudo = (i < OP_MOV);
245 opInfo[i].predicate = !opInfo[i].pseudo;
246 opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
247 opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
248 }
249 for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
250 opInfo[noDest[i]].hasDest = 0;
251 for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
252 opInfo[noPred[i]].predicate = 0;
253
254 initProps(_initProps, ARRAY_SIZE(_initProps));
255 if (chipset >= NVISA_GM107_CHIPSET)
256 initProps(_initPropsGM107, ARRAY_SIZE(_initPropsGM107));
257 else if (chipset >= NVISA_GK104_CHIPSET)
258 initProps(_initPropsNVE4, ARRAY_SIZE(_initPropsNVE4));
259 }
260
261 unsigned int
262 TargetNVC0::getFileSize(DataFile file) const
263 {
264 const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
265 const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
266 switch (file) {
267 case FILE_NULL: return 0;
268 case FILE_GPR: return MIN2(gprs, smregs / threads);
269 case FILE_PREDICATE: return 7;
270 case FILE_FLAGS: return 1;
271 case FILE_ADDRESS: return 0;
272 case FILE_IMMEDIATE: return 0;
273 case FILE_MEMORY_CONST: return 65536;
274 case FILE_SHADER_INPUT: return 0x400;
275 case FILE_SHADER_OUTPUT: return 0x400;
276 case FILE_MEMORY_BUFFER: return 0xffffffff;
277 case FILE_MEMORY_GLOBAL: return 0xffffffff;
278 case FILE_MEMORY_SHARED: return 16 << 10;
279 case FILE_MEMORY_LOCAL: return 48 << 10;
280 case FILE_SYSTEM_VALUE: return 32;
281 default:
282 assert(!"invalid file");
283 return 0;
284 }
285 }
286
287 unsigned int
288 TargetNVC0::getFileUnit(DataFile file) const
289 {
290 if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
291 return 2;
292 return 0;
293 }
294
295 uint32_t
296 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
297 {
298 const int idx = sym->reg.data.sv.index;
299 const SVSemantic sv = sym->reg.data.sv.sv;
300
301 const bool isInput = shaderFile == FILE_SHADER_INPUT;
302 const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
303
304 switch (sv) {
305 case SV_POSITION: return 0x070 + idx * 4;
306 case SV_INSTANCE_ID: return 0x2f8;
307 case SV_VERTEX_ID: return 0x2fc;
308 case SV_PRIMITIVE_ID: return isInput ? 0x060 : 0x040;
309 case SV_LAYER: return 0x064;
310 case SV_VIEWPORT_INDEX: return 0x068;
311 case SV_POINT_SIZE: return 0x06c;
312 case SV_CLIP_DISTANCE: return 0x2c0 + idx * 4;
313 case SV_POINT_COORD: return 0x2e0 + idx * 4;
314 case SV_FACE: return 0x3fc;
315 case SV_TESS_OUTER: return 0x000 + idx * 4;
316 case SV_TESS_INNER: return 0x010 + idx * 4;
317 case SV_TESS_COORD: return 0x2f0 + idx * 4;
318 case SV_NTID: return kepler ? (0x00 + idx * 4) : ~0;
319 case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
320 case SV_GRIDID: return kepler ? 0x18 : ~0;
321 case SV_WORK_DIM: return 0x1c;
322 case SV_SAMPLE_INDEX: return 0;
323 case SV_SAMPLE_POS: return 0;
324 case SV_SAMPLE_MASK: return 0;
325 case SV_BASEVERTEX: return 0;
326 case SV_BASEINSTANCE: return 0;
327 case SV_DRAWID: return 0;
328 default:
329 return 0xffffffff;
330 }
331 }
332
333 bool
334 TargetNVC0::insnCanLoad(const Instruction *i, int s,
335 const Instruction *ld) const
336 {
337 DataFile sf = ld->src(0).getFile();
338
339 // immediate 0 can be represented by GPR $r63/$r255
340 if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
341 return (!i->isPseudo() &&
342 !i->asTex() &&
343 i->op != OP_EXPORT && i->op != OP_STORE);
344
345 if (s >= opInfo[i->op].srcNr)
346 return false;
347 if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
348 return false;
349
350 // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
351 if (ld->src(0).isIndirect(0))
352 return false;
353 // these are implemented using shf.r and shf.l which can't load consts
354 if ((i->op == OP_SHL || i->op == OP_SHR) && typeSizeof(i->sType) == 8 &&
355 sf == FILE_MEMORY_CONST)
356 return false;
357
358 for (int k = 0; i->srcExists(k); ++k) {
359 if (i->src(k).getFile() == FILE_IMMEDIATE) {
360 if (k == 2 && i->op == OP_SUCLAMP) // special case
361 continue;
362 if (k == 1 && i->op == OP_SHLADD) // special case
363 continue;
364 if (i->getSrc(k)->reg.data.u64 != 0)
365 return false;
366 } else
367 if (i->src(k).getFile() != FILE_GPR &&
368 i->src(k).getFile() != FILE_PREDICATE &&
369 i->src(k).getFile() != FILE_FLAGS) {
370 return false;
371 }
372 }
373
374 // not all instructions support full 32 bit immediates
375 if (sf == FILE_IMMEDIATE) {
376 Storage &reg = ld->getSrc(0)->asImm()->reg;
377
378 if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
379 switch (i->sType) {
380 case TYPE_F64:
381 if (reg.data.u64 & 0x00000fffffffffffULL)
382 return false;
383 break;
384 case TYPE_F32:
385 if (reg.data.u32 & 0xfff)
386 return false;
387 break;
388 case TYPE_S32:
389 case TYPE_U32:
390 // with u32, 0xfffff counts as 0xffffffff as well
391 if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
392 return false;
393 break;
394 case TYPE_U8:
395 case TYPE_S8:
396 case TYPE_U16:
397 case TYPE_S16:
398 case TYPE_F16:
399 break;
400 default:
401 return false;
402 }
403 } else
404 if (i->op == OP_ADD && i->sType == TYPE_F32) {
405 // add f32 LIMM cannot saturate
406 if (i->saturate && (reg.data.u32 & 0xfff))
407 return false;
408 }
409 }
410
411 return true;
412 }
413
414 bool
415 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
416 {
417 const ValueRef& ref = insn->src(s);
418 if (ref.getFile() == FILE_MEMORY_CONST &&
419 (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
420 return offset >= -0x8000 && offset < 0x8000;
421 return true;
422 }
423
424 bool
425 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
426 {
427 if (ty == TYPE_NONE)
428 return false;
429 if (file == FILE_MEMORY_CONST) {
430 if (getChipset() >= NVISA_GM107_CHIPSET)
431 return typeSizeof(ty) <= 4;
432 else
433 if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?
434 return typeSizeof(ty) <= 8;
435 }
436 if (ty == TYPE_B96)
437 return false;
438 return true;
439 }
440
441 bool
442 TargetNVC0::isOpSupported(operation op, DataType ty) const
443 {
444 if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
445 return false;
446 if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
447 return false;
448 return true;
449 }
450
451 bool
452 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
453 {
454 if (!isFloatType(insn->dType)) {
455 switch (insn->op) {
456 case OP_ABS:
457 case OP_NEG:
458 case OP_CVT:
459 case OP_CEIL:
460 case OP_FLOOR:
461 case OP_TRUNC:
462 case OP_AND:
463 case OP_OR:
464 case OP_XOR:
465 case OP_POPCNT:
466 case OP_BFIND:
467 break;
468 case OP_SET:
469 if (insn->sType != TYPE_F32)
470 return false;
471 break;
472 case OP_ADD:
473 if (mod.abs())
474 return false;
475 if (insn->src(s ? 0 : 1).mod.neg())
476 return false;
477 break;
478 case OP_SUB:
479 if (s == 0)
480 return insn->src(1).mod.neg() ? false : true;
481 break;
482 case OP_SHLADD:
483 if (s == 1)
484 return false;
485 if (insn->src(s ? 0 : 2).mod.neg())
486 return false;
487 break;
488 default:
489 return false;
490 }
491 }
492 if (s >= opInfo[insn->op].srcNr || s >= 3)
493 return false;
494 return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
495 }
496
497 bool
498 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
499 {
500 if (insn->getPredicate())
501 return false;
502 return opInfo[insn->op].predicate;
503 }
504
505 bool
506 TargetNVC0::isSatSupported(const Instruction *insn) const
507 {
508 if (insn->op == OP_CVT)
509 return true;
510 if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
511 return false;
512
513 if (insn->dType == TYPE_U32)
514 return (insn->op == OP_ADD) || (insn->op == OP_MAD);
515
516 // add f32 LIMM cannot saturate
517 if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
518 if (insn->getSrc(1)->asImm() &&
519 insn->getSrc(1)->reg.data.u32 & 0xfff)
520 return false;
521 }
522
523 return insn->dType == TYPE_F32;
524 }
525
526 bool
527 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
528 {
529 if (op != OP_MUL)
530 return false;
531 f = fabsf(f);
532 e = static_cast<int>(log2f(f));
533 if (e < -3 || e > 3)
534 return false;
535 return f == exp2f(static_cast<float>(e));
536 }
537
538 // TODO: better values
539 // this could be more precise, e.g. depending on the issue-to-read/write delay
540 // of the depending instruction, but it's good enough
541 int TargetNVC0::getLatency(const Instruction *i) const
542 {
543 if (chipset >= 0xe4) {
544 if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
545 return 20;
546 switch (i->op) {
547 case OP_LINTERP:
548 case OP_PINTERP:
549 return 15;
550 case OP_LOAD:
551 if (i->src(0).getFile() == FILE_MEMORY_CONST)
552 return 9;
553 // fall through
554 case OP_VFETCH:
555 return 24;
556 default:
557 if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
558 return 17;
559 if (i->op == OP_MUL && i->dType != TYPE_F32)
560 return 15;
561 return 9;
562 }
563 } else {
564 if (i->op == OP_LOAD) {
565 if (i->cache == CACHE_CV)
566 return 700;
567 return 48;
568 }
569 return 24;
570 }
571 return 32;
572 }
573
574 // These are "inverse" throughput values, i.e. the number of cycles required
575 // to issue a specific instruction for a full warp (32 threads).
576 //
577 // Assuming we have more than 1 warp in flight, a higher issue latency results
578 // in a lower result latency since the MP will have spent more time with other
579 // warps.
580 // This also helps to determine the number of cycles between instructions in
581 // a single warp.
582 //
583 int TargetNVC0::getThroughput(const Instruction *i) const
584 {
585 // TODO: better values
586 if (i->dType == TYPE_F32) {
587 switch (i->op) {
588 case OP_ADD:
589 case OP_MUL:
590 case OP_MAD:
591 case OP_FMA:
592 return 1;
593 case OP_CVT:
594 case OP_CEIL:
595 case OP_FLOOR:
596 case OP_TRUNC:
597 case OP_SET:
598 case OP_SLCT:
599 case OP_MIN:
600 case OP_MAX:
601 return 2;
602 case OP_RCP:
603 case OP_RSQ:
604 case OP_LG2:
605 case OP_SIN:
606 case OP_COS:
607 case OP_PRESIN:
608 case OP_PREEX2:
609 default:
610 return 8;
611 }
612 } else
613 if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
614 switch (i->op) {
615 case OP_ADD:
616 case OP_AND:
617 case OP_OR:
618 case OP_XOR:
619 case OP_NOT:
620 return 1;
621 case OP_MUL:
622 case OP_MAD:
623 case OP_CVT:
624 case OP_SET:
625 case OP_SLCT:
626 case OP_SHL:
627 case OP_SHR:
628 case OP_NEG:
629 case OP_ABS:
630 case OP_MIN:
631 case OP_MAX:
632 default:
633 return 2;
634 }
635 } else
636 if (i->dType == TYPE_F64) {
637 return 2;
638 } else {
639 return 1;
640 }
641 }
642
643 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
644 {
645 const OpClass clA = operationClass[a->op];
646 const OpClass clB = operationClass[b->op];
647
648 if (getChipset() >= 0xe4) {
649 // not texturing
650 // not if the 2nd instruction isn't necessarily executed
651 if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
652 return false;
653
654 // Check that a and b don't write to the same sources, nor that b reads
655 // anything that a writes.
656 if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b))
657 return false;
658
659 // anything with MOV
660 if (a->op == OP_MOV || b->op == OP_MOV)
661 return true;
662 if (clA == clB) {
663 switch (clA) {
664 // there might be more
665 case OPCLASS_COMPARE:
666 if ((a->op == OP_MIN || a->op == OP_MAX) &&
667 (b->op == OP_MIN || b->op == OP_MAX))
668 break;
669 return false;
670 case OPCLASS_ARITH:
671 break;
672 default:
673 return false;
674 }
675 // only F32 arith or integer additions
676 return (a->dType == TYPE_F32 || a->op == OP_ADD ||
677 b->dType == TYPE_F32 || b->op == OP_ADD);
678 }
679 // nothing with TEXBAR
680 if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
681 return false;
682 // no loads and stores accessing the same space
683 if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
684 (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
685 if (a->src(0).getFile() == b->src(0).getFile())
686 return false;
687 // no > 32-bit ops
688 if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
689 typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
690 return false;
691 return true;
692 } else {
693 return false; // info not needed (yet)
694 }
695 }
696
697 } // namespace nv50_ir