2 #include "util/u_inlines.h"
3 #include "util/u_memory.h"
4 #include "util/u_math.h"
5 #include "util/u_surface.h"
7 #include "nouveau_screen.h"
8 #include "nouveau_context.h"
9 #include "nouveau_winsys.h"
10 #include "nouveau_fence.h"
11 #include "nouveau_buffer.h"
12 #include "nouveau_mm.h"
14 struct nouveau_transfer
{
15 struct pipe_transfer base
;
18 struct nouveau_bo
*bo
;
19 struct nouveau_mm_allocation
*mm
;
23 static inline struct nouveau_transfer
*
24 nouveau_transfer(struct pipe_transfer
*transfer
)
26 return (struct nouveau_transfer
*)transfer
;
30 nouveau_buffer_malloc(struct nv04_resource
*buf
)
33 buf
->data
= align_malloc(buf
->base
.width0
, NOUVEAU_MIN_BUFFER_MAP_ALIGN
);
38 nouveau_buffer_allocate(struct nouveau_screen
*screen
,
39 struct nv04_resource
*buf
, unsigned domain
)
41 uint32_t size
= align(buf
->base
.width0
, 0x100);
43 if (domain
== NOUVEAU_BO_VRAM
) {
44 buf
->mm
= nouveau_mm_allocate(screen
->mm_VRAM
, size
,
45 &buf
->bo
, &buf
->offset
);
47 return nouveau_buffer_allocate(screen
, buf
, NOUVEAU_BO_GART
);
48 NOUVEAU_DRV_STAT(screen
, buf_obj_current_bytes_vid
, buf
->base
.width0
);
50 if (domain
== NOUVEAU_BO_GART
) {
51 buf
->mm
= nouveau_mm_allocate(screen
->mm_GART
, size
,
52 &buf
->bo
, &buf
->offset
);
55 NOUVEAU_DRV_STAT(screen
, buf_obj_current_bytes_sys
, buf
->base
.width0
);
58 if (!nouveau_buffer_malloc(buf
))
63 buf
->address
= buf
->bo
->offset
+ buf
->offset
;
65 util_range_set_empty(&buf
->valid_buffer_range
);
71 release_allocation(struct nouveau_mm_allocation
**mm
,
72 struct nouveau_fence
*fence
)
74 nouveau_fence_work(fence
, nouveau_mm_free_work
, *mm
);
79 nouveau_buffer_release_gpu_storage(struct nv04_resource
*buf
)
81 if (buf
->fence
&& buf
->fence
->state
< NOUVEAU_FENCE_STATE_FLUSHED
) {
82 nouveau_fence_work(buf
->fence
, nouveau_fence_unref_bo
, buf
->bo
);
85 nouveau_bo_ref(NULL
, &buf
->bo
);
89 release_allocation(&buf
->mm
, buf
->fence
);
91 if (buf
->domain
== NOUVEAU_BO_VRAM
)
92 NOUVEAU_DRV_STAT_RES(buf
, buf_obj_current_bytes_vid
, -(uint64_t)buf
->base
.width0
);
93 if (buf
->domain
== NOUVEAU_BO_GART
)
94 NOUVEAU_DRV_STAT_RES(buf
, buf_obj_current_bytes_sys
, -(uint64_t)buf
->base
.width0
);
100 nouveau_buffer_reallocate(struct nouveau_screen
*screen
,
101 struct nv04_resource
*buf
, unsigned domain
)
103 nouveau_buffer_release_gpu_storage(buf
);
105 nouveau_fence_ref(NULL
, &buf
->fence
);
106 nouveau_fence_ref(NULL
, &buf
->fence_wr
);
108 buf
->status
&= NOUVEAU_BUFFER_STATUS_REALLOC_MASK
;
110 return nouveau_buffer_allocate(screen
, buf
, domain
);
114 nouveau_buffer_destroy(struct pipe_screen
*pscreen
,
115 struct pipe_resource
*presource
)
117 struct nv04_resource
*res
= nv04_resource(presource
);
119 nouveau_buffer_release_gpu_storage(res
);
121 if (res
->data
&& !(res
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
))
122 align_free(res
->data
);
124 nouveau_fence_ref(NULL
, &res
->fence
);
125 nouveau_fence_ref(NULL
, &res
->fence_wr
);
127 util_range_destroy(&res
->valid_buffer_range
);
131 NOUVEAU_DRV_STAT(nouveau_screen(pscreen
), buf_obj_current_count
, -1);
134 /* Set up a staging area for the transfer. This is either done in "regular"
135 * system memory if the driver supports push_data (nv50+) and the data is
136 * small enough (and permit_pb == true), or in GART memory.
139 nouveau_transfer_staging(struct nouveau_context
*nv
,
140 struct nouveau_transfer
*tx
, bool permit_pb
)
142 const unsigned adj
= tx
->base
.box
.x
& NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK
;
143 const unsigned size
= align(tx
->base
.box
.width
, 4) + adj
;
148 if ((size
<= nv
->screen
->transfer_pushbuf_threshold
) && permit_pb
) {
149 tx
->map
= align_malloc(size
, NOUVEAU_MIN_BUFFER_MAP_ALIGN
);
154 nouveau_mm_allocate(nv
->screen
->mm_GART
, size
, &tx
->bo
, &tx
->offset
);
157 if (!nouveau_bo_map(tx
->bo
, 0, NULL
))
158 tx
->map
= (uint8_t *)tx
->bo
->map
+ tx
->offset
;
164 /* Copies data from the resource into the transfer's temporary GART
165 * buffer. Also updates buf->data if present.
167 * Maybe just migrate to GART right away if we actually need to do this. */
169 nouveau_transfer_read(struct nouveau_context
*nv
, struct nouveau_transfer
*tx
)
171 struct nv04_resource
*buf
= nv04_resource(tx
->base
.resource
);
172 const unsigned base
= tx
->base
.box
.x
;
173 const unsigned size
= tx
->base
.box
.width
;
175 NOUVEAU_DRV_STAT(nv
->screen
, buf_read_bytes_staging_vid
, size
);
177 nv
->copy_data(nv
, tx
->bo
, tx
->offset
, NOUVEAU_BO_GART
,
178 buf
->bo
, buf
->offset
+ base
, buf
->domain
, size
);
180 if (nouveau_bo_wait(tx
->bo
, NOUVEAU_BO_RD
, nv
->client
))
184 memcpy(buf
->data
+ base
, tx
->map
, size
);
190 nouveau_transfer_write(struct nouveau_context
*nv
, struct nouveau_transfer
*tx
,
191 unsigned offset
, unsigned size
)
193 struct nv04_resource
*buf
= nv04_resource(tx
->base
.resource
);
194 uint8_t *data
= tx
->map
+ offset
;
195 const unsigned base
= tx
->base
.box
.x
+ offset
;
196 const bool can_cb
= !((base
| size
) & 3);
199 memcpy(data
, buf
->data
+ base
, size
);
201 buf
->status
|= NOUVEAU_BUFFER_STATUS_DIRTY
;
203 if (buf
->domain
== NOUVEAU_BO_VRAM
)
204 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_staging_vid
, size
);
205 if (buf
->domain
== NOUVEAU_BO_GART
)
206 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_staging_sys
, size
);
209 nv
->copy_data(nv
, buf
->bo
, buf
->offset
+ base
, buf
->domain
,
210 tx
->bo
, tx
->offset
+ offset
, NOUVEAU_BO_GART
, size
);
212 if (nv
->push_cb
&& can_cb
)
214 base
, size
/ 4, (const uint32_t *)data
);
216 nv
->push_data(nv
, buf
->bo
, buf
->offset
+ base
, buf
->domain
, size
, data
);
218 nouveau_fence_ref(nv
->screen
->fence
.current
, &buf
->fence
);
219 nouveau_fence_ref(nv
->screen
->fence
.current
, &buf
->fence_wr
);
222 /* Does a CPU wait for the buffer's backing data to become reliably accessible
223 * for write/read by waiting on the buffer's relevant fences.
226 nouveau_buffer_sync(struct nouveau_context
*nv
,
227 struct nv04_resource
*buf
, unsigned rw
)
229 if (rw
== PIPE_TRANSFER_READ
) {
232 NOUVEAU_DRV_STAT_RES(buf
, buf_non_kernel_fence_sync_count
,
233 !nouveau_fence_signalled(buf
->fence_wr
));
234 if (!nouveau_fence_wait(buf
->fence_wr
, &nv
->debug
))
239 NOUVEAU_DRV_STAT_RES(buf
, buf_non_kernel_fence_sync_count
,
240 !nouveau_fence_signalled(buf
->fence
));
241 if (!nouveau_fence_wait(buf
->fence
, &nv
->debug
))
244 nouveau_fence_ref(NULL
, &buf
->fence
);
246 nouveau_fence_ref(NULL
, &buf
->fence_wr
);
252 nouveau_buffer_busy(struct nv04_resource
*buf
, unsigned rw
)
254 if (rw
== PIPE_TRANSFER_READ
)
255 return (buf
->fence_wr
&& !nouveau_fence_signalled(buf
->fence_wr
));
257 return (buf
->fence
&& !nouveau_fence_signalled(buf
->fence
));
261 nouveau_buffer_transfer_init(struct nouveau_transfer
*tx
,
262 struct pipe_resource
*resource
,
263 const struct pipe_box
*box
,
266 tx
->base
.resource
= resource
;
268 tx
->base
.usage
= usage
;
269 tx
->base
.box
.x
= box
->x
;
272 tx
->base
.box
.width
= box
->width
;
273 tx
->base
.box
.height
= 1;
274 tx
->base
.box
.depth
= 1;
276 tx
->base
.layer_stride
= 0;
283 nouveau_buffer_transfer_del(struct nouveau_context
*nv
,
284 struct nouveau_transfer
*tx
)
287 if (likely(tx
->bo
)) {
288 nouveau_fence_work(nv
->screen
->fence
.current
,
289 nouveau_fence_unref_bo
, tx
->bo
);
291 release_allocation(&tx
->mm
, nv
->screen
->fence
.current
);
294 (tx
->base
.box
.x
& NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK
));
299 /* Creates a cache in system memory of the buffer data. */
301 nouveau_buffer_cache(struct nouveau_context
*nv
, struct nv04_resource
*buf
)
303 struct nouveau_transfer tx
;
305 tx
.base
.resource
= &buf
->base
;
307 tx
.base
.box
.width
= buf
->base
.width0
;
312 if (!nouveau_buffer_malloc(buf
))
314 if (!(buf
->status
& NOUVEAU_BUFFER_STATUS_DIRTY
))
316 nv
->stats
.buf_cache_count
++;
318 if (!nouveau_transfer_staging(nv
, &tx
, false))
321 ret
= nouveau_transfer_read(nv
, &tx
);
323 buf
->status
&= ~NOUVEAU_BUFFER_STATUS_DIRTY
;
324 memcpy(buf
->data
, tx
.map
, buf
->base
.width0
);
326 nouveau_buffer_transfer_del(nv
, &tx
);
331 #define NOUVEAU_TRANSFER_DISCARD \
332 (PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)
334 /* Checks whether it is possible to completely discard the memory backing this
335 * resource. This can be useful if we would otherwise have to wait for a read
336 * operation to complete on this data.
339 nouveau_buffer_should_discard(struct nv04_resource
*buf
, unsigned usage
)
341 if (!(usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
))
343 if (unlikely(buf
->base
.bind
& PIPE_BIND_SHARED
))
345 if (unlikely(usage
& PIPE_TRANSFER_PERSISTENT
))
347 return buf
->mm
&& nouveau_buffer_busy(buf
, PIPE_TRANSFER_WRITE
);
350 /* Returns a pointer to a memory area representing a window into the
353 * This may or may not be the _actual_ memory area of the resource. However
354 * when calling nouveau_buffer_transfer_unmap, if it wasn't the actual memory
355 * area, the contents of the returned map are copied over to the resource.
357 * The usage indicates what the caller plans to do with the map:
359 * WRITE means that the user plans to write to it
361 * READ means that the user plans on reading from it
363 * DISCARD_WHOLE_RESOURCE means that the whole resource is going to be
364 * potentially overwritten, and even if it isn't, the bits that aren't don't
365 * need to be maintained.
367 * DISCARD_RANGE means that all the data in the specified range is going to
370 * The strategy for determining what kind of memory area to return is complex,
371 * see comments inside of the function.
374 nouveau_buffer_transfer_map(struct pipe_context
*pipe
,
375 struct pipe_resource
*resource
,
376 unsigned level
, unsigned usage
,
377 const struct pipe_box
*box
,
378 struct pipe_transfer
**ptransfer
)
380 struct nouveau_context
*nv
= nouveau_context(pipe
);
381 struct nv04_resource
*buf
= nv04_resource(resource
);
382 struct nouveau_transfer
*tx
= MALLOC_STRUCT(nouveau_transfer
);
388 nouveau_buffer_transfer_init(tx
, resource
, box
, usage
);
389 *ptransfer
= &tx
->base
;
391 if (usage
& PIPE_TRANSFER_READ
)
392 NOUVEAU_DRV_STAT(nv
->screen
, buf_transfers_rd
, 1);
393 if (usage
& PIPE_TRANSFER_WRITE
)
394 NOUVEAU_DRV_STAT(nv
->screen
, buf_transfers_wr
, 1);
396 /* If we are trying to write to an uninitialized range, the user shouldn't
397 * care what was there before. So we can treat the write as if the target
398 * range were being discarded. Furthermore, since we know that even if this
399 * buffer is busy due to GPU activity, because the contents were
400 * uninitialized, the GPU can't care what was there, and so we can treat
401 * the write as being unsynchronized.
403 if ((usage
& PIPE_TRANSFER_WRITE
) &&
404 !util_ranges_intersect(&buf
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
))
405 usage
|= PIPE_TRANSFER_DISCARD_RANGE
| PIPE_TRANSFER_UNSYNCHRONIZED
;
407 if (buf
->domain
== NOUVEAU_BO_VRAM
) {
408 if (usage
& NOUVEAU_TRANSFER_DISCARD
) {
409 /* Set up a staging area for the user to write to. It will be copied
410 * back into VRAM on unmap. */
411 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)
412 buf
->status
&= NOUVEAU_BUFFER_STATUS_REALLOC_MASK
;
413 nouveau_transfer_staging(nv
, tx
, true);
415 if (buf
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
416 /* The GPU is currently writing to this buffer. Copy its current
417 * contents to a staging area in the GART. This is necessary since
418 * not the whole area being mapped is being discarded.
421 align_free(buf
->data
);
424 nouveau_transfer_staging(nv
, tx
, false);
425 nouveau_transfer_read(nv
, tx
);
427 /* The buffer is currently idle. Create a staging area for writes,
428 * and make sure that the cached data is up-to-date. */
429 if (usage
& PIPE_TRANSFER_WRITE
)
430 nouveau_transfer_staging(nv
, tx
, true);
432 nouveau_buffer_cache(nv
, buf
);
435 return buf
->data
? (buf
->data
+ box
->x
) : tx
->map
;
437 if (unlikely(buf
->domain
== 0)) {
438 return buf
->data
+ box
->x
;
441 /* At this point, buf->domain == GART */
443 if (nouveau_buffer_should_discard(buf
, usage
)) {
444 int ref
= buf
->base
.reference
.count
- 1;
445 nouveau_buffer_reallocate(nv
->screen
, buf
, buf
->domain
);
446 if (ref
> 0) /* any references inside context possible ? */
447 nv
->invalidate_resource_storage(nv
, &buf
->base
, ref
);
450 /* Note that nouveau_bo_map ends up doing a nouveau_bo_wait with the
451 * relevant flags. If buf->mm is set, that means this resource is part of a
452 * larger slab bo that holds multiple resources. So in that case, don't
453 * wait on the whole slab and instead use the logic below to return a
454 * reasonable buffer for that case.
456 ret
= nouveau_bo_map(buf
->bo
,
457 buf
->mm
? 0 : nouveau_screen_transfer_flags(usage
),
463 map
= (uint8_t *)buf
->bo
->map
+ buf
->offset
+ box
->x
;
465 /* using kernel fences only if !buf->mm */
466 if ((usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) || !buf
->mm
)
469 /* If the GPU is currently reading/writing this buffer, we shouldn't
470 * interfere with its progress. So instead we either wait for the GPU to
471 * complete its operation, or set up a staging area to perform our work in.
473 if (nouveau_buffer_busy(buf
, usage
& PIPE_TRANSFER_READ_WRITE
)) {
474 if (unlikely(usage
& (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
475 PIPE_TRANSFER_PERSISTENT
))) {
476 /* Discarding was not possible, must sync because
477 * subsequent transfers might use UNSYNCHRONIZED. */
478 nouveau_buffer_sync(nv
, buf
, usage
& PIPE_TRANSFER_READ_WRITE
);
480 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
) {
481 /* The whole range is being discarded, so it doesn't matter what was
482 * there before. No need to copy anything over. */
483 nouveau_transfer_staging(nv
, tx
, true);
486 if (nouveau_buffer_busy(buf
, PIPE_TRANSFER_READ
)) {
487 if (usage
& PIPE_TRANSFER_DONTBLOCK
)
490 nouveau_buffer_sync(nv
, buf
, usage
& PIPE_TRANSFER_READ_WRITE
);
492 /* It is expected that the returned buffer be a representation of the
493 * data in question, so we must copy it over from the buffer. */
494 nouveau_transfer_staging(nv
, tx
, true);
496 memcpy(tx
->map
, map
, box
->width
);
508 nouveau_buffer_transfer_flush_region(struct pipe_context
*pipe
,
509 struct pipe_transfer
*transfer
,
510 const struct pipe_box
*box
)
512 struct nouveau_transfer
*tx
= nouveau_transfer(transfer
);
513 struct nv04_resource
*buf
= nv04_resource(transfer
->resource
);
516 nouveau_transfer_write(nouveau_context(pipe
), tx
, box
->x
, box
->width
);
518 util_range_add(&buf
->base
, &buf
->valid_buffer_range
,
519 tx
->base
.box
.x
+ box
->x
,
520 tx
->base
.box
.x
+ box
->x
+ box
->width
);
523 /* Unmap stage of the transfer. If it was a WRITE transfer and the map that
524 * was returned was not the real resource's data, this needs to transfer the
525 * data back to the resource.
527 * Also marks vbo dirty based on the buffer's binding
530 nouveau_buffer_transfer_unmap(struct pipe_context
*pipe
,
531 struct pipe_transfer
*transfer
)
533 struct nouveau_context
*nv
= nouveau_context(pipe
);
534 struct nouveau_transfer
*tx
= nouveau_transfer(transfer
);
535 struct nv04_resource
*buf
= nv04_resource(transfer
->resource
);
537 if (tx
->base
.usage
& PIPE_TRANSFER_WRITE
) {
538 if (!(tx
->base
.usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
540 nouveau_transfer_write(nv
, tx
, 0, tx
->base
.box
.width
);
542 util_range_add(&buf
->base
, &buf
->valid_buffer_range
,
543 tx
->base
.box
.x
, tx
->base
.box
.x
+ tx
->base
.box
.width
);
546 if (likely(buf
->domain
)) {
547 const uint8_t bind
= buf
->base
.bind
;
548 /* make sure we invalidate dedicated caches */
549 if (bind
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
550 nv
->vbo_dirty
= true;
554 if (!tx
->bo
&& (tx
->base
.usage
& PIPE_TRANSFER_WRITE
))
555 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_direct
, tx
->base
.box
.width
);
557 nouveau_buffer_transfer_del(nv
, tx
);
563 nouveau_copy_buffer(struct nouveau_context
*nv
,
564 struct nv04_resource
*dst
, unsigned dstx
,
565 struct nv04_resource
*src
, unsigned srcx
, unsigned size
)
567 assert(dst
->base
.target
== PIPE_BUFFER
&& src
->base
.target
== PIPE_BUFFER
);
569 if (likely(dst
->domain
) && likely(src
->domain
)) {
571 dst
->bo
, dst
->offset
+ dstx
, dst
->domain
,
572 src
->bo
, src
->offset
+ srcx
, src
->domain
, size
);
574 dst
->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
575 nouveau_fence_ref(nv
->screen
->fence
.current
, &dst
->fence
);
576 nouveau_fence_ref(nv
->screen
->fence
.current
, &dst
->fence_wr
);
578 src
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
579 nouveau_fence_ref(nv
->screen
->fence
.current
, &src
->fence
);
581 struct pipe_box src_box
;
585 src_box
.width
= size
;
588 util_resource_copy_region(&nv
->pipe
,
589 &dst
->base
, 0, dstx
, 0, 0,
590 &src
->base
, 0, &src_box
);
593 util_range_add(&dst
->base
, &dst
->valid_buffer_range
, dstx
, dstx
+ size
);
598 nouveau_resource_map_offset(struct nouveau_context
*nv
,
599 struct nv04_resource
*res
, uint32_t offset
,
602 if (unlikely(res
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
))
603 return res
->data
+ offset
;
605 if (res
->domain
== NOUVEAU_BO_VRAM
) {
606 if (!res
->data
|| (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
))
607 nouveau_buffer_cache(nv
, res
);
609 if (res
->domain
!= NOUVEAU_BO_GART
)
610 return res
->data
+ offset
;
614 rw
= (flags
& NOUVEAU_BO_WR
) ? PIPE_TRANSFER_WRITE
: PIPE_TRANSFER_READ
;
615 nouveau_buffer_sync(nv
, res
, rw
);
616 if (nouveau_bo_map(res
->bo
, 0, NULL
))
619 if (nouveau_bo_map(res
->bo
, flags
, nv
->client
))
622 return (uint8_t *)res
->bo
->map
+ res
->offset
+ offset
;
626 const struct u_resource_vtbl nouveau_buffer_vtbl
=
628 u_default_resource_get_handle
, /* get_handle */
629 nouveau_buffer_destroy
, /* resource_destroy */
630 nouveau_buffer_transfer_map
, /* transfer_map */
631 nouveau_buffer_transfer_flush_region
, /* transfer_flush_region */
632 nouveau_buffer_transfer_unmap
, /* transfer_unmap */
635 struct pipe_resource
*
636 nouveau_buffer_create(struct pipe_screen
*pscreen
,
637 const struct pipe_resource
*templ
)
639 struct nouveau_screen
*screen
= nouveau_screen(pscreen
);
640 struct nv04_resource
*buffer
;
643 buffer
= CALLOC_STRUCT(nv04_resource
);
647 buffer
->base
= *templ
;
648 buffer
->vtbl
= &nouveau_buffer_vtbl
;
649 pipe_reference_init(&buffer
->base
.reference
, 1);
650 buffer
->base
.screen
= pscreen
;
652 if (buffer
->base
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
653 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
654 buffer
->domain
= NOUVEAU_BO_GART
;
655 } else if (buffer
->base
.bind
== 0 || (buffer
->base
.bind
&
656 (screen
->vidmem_bindings
& screen
->sysmem_bindings
))) {
657 switch (buffer
->base
.usage
) {
658 case PIPE_USAGE_DEFAULT
:
659 case PIPE_USAGE_IMMUTABLE
:
660 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
662 case PIPE_USAGE_DYNAMIC
:
663 /* For most apps, we'd have to do staging transfers to avoid sync
664 * with this usage, and GART -> GART copies would be suboptimal.
666 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
668 case PIPE_USAGE_STAGING
:
669 case PIPE_USAGE_STREAM
:
670 buffer
->domain
= NOUVEAU_BO_GART
;
677 if (buffer
->base
.bind
& screen
->vidmem_bindings
)
678 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
680 if (buffer
->base
.bind
& screen
->sysmem_bindings
)
681 buffer
->domain
= NOUVEAU_BO_GART
;
684 ret
= nouveau_buffer_allocate(screen
, buffer
, buffer
->domain
);
689 if (buffer
->domain
== NOUVEAU_BO_VRAM
&& screen
->hint_buf_keep_sysmem_copy
)
690 nouveau_buffer_cache(NULL
, buffer
);
692 NOUVEAU_DRV_STAT(screen
, buf_obj_current_count
, 1);
694 util_range_init(&buffer
->valid_buffer_range
);
696 return &buffer
->base
;
704 struct pipe_resource
*
705 nouveau_user_buffer_create(struct pipe_screen
*pscreen
, void *ptr
,
706 unsigned bytes
, unsigned bind
)
708 struct nv04_resource
*buffer
;
710 buffer
= CALLOC_STRUCT(nv04_resource
);
714 pipe_reference_init(&buffer
->base
.reference
, 1);
715 buffer
->vtbl
= &nouveau_buffer_vtbl
;
716 buffer
->base
.screen
= pscreen
;
717 buffer
->base
.format
= PIPE_FORMAT_R8_UNORM
;
718 buffer
->base
.usage
= PIPE_USAGE_IMMUTABLE
;
719 buffer
->base
.bind
= bind
;
720 buffer
->base
.width0
= bytes
;
721 buffer
->base
.height0
= 1;
722 buffer
->base
.depth0
= 1;
725 buffer
->status
= NOUVEAU_BUFFER_STATUS_USER_MEMORY
;
727 util_range_init(&buffer
->valid_buffer_range
);
728 util_range_add(&buffer
->base
, &buffer
->valid_buffer_range
, 0, bytes
);
730 return &buffer
->base
;
734 nouveau_buffer_data_fetch(struct nouveau_context
*nv
, struct nv04_resource
*buf
,
735 struct nouveau_bo
*bo
, unsigned offset
, unsigned size
)
737 if (!nouveau_buffer_malloc(buf
))
739 if (nouveau_bo_map(bo
, NOUVEAU_BO_RD
, nv
->client
))
741 memcpy(buf
->data
, (uint8_t *)bo
->map
+ offset
, size
);
745 /* Migrate a linear buffer (vertex, index, constants) USER -> GART -> VRAM. */
747 nouveau_buffer_migrate(struct nouveau_context
*nv
,
748 struct nv04_resource
*buf
, const unsigned new_domain
)
750 struct nouveau_screen
*screen
= nv
->screen
;
751 struct nouveau_bo
*bo
;
752 const unsigned old_domain
= buf
->domain
;
753 unsigned size
= buf
->base
.width0
;
757 assert(new_domain
!= old_domain
);
759 if (new_domain
== NOUVEAU_BO_GART
&& old_domain
== 0) {
760 if (!nouveau_buffer_allocate(screen
, buf
, new_domain
))
762 ret
= nouveau_bo_map(buf
->bo
, 0, nv
->client
);
765 memcpy((uint8_t *)buf
->bo
->map
+ buf
->offset
, buf
->data
, size
);
766 align_free(buf
->data
);
768 if (old_domain
!= 0 && new_domain
!= 0) {
769 struct nouveau_mm_allocation
*mm
= buf
->mm
;
771 if (new_domain
== NOUVEAU_BO_VRAM
) {
772 /* keep a system memory copy of our data in case we hit a fallback */
773 if (!nouveau_buffer_data_fetch(nv
, buf
, buf
->bo
, buf
->offset
, size
))
775 if (nouveau_mesa_debug
)
776 debug_printf("migrating %u KiB to VRAM\n", size
/ 1024);
779 offset
= buf
->offset
;
783 nouveau_buffer_allocate(screen
, buf
, new_domain
);
785 nv
->copy_data(nv
, buf
->bo
, buf
->offset
, new_domain
,
786 bo
, offset
, old_domain
, buf
->base
.width0
);
788 nouveau_fence_work(screen
->fence
.current
, nouveau_fence_unref_bo
, bo
);
790 release_allocation(&mm
, screen
->fence
.current
);
792 if (new_domain
== NOUVEAU_BO_VRAM
&& old_domain
== 0) {
793 struct nouveau_transfer tx
;
794 if (!nouveau_buffer_allocate(screen
, buf
, NOUVEAU_BO_VRAM
))
796 tx
.base
.resource
= &buf
->base
;
798 tx
.base
.box
.width
= buf
->base
.width0
;
801 if (!nouveau_transfer_staging(nv
, &tx
, false))
803 nouveau_transfer_write(nv
, &tx
, 0, tx
.base
.box
.width
);
804 nouveau_buffer_transfer_del(nv
, &tx
);
808 assert(buf
->domain
== new_domain
);
812 /* Migrate data from glVertexAttribPointer(non-VBO) user buffers to GART.
813 * We'd like to only allocate @size bytes here, but then we'd have to rebase
814 * the vertex indices ...
817 nouveau_user_buffer_upload(struct nouveau_context
*nv
,
818 struct nv04_resource
*buf
,
819 unsigned base
, unsigned size
)
821 struct nouveau_screen
*screen
= nouveau_screen(buf
->base
.screen
);
824 assert(buf
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
);
826 buf
->base
.width0
= base
+ size
;
827 if (!nouveau_buffer_reallocate(screen
, buf
, NOUVEAU_BO_GART
))
830 ret
= nouveau_bo_map(buf
->bo
, 0, nv
->client
);
833 memcpy((uint8_t *)buf
->bo
->map
+ buf
->offset
+ base
, buf
->data
+ base
, size
);
838 /* Invalidate underlying buffer storage, reset fences, reallocate to non-busy
842 nouveau_buffer_invalidate(struct pipe_context
*pipe
,
843 struct pipe_resource
*resource
)
845 struct nouveau_context
*nv
= nouveau_context(pipe
);
846 struct nv04_resource
*buf
= nv04_resource(resource
);
847 int ref
= buf
->base
.reference
.count
- 1;
849 /* Shared buffers shouldn't get reallocated */
850 if (unlikely(buf
->base
.bind
& PIPE_BIND_SHARED
))
853 /* We can't touch persistent/coherent buffers */
854 if (buf
->base
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
855 PIPE_RESOURCE_FLAG_MAP_COHERENT
))
858 /* If the buffer is sub-allocated and not currently being written, just
859 * wipe the valid buffer range. Otherwise we have to create fresh
860 * storage. (We don't keep track of fences for non-sub-allocated BO's.)
862 if (buf
->mm
&& !nouveau_buffer_busy(buf
, PIPE_TRANSFER_WRITE
)) {
863 util_range_set_empty(&buf
->valid_buffer_range
);
865 nouveau_buffer_reallocate(nv
->screen
, buf
, buf
->domain
);
866 if (ref
> 0) /* any references inside context possible ? */
867 nv
->invalidate_resource_storage(nv
, &buf
->base
, ref
);
872 /* Scratch data allocation. */
875 nouveau_scratch_bo_alloc(struct nouveau_context
*nv
, struct nouveau_bo
**pbo
,
878 return nouveau_bo_new(nv
->screen
->device
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
,
879 4096, size
, NULL
, pbo
);
883 nouveau_scratch_unref_bos(void *d
)
885 struct runout
*b
= d
;
888 for (i
= 0; i
< b
->nr
; ++i
)
889 nouveau_bo_ref(NULL
, &b
->bo
[i
]);
895 nouveau_scratch_runout_release(struct nouveau_context
*nv
)
897 if (!nv
->scratch
.runout
)
900 if (!nouveau_fence_work(nv
->screen
->fence
.current
, nouveau_scratch_unref_bos
,
905 nv
->scratch
.runout
= NULL
;
908 /* Allocate an extra bo if we can't fit everything we need simultaneously.
909 * (Could happen for very large user arrays.)
912 nouveau_scratch_runout(struct nouveau_context
*nv
, unsigned size
)
917 if (nv
->scratch
.runout
)
918 n
= nv
->scratch
.runout
->nr
;
921 nv
->scratch
.runout
= REALLOC(nv
->scratch
.runout
, n
== 0 ? 0 :
922 (sizeof(*nv
->scratch
.runout
) + (n
+ 0) * sizeof(void *)),
923 sizeof(*nv
->scratch
.runout
) + (n
+ 1) * sizeof(void *));
924 nv
->scratch
.runout
->nr
= n
+ 1;
925 nv
->scratch
.runout
->bo
[n
] = NULL
;
927 ret
= nouveau_scratch_bo_alloc(nv
, &nv
->scratch
.runout
->bo
[n
], size
);
929 ret
= nouveau_bo_map(nv
->scratch
.runout
->bo
[n
], 0, NULL
);
931 nouveau_bo_ref(NULL
, &nv
->scratch
.runout
->bo
[--nv
->scratch
.runout
->nr
]);
934 nv
->scratch
.current
= nv
->scratch
.runout
->bo
[n
];
935 nv
->scratch
.offset
= 0;
936 nv
->scratch
.end
= size
;
937 nv
->scratch
.map
= nv
->scratch
.current
->map
;
942 /* Continue to next scratch buffer, if available (no wrapping, large enough).
943 * Allocate it if it has not yet been created.
946 nouveau_scratch_next(struct nouveau_context
*nv
, unsigned size
)
948 struct nouveau_bo
*bo
;
950 const unsigned i
= (nv
->scratch
.id
+ 1) % NOUVEAU_MAX_SCRATCH_BUFS
;
952 if ((size
> nv
->scratch
.bo_size
) || (i
== nv
->scratch
.wrap
))
956 bo
= nv
->scratch
.bo
[i
];
958 ret
= nouveau_scratch_bo_alloc(nv
, &bo
, nv
->scratch
.bo_size
);
961 nv
->scratch
.bo
[i
] = bo
;
963 nv
->scratch
.current
= bo
;
964 nv
->scratch
.offset
= 0;
965 nv
->scratch
.end
= nv
->scratch
.bo_size
;
967 ret
= nouveau_bo_map(bo
, NOUVEAU_BO_WR
, nv
->client
);
969 nv
->scratch
.map
= bo
->map
;
974 nouveau_scratch_more(struct nouveau_context
*nv
, unsigned min_size
)
978 ret
= nouveau_scratch_next(nv
, min_size
);
980 ret
= nouveau_scratch_runout(nv
, min_size
);
985 /* Copy data to a scratch buffer and return address & bo the data resides in. */
987 nouveau_scratch_data(struct nouveau_context
*nv
,
988 const void *data
, unsigned base
, unsigned size
,
989 struct nouveau_bo
**bo
)
991 unsigned bgn
= MAX2(base
, nv
->scratch
.offset
);
992 unsigned end
= bgn
+ size
;
994 if (end
>= nv
->scratch
.end
) {
996 if (!nouveau_scratch_more(nv
, end
))
1000 nv
->scratch
.offset
= align(end
, 4);
1002 memcpy(nv
->scratch
.map
+ bgn
, (const uint8_t *)data
+ base
, size
);
1004 *bo
= nv
->scratch
.current
;
1005 return (*bo
)->offset
+ (bgn
- base
);
1009 nouveau_scratch_get(struct nouveau_context
*nv
,
1010 unsigned size
, uint64_t *gpu_addr
, struct nouveau_bo
**pbo
)
1012 unsigned bgn
= nv
->scratch
.offset
;
1013 unsigned end
= nv
->scratch
.offset
+ size
;
1015 if (end
>= nv
->scratch
.end
) {
1017 if (!nouveau_scratch_more(nv
, end
))
1021 nv
->scratch
.offset
= align(end
, 4);
1023 *pbo
= nv
->scratch
.current
;
1024 *gpu_addr
= nv
->scratch
.current
->offset
+ bgn
;
1025 return nv
->scratch
.map
+ bgn
;