2 #include "util/u_inlines.h"
3 #include "util/u_memory.h"
4 #include "util/u_math.h"
5 #include "util/u_surface.h"
7 #include "nouveau_screen.h"
8 #include "nouveau_context.h"
9 #include "nouveau_winsys.h"
10 #include "nouveau_fence.h"
11 #include "nouveau_buffer.h"
12 #include "nouveau_mm.h"
14 #define NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD 192
16 struct nouveau_transfer
{
17 struct pipe_transfer base
;
20 struct nouveau_bo
*bo
;
21 struct nouveau_mm_allocation
*mm
;
25 static inline struct nouveau_transfer
*
26 nouveau_transfer(struct pipe_transfer
*transfer
)
28 return (struct nouveau_transfer
*)transfer
;
32 nouveau_buffer_malloc(struct nv04_resource
*buf
)
35 buf
->data
= align_malloc(buf
->base
.width0
, NOUVEAU_MIN_BUFFER_MAP_ALIGN
);
40 nouveau_buffer_allocate(struct nouveau_screen
*screen
,
41 struct nv04_resource
*buf
, unsigned domain
)
43 uint32_t size
= align(buf
->base
.width0
, 0x100);
45 if (domain
== NOUVEAU_BO_VRAM
) {
46 buf
->mm
= nouveau_mm_allocate(screen
->mm_VRAM
, size
,
47 &buf
->bo
, &buf
->offset
);
49 return nouveau_buffer_allocate(screen
, buf
, NOUVEAU_BO_GART
);
50 NOUVEAU_DRV_STAT(screen
, buf_obj_current_bytes_vid
, buf
->base
.width0
);
52 if (domain
== NOUVEAU_BO_GART
) {
53 buf
->mm
= nouveau_mm_allocate(screen
->mm_GART
, size
,
54 &buf
->bo
, &buf
->offset
);
57 NOUVEAU_DRV_STAT(screen
, buf_obj_current_bytes_sys
, buf
->base
.width0
);
60 if (!nouveau_buffer_malloc(buf
))
65 buf
->address
= buf
->bo
->offset
+ buf
->offset
;
67 util_range_set_empty(&buf
->valid_buffer_range
);
73 release_allocation(struct nouveau_mm_allocation
**mm
,
74 struct nouveau_fence
*fence
)
76 nouveau_fence_work(fence
, nouveau_mm_free_work
, *mm
);
81 nouveau_buffer_release_gpu_storage(struct nv04_resource
*buf
)
83 nouveau_bo_ref(NULL
, &buf
->bo
);
86 release_allocation(&buf
->mm
, buf
->fence
);
88 if (buf
->domain
== NOUVEAU_BO_VRAM
)
89 NOUVEAU_DRV_STAT_RES(buf
, buf_obj_current_bytes_vid
, -(uint64_t)buf
->base
.width0
);
90 if (buf
->domain
== NOUVEAU_BO_GART
)
91 NOUVEAU_DRV_STAT_RES(buf
, buf_obj_current_bytes_sys
, -(uint64_t)buf
->base
.width0
);
97 nouveau_buffer_reallocate(struct nouveau_screen
*screen
,
98 struct nv04_resource
*buf
, unsigned domain
)
100 nouveau_buffer_release_gpu_storage(buf
);
102 nouveau_fence_ref(NULL
, &buf
->fence
);
103 nouveau_fence_ref(NULL
, &buf
->fence_wr
);
105 buf
->status
&= NOUVEAU_BUFFER_STATUS_REALLOC_MASK
;
107 return nouveau_buffer_allocate(screen
, buf
, domain
);
111 nouveau_buffer_destroy(struct pipe_screen
*pscreen
,
112 struct pipe_resource
*presource
)
114 struct nv04_resource
*res
= nv04_resource(presource
);
116 nouveau_buffer_release_gpu_storage(res
);
118 if (res
->data
&& !(res
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
))
119 align_free(res
->data
);
121 nouveau_fence_ref(NULL
, &res
->fence
);
122 nouveau_fence_ref(NULL
, &res
->fence_wr
);
124 util_range_destroy(&res
->valid_buffer_range
);
128 NOUVEAU_DRV_STAT(nouveau_screen(pscreen
), buf_obj_current_count
, -1);
131 /* Set up a staging area for the transfer. This is either done in "regular"
132 * system memory if the driver supports push_data (nv50+) and the data is
133 * small enough (and permit_pb == true), or in GART memory.
136 nouveau_transfer_staging(struct nouveau_context
*nv
,
137 struct nouveau_transfer
*tx
, bool permit_pb
)
139 const unsigned adj
= tx
->base
.box
.x
& NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK
;
140 const unsigned size
= align(tx
->base
.box
.width
, 4) + adj
;
145 if ((size
<= NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD
) && permit_pb
) {
146 tx
->map
= align_malloc(size
, NOUVEAU_MIN_BUFFER_MAP_ALIGN
);
151 nouveau_mm_allocate(nv
->screen
->mm_GART
, size
, &tx
->bo
, &tx
->offset
);
154 if (!nouveau_bo_map(tx
->bo
, 0, NULL
))
155 tx
->map
= (uint8_t *)tx
->bo
->map
+ tx
->offset
;
161 /* Copies data from the resource into the the transfer's temporary GART
162 * buffer. Also updates buf->data if present.
164 * Maybe just migrate to GART right away if we actually need to do this. */
166 nouveau_transfer_read(struct nouveau_context
*nv
, struct nouveau_transfer
*tx
)
168 struct nv04_resource
*buf
= nv04_resource(tx
->base
.resource
);
169 const unsigned base
= tx
->base
.box
.x
;
170 const unsigned size
= tx
->base
.box
.width
;
172 NOUVEAU_DRV_STAT(nv
->screen
, buf_read_bytes_staging_vid
, size
);
174 nv
->copy_data(nv
, tx
->bo
, tx
->offset
, NOUVEAU_BO_GART
,
175 buf
->bo
, buf
->offset
+ base
, buf
->domain
, size
);
177 if (nouveau_bo_wait(tx
->bo
, NOUVEAU_BO_RD
, nv
->client
))
181 memcpy(buf
->data
+ base
, tx
->map
, size
);
187 nouveau_transfer_write(struct nouveau_context
*nv
, struct nouveau_transfer
*tx
,
188 unsigned offset
, unsigned size
)
190 struct nv04_resource
*buf
= nv04_resource(tx
->base
.resource
);
191 uint8_t *data
= tx
->map
+ offset
;
192 const unsigned base
= tx
->base
.box
.x
+ offset
;
193 const bool can_cb
= !((base
| size
) & 3);
196 memcpy(data
, buf
->data
+ base
, size
);
198 buf
->status
|= NOUVEAU_BUFFER_STATUS_DIRTY
;
200 if (buf
->domain
== NOUVEAU_BO_VRAM
)
201 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_staging_vid
, size
);
202 if (buf
->domain
== NOUVEAU_BO_GART
)
203 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_staging_sys
, size
);
206 nv
->copy_data(nv
, buf
->bo
, buf
->offset
+ base
, buf
->domain
,
207 tx
->bo
, tx
->offset
+ offset
, NOUVEAU_BO_GART
, size
);
209 if (nv
->push_cb
&& can_cb
)
211 base
, size
/ 4, (const uint32_t *)data
);
213 nv
->push_data(nv
, buf
->bo
, buf
->offset
+ base
, buf
->domain
, size
, data
);
215 nouveau_fence_ref(nv
->screen
->fence
.current
, &buf
->fence
);
216 nouveau_fence_ref(nv
->screen
->fence
.current
, &buf
->fence_wr
);
219 /* Does a CPU wait for the buffer's backing data to become reliably accessible
220 * for write/read by waiting on the buffer's relevant fences.
223 nouveau_buffer_sync(struct nv04_resource
*buf
, unsigned rw
)
225 if (rw
== PIPE_TRANSFER_READ
) {
228 NOUVEAU_DRV_STAT_RES(buf
, buf_non_kernel_fence_sync_count
,
229 !nouveau_fence_signalled(buf
->fence_wr
));
230 if (!nouveau_fence_wait(buf
->fence_wr
))
235 NOUVEAU_DRV_STAT_RES(buf
, buf_non_kernel_fence_sync_count
,
236 !nouveau_fence_signalled(buf
->fence
));
237 if (!nouveau_fence_wait(buf
->fence
))
240 nouveau_fence_ref(NULL
, &buf
->fence
);
242 nouveau_fence_ref(NULL
, &buf
->fence_wr
);
248 nouveau_buffer_busy(struct nv04_resource
*buf
, unsigned rw
)
250 if (rw
== PIPE_TRANSFER_READ
)
251 return (buf
->fence_wr
&& !nouveau_fence_signalled(buf
->fence_wr
));
253 return (buf
->fence
&& !nouveau_fence_signalled(buf
->fence
));
257 nouveau_buffer_transfer_init(struct nouveau_transfer
*tx
,
258 struct pipe_resource
*resource
,
259 const struct pipe_box
*box
,
262 tx
->base
.resource
= resource
;
264 tx
->base
.usage
= usage
;
265 tx
->base
.box
.x
= box
->x
;
268 tx
->base
.box
.width
= box
->width
;
269 tx
->base
.box
.height
= 1;
270 tx
->base
.box
.depth
= 1;
272 tx
->base
.layer_stride
= 0;
279 nouveau_buffer_transfer_del(struct nouveau_context
*nv
,
280 struct nouveau_transfer
*tx
)
283 if (likely(tx
->bo
)) {
284 nouveau_bo_ref(NULL
, &tx
->bo
);
286 release_allocation(&tx
->mm
, nv
->screen
->fence
.current
);
289 (tx
->base
.box
.x
& NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK
));
294 /* Creates a cache in system memory of the buffer data. */
296 nouveau_buffer_cache(struct nouveau_context
*nv
, struct nv04_resource
*buf
)
298 struct nouveau_transfer tx
;
300 tx
.base
.resource
= &buf
->base
;
302 tx
.base
.box
.width
= buf
->base
.width0
;
307 if (!nouveau_buffer_malloc(buf
))
309 if (!(buf
->status
& NOUVEAU_BUFFER_STATUS_DIRTY
))
311 nv
->stats
.buf_cache_count
++;
313 if (!nouveau_transfer_staging(nv
, &tx
, false))
316 ret
= nouveau_transfer_read(nv
, &tx
);
318 buf
->status
&= ~NOUVEAU_BUFFER_STATUS_DIRTY
;
319 memcpy(buf
->data
, tx
.map
, buf
->base
.width0
);
321 nouveau_buffer_transfer_del(nv
, &tx
);
326 #define NOUVEAU_TRANSFER_DISCARD \
327 (PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)
329 /* Checks whether it is possible to completely discard the memory backing this
330 * resource. This can be useful if we would otherwise have to wait for a read
331 * operation to complete on this data.
334 nouveau_buffer_should_discard(struct nv04_resource
*buf
, unsigned usage
)
336 if (!(usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
))
338 if (unlikely(buf
->base
.bind
& PIPE_BIND_SHARED
))
340 if (unlikely(usage
& PIPE_TRANSFER_PERSISTENT
))
342 return buf
->mm
&& nouveau_buffer_busy(buf
, PIPE_TRANSFER_WRITE
);
345 /* Returns a pointer to a memory area representing a window into the
348 * This may or may not be the _actual_ memory area of the resource. However
349 * when calling nouveau_buffer_transfer_unmap, if it wasn't the actual memory
350 * area, the contents of the returned map are copied over to the resource.
352 * The usage indicates what the caller plans to do with the map:
354 * WRITE means that the user plans to write to it
356 * READ means that the user plans on reading from it
358 * DISCARD_WHOLE_RESOURCE means that the whole resource is going to be
359 * potentially overwritten, and even if it isn't, the bits that aren't don't
360 * need to be maintained.
362 * DISCARD_RANGE means that all the data in the specified range is going to
365 * The strategy for determining what kind of memory area to return is complex,
366 * see comments inside of the function.
369 nouveau_buffer_transfer_map(struct pipe_context
*pipe
,
370 struct pipe_resource
*resource
,
371 unsigned level
, unsigned usage
,
372 const struct pipe_box
*box
,
373 struct pipe_transfer
**ptransfer
)
375 struct nouveau_context
*nv
= nouveau_context(pipe
);
376 struct nv04_resource
*buf
= nv04_resource(resource
);
377 struct nouveau_transfer
*tx
= MALLOC_STRUCT(nouveau_transfer
);
383 nouveau_buffer_transfer_init(tx
, resource
, box
, usage
);
384 *ptransfer
= &tx
->base
;
386 if (usage
& PIPE_TRANSFER_READ
)
387 NOUVEAU_DRV_STAT(nv
->screen
, buf_transfers_rd
, 1);
388 if (usage
& PIPE_TRANSFER_WRITE
)
389 NOUVEAU_DRV_STAT(nv
->screen
, buf_transfers_wr
, 1);
391 /* If we are trying to write to an uninitialized range, the user shouldn't
392 * care what was there before. So we can treat the write as if the target
393 * range were being discarded. Furthermore, since we know that even if this
394 * buffer is busy due to GPU activity, because the contents were
395 * uninitialized, the GPU can't care what was there, and so we can treat
396 * the write as being unsynchronized.
398 if ((usage
& PIPE_TRANSFER_WRITE
) &&
399 !util_ranges_intersect(&buf
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
))
400 usage
|= PIPE_TRANSFER_DISCARD_RANGE
| PIPE_TRANSFER_UNSYNCHRONIZED
;
402 if (usage
& PIPE_TRANSFER_PERSISTENT
)
403 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
405 if (buf
->domain
== NOUVEAU_BO_VRAM
) {
406 if (usage
& NOUVEAU_TRANSFER_DISCARD
) {
407 /* Set up a staging area for the user to write to. It will be copied
408 * back into VRAM on unmap. */
409 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)
410 buf
->status
&= NOUVEAU_BUFFER_STATUS_REALLOC_MASK
;
411 nouveau_transfer_staging(nv
, tx
, true);
413 if (buf
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
414 /* The GPU is currently writing to this buffer. Copy its current
415 * contents to a staging area in the GART. This is necessary since
416 * not the whole area being mapped is being discarded.
419 align_free(buf
->data
);
422 nouveau_transfer_staging(nv
, tx
, false);
423 nouveau_transfer_read(nv
, tx
);
425 /* The buffer is currently idle. Create a staging area for writes,
426 * and make sure that the cached data is up-to-date. */
427 if (usage
& PIPE_TRANSFER_WRITE
)
428 nouveau_transfer_staging(nv
, tx
, true);
430 nouveau_buffer_cache(nv
, buf
);
433 return buf
->data
? (buf
->data
+ box
->x
) : tx
->map
;
435 if (unlikely(buf
->domain
== 0)) {
436 return buf
->data
+ box
->x
;
439 /* At this point, buf->domain == GART */
441 if (nouveau_buffer_should_discard(buf
, usage
)) {
442 int ref
= buf
->base
.reference
.count
- 1;
443 nouveau_buffer_reallocate(nv
->screen
, buf
, buf
->domain
);
444 if (ref
> 0) /* any references inside context possible ? */
445 nv
->invalidate_resource_storage(nv
, &buf
->base
, ref
);
448 /* Note that nouveau_bo_map ends up doing a nouveau_bo_wait with the
449 * relevant flags. If buf->mm is set, that means this resource is part of a
450 * larger slab bo that holds multiple resources. So in that case, don't
451 * wait on the whole slab and instead use the logic below to return a
452 * reasonable buffer for that case.
454 ret
= nouveau_bo_map(buf
->bo
,
455 buf
->mm
? 0 : nouveau_screen_transfer_flags(usage
),
461 map
= (uint8_t *)buf
->bo
->map
+ buf
->offset
+ box
->x
;
463 /* using kernel fences only if !buf->mm */
464 if ((usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) || !buf
->mm
)
467 /* If the GPU is currently reading/writing this buffer, we shouldn't
468 * interfere with its progress. So instead we either wait for the GPU to
469 * complete its operation, or set up a staging area to perform our work in.
471 if (nouveau_buffer_busy(buf
, usage
& PIPE_TRANSFER_READ_WRITE
)) {
472 if (unlikely(usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)) {
473 /* Discarding was not possible, must sync because
474 * subsequent transfers might use UNSYNCHRONIZED. */
475 nouveau_buffer_sync(buf
, usage
& PIPE_TRANSFER_READ_WRITE
);
477 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
) {
478 /* The whole range is being discarded, so it doesn't matter what was
479 * there before. No need to copy anything over. */
480 nouveau_transfer_staging(nv
, tx
, true);
483 if (nouveau_buffer_busy(buf
, PIPE_TRANSFER_READ
)) {
484 if (usage
& PIPE_TRANSFER_DONTBLOCK
)
487 nouveau_buffer_sync(buf
, usage
& PIPE_TRANSFER_READ_WRITE
);
489 /* It is expected that the returned buffer be a representation of the
490 * data in question, so we must copy it over from the buffer. */
491 nouveau_transfer_staging(nv
, tx
, true);
493 memcpy(tx
->map
, map
, box
->width
);
505 nouveau_buffer_transfer_flush_region(struct pipe_context
*pipe
,
506 struct pipe_transfer
*transfer
,
507 const struct pipe_box
*box
)
509 struct nouveau_transfer
*tx
= nouveau_transfer(transfer
);
510 struct nv04_resource
*buf
= nv04_resource(transfer
->resource
);
513 nouveau_transfer_write(nouveau_context(pipe
), tx
, box
->x
, box
->width
);
515 util_range_add(&buf
->valid_buffer_range
,
516 tx
->base
.box
.x
+ box
->x
,
517 tx
->base
.box
.x
+ box
->x
+ box
->width
);
520 /* Unmap stage of the transfer. If it was a WRITE transfer and the map that
521 * was returned was not the real resource's data, this needs to transfer the
522 * data back to the resource.
524 * Also marks vbo dirty based on the buffer's binding
527 nouveau_buffer_transfer_unmap(struct pipe_context
*pipe
,
528 struct pipe_transfer
*transfer
)
530 struct nouveau_context
*nv
= nouveau_context(pipe
);
531 struct nouveau_transfer
*tx
= nouveau_transfer(transfer
);
532 struct nv04_resource
*buf
= nv04_resource(transfer
->resource
);
534 if (tx
->base
.usage
& PIPE_TRANSFER_WRITE
) {
535 if (!(tx
->base
.usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
537 nouveau_transfer_write(nv
, tx
, 0, tx
->base
.box
.width
);
539 util_range_add(&buf
->valid_buffer_range
,
540 tx
->base
.box
.x
, tx
->base
.box
.x
+ tx
->base
.box
.width
);
543 if (likely(buf
->domain
)) {
544 const uint8_t bind
= buf
->base
.bind
;
545 /* make sure we invalidate dedicated caches */
546 if (bind
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
547 nv
->vbo_dirty
= true;
551 if (!tx
->bo
&& (tx
->base
.usage
& PIPE_TRANSFER_WRITE
))
552 NOUVEAU_DRV_STAT(nv
->screen
, buf_write_bytes_direct
, tx
->base
.box
.width
);
554 nouveau_buffer_transfer_del(nv
, tx
);
560 nouveau_copy_buffer(struct nouveau_context
*nv
,
561 struct nv04_resource
*dst
, unsigned dstx
,
562 struct nv04_resource
*src
, unsigned srcx
, unsigned size
)
564 assert(dst
->base
.target
== PIPE_BUFFER
&& src
->base
.target
== PIPE_BUFFER
);
566 if (likely(dst
->domain
) && likely(src
->domain
)) {
568 dst
->bo
, dst
->offset
+ dstx
, dst
->domain
,
569 src
->bo
, src
->offset
+ srcx
, src
->domain
, size
);
571 dst
->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
572 nouveau_fence_ref(nv
->screen
->fence
.current
, &dst
->fence
);
573 nouveau_fence_ref(nv
->screen
->fence
.current
, &dst
->fence_wr
);
575 src
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
576 nouveau_fence_ref(nv
->screen
->fence
.current
, &src
->fence
);
578 struct pipe_box src_box
;
582 src_box
.width
= size
;
585 util_resource_copy_region(&nv
->pipe
,
586 &dst
->base
, 0, dstx
, 0, 0,
587 &src
->base
, 0, &src_box
);
590 util_range_add(&dst
->valid_buffer_range
, dstx
, dstx
+ size
);
595 nouveau_resource_map_offset(struct nouveau_context
*nv
,
596 struct nv04_resource
*res
, uint32_t offset
,
599 if (unlikely(res
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
))
600 return res
->data
+ offset
;
602 if (res
->domain
== NOUVEAU_BO_VRAM
) {
603 if (!res
->data
|| (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
))
604 nouveau_buffer_cache(nv
, res
);
606 if (res
->domain
!= NOUVEAU_BO_GART
)
607 return res
->data
+ offset
;
611 rw
= (flags
& NOUVEAU_BO_WR
) ? PIPE_TRANSFER_WRITE
: PIPE_TRANSFER_READ
;
612 nouveau_buffer_sync(res
, rw
);
613 if (nouveau_bo_map(res
->bo
, 0, NULL
))
616 if (nouveau_bo_map(res
->bo
, flags
, nv
->client
))
619 return (uint8_t *)res
->bo
->map
+ res
->offset
+ offset
;
623 const struct u_resource_vtbl nouveau_buffer_vtbl
=
625 u_default_resource_get_handle
, /* get_handle */
626 nouveau_buffer_destroy
, /* resource_destroy */
627 nouveau_buffer_transfer_map
, /* transfer_map */
628 nouveau_buffer_transfer_flush_region
, /* transfer_flush_region */
629 nouveau_buffer_transfer_unmap
, /* transfer_unmap */
630 u_default_transfer_inline_write
/* transfer_inline_write */
633 struct pipe_resource
*
634 nouveau_buffer_create(struct pipe_screen
*pscreen
,
635 const struct pipe_resource
*templ
)
637 struct nouveau_screen
*screen
= nouveau_screen(pscreen
);
638 struct nv04_resource
*buffer
;
641 buffer
= CALLOC_STRUCT(nv04_resource
);
645 buffer
->base
= *templ
;
646 buffer
->vtbl
= &nouveau_buffer_vtbl
;
647 pipe_reference_init(&buffer
->base
.reference
, 1);
648 buffer
->base
.screen
= pscreen
;
650 if (buffer
->base
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
651 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
652 buffer
->domain
= NOUVEAU_BO_GART
;
653 } else if (buffer
->base
.bind
&
654 (screen
->vidmem_bindings
& screen
->sysmem_bindings
)) {
655 switch (buffer
->base
.usage
) {
656 case PIPE_USAGE_DEFAULT
:
657 case PIPE_USAGE_IMMUTABLE
:
658 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
660 case PIPE_USAGE_DYNAMIC
:
661 /* For most apps, we'd have to do staging transfers to avoid sync
662 * with this usage, and GART -> GART copies would be suboptimal.
664 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
666 case PIPE_USAGE_STAGING
:
667 case PIPE_USAGE_STREAM
:
668 buffer
->domain
= NOUVEAU_BO_GART
;
675 if (buffer
->base
.bind
& screen
->vidmem_bindings
)
676 buffer
->domain
= NV_VRAM_DOMAIN(screen
);
678 if (buffer
->base
.bind
& screen
->sysmem_bindings
)
679 buffer
->domain
= NOUVEAU_BO_GART
;
681 ret
= nouveau_buffer_allocate(screen
, buffer
, buffer
->domain
);
686 if (buffer
->domain
== NOUVEAU_BO_VRAM
&& screen
->hint_buf_keep_sysmem_copy
)
687 nouveau_buffer_cache(NULL
, buffer
);
689 NOUVEAU_DRV_STAT(screen
, buf_obj_current_count
, 1);
691 util_range_init(&buffer
->valid_buffer_range
);
693 return &buffer
->base
;
701 struct pipe_resource
*
702 nouveau_user_buffer_create(struct pipe_screen
*pscreen
, void *ptr
,
703 unsigned bytes
, unsigned bind
)
705 struct nv04_resource
*buffer
;
707 buffer
= CALLOC_STRUCT(nv04_resource
);
711 pipe_reference_init(&buffer
->base
.reference
, 1);
712 buffer
->vtbl
= &nouveau_buffer_vtbl
;
713 buffer
->base
.screen
= pscreen
;
714 buffer
->base
.format
= PIPE_FORMAT_R8_UNORM
;
715 buffer
->base
.usage
= PIPE_USAGE_IMMUTABLE
;
716 buffer
->base
.bind
= bind
;
717 buffer
->base
.width0
= bytes
;
718 buffer
->base
.height0
= 1;
719 buffer
->base
.depth0
= 1;
722 buffer
->status
= NOUVEAU_BUFFER_STATUS_USER_MEMORY
;
724 util_range_init(&buffer
->valid_buffer_range
);
725 util_range_add(&buffer
->valid_buffer_range
, 0, bytes
);
727 return &buffer
->base
;
731 nouveau_buffer_data_fetch(struct nouveau_context
*nv
, struct nv04_resource
*buf
,
732 struct nouveau_bo
*bo
, unsigned offset
, unsigned size
)
734 if (!nouveau_buffer_malloc(buf
))
736 if (nouveau_bo_map(bo
, NOUVEAU_BO_RD
, nv
->client
))
738 memcpy(buf
->data
, (uint8_t *)bo
->map
+ offset
, size
);
742 /* Migrate a linear buffer (vertex, index, constants) USER -> GART -> VRAM. */
744 nouveau_buffer_migrate(struct nouveau_context
*nv
,
745 struct nv04_resource
*buf
, const unsigned new_domain
)
747 struct nouveau_screen
*screen
= nv
->screen
;
748 struct nouveau_bo
*bo
;
749 const unsigned old_domain
= buf
->domain
;
750 unsigned size
= buf
->base
.width0
;
754 assert(new_domain
!= old_domain
);
756 if (new_domain
== NOUVEAU_BO_GART
&& old_domain
== 0) {
757 if (!nouveau_buffer_allocate(screen
, buf
, new_domain
))
759 ret
= nouveau_bo_map(buf
->bo
, 0, nv
->client
);
762 memcpy((uint8_t *)buf
->bo
->map
+ buf
->offset
, buf
->data
, size
);
763 align_free(buf
->data
);
765 if (old_domain
!= 0 && new_domain
!= 0) {
766 struct nouveau_mm_allocation
*mm
= buf
->mm
;
768 if (new_domain
== NOUVEAU_BO_VRAM
) {
769 /* keep a system memory copy of our data in case we hit a fallback */
770 if (!nouveau_buffer_data_fetch(nv
, buf
, buf
->bo
, buf
->offset
, size
))
772 if (nouveau_mesa_debug
)
773 debug_printf("migrating %u KiB to VRAM\n", size
/ 1024);
776 offset
= buf
->offset
;
780 nouveau_buffer_allocate(screen
, buf
, new_domain
);
782 nv
->copy_data(nv
, buf
->bo
, buf
->offset
, new_domain
,
783 bo
, offset
, old_domain
, buf
->base
.width0
);
785 nouveau_bo_ref(NULL
, &bo
);
787 release_allocation(&mm
, screen
->fence
.current
);
789 if (new_domain
== NOUVEAU_BO_VRAM
&& old_domain
== 0) {
790 struct nouveau_transfer tx
;
791 if (!nouveau_buffer_allocate(screen
, buf
, NOUVEAU_BO_VRAM
))
793 tx
.base
.resource
= &buf
->base
;
795 tx
.base
.box
.width
= buf
->base
.width0
;
798 if (!nouveau_transfer_staging(nv
, &tx
, false))
800 nouveau_transfer_write(nv
, &tx
, 0, tx
.base
.box
.width
);
801 nouveau_buffer_transfer_del(nv
, &tx
);
805 assert(buf
->domain
== new_domain
);
809 /* Migrate data from glVertexAttribPointer(non-VBO) user buffers to GART.
810 * We'd like to only allocate @size bytes here, but then we'd have to rebase
811 * the vertex indices ...
814 nouveau_user_buffer_upload(struct nouveau_context
*nv
,
815 struct nv04_resource
*buf
,
816 unsigned base
, unsigned size
)
818 struct nouveau_screen
*screen
= nouveau_screen(buf
->base
.screen
);
821 assert(buf
->status
& NOUVEAU_BUFFER_STATUS_USER_MEMORY
);
823 buf
->base
.width0
= base
+ size
;
824 if (!nouveau_buffer_reallocate(screen
, buf
, NOUVEAU_BO_GART
))
827 ret
= nouveau_bo_map(buf
->bo
, 0, nv
->client
);
830 memcpy((uint8_t *)buf
->bo
->map
+ buf
->offset
+ base
, buf
->data
+ base
, size
);
836 /* Scratch data allocation. */
839 nouveau_scratch_bo_alloc(struct nouveau_context
*nv
, struct nouveau_bo
**pbo
,
842 return nouveau_bo_new(nv
->screen
->device
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
,
843 4096, size
, NULL
, pbo
);
847 nouveau_scratch_unref_bos(void *d
)
849 struct runout
*b
= d
;
852 for (i
= 0; i
< b
->nr
; ++i
)
853 nouveau_bo_ref(NULL
, &b
->bo
[i
]);
859 nouveau_scratch_runout_release(struct nouveau_context
*nv
)
861 if (!nv
->scratch
.runout
)
864 if (!nouveau_fence_work(nv
->screen
->fence
.current
, nouveau_scratch_unref_bos
,
869 nv
->scratch
.runout
= NULL
;
872 /* Allocate an extra bo if we can't fit everything we need simultaneously.
873 * (Could happen for very large user arrays.)
876 nouveau_scratch_runout(struct nouveau_context
*nv
, unsigned size
)
881 if (nv
->scratch
.runout
)
882 n
= nv
->scratch
.runout
->nr
;
885 nv
->scratch
.runout
= REALLOC(nv
->scratch
.runout
, n
== 0 ? 0 :
886 (sizeof(*nv
->scratch
.runout
) + (n
+ 0) * sizeof(void *)),
887 sizeof(*nv
->scratch
.runout
) + (n
+ 1) * sizeof(void *));
888 nv
->scratch
.runout
->nr
= n
+ 1;
889 nv
->scratch
.runout
->bo
[n
] = NULL
;
891 ret
= nouveau_scratch_bo_alloc(nv
, &nv
->scratch
.runout
->bo
[n
], size
);
893 ret
= nouveau_bo_map(nv
->scratch
.runout
->bo
[n
], 0, NULL
);
895 nouveau_bo_ref(NULL
, &nv
->scratch
.runout
->bo
[--nv
->scratch
.runout
->nr
]);
898 nv
->scratch
.current
= nv
->scratch
.runout
->bo
[n
];
899 nv
->scratch
.offset
= 0;
900 nv
->scratch
.end
= size
;
901 nv
->scratch
.map
= nv
->scratch
.current
->map
;
906 /* Continue to next scratch buffer, if available (no wrapping, large enough).
907 * Allocate it if it has not yet been created.
910 nouveau_scratch_next(struct nouveau_context
*nv
, unsigned size
)
912 struct nouveau_bo
*bo
;
914 const unsigned i
= (nv
->scratch
.id
+ 1) % NOUVEAU_MAX_SCRATCH_BUFS
;
916 if ((size
> nv
->scratch
.bo_size
) || (i
== nv
->scratch
.wrap
))
920 bo
= nv
->scratch
.bo
[i
];
922 ret
= nouveau_scratch_bo_alloc(nv
, &bo
, nv
->scratch
.bo_size
);
925 nv
->scratch
.bo
[i
] = bo
;
927 nv
->scratch
.current
= bo
;
928 nv
->scratch
.offset
= 0;
929 nv
->scratch
.end
= nv
->scratch
.bo_size
;
931 ret
= nouveau_bo_map(bo
, NOUVEAU_BO_WR
, nv
->client
);
933 nv
->scratch
.map
= bo
->map
;
938 nouveau_scratch_more(struct nouveau_context
*nv
, unsigned min_size
)
942 ret
= nouveau_scratch_next(nv
, min_size
);
944 ret
= nouveau_scratch_runout(nv
, min_size
);
949 /* Copy data to a scratch buffer and return address & bo the data resides in. */
951 nouveau_scratch_data(struct nouveau_context
*nv
,
952 const void *data
, unsigned base
, unsigned size
,
953 struct nouveau_bo
**bo
)
955 unsigned bgn
= MAX2(base
, nv
->scratch
.offset
);
956 unsigned end
= bgn
+ size
;
958 if (end
>= nv
->scratch
.end
) {
960 if (!nouveau_scratch_more(nv
, end
))
964 nv
->scratch
.offset
= align(end
, 4);
966 memcpy(nv
->scratch
.map
+ bgn
, (const uint8_t *)data
+ base
, size
);
968 *bo
= nv
->scratch
.current
;
969 return (*bo
)->offset
+ (bgn
- base
);
973 nouveau_scratch_get(struct nouveau_context
*nv
,
974 unsigned size
, uint64_t *gpu_addr
, struct nouveau_bo
**pbo
)
976 unsigned bgn
= nv
->scratch
.offset
;
977 unsigned end
= nv
->scratch
.offset
+ size
;
979 if (end
>= nv
->scratch
.end
) {
981 if (!nouveau_scratch_more(nv
, end
))
985 nv
->scratch
.offset
= align(end
, 4);
987 *pbo
= nv
->scratch
.current
;
988 *gpu_addr
= nv
->scratch
.current
->offset
+ bgn
;
989 return nv
->scratch
.map
+ bgn
;