nv50,nvc0: fix push hint logic in presence of a start offset
[mesa.git] / src / gallium / drivers / nouveau / nouveau_screen.h
1 #ifndef __NOUVEAU_SCREEN_H__
2 #define __NOUVEAU_SCREEN_H__
3
4 #include "pipe/p_screen.h"
5 #include "util/disk_cache.h"
6 #include "util/u_memory.h"
7
8 #ifdef DEBUG
9 # define NOUVEAU_ENABLE_DRIVER_STATISTICS
10 #endif
11
12 typedef uint32_t u32;
13 typedef uint16_t u16;
14
15 extern int nouveau_mesa_debug;
16
17 struct nouveau_bo;
18
19 struct nouveau_screen {
20 struct pipe_screen base;
21 struct nouveau_drm *drm;
22 struct nouveau_device *device;
23 struct nouveau_object *channel;
24 struct nouveau_client *client;
25 struct nouveau_pushbuf *pushbuf;
26
27 int refcount;
28
29 unsigned vidmem_bindings; /* PIPE_BIND_* where VRAM placement is desired */
30 unsigned sysmem_bindings; /* PIPE_BIND_* where GART placement is desired */
31 unsigned lowmem_bindings; /* PIPE_BIND_* that require an address < 4 GiB */
32 /*
33 * For bindings with (vidmem & sysmem) bits set, PIPE_USAGE_* decides
34 * placement.
35 */
36
37 uint16_t class_3d;
38
39 struct {
40 struct nouveau_fence *head;
41 struct nouveau_fence *tail;
42 struct nouveau_fence *current;
43 u32 sequence;
44 u32 sequence_ack;
45 void (*emit)(struct pipe_screen *, u32 *sequence);
46 u32 (*update)(struct pipe_screen *);
47 } fence;
48
49 struct nouveau_mman *mm_VRAM;
50 struct nouveau_mman *mm_GART;
51
52 int64_t cpu_gpu_time_delta;
53
54 bool hint_buf_keep_sysmem_copy;
55
56 unsigned vram_domain;
57
58 struct {
59 unsigned profiles_checked;
60 unsigned profiles_present;
61 } firmware_info;
62
63 struct disk_cache *disk_shader_cache;
64
65 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
66 union {
67 uint64_t v[29];
68 struct {
69 uint64_t tex_obj_current_count;
70 uint64_t tex_obj_current_bytes;
71 uint64_t buf_obj_current_count;
72 uint64_t buf_obj_current_bytes_vid;
73 uint64_t buf_obj_current_bytes_sys;
74 uint64_t tex_transfers_rd;
75 uint64_t tex_transfers_wr;
76 uint64_t tex_copy_count;
77 uint64_t tex_blit_count;
78 uint64_t tex_cache_flush_count;
79 uint64_t buf_transfers_rd;
80 uint64_t buf_transfers_wr;
81 uint64_t buf_read_bytes_staging_vid;
82 uint64_t buf_write_bytes_direct;
83 uint64_t buf_write_bytes_staging_vid;
84 uint64_t buf_write_bytes_staging_sys;
85 uint64_t buf_copy_bytes;
86 uint64_t buf_non_kernel_fence_sync_count;
87 uint64_t any_non_kernel_fence_sync_count;
88 uint64_t query_sync_count;
89 uint64_t gpu_serialize_count;
90 uint64_t draw_calls_array;
91 uint64_t draw_calls_indexed;
92 uint64_t draw_calls_fallback_count;
93 uint64_t user_buffer_upload_bytes;
94 uint64_t constbuf_upload_count;
95 uint64_t constbuf_upload_bytes;
96 uint64_t pushbuf_count;
97 uint64_t resource_validate_count;
98 } named;
99 } stats;
100 #endif
101 };
102
103 #define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain)
104
105 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
106 # define NOUVEAU_DRV_STAT(s, n, v) do { \
107 (s)->stats.named.n += (v); \
108 } while(0)
109 # define NOUVEAU_DRV_STAT_RES(r, n, v) do { \
110 nouveau_screen((r)->base.screen)->stats.named.n += (v); \
111 } while(0)
112 # define NOUVEAU_DRV_STAT_IFD(x) x
113 #else
114 # define NOUVEAU_DRV_STAT(s, n, v) do { } while(0)
115 # define NOUVEAU_DRV_STAT_RES(r, n, v) do { } while(0)
116 # define NOUVEAU_DRV_STAT_IFD(x)
117 #endif
118
119 static inline struct nouveau_screen *
120 nouveau_screen(struct pipe_screen *pscreen)
121 {
122 return (struct nouveau_screen *)pscreen;
123 }
124
125 bool nouveau_drm_screen_unref(struct nouveau_screen *screen);
126
127 bool
128 nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
129 struct nouveau_bo *bo,
130 unsigned stride,
131 struct winsys_handle *whandle);
132 struct nouveau_bo *
133 nouveau_screen_bo_from_handle(struct pipe_screen *pscreen,
134 struct winsys_handle *whandle,
135 unsigned *out_stride);
136
137
138 int nouveau_screen_init(struct nouveau_screen *, struct nouveau_device *);
139 void nouveau_screen_fini(struct nouveau_screen *);
140
141 void nouveau_screen_init_vdec(struct nouveau_screen *);
142
143 #endif