2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
50 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
52 struct nv30_screen
*screen
= nv30_screen(pscreen
);
53 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS
:
59 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
66 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
68 case PIPE_CAP_ENDIANNESS
:
69 return PIPE_ENDIAN_LITTLE
;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
72 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
73 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
74 case PIPE_CAP_MAX_VIEWPORTS
:
76 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
78 /* supported capabilities */
79 case PIPE_CAP_ANISOTROPIC_FILTER
:
80 case PIPE_CAP_POINT_SPRITE
:
81 case PIPE_CAP_OCCLUSION_QUERY
:
82 case PIPE_CAP_QUERY_TIME_ELAPSED
:
83 case PIPE_CAP_QUERY_TIMESTAMP
:
84 case PIPE_CAP_TEXTURE_SWIZZLE
:
85 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
86 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
87 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
88 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
89 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
90 case PIPE_CAP_TGSI_TEXCOORD
:
91 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
92 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
93 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
94 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
95 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
96 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
98 /* nv35 capabilities */
99 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
100 return eng3d
->oclass
== NV35_3D_CLASS
|| eng3d
->oclass
>= NV40_3D_CLASS
;
101 /* nv4x capabilities */
102 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
103 case PIPE_CAP_NPOT_TEXTURES
:
104 case PIPE_CAP_CONDITIONAL_RENDER
:
105 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
106 case PIPE_CAP_PRIMITIVE_RESTART
:
107 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
109 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
111 case PIPE_CAP_INDEP_BLEND_ENABLE
:
112 case PIPE_CAP_INDEP_BLEND_FUNC
:
113 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
114 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
115 case PIPE_CAP_TGSI_INSTANCEID
:
116 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
117 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
118 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
119 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
120 case PIPE_CAP_MIN_TEXEL_OFFSET
:
121 case PIPE_CAP_MAX_TEXEL_OFFSET
:
122 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
123 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
124 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
125 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
126 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
127 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
128 case PIPE_CAP_MAX_VERTEX_STREAMS
:
129 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
130 case PIPE_CAP_TEXTURE_BARRIER
:
131 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
132 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
133 case PIPE_CAP_CUBE_MAP_ARRAY
:
134 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
135 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
136 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
137 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
139 case PIPE_CAP_START_INSTANCE
:
140 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
141 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
142 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
143 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
144 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
145 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
146 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
147 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
148 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
149 case PIPE_CAP_TEXTURE_GATHER_SM5
:
150 case PIPE_CAP_FAKE_SW_MSAA
:
151 case PIPE_CAP_TEXTURE_QUERY_LOD
:
152 case PIPE_CAP_SAMPLE_SHADING
:
153 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
154 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
155 case PIPE_CAP_USER_VERTEX_BUFFERS
:
156 case PIPE_CAP_COMPUTE
:
157 case PIPE_CAP_DRAW_INDIRECT
:
158 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
159 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
160 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
161 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
162 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
163 case PIPE_CAP_CLIP_HALFZ
:
164 case PIPE_CAP_VERTEXID_NOBASE
:
165 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
166 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
167 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
168 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
169 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
170 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
171 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
172 case PIPE_CAP_TGSI_TXQS
:
173 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
174 case PIPE_CAP_SHAREABLE_SHADERS
:
175 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
176 case PIPE_CAP_CLEAR_TEXTURE
:
177 case PIPE_CAP_DRAW_PARAMETERS
:
178 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
179 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
180 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
181 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
182 case PIPE_CAP_INVALIDATE_BUFFER
:
183 case PIPE_CAP_GENERATE_MIPMAP
:
184 case PIPE_CAP_STRING_MARKER
:
185 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
186 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
187 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
188 case PIPE_CAP_QUERY_MEMORY_INFO
:
189 case PIPE_CAP_PCI_GROUP
:
190 case PIPE_CAP_PCI_BUS
:
191 case PIPE_CAP_PCI_DEVICE
:
192 case PIPE_CAP_PCI_FUNCTION
:
193 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
194 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
195 case PIPE_CAP_CULL_DISTANCE
:
196 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
197 case PIPE_CAP_TGSI_VOTE
:
198 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
199 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
200 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
201 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
202 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
203 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
204 case PIPE_CAP_NATIVE_FENCE_FD
:
205 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
206 case PIPE_CAP_TGSI_FS_FBFETCH
:
207 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
208 case PIPE_CAP_DOUBLES
:
210 case PIPE_CAP_INT64_DIVMOD
:
211 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
212 case PIPE_CAP_TGSI_CLOCK
:
213 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
214 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
215 case PIPE_CAP_TGSI_BALLOT
:
216 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
217 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
218 case PIPE_CAP_POST_DEPTH_COVERAGE
:
219 case PIPE_CAP_BINDLESS_TEXTURE
:
220 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
221 case PIPE_CAP_QUERY_SO_OVERFLOW
:
222 case PIPE_CAP_MEMOBJ
:
223 case PIPE_CAP_LOAD_CONSTBUF
:
224 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
225 case PIPE_CAP_TILE_RASTER_ORDER
:
226 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
227 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
228 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
229 case PIPE_CAP_FENCE_SIGNAL
:
232 case PIPE_CAP_VENDOR_ID
:
234 case PIPE_CAP_DEVICE_ID
: {
236 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
237 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
242 case PIPE_CAP_ACCELERATED
:
244 case PIPE_CAP_VIDEO_MEMORY
:
245 return dev
->vram_size
>> 20;
250 debug_printf("unknown param %d\n", param
);
255 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
257 struct nv30_screen
*screen
= nv30_screen(pscreen
);
258 struct nouveau_object
*eng3d
= screen
->eng3d
;
261 case PIPE_CAPF_MAX_LINE_WIDTH
:
262 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
264 case PIPE_CAPF_MAX_POINT_WIDTH
:
265 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
267 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
268 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
269 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
272 debug_printf("unknown paramf %d\n", param
);
278 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
,
279 enum pipe_shader_type shader
,
280 enum pipe_shader_cap param
)
282 struct nv30_screen
*screen
= nv30_screen(pscreen
);
283 struct nouveau_object
*eng3d
= screen
->eng3d
;
286 case PIPE_SHADER_VERTEX
:
288 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
289 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
290 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
291 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
292 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
293 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
294 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
296 case PIPE_SHADER_CAP_MAX_INPUTS
:
297 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
299 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
300 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
301 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
303 case PIPE_SHADER_CAP_MAX_TEMPS
:
304 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
305 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
307 case PIPE_SHADER_CAP_PREFERRED_IR
:
308 return PIPE_SHADER_IR_TGSI
;
309 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
310 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
312 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
313 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
314 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
315 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
316 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
317 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
318 case PIPE_SHADER_CAP_SUBROUTINES
:
319 case PIPE_SHADER_CAP_INTEGERS
:
320 case PIPE_SHADER_CAP_INT64_ATOMICS
:
321 case PIPE_SHADER_CAP_FP16
:
322 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
323 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
324 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
325 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
326 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
327 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
328 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
329 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
330 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
331 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
332 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
335 debug_printf("unknown vertex shader param %d\n", param
);
339 case PIPE_SHADER_FRAGMENT
:
341 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
342 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
343 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
344 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
346 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
348 case PIPE_SHADER_CAP_MAX_INPUTS
:
349 return 8; /* should be possible to do 10 with nv4x */
350 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
352 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
353 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32) * sizeof(float[4]);
354 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
356 case PIPE_SHADER_CAP_MAX_TEMPS
:
358 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
359 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
361 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
363 case PIPE_SHADER_CAP_PREFERRED_IR
:
364 return PIPE_SHADER_IR_TGSI
;
365 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
366 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
367 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
368 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
369 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
370 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
371 case PIPE_SHADER_CAP_SUBROUTINES
:
372 case PIPE_SHADER_CAP_INTEGERS
:
373 case PIPE_SHADER_CAP_FP16
:
374 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
375 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
376 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
377 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
378 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
379 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
380 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
381 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
382 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
385 debug_printf("unknown fragment shader param %d\n", param
);
395 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
396 enum pipe_format format
,
397 enum pipe_texture_target target
,
398 unsigned sample_count
,
401 if (sample_count
> nv30_screen(pscreen
)->max_sample_count
)
404 if (!(0x00000017 & (1 << sample_count
)))
407 if (!util_format_is_supported(format
, bindings
)) {
411 /* shared is always supported */
412 bindings
&= ~PIPE_BIND_SHARED
;
414 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
418 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
420 struct nv30_screen
*screen
= nv30_screen(pscreen
);
421 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
423 *sequence
= ++screen
->base
.fence
.sequence
;
425 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 3);
426 PUSH_DATA (push
, NV30_3D_FENCE_OFFSET
|
427 (2 /* size */ << 18) | (7 /* subchan */ << 13));
429 PUSH_DATA (push
, *sequence
);
433 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
435 struct nv30_screen
*screen
= nv30_screen(pscreen
);
436 struct nv04_notify
*fence
= screen
->fence
->data
;
437 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
441 nv30_screen_destroy(struct pipe_screen
*pscreen
)
443 struct nv30_screen
*screen
= nv30_screen(pscreen
);
445 if (!nouveau_drm_screen_unref(&screen
->base
))
448 if (screen
->base
.fence
.current
) {
449 struct nouveau_fence
*current
= NULL
;
451 /* nouveau_fence_wait will create a new current fence, so wait on the
452 * _current_ one, and remove both.
454 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
455 nouveau_fence_wait(current
, NULL
);
456 nouveau_fence_ref(NULL
, ¤t
);
457 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
460 nouveau_bo_ref(NULL
, &screen
->notify
);
462 nouveau_heap_destroy(&screen
->query_heap
);
463 nouveau_heap_destroy(&screen
->vp_exec_heap
);
464 nouveau_heap_destroy(&screen
->vp_data_heap
);
466 nouveau_object_del(&screen
->query
);
467 nouveau_object_del(&screen
->fence
);
468 nouveau_object_del(&screen
->ntfy
);
470 nouveau_object_del(&screen
->sifm
);
471 nouveau_object_del(&screen
->swzsurf
);
472 nouveau_object_del(&screen
->surf2d
);
473 nouveau_object_del(&screen
->m2mf
);
474 nouveau_object_del(&screen
->eng3d
);
475 nouveau_object_del(&screen
->null
);
477 nouveau_screen_fini(&screen
->base
);
481 #define FAIL_SCREEN_INIT(str, err) \
483 NOUVEAU_ERR(str, err); \
484 screen->base.base.context_create = NULL; \
485 return &screen->base; \
488 struct nouveau_screen
*
489 nv30_screen_create(struct nouveau_device
*dev
)
491 struct nv30_screen
*screen
;
492 struct pipe_screen
*pscreen
;
493 struct nouveau_pushbuf
*push
;
494 struct nv04_fifo
*fifo
;
498 switch (dev
->chipset
& 0xf0) {
500 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
501 oclass
= NV30_3D_CLASS
;
503 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
504 oclass
= NV34_3D_CLASS
;
506 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
507 oclass
= NV35_3D_CLASS
;
510 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
511 oclass
= NV40_3D_CLASS
;
513 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
514 oclass
= NV44_3D_CLASS
;
517 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
518 oclass
= NV44_3D_CLASS
;
525 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
529 screen
= CALLOC_STRUCT(nv30_screen
);
533 pscreen
= &screen
->base
.base
;
534 pscreen
->destroy
= nv30_screen_destroy
;
537 * Some modern apps try to use msaa without keeping in mind the
538 * restrictions on videomem of older cards. Resulting in dmesg saying:
539 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
540 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
541 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
543 * Because we are running out of video memory, after which the program
544 * using the msaa visual freezes, and eventually the entire system freezes.
546 * To work around this we do not allow msaa visauls by default and allow
547 * the user to override this via NV30_MAX_MSAA.
549 screen
->max_sample_count
= debug_get_num_option("NV30_MAX_MSAA", 0);
550 if (screen
->max_sample_count
> 4)
551 screen
->max_sample_count
= 4;
553 pscreen
->get_param
= nv30_screen_get_param
;
554 pscreen
->get_paramf
= nv30_screen_get_paramf
;
555 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
556 pscreen
->context_create
= nv30_context_create
;
557 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
558 nv30_resource_screen_init(pscreen
);
559 nouveau_screen_init_vdec(&screen
->base
);
561 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
562 screen
->base
.fence
.update
= nv30_screen_fence_update
;
564 ret
= nouveau_screen_init(&screen
->base
, dev
);
566 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
568 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
569 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
570 if (oclass
== NV40_3D_CLASS
) {
571 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
572 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
575 fifo
= screen
->base
.channel
->data
;
576 push
= screen
->base
.pushbuf
;
577 push
->rsvd_kick
= 16;
579 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
580 NULL
, 0, &screen
->null
);
582 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
584 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
585 * this means that the address pointed at by the DMA object must
586 * be 4KiB aligned, which means this object needs to be the first
587 * one allocated on the channel.
589 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
590 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
591 .length
= 32 }, sizeof(struct nv04_notify
),
594 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
596 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
597 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
598 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
599 .length
= 32 }, sizeof(struct nv04_notify
),
602 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
604 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
605 * the remainder of the "notifier block" assigned by the kernel for
606 * use as query objects
608 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
609 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
610 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
613 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
615 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
617 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
619 LIST_INITHEAD(&screen
->queries
);
621 /* Vertex program resources (code/data), currently 6 of the constant
622 * slots are reserved to implement user clipping planes
624 if (oclass
< NV40_3D_CLASS
) {
625 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
626 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
628 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
629 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
632 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
634 ret
= nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
636 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
638 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
639 NULL
, 0, &screen
->eng3d
);
641 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
643 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
644 PUSH_DATA (push
, screen
->eng3d
->handle
);
645 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
646 PUSH_DATA (push
, screen
->ntfy
->handle
);
647 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
648 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
649 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
650 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
651 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
652 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
653 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
654 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
655 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
656 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
657 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
658 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
659 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
660 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
661 PUSH_DATA (push
, 0x00100000);
662 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
665 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
667 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
668 PUSH_DATA (push
, fui(0.0));
669 PUSH_DATA (push
, fui(0.0));
670 PUSH_DATA (push
, fui(1.0));
671 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
672 for (i
= 0; i
< 16; i
++)
673 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
675 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
678 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
679 PUSH_DATA (push
, fifo
->vram
);
680 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
682 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
683 PUSH_DATA (push
, 0x00000004);
685 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
686 PUSH_DATA (push
, 0x00000010);
687 PUSH_DATA (push
, 0x01000100);
688 PUSH_DATA (push
, 0xff800006);
690 /* vtxprog output routing */
691 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
692 PUSH_DATA (push
, 0x06144321);
693 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
694 PUSH_DATA (push
, 0xedcba987);
695 PUSH_DATA (push
, 0x0000006f);
696 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
697 PUSH_DATA (push
, 0x00171615);
698 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
699 PUSH_DATA (push
, 0x001b1a19);
701 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
702 PUSH_DATA (push
, 0x0020ffff);
703 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
704 PUSH_DATA (push
, 0x01d300d4);
706 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
707 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
710 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
711 NULL
, 0, &screen
->m2mf
);
713 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
715 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
716 PUSH_DATA (push
, screen
->m2mf
->handle
);
717 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
718 PUSH_DATA (push
, screen
->ntfy
->handle
);
720 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
721 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
723 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
725 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
726 PUSH_DATA (push
, screen
->surf2d
->handle
);
727 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
728 PUSH_DATA (push
, screen
->ntfy
->handle
);
730 if (dev
->chipset
< 0x40)
731 oclass
= NV30_SURFACE_SWZ_CLASS
;
733 oclass
= NV40_SURFACE_SWZ_CLASS
;
735 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
736 NULL
, 0, &screen
->swzsurf
);
738 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
740 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
741 PUSH_DATA (push
, screen
->swzsurf
->handle
);
742 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
743 PUSH_DATA (push
, screen
->ntfy
->handle
);
745 if (dev
->chipset
< 0x40)
746 oclass
= NV30_SIFM_CLASS
;
748 oclass
= NV40_SIFM_CLASS
;
750 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
751 NULL
, 0, &screen
->sifm
);
753 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
755 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
756 PUSH_DATA (push
, screen
->sifm
->handle
);
757 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
758 PUSH_DATA (push
, screen
->ntfy
->handle
);
759 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
760 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
762 nouveau_pushbuf_kick(push
, push
->channel
);
764 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
);
765 return &screen
->base
;