src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    case PIPE_CAP_ENDIANNESS:
  66       return PIPE_ENDIAN_LITTLE;
  67    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  68       return 16;
  69    case PIPE_CAP_MAX_VIEWPORTS:
  70       return 1;
  71    /* supported capabilities */
  72    case PIPE_CAP_TWO_SIDED_STENCIL:
  73    case PIPE_CAP_ANISOTROPIC_FILTER:
  74    case PIPE_CAP_POINT_SPRITE:
  75    case PIPE_CAP_OCCLUSION_QUERY:
  76    case PIPE_CAP_QUERY_TIME_ELAPSED:
  77    case PIPE_CAP_QUERY_TIMESTAMP:
  78    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  79    case PIPE_CAP_TEXTURE_SWIZZLE:
  80    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  81    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  82    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  83    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  84    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  85    case PIPE_CAP_TGSI_TEXCOORD:
  86    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  87    case PIPE_CAP_USER_INDEX_BUFFERS:
  88    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  89    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  90    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  91    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  92    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  93       return 1;
  94    /* nv4x capabilities */
  95    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  96    case PIPE_CAP_NPOT_TEXTURES:
  97    case PIPE_CAP_CONDITIONAL_RENDER:
  98    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  99    case PIPE_CAP_PRIMITIVE_RESTART:
 100       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 101    /* unsupported */
 102    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 103    case PIPE_CAP_SM3:
 104    case PIPE_CAP_INDEP_BLEND_ENABLE:
 105    case PIPE_CAP_INDEP_BLEND_FUNC:
 106    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 107    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 108    case PIPE_CAP_TGSI_INSTANCEID:
 109    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 111    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113    case PIPE_CAP_MAX_TEXEL_OFFSET:
 114    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 115    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 117    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 118    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 119    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 120    case PIPE_CAP_MAX_VERTEX_STREAMS:
 121    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 122    case PIPE_CAP_TEXTURE_BARRIER:
 123    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 124    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 127    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 128    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 129    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 130    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 131    case PIPE_CAP_START_INSTANCE:
 132    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 133    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 134    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 135    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 136    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 137    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 138    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 139    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 140    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 141    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 142    case PIPE_CAP_TEXTURE_GATHER_SM5:
 143    case PIPE_CAP_FAKE_SW_MSAA:
 144    case PIPE_CAP_TEXTURE_QUERY_LOD:
 145    case PIPE_CAP_SAMPLE_SHADING:
 146    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 147    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 148    case PIPE_CAP_USER_VERTEX_BUFFERS:
 149    case PIPE_CAP_COMPUTE:
 150    case PIPE_CAP_DRAW_INDIRECT:
 151       return 0;
 152    }
 153
 154    debug_printf("unknown param %d\n", param);
 155    return 0;
 156 }
 157
 158 static float
 159 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 160 {
 161    struct nv30_screen *screen = nv30_screen(pscreen);
 162    struct nouveau_object *eng3d = screen->eng3d;
 163
 164    switch (param) {
 165    case PIPE_CAPF_MAX_LINE_WIDTH:
 166    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 167       return 10.0;
 168    case PIPE_CAPF_MAX_POINT_WIDTH:
 169    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 170       return 64.0;
 171    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 172       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 173    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 174       return 15.0;
 175    default:
 176       debug_printf("unknown paramf %d\n", param);
 177       return 0;
 178    }
 179 }
 180
 181 static int
 182 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 183                              enum pipe_shader_cap param)
 184 {
 185    struct nv30_screen *screen = nv30_screen(pscreen);
 186    struct nouveau_object *eng3d = screen->eng3d;
 187
 188    switch (shader) {
 189    case PIPE_SHADER_VERTEX:
 190       switch (param) {
 191       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 192       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 193          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 194       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 195       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 196          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 197       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 198          return 0;
 199       case PIPE_SHADER_CAP_MAX_INPUTS:
 200          return 16;
 201       case PIPE_SHADER_CAP_MAX_CONSTS:
 202          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 203       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 204          return 1;
 205       case PIPE_SHADER_CAP_MAX_TEMPS:
 206          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 207       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 208       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 209          return 0;
 210       case PIPE_SHADER_CAP_MAX_ADDRS:
 211          return 2;
 212       case PIPE_SHADER_CAP_MAX_PREDS:
 213       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 214       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 215       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 216       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 217       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 218       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 219       case PIPE_SHADER_CAP_SUBROUTINES:
 220       case PIPE_SHADER_CAP_INTEGERS:
 221          return 0;
 222       default:
 223          debug_printf("unknown vertex shader param %d\n", param);
 224          return 0;
 225       }
 226       break;
 227    case PIPE_SHADER_FRAGMENT:
 228       switch (param) {
 229       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 230       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 231       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 232       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 233          return 4096;
 234       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 235          return 0;
 236       case PIPE_SHADER_CAP_MAX_INPUTS:
 237          return 8; /* should be possible to do 10 with nv4x */
 238       case PIPE_SHADER_CAP_MAX_CONSTS:
 239          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 240       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 241          return 1;
 242       case PIPE_SHADER_CAP_MAX_TEMPS:
 243          return 32;
 244       case PIPE_SHADER_CAP_MAX_ADDRS:
 245          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 246       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 247       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 248          return 16;
 249       case PIPE_SHADER_CAP_MAX_PREDS:
 250       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 251       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 252       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 253       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 254       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 255       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 256       case PIPE_SHADER_CAP_SUBROUTINES:
 257          return 0;
 258       default:
 259          debug_printf("unknown fragment shader param %d\n", param);
 260          return 0;
 261       }
 262       break;
 263    default:
 264       return 0;
 265    }
 266 }
 267
 268 static boolean
 269 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 270                                 enum pipe_format format,
 271                                 enum pipe_texture_target target,
 272                                 unsigned sample_count,
 273                                 unsigned bindings)
 274 {
 275    if (sample_count > 4)
 276       return FALSE;
 277    if (!(0x00000017 & (1 << sample_count)))
 278       return FALSE;
 279
 280    if (!util_format_is_supported(format, bindings)) {
 281       return FALSE;
 282    }
 283
 284    /* transfers & shared are always supported */
 285    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 286                  PIPE_BIND_TRANSFER_WRITE |
 287                  PIPE_BIND_SHARED);
 288
 289    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 290 }
 291
 292 static void
 293 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 294 {
 295    struct nv30_screen *screen = nv30_screen(pscreen);
 296    struct nouveau_pushbuf *push = screen->base.pushbuf;
 297
 298    *sequence = ++screen->base.fence.sequence;
 299
 300    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 301    PUSH_DATA (push, 0);
 302    PUSH_DATA (push, *sequence);
 303 }
 304
 305 static uint32_t
 306 nv30_screen_fence_update(struct pipe_screen *pscreen)
 307 {
 308    struct nv30_screen *screen = nv30_screen(pscreen);
 309    struct nv04_notify *fence = screen->fence->data;
 310    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 311 }
 312
 313 static void
 314 nv30_screen_destroy(struct pipe_screen *pscreen)
 315 {
 316    struct nv30_screen *screen = nv30_screen(pscreen);
 317
 318    if (!nouveau_drm_screen_unref(&screen->base))
 319       return;
 320
 321    if (screen->base.fence.current) {
 322       struct nouveau_fence *current = NULL;
 323
 324       /* nouveau_fence_wait will create a new current fence, so wait on the
 325        * _current_ one, and remove both.
 326        */
 327       nouveau_fence_ref(screen->base.fence.current, &current);
 328       nouveau_fence_wait(current);
 329       nouveau_fence_ref(NULL, &current);
 330       nouveau_fence_ref(NULL, &screen->base.fence.current);
 331    }
 332
 333    nouveau_bo_ref(NULL, &screen->notify);
 334
 335    nouveau_heap_destroy(&screen->query_heap);
 336    nouveau_heap_destroy(&screen->vp_exec_heap);
 337    nouveau_heap_destroy(&screen->vp_data_heap);
 338
 339    nouveau_object_del(&screen->query);
 340    nouveau_object_del(&screen->fence);
 341    nouveau_object_del(&screen->ntfy);
 342
 343    nouveau_object_del(&screen->sifm);
 344    nouveau_object_del(&screen->swzsurf);
 345    nouveau_object_del(&screen->surf2d);
 346    nouveau_object_del(&screen->m2mf);
 347    nouveau_object_del(&screen->eng3d);
 348    nouveau_object_del(&screen->null);
 349
 350    nouveau_screen_fini(&screen->base);
 351    FREE(screen);
 352 }
 353
 354 #define FAIL_SCREEN_INIT(str, err)                    \
 355    do {                                               \
 356       NOUVEAU_ERR(str, err);                          \
 357       nv30_screen_destroy(pscreen);                   \
 358       return NULL;                                    \
 359    } while(0)
 360
 361 struct pipe_screen *
 362 nv30_screen_create(struct nouveau_device *dev)
 363 {
 364    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 365    struct pipe_screen *pscreen;
 366    struct nouveau_pushbuf *push;
 367    struct nv04_fifo *fifo;
 368    unsigned oclass = 0;
 369    int ret, i;
 370
 371    if (!screen)
 372       return NULL;
 373
 374    switch (dev->chipset & 0xf0) {
 375    case 0x30:
 376       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 377          oclass = NV30_3D_CLASS;
 378       else
 379       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 380          oclass = NV34_3D_CLASS;
 381       else
 382       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 383          oclass = NV35_3D_CLASS;
 384       break;
 385    case 0x40:
 386       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 387          oclass = NV40_3D_CLASS;
 388       else
 389       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 390          oclass = NV44_3D_CLASS;
 391       break;
 392    case 0x60:
 393       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 394          oclass = NV44_3D_CLASS;
 395       break;
 396    default:
 397       break;
 398    }
 399
 400    if (!oclass) {
 401       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 402       FREE(screen);
 403       return NULL;
 404    }
 405
 406    pscreen = &screen->base.base;
 407    pscreen->destroy = nv30_screen_destroy;
 408    pscreen->get_param = nv30_screen_get_param;
 409    pscreen->get_paramf = nv30_screen_get_paramf;
 410    pscreen->get_shader_param = nv30_screen_get_shader_param;
 411    pscreen->context_create = nv30_context_create;
 412    pscreen->is_format_supported = nv30_screen_is_format_supported;
 413    nv30_resource_screen_init(pscreen);
 414    nouveau_screen_init_vdec(&screen->base);
 415
 416    screen->base.fence.emit = nv30_screen_fence_emit;
 417    screen->base.fence.update = nv30_screen_fence_update;
 418
 419    ret = nouveau_screen_init(&screen->base, dev);
 420    if (ret)
 421       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 422
 423    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 424    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 425    if (oclass == NV40_3D_CLASS) {
 426       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 427       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 428    }
 429
 430    fifo = screen->base.channel->data;
 431    push = screen->base.pushbuf;
 432    push->rsvd_kick = 16;
 433
 434    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 435                             NULL, 0, &screen->null);
 436    if (ret)
 437       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 438
 439    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 440     * this means that the address pointed at by the DMA object must
 441     * be 4KiB aligned, which means this object needs to be the first
 442     * one allocated on the channel.
 443     */
 444    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 445                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 446                             .length = 32 }, sizeof(struct nv04_notify),
 447                             &screen->fence);
 448    if (ret)
 449       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 450
 451    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 452    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 453                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 454                             .length = 32 }, sizeof(struct nv04_notify),
 455                             &screen->ntfy);
 456    if (ret)
 457       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 458
 459    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 460     * the remainder of the "notifier block" assigned by the kernel for
 461     * use as query objects
 462     */
 463    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 464                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 465                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 466                             &screen->query);
 467    if (ret)
 468       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 469
 470    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 471    if (ret)
 472       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 473
 474    LIST_INITHEAD(&screen->queries);
 475
 476    /* Vertex program resources (code/data), currently 6 of the constant
 477     * slots are reserved to implement user clipping planes
 478     */
 479    if (oclass < NV40_3D_CLASS) {
 480       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 481       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 482    } else {
 483       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 484       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 485    }
 486
 487    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 488    if (ret == 0)
 489       nouveau_bo_map(screen->notify, 0, screen->base.client);
 490    if (ret)
 491       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 492
 493    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 494                             NULL, 0, &screen->eng3d);
 495    if (ret)
 496       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 497
 498    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 499    PUSH_DATA (push, screen->eng3d->handle);
 500    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 501    PUSH_DATA (push, screen->ntfy->handle);
 502    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 503    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 504    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 505    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 506    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 507    PUSH_DATA (push, fifo->vram);     /* ZETA */
 508    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 509    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 510    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 511    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 512    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 513    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 514    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 515       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 516       PUSH_DATA (push, 0x00100000);
 517       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 518       PUSH_DATA (push, 3);
 519
 520       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 521       PUSH_DATA (push, 0);
 522       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 523       PUSH_DATA (push, fui(0.0));
 524       PUSH_DATA (push, fui(0.0));
 525       PUSH_DATA (push, fui(1.0));
 526       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 527       for (i = 0; i < 16; i++)
 528          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 529
 530       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 531       PUSH_DATA (push, 0);
 532    } else {
 533       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 534       PUSH_DATA (push, fifo->vram);
 535       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 536
 537       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 538       PUSH_DATA (push, 0x00000004);
 539
 540       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 541       PUSH_DATA (push, 0x00000010);
 542       PUSH_DATA (push, 0x01000100);
 543       PUSH_DATA (push, 0xff800006);
 544
 545       /* vtxprog output routing */
 546       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 547       PUSH_DATA (push, 0x06144321);
 548       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 549       PUSH_DATA (push, 0xedcba987);
 550       PUSH_DATA (push, 0x0000006f);
 551       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 552       PUSH_DATA (push, 0x00171615);
 553       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 554       PUSH_DATA (push, 0x001b1a19);
 555
 556       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 557       PUSH_DATA (push, 0x0020ffff);
 558       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 559       PUSH_DATA (push, 0x01d300d4);
 560
 561       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 562       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 563    }
 564
 565    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 566                             NULL, 0, &screen->m2mf);
 567    if (ret)
 568       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 569
 570    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 571    PUSH_DATA (push, screen->m2mf->handle);
 572    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 573    PUSH_DATA (push, screen->ntfy->handle);
 574
 575    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 576                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 577    if (ret)
 578       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 579
 580    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 581    PUSH_DATA (push, screen->surf2d->handle);
 582    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 583    PUSH_DATA (push, screen->ntfy->handle);
 584
 585    if (dev->chipset < 0x40)
 586       oclass = NV30_SURFACE_SWZ_CLASS;
 587    else
 588       oclass = NV40_SURFACE_SWZ_CLASS;
 589
 590    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 591                             NULL, 0, &screen->swzsurf);
 592    if (ret)
 593       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 594
 595    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 596    PUSH_DATA (push, screen->swzsurf->handle);
 597    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 598    PUSH_DATA (push, screen->ntfy->handle);
 599
 600    if (dev->chipset < 0x40)
 601       oclass = NV30_SIFM_CLASS;
 602    else
 603       oclass = NV40_SIFM_CLASS;
 604
 605    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 606                             NULL, 0, &screen->sifm);
 607    if (ret)
 608       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 609
 610    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 611    PUSH_DATA (push, screen->sifm->handle);
 612    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 613    PUSH_DATA (push, screen->ntfy->handle);
 614    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 615    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 616
 617    nouveau_pushbuf_kick(push, push->channel);
 618
 619    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 620    return pscreen;
 621 }