src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    /* supported capabilities */
  66    case PIPE_CAP_TWO_SIDED_STENCIL:
  67    case PIPE_CAP_ANISOTROPIC_FILTER:
  68    case PIPE_CAP_POINT_SPRITE:
  69    case PIPE_CAP_OCCLUSION_QUERY:
  70    case PIPE_CAP_QUERY_TIME_ELAPSED:
  71    case PIPE_CAP_QUERY_TIMESTAMP:
  72    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  73    case PIPE_CAP_TEXTURE_SWIZZLE:
  74    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  75    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  77    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  78    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79    case PIPE_CAP_TGSI_TEXCOORD:
  80    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  81    case PIPE_CAP_USER_INDEX_BUFFERS:
  82    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  83       return 1;
  84    case PIPE_CAP_USER_VERTEX_BUFFERS:
  85       return 0;
  86    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  87       return 16;
  88    case PIPE_CAP_MAX_VIEWPORTS:
  89       return 1;
  90    /* nv4x capabilities */
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_CONDITIONAL_RENDER:
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_PRIMITIVE_RESTART:
  96       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  97    /* unsupported */
  98    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  99    case PIPE_CAP_SM3:
 100    case PIPE_CAP_INDEP_BLEND_ENABLE:
 101    case PIPE_CAP_INDEP_BLEND_FUNC:
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 104    case PIPE_CAP_TGSI_INSTANCEID:
 105    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 106    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 107    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 108    case PIPE_CAP_MIN_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 111    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 114    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 115    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 116    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 117    case PIPE_CAP_TEXTURE_BARRIER:
 118    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 120    case PIPE_CAP_CUBE_MAP_ARRAY:
 121    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 123    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 124    case PIPE_CAP_START_INSTANCE:
 125    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 128    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 129    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER:
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135    case PIPE_CAP_TEXTURE_GATHER_SM5:
 136    case PIPE_CAP_FAKE_SW_MSAA:
 137    case PIPE_CAP_TEXTURE_QUERY_LOD:
 138    case PIPE_CAP_SAMPLE_SHADING:
 139    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 140       return 0;
 141    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 142    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 143    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 144    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 145       return 1;
 146    case PIPE_CAP_ENDIANNESS:
 147       return PIPE_ENDIAN_LITTLE;
 148    default:
 149       debug_printf("unknown param %d\n", param);
 150       return 0;
 151    }
 152 }
 153
 154 static float
 155 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 156 {
 157    struct nv30_screen *screen = nv30_screen(pscreen);
 158    struct nouveau_object *eng3d = screen->eng3d;
 159
 160    switch (param) {
 161    case PIPE_CAPF_MAX_LINE_WIDTH:
 162    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 163       return 10.0;
 164    case PIPE_CAPF_MAX_POINT_WIDTH:
 165    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 166       return 64.0;
 167    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 168       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 169    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 170       return 15.0;
 171    default:
 172       debug_printf("unknown paramf %d\n", param);
 173       return 0;
 174    }
 175 }
 176
 177 static int
 178 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 179                              enum pipe_shader_cap param)
 180 {
 181    struct nv30_screen *screen = nv30_screen(pscreen);
 182    struct nouveau_object *eng3d = screen->eng3d;
 183
 184    switch (shader) {
 185    case PIPE_SHADER_VERTEX:
 186       switch (param) {
 187       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 188       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 189          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 190       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 191       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 192          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 193       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 194          return 0;
 195       case PIPE_SHADER_CAP_MAX_INPUTS:
 196          return 16;
 197       case PIPE_SHADER_CAP_MAX_CONSTS:
 198          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 199       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 200          return 1;
 201       case PIPE_SHADER_CAP_MAX_TEMPS:
 202          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 203       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 204       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 205          return 0;
 206       case PIPE_SHADER_CAP_MAX_ADDRS:
 207          return 2;
 208       case PIPE_SHADER_CAP_MAX_PREDS:
 209       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 210       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 211       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 212       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 213       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 214       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 215       case PIPE_SHADER_CAP_SUBROUTINES:
 216       case PIPE_SHADER_CAP_INTEGERS:
 217          return 0;
 218       default:
 219          debug_printf("unknown vertex shader param %d\n", param);
 220          return 0;
 221       }
 222       break;
 223    case PIPE_SHADER_FRAGMENT:
 224       switch (param) {
 225       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 226       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 227       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 228       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 229          return 4096;
 230       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 231          return 0;
 232       case PIPE_SHADER_CAP_MAX_INPUTS:
 233          return 8; /* should be possible to do 10 with nv4x */
 234       case PIPE_SHADER_CAP_MAX_CONSTS:
 235          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 236       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 237          return 1;
 238       case PIPE_SHADER_CAP_MAX_TEMPS:
 239          return 32;
 240       case PIPE_SHADER_CAP_MAX_ADDRS:
 241          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 242       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 243       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 244          return 16;
 245       case PIPE_SHADER_CAP_MAX_PREDS:
 246       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 247       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 248       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 249       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 250       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 251       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 252       case PIPE_SHADER_CAP_SUBROUTINES:
 253          return 0;
 254       default:
 255          debug_printf("unknown fragment shader param %d\n", param);
 256          return 0;
 257       }
 258       break;
 259    default:
 260       return 0;
 261    }
 262 }
 263
 264 static boolean
 265 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 266                                 enum pipe_format format,
 267                                 enum pipe_texture_target target,
 268                                 unsigned sample_count,
 269                                 unsigned bindings)
 270 {
 271    if (sample_count > 4)
 272       return FALSE;
 273    if (!(0x00000017 & (1 << sample_count)))
 274       return FALSE;
 275
 276    if (!util_format_is_supported(format, bindings)) {
 277       return FALSE;
 278    }
 279
 280    /* transfers & shared are always supported */
 281    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 282                  PIPE_BIND_TRANSFER_WRITE |
 283                  PIPE_BIND_SHARED);
 284
 285    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 286 }
 287
 288 static void
 289 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 290 {
 291    struct nv30_screen *screen = nv30_screen(pscreen);
 292    struct nouveau_pushbuf *push = screen->base.pushbuf;
 293
 294    *sequence = ++screen->base.fence.sequence;
 295
 296    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 297    PUSH_DATA (push, 0);
 298    PUSH_DATA (push, *sequence);
 299 }
 300
 301 static uint32_t
 302 nv30_screen_fence_update(struct pipe_screen *pscreen)
 303 {
 304    struct nv30_screen *screen = nv30_screen(pscreen);
 305    struct nv04_notify *fence = screen->fence->data;
 306    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 307 }
 308
 309 static void
 310 nv30_screen_destroy(struct pipe_screen *pscreen)
 311 {
 312    struct nv30_screen *screen = nv30_screen(pscreen);
 313
 314    if (!nouveau_drm_screen_unref(&screen->base))
 315       return;
 316
 317    if (screen->base.fence.current) {
 318       struct nouveau_fence *current = NULL;
 319
 320       /* nouveau_fence_wait will create a new current fence, so wait on the
 321        * _current_ one, and remove both.
 322        */
 323       nouveau_fence_ref(screen->base.fence.current, &current);
 324       nouveau_fence_wait(current);
 325       nouveau_fence_ref(NULL, &current);
 326       nouveau_fence_ref(NULL, &screen->base.fence.current);
 327    }
 328
 329    nouveau_object_del(&screen->query);
 330    nouveau_object_del(&screen->fence);
 331    nouveau_object_del(&screen->ntfy);
 332
 333    nouveau_object_del(&screen->sifm);
 334    nouveau_object_del(&screen->swzsurf);
 335    nouveau_object_del(&screen->surf2d);
 336    nouveau_object_del(&screen->m2mf);
 337    nouveau_object_del(&screen->eng3d);
 338    nouveau_object_del(&screen->null);
 339
 340    nouveau_screen_fini(&screen->base);
 341    FREE(screen);
 342 }
 343
 344 #define FAIL_SCREEN_INIT(str, err)                    \
 345    do {                                               \
 346       NOUVEAU_ERR(str, err);                          \
 347       nv30_screen_destroy(pscreen);                   \
 348       return NULL;                                    \
 349    } while(0)
 350
 351 struct pipe_screen *
 352 nv30_screen_create(struct nouveau_device *dev)
 353 {
 354    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 355    struct pipe_screen *pscreen;
 356    struct nouveau_pushbuf *push;
 357    struct nv04_fifo *fifo;
 358    unsigned oclass = 0;
 359    int ret, i;
 360
 361    if (!screen)
 362       return NULL;
 363
 364    switch (dev->chipset & 0xf0) {
 365    case 0x30:
 366       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 367          oclass = NV30_3D_CLASS;
 368       else
 369       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 370          oclass = NV34_3D_CLASS;
 371       else
 372       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 373          oclass = NV35_3D_CLASS;
 374       break;
 375    case 0x40:
 376       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 377          oclass = NV40_3D_CLASS;
 378       else
 379       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 380          oclass = NV44_3D_CLASS;
 381       break;
 382    case 0x60:
 383       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 384          oclass = NV44_3D_CLASS;
 385       break;
 386    default:
 387       break;
 388    }
 389
 390    if (!oclass) {
 391       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 392       FREE(screen);
 393       return NULL;
 394    }
 395
 396    pscreen = &screen->base.base;
 397    pscreen->destroy = nv30_screen_destroy;
 398    pscreen->get_param = nv30_screen_get_param;
 399    pscreen->get_paramf = nv30_screen_get_paramf;
 400    pscreen->get_shader_param = nv30_screen_get_shader_param;
 401    pscreen->context_create = nv30_context_create;
 402    pscreen->is_format_supported = nv30_screen_is_format_supported;
 403    nv30_resource_screen_init(pscreen);
 404    nouveau_screen_init_vdec(&screen->base);
 405
 406    screen->base.fence.emit = nv30_screen_fence_emit;
 407    screen->base.fence.update = nv30_screen_fence_update;
 408
 409    ret = nouveau_screen_init(&screen->base, dev);
 410    if (ret)
 411       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 412
 413    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 414    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 415    if (oclass == NV40_3D_CLASS) {
 416       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 417       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 418    }
 419
 420    fifo = screen->base.channel->data;
 421    push = screen->base.pushbuf;
 422    push->rsvd_kick = 16;
 423
 424    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 425                             NULL, 0, &screen->null);
 426    if (ret)
 427       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 428
 429    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 430     * this means that the address pointed at by the DMA object must
 431     * be 4KiB aligned, which means this object needs to be the first
 432     * one allocated on the channel.
 433     */
 434    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 435                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 436                             .length = 32 }, sizeof(struct nv04_notify),
 437                             &screen->fence);
 438    if (ret)
 439       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 440
 441    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 442    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 443                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 444                             .length = 32 }, sizeof(struct nv04_notify),
 445                             &screen->ntfy);
 446    if (ret)
 447       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 448
 449    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 450     * the remainder of the "notifier block" assigned by the kernel for
 451     * use as query objects
 452     */
 453    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 454                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 455                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 456                             &screen->query);
 457    if (ret)
 458       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 459
 460    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 461    if (ret)
 462       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 463
 464    LIST_INITHEAD(&screen->queries);
 465
 466    /* Vertex program resources (code/data), currently 6 of the constant
 467     * slots are reserved to implement user clipping planes
 468     */
 469    if (oclass < NV40_3D_CLASS) {
 470       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 471       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 472    } else {
 473       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 474       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 475    }
 476
 477    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 478    if (ret == 0)
 479       nouveau_bo_map(screen->notify, 0, screen->base.client);
 480    if (ret)
 481       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 482
 483    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 484                             NULL, 0, &screen->eng3d);
 485    if (ret)
 486       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 487
 488    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 489    PUSH_DATA (push, screen->eng3d->handle);
 490    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 491    PUSH_DATA (push, screen->ntfy->handle);
 492    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 493    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 494    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 495    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 496    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 497    PUSH_DATA (push, fifo->vram);     /* ZETA */
 498    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 499    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 500    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 501    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 502    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 503    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 504    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 505       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 506       PUSH_DATA (push, 0x00100000);
 507       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 508       PUSH_DATA (push, 3);
 509
 510       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 511       PUSH_DATA (push, 0);
 512       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 513       PUSH_DATA (push, fui(0.0));
 514       PUSH_DATA (push, fui(0.0));
 515       PUSH_DATA (push, fui(1.0));
 516       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 517       for (i = 0; i < 16; i++)
 518          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 519
 520       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 521       PUSH_DATA (push, 0);
 522    } else {
 523       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 524       PUSH_DATA (push, fifo->vram);
 525       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 526
 527       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 528       PUSH_DATA (push, 0x00000004);
 529
 530       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 531       PUSH_DATA (push, 0x00000010);
 532       PUSH_DATA (push, 0x01000100);
 533       PUSH_DATA (push, 0xff800006);
 534
 535       /* vtxprog output routing */
 536       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 537       PUSH_DATA (push, 0x06144321);
 538       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 539       PUSH_DATA (push, 0xedcba987);
 540       PUSH_DATA (push, 0x0000006f);
 541       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 542       PUSH_DATA (push, 0x00171615);
 543       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 544       PUSH_DATA (push, 0x001b1a19);
 545
 546       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 547       PUSH_DATA (push, 0x0020ffff);
 548       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 549       PUSH_DATA (push, 0x01d300d4);
 550
 551       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 552       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 553    }
 554
 555    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 556                             NULL, 0, &screen->m2mf);
 557    if (ret)
 558       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 559
 560    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 561    PUSH_DATA (push, screen->m2mf->handle);
 562    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 563    PUSH_DATA (push, screen->ntfy->handle);
 564
 565    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 566                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 567    if (ret)
 568       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 569
 570    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 571    PUSH_DATA (push, screen->surf2d->handle);
 572    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 573    PUSH_DATA (push, screen->ntfy->handle);
 574
 575    if (dev->chipset < 0x40)
 576       oclass = NV30_SURFACE_SWZ_CLASS;
 577    else
 578       oclass = NV40_SURFACE_SWZ_CLASS;
 579
 580    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 581                             NULL, 0, &screen->swzsurf);
 582    if (ret)
 583       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 584
 585    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 586    PUSH_DATA (push, screen->swzsurf->handle);
 587    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 588    PUSH_DATA (push, screen->ntfy->handle);
 589
 590    if (dev->chipset < 0x40)
 591       oclass = NV30_SIFM_CLASS;
 592    else
 593       oclass = NV40_SIFM_CLASS;
 594
 595    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 596                             NULL, 0, &screen->sifm);
 597    if (ret)
 598       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 599
 600    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 601    PUSH_DATA (push, screen->sifm->handle);
 602    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 603    PUSH_DATA (push, screen->ntfy->handle);
 604    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 605    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 606
 607    nouveau_pushbuf_kick(push, push->channel);
 608
 609    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 610    return pscreen;
 611 }