src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  95    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  99    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 123    case PIPE_CAP_MIN_TEXEL_OFFSET:
 124    case PIPE_CAP_MAX_TEXEL_OFFSET:
 125    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 129    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 130    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 131    case PIPE_CAP_MAX_VERTEX_STREAMS:
 132    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 133    case PIPE_CAP_TEXTURE_BARRIER:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 136    case PIPE_CAP_CUBE_MAP_ARRAY:
 137    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 138    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 139    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 140    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 141    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 142    case PIPE_CAP_START_INSTANCE:
 143    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 147    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 148    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 151    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 152    case PIPE_CAP_TEXTURE_GATHER_SM5:
 153    case PIPE_CAP_FAKE_SW_MSAA:
 154    case PIPE_CAP_TEXTURE_QUERY_LOD:
 155    case PIPE_CAP_SAMPLE_SHADING:
 156    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 157    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 158    case PIPE_CAP_USER_VERTEX_BUFFERS:
 159    case PIPE_CAP_COMPUTE:
 160    case PIPE_CAP_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 162    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 163    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 164    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 165    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 166    case PIPE_CAP_CLIP_HALFZ:
 167    case PIPE_CAP_VERTEXID_NOBASE:
 168    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 169    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 170    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 171    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 172    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 173    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 174    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 175    case PIPE_CAP_TGSI_TXQS:
 176    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 177    case PIPE_CAP_SHAREABLE_SHADERS:
 178    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 179    case PIPE_CAP_CLEAR_TEXTURE:
 180    case PIPE_CAP_DRAW_PARAMETERS:
 181    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 182    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 183    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 184    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 185    case PIPE_CAP_INVALIDATE_BUFFER:
 186    case PIPE_CAP_GENERATE_MIPMAP:
 187    case PIPE_CAP_STRING_MARKER:
 188    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 189    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 190    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 191    case PIPE_CAP_QUERY_MEMORY_INFO:
 192    case PIPE_CAP_PCI_GROUP:
 193    case PIPE_CAP_PCI_BUS:
 194    case PIPE_CAP_PCI_DEVICE:
 195    case PIPE_CAP_PCI_FUNCTION:
 196    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 197    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 200    case PIPE_CAP_TGSI_VOTE:
 201    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 202    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 203    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 204    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 205    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 206    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 207    case PIPE_CAP_NATIVE_FENCE_FD:
 208    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 209    case PIPE_CAP_TGSI_FS_FBFETCH:
 210    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 211    case PIPE_CAP_DOUBLES:
 212    case PIPE_CAP_INT64:
 213    case PIPE_CAP_INT64_DIVMOD:
 214    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 215    case PIPE_CAP_TGSI_CLOCK:
 216    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 217    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 218    case PIPE_CAP_TGSI_BALLOT:
 219    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 220    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 221    case PIPE_CAP_POST_DEPTH_COVERAGE:
 222    case PIPE_CAP_BINDLESS_TEXTURE:
 223    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 224    case PIPE_CAP_QUERY_SO_OVERFLOW:
 225    case PIPE_CAP_MEMOBJ:
 226    case PIPE_CAP_LOAD_CONSTBUF:
 227    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 228    case PIPE_CAP_TILE_RASTER_ORDER:
 229    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 230    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 231       return 0;
 232
 233    case PIPE_CAP_VENDOR_ID:
 234       return 0x10de;
 235    case PIPE_CAP_DEVICE_ID: {
 236       uint64_t device_id;
 237       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 238          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 239          return -1;
 240       }
 241       return device_id;
 242    }
 243    case PIPE_CAP_ACCELERATED:
 244       return 1;
 245    case PIPE_CAP_VIDEO_MEMORY:
 246       return dev->vram_size >> 20;
 247    case PIPE_CAP_UMA:
 248       return 0;
 249    }
 250
 251    debug_printf("unknown param %d\n", param);
 252    return 0;
 253 }
 254
 255 static float
 256 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 257 {
 258    struct nv30_screen *screen = nv30_screen(pscreen);
 259    struct nouveau_object *eng3d = screen->eng3d;
 260
 261    switch (param) {
 262    case PIPE_CAPF_MAX_LINE_WIDTH:
 263    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 264       return 10.0;
 265    case PIPE_CAPF_MAX_POINT_WIDTH:
 266    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 267       return 64.0;
 268    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 269       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 270    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 271       return 15.0;
 272    default:
 273       debug_printf("unknown paramf %d\n", param);
 274       return 0;
 275    }
 276 }
 277
 278 static int
 279 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 280                              enum pipe_shader_type shader,
 281                              enum pipe_shader_cap param)
 282 {
 283    struct nv30_screen *screen = nv30_screen(pscreen);
 284    struct nouveau_object *eng3d = screen->eng3d;
 285
 286    switch (shader) {
 287    case PIPE_SHADER_VERTEX:
 288       switch (param) {
 289       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 290       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 291          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 292       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 293       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 294          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 295       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 296          return 0;
 297       case PIPE_SHADER_CAP_MAX_INPUTS:
 298       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 299          return 16;
 300       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 301          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 302       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 303          return 1;
 304       case PIPE_SHADER_CAP_MAX_TEMPS:
 305          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 306       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 307          return 32;
 308       case PIPE_SHADER_CAP_PREFERRED_IR:
 309          return PIPE_SHADER_IR_TGSI;
 310       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 311       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 312          return 0;
 313       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 314       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 315       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 316       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 317       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 318       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 319       case PIPE_SHADER_CAP_SUBROUTINES:
 320       case PIPE_SHADER_CAP_INTEGERS:
 321       case PIPE_SHADER_CAP_INT64_ATOMICS:
 322       case PIPE_SHADER_CAP_FP16:
 323       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 324       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 325       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 326       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 327       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 328       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 329       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 330       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 331       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 332          return 0;
 333       default:
 334          debug_printf("unknown vertex shader param %d\n", param);
 335          return 0;
 336       }
 337       break;
 338    case PIPE_SHADER_FRAGMENT:
 339       switch (param) {
 340       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 341       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 342       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 343       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 344          return 4096;
 345       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 346          return 0;
 347       case PIPE_SHADER_CAP_MAX_INPUTS:
 348          return 8; /* should be possible to do 10 with nv4x */
 349       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 350          return 4;
 351       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 352          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 353       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 354          return 1;
 355       case PIPE_SHADER_CAP_MAX_TEMPS:
 356          return 32;
 357       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 358       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 359          return 16;
 360       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 361          return 32;
 362       case PIPE_SHADER_CAP_PREFERRED_IR:
 363          return PIPE_SHADER_IR_TGSI;
 364       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 365       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 366       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 367       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 368       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 369       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 370       case PIPE_SHADER_CAP_SUBROUTINES:
 371       case PIPE_SHADER_CAP_INTEGERS:
 372       case PIPE_SHADER_CAP_FP16:
 373       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 374       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 375       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 376       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 377       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 378       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 379       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 380       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 381       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 382          return 0;
 383       default:
 384          debug_printf("unknown fragment shader param %d\n", param);
 385          return 0;
 386       }
 387       break;
 388    default:
 389       return 0;
 390    }
 391 }
 392
 393 static boolean
 394 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 395                                 enum pipe_format format,
 396                                 enum pipe_texture_target target,
 397                                 unsigned sample_count,
 398                                 unsigned bindings)
 399 {
 400    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 401       return false;
 402
 403    if (!(0x00000017 & (1 << sample_count)))
 404       return false;
 405
 406    if (!util_format_is_supported(format, bindings)) {
 407       return false;
 408    }
 409
 410    /* shared is always supported */
 411    bindings &= ~PIPE_BIND_SHARED;
 412
 413    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 414 }
 415
 416 static void
 417 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 418 {
 419    struct nv30_screen *screen = nv30_screen(pscreen);
 420    struct nouveau_pushbuf *push = screen->base.pushbuf;
 421
 422    *sequence = ++screen->base.fence.sequence;
 423
 424    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 425    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 426               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 427    PUSH_DATA (push, 0);
 428    PUSH_DATA (push, *sequence);
 429 }
 430
 431 static uint32_t
 432 nv30_screen_fence_update(struct pipe_screen *pscreen)
 433 {
 434    struct nv30_screen *screen = nv30_screen(pscreen);
 435    struct nv04_notify *fence = screen->fence->data;
 436    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 437 }
 438
 439 static void
 440 nv30_screen_destroy(struct pipe_screen *pscreen)
 441 {
 442    struct nv30_screen *screen = nv30_screen(pscreen);
 443
 444    if (!nouveau_drm_screen_unref(&screen->base))
 445       return;
 446
 447    if (screen->base.fence.current) {
 448       struct nouveau_fence *current = NULL;
 449
 450       /* nouveau_fence_wait will create a new current fence, so wait on the
 451        * _current_ one, and remove both.
 452        */
 453       nouveau_fence_ref(screen->base.fence.current, &current);
 454       nouveau_fence_wait(current, NULL);
 455       nouveau_fence_ref(NULL, &current);
 456       nouveau_fence_ref(NULL, &screen->base.fence.current);
 457    }
 458
 459    nouveau_bo_ref(NULL, &screen->notify);
 460
 461    nouveau_heap_destroy(&screen->query_heap);
 462    nouveau_heap_destroy(&screen->vp_exec_heap);
 463    nouveau_heap_destroy(&screen->vp_data_heap);
 464
 465    nouveau_object_del(&screen->query);
 466    nouveau_object_del(&screen->fence);
 467    nouveau_object_del(&screen->ntfy);
 468
 469    nouveau_object_del(&screen->sifm);
 470    nouveau_object_del(&screen->swzsurf);
 471    nouveau_object_del(&screen->surf2d);
 472    nouveau_object_del(&screen->m2mf);
 473    nouveau_object_del(&screen->eng3d);
 474    nouveau_object_del(&screen->null);
 475
 476    nouveau_screen_fini(&screen->base);
 477    FREE(screen);
 478 }
 479
 480 #define FAIL_SCREEN_INIT(str, err)                    \
 481    do {                                               \
 482       NOUVEAU_ERR(str, err);                          \
 483       screen->base.base.context_create = NULL;        \
 484       return &screen->base;                           \
 485    } while(0)
 486
 487 struct nouveau_screen *
 488 nv30_screen_create(struct nouveau_device *dev)
 489 {
 490    struct nv30_screen *screen;
 491    struct pipe_screen *pscreen;
 492    struct nouveau_pushbuf *push;
 493    struct nv04_fifo *fifo;
 494    unsigned oclass = 0;
 495    int ret, i;
 496
 497    switch (dev->chipset & 0xf0) {
 498    case 0x30:
 499       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 500          oclass = NV30_3D_CLASS;
 501       else
 502       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 503          oclass = NV34_3D_CLASS;
 504       else
 505       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 506          oclass = NV35_3D_CLASS;
 507       break;
 508    case 0x40:
 509       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 510          oclass = NV40_3D_CLASS;
 511       else
 512       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 513          oclass = NV44_3D_CLASS;
 514       break;
 515    case 0x60:
 516       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 517          oclass = NV44_3D_CLASS;
 518       break;
 519    default:
 520       break;
 521    }
 522
 523    if (!oclass) {
 524       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 525       return NULL;
 526    }
 527
 528    screen = CALLOC_STRUCT(nv30_screen);
 529    if (!screen)
 530       return NULL;
 531
 532    pscreen = &screen->base.base;
 533    pscreen->destroy = nv30_screen_destroy;
 534
 535    /*
 536     * Some modern apps try to use msaa without keeping in mind the
 537     * restrictions on videomem of older cards. Resulting in dmesg saying:
 538     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 539     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 540     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 541     *
 542     * Because we are running out of video memory, after which the program
 543     * using the msaa visual freezes, and eventually the entire system freezes.
 544     *
 545     * To work around this we do not allow msaa visauls by default and allow
 546     * the user to override this via NV30_MAX_MSAA.
 547     */
 548    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 549    if (screen->max_sample_count > 4)
 550       screen->max_sample_count = 4;
 551
 552    pscreen->get_param = nv30_screen_get_param;
 553    pscreen->get_paramf = nv30_screen_get_paramf;
 554    pscreen->get_shader_param = nv30_screen_get_shader_param;
 555    pscreen->context_create = nv30_context_create;
 556    pscreen->is_format_supported = nv30_screen_is_format_supported;
 557    nv30_resource_screen_init(pscreen);
 558    nouveau_screen_init_vdec(&screen->base);
 559
 560    screen->base.fence.emit = nv30_screen_fence_emit;
 561    screen->base.fence.update = nv30_screen_fence_update;
 562
 563    ret = nouveau_screen_init(&screen->base, dev);
 564    if (ret)
 565       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 566
 567    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 568    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 569    if (oclass == NV40_3D_CLASS) {
 570       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 571       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 572    }
 573
 574    fifo = screen->base.channel->data;
 575    push = screen->base.pushbuf;
 576    push->rsvd_kick = 16;
 577
 578    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 579                             NULL, 0, &screen->null);
 580    if (ret)
 581       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 582
 583    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 584     * this means that the address pointed at by the DMA object must
 585     * be 4KiB aligned, which means this object needs to be the first
 586     * one allocated on the channel.
 587     */
 588    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 589                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 590                             .length = 32 }, sizeof(struct nv04_notify),
 591                             &screen->fence);
 592    if (ret)
 593       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 594
 595    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 596    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 597                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 598                             .length = 32 }, sizeof(struct nv04_notify),
 599                             &screen->ntfy);
 600    if (ret)
 601       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 602
 603    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 604     * the remainder of the "notifier block" assigned by the kernel for
 605     * use as query objects
 606     */
 607    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 608                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 609                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 610                             &screen->query);
 611    if (ret)
 612       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 613
 614    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 615    if (ret)
 616       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 617
 618    LIST_INITHEAD(&screen->queries);
 619
 620    /* Vertex program resources (code/data), currently 6 of the constant
 621     * slots are reserved to implement user clipping planes
 622     */
 623    if (oclass < NV40_3D_CLASS) {
 624       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 625       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 626    } else {
 627       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 628       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 629    }
 630
 631    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 632    if (ret == 0)
 633       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 634    if (ret)
 635       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 636
 637    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 638                             NULL, 0, &screen->eng3d);
 639    if (ret)
 640       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 641
 642    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 643    PUSH_DATA (push, screen->eng3d->handle);
 644    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 645    PUSH_DATA (push, screen->ntfy->handle);
 646    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 647    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 648    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 649    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 650    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 651    PUSH_DATA (push, fifo->vram);     /* ZETA */
 652    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 653    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 654    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 655    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 656    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 657    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 658    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 659       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 660       PUSH_DATA (push, 0x00100000);
 661       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 662       PUSH_DATA (push, 3);
 663
 664       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 665       PUSH_DATA (push, 0);
 666       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 667       PUSH_DATA (push, fui(0.0));
 668       PUSH_DATA (push, fui(0.0));
 669       PUSH_DATA (push, fui(1.0));
 670       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 671       for (i = 0; i < 16; i++)
 672          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 673
 674       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 675       PUSH_DATA (push, 0);
 676    } else {
 677       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 678       PUSH_DATA (push, fifo->vram);
 679       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 680
 681       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 682       PUSH_DATA (push, 0x00000004);
 683
 684       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 685       PUSH_DATA (push, 0x00000010);
 686       PUSH_DATA (push, 0x01000100);
 687       PUSH_DATA (push, 0xff800006);
 688
 689       /* vtxprog output routing */
 690       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 691       PUSH_DATA (push, 0x06144321);
 692       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 693       PUSH_DATA (push, 0xedcba987);
 694       PUSH_DATA (push, 0x0000006f);
 695       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 696       PUSH_DATA (push, 0x00171615);
 697       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 698       PUSH_DATA (push, 0x001b1a19);
 699
 700       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 701       PUSH_DATA (push, 0x0020ffff);
 702       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 703       PUSH_DATA (push, 0x01d300d4);
 704
 705       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 706       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 707    }
 708
 709    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 710                             NULL, 0, &screen->m2mf);
 711    if (ret)
 712       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 713
 714    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 715    PUSH_DATA (push, screen->m2mf->handle);
 716    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 717    PUSH_DATA (push, screen->ntfy->handle);
 718
 719    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 720                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 721    if (ret)
 722       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 723
 724    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 725    PUSH_DATA (push, screen->surf2d->handle);
 726    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 727    PUSH_DATA (push, screen->ntfy->handle);
 728
 729    if (dev->chipset < 0x40)
 730       oclass = NV30_SURFACE_SWZ_CLASS;
 731    else
 732       oclass = NV40_SURFACE_SWZ_CLASS;
 733
 734    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 735                             NULL, 0, &screen->swzsurf);
 736    if (ret)
 737       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 738
 739    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 740    PUSH_DATA (push, screen->swzsurf->handle);
 741    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 742    PUSH_DATA (push, screen->ntfy->handle);
 743
 744    if (dev->chipset < 0x40)
 745       oclass = NV30_SIFM_CLASS;
 746    else
 747       oclass = NV40_SIFM_CLASS;
 748
 749    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 750                             NULL, 0, &screen->sifm);
 751    if (ret)
 752       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 753
 754    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 755    PUSH_DATA (push, screen->sifm->handle);
 756    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 757    PUSH_DATA (push, screen->ntfy->handle);
 758    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 759    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 760
 761    nouveau_pushbuf_kick(push, push->channel);
 762
 763    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 764    return &screen->base;
 765 }