src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_USER_INDEX_BUFFERS:
  95    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  99    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 162    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 163    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_CLIP_HALFZ:
 166    case PIPE_CAP_VERTEXID_NOBASE:
 167    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_TGSI_TXQS:
 175    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 176    case PIPE_CAP_SHAREABLE_SHADERS:
 177    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 178    case PIPE_CAP_CLEAR_TEXTURE:
 179    case PIPE_CAP_DRAW_PARAMETERS:
 180    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 181    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 182    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 183    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184    case PIPE_CAP_INVALIDATE_BUFFER:
 185    case PIPE_CAP_GENERATE_MIPMAP:
 186    case PIPE_CAP_STRING_MARKER:
 187    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 188    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 189    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 190    case PIPE_CAP_QUERY_MEMORY_INFO:
 191    case PIPE_CAP_PCI_GROUP:
 192    case PIPE_CAP_PCI_BUS:
 193    case PIPE_CAP_PCI_DEVICE:
 194    case PIPE_CAP_PCI_FUNCTION:
 195    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 196    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 197    case PIPE_CAP_CULL_DISTANCE:
 198    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 199    case PIPE_CAP_TGSI_VOTE:
 200    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 201    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 202    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 203    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 204       return 0;
 205
 206    case PIPE_CAP_VENDOR_ID:
 207       return 0x10de;
 208    case PIPE_CAP_DEVICE_ID: {
 209       uint64_t device_id;
 210       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 211          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 212          return -1;
 213       }
 214       return device_id;
 215    }
 216    case PIPE_CAP_ACCELERATED:
 217       return 1;
 218    case PIPE_CAP_VIDEO_MEMORY:
 219       return dev->vram_size >> 20;
 220    case PIPE_CAP_UMA:
 221       return 0;
 222    }
 223
 224    debug_printf("unknown param %d\n", param);
 225    return 0;
 226 }
 227
 228 static float
 229 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 230 {
 231    struct nv30_screen *screen = nv30_screen(pscreen);
 232    struct nouveau_object *eng3d = screen->eng3d;
 233
 234    switch (param) {
 235    case PIPE_CAPF_MAX_LINE_WIDTH:
 236    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 237       return 10.0;
 238    case PIPE_CAPF_MAX_POINT_WIDTH:
 239    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 240       return 64.0;
 241    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 242       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 243    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 244       return 15.0;
 245    default:
 246       debug_printf("unknown paramf %d\n", param);
 247       return 0;
 248    }
 249 }
 250
 251 static int
 252 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 253                              enum pipe_shader_cap param)
 254 {
 255    struct nv30_screen *screen = nv30_screen(pscreen);
 256    struct nouveau_object *eng3d = screen->eng3d;
 257
 258    switch (shader) {
 259    case PIPE_SHADER_VERTEX:
 260       switch (param) {
 261       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 262       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 263          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 264       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 265       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 266          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 267       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 268          return 0;
 269       case PIPE_SHADER_CAP_MAX_INPUTS:
 270       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 271          return 16;
 272       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 273          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 274       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 275          return 1;
 276       case PIPE_SHADER_CAP_MAX_TEMPS:
 277          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 278       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 279          return 32;
 280       case PIPE_SHADER_CAP_PREFERRED_IR:
 281          return PIPE_SHADER_IR_TGSI;
 282       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 283       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 284          return 0;
 285       case PIPE_SHADER_CAP_MAX_PREDS:
 286       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 287       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 288       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 289       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 290       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 291       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 292       case PIPE_SHADER_CAP_SUBROUTINES:
 293       case PIPE_SHADER_CAP_INTEGERS:
 294       case PIPE_SHADER_CAP_DOUBLES:
 295       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 296       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 297       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 298       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 299       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 300       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 301          return 0;
 302       default:
 303          debug_printf("unknown vertex shader param %d\n", param);
 304          return 0;
 305       }
 306       break;
 307    case PIPE_SHADER_FRAGMENT:
 308       switch (param) {
 309       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 310       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 311       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 312       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 313          return 4096;
 314       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 315          return 0;
 316       case PIPE_SHADER_CAP_MAX_INPUTS:
 317          return 8; /* should be possible to do 10 with nv4x */
 318       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 319          return 4;
 320       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 321          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 322       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 323          return 1;
 324       case PIPE_SHADER_CAP_MAX_TEMPS:
 325          return 32;
 326       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 327       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 328          return 16;
 329       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 330          return 32;
 331       case PIPE_SHADER_CAP_PREFERRED_IR:
 332          return PIPE_SHADER_IR_TGSI;
 333       case PIPE_SHADER_CAP_MAX_PREDS:
 334       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 335       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 336       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 337       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 338       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 339       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 340       case PIPE_SHADER_CAP_SUBROUTINES:
 341       case PIPE_SHADER_CAP_INTEGERS:
 342       case PIPE_SHADER_CAP_DOUBLES:
 343       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 344       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 345       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 346       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 347       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 348       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 349          return 0;
 350       default:
 351          debug_printf("unknown fragment shader param %d\n", param);
 352          return 0;
 353       }
 354       break;
 355    default:
 356       return 0;
 357    }
 358 }
 359
 360 static boolean
 361 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 362                                 enum pipe_format format,
 363                                 enum pipe_texture_target target,
 364                                 unsigned sample_count,
 365                                 unsigned bindings)
 366 {
 367    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 368       return false;
 369
 370    if (!(0x00000017 & (1 << sample_count)))
 371       return false;
 372
 373    if (!util_format_is_supported(format, bindings)) {
 374       return false;
 375    }
 376
 377    /* transfers & shared are always supported */
 378    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 379                  PIPE_BIND_TRANSFER_WRITE |
 380                  PIPE_BIND_SHARED);
 381
 382    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 383 }
 384
 385 static void
 386 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 387 {
 388    struct nv30_screen *screen = nv30_screen(pscreen);
 389    struct nouveau_pushbuf *push = screen->base.pushbuf;
 390
 391    *sequence = ++screen->base.fence.sequence;
 392
 393    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 394    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 395               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 396    PUSH_DATA (push, 0);
 397    PUSH_DATA (push, *sequence);
 398 }
 399
 400 static uint32_t
 401 nv30_screen_fence_update(struct pipe_screen *pscreen)
 402 {
 403    struct nv30_screen *screen = nv30_screen(pscreen);
 404    struct nv04_notify *fence = screen->fence->data;
 405    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 406 }
 407
 408 static void
 409 nv30_screen_destroy(struct pipe_screen *pscreen)
 410 {
 411    struct nv30_screen *screen = nv30_screen(pscreen);
 412
 413    if (!nouveau_drm_screen_unref(&screen->base))
 414       return;
 415
 416    if (screen->base.fence.current) {
 417       struct nouveau_fence *current = NULL;
 418
 419       /* nouveau_fence_wait will create a new current fence, so wait on the
 420        * _current_ one, and remove both.
 421        */
 422       nouveau_fence_ref(screen->base.fence.current, &current);
 423       nouveau_fence_wait(current, NULL);
 424       nouveau_fence_ref(NULL, &current);
 425       nouveau_fence_ref(NULL, &screen->base.fence.current);
 426    }
 427
 428    nouveau_bo_ref(NULL, &screen->notify);
 429
 430    nouveau_heap_destroy(&screen->query_heap);
 431    nouveau_heap_destroy(&screen->vp_exec_heap);
 432    nouveau_heap_destroy(&screen->vp_data_heap);
 433
 434    nouveau_object_del(&screen->query);
 435    nouveau_object_del(&screen->fence);
 436    nouveau_object_del(&screen->ntfy);
 437
 438    nouveau_object_del(&screen->sifm);
 439    nouveau_object_del(&screen->swzsurf);
 440    nouveau_object_del(&screen->surf2d);
 441    nouveau_object_del(&screen->m2mf);
 442    nouveau_object_del(&screen->eng3d);
 443    nouveau_object_del(&screen->null);
 444
 445    nouveau_screen_fini(&screen->base);
 446    FREE(screen);
 447 }
 448
 449 #define FAIL_SCREEN_INIT(str, err)                    \
 450    do {                                               \
 451       NOUVEAU_ERR(str, err);                          \
 452       screen->base.base.context_create = NULL;        \
 453       return &screen->base;                           \
 454    } while(0)
 455
 456 struct nouveau_screen *
 457 nv30_screen_create(struct nouveau_device *dev)
 458 {
 459    struct nv30_screen *screen;
 460    struct pipe_screen *pscreen;
 461    struct nouveau_pushbuf *push;
 462    struct nv04_fifo *fifo;
 463    unsigned oclass = 0;
 464    int ret, i;
 465
 466    switch (dev->chipset & 0xf0) {
 467    case 0x30:
 468       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 469          oclass = NV30_3D_CLASS;
 470       else
 471       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 472          oclass = NV34_3D_CLASS;
 473       else
 474       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 475          oclass = NV35_3D_CLASS;
 476       break;
 477    case 0x40:
 478       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 479          oclass = NV40_3D_CLASS;
 480       else
 481       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 482          oclass = NV44_3D_CLASS;
 483       break;
 484    case 0x60:
 485       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 486          oclass = NV44_3D_CLASS;
 487       break;
 488    default:
 489       break;
 490    }
 491
 492    if (!oclass) {
 493       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 494       return NULL;
 495    }
 496
 497    screen = CALLOC_STRUCT(nv30_screen);
 498    if (!screen)
 499       return NULL;
 500
 501    pscreen = &screen->base.base;
 502    pscreen->destroy = nv30_screen_destroy;
 503
 504    /*
 505     * Some modern apps try to use msaa without keeping in mind the
 506     * restrictions on videomem of older cards. Resulting in dmesg saying:
 507     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 508     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 509     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 510     *
 511     * Because we are running out of video memory, after which the program
 512     * using the msaa visual freezes, and eventually the entire system freezes.
 513     *
 514     * To work around this we do not allow msaa visauls by default and allow
 515     * the user to override this via NV30_MAX_MSAA.
 516     */
 517    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 518    if (screen->max_sample_count > 4)
 519       screen->max_sample_count = 4;
 520
 521    pscreen->get_param = nv30_screen_get_param;
 522    pscreen->get_paramf = nv30_screen_get_paramf;
 523    pscreen->get_shader_param = nv30_screen_get_shader_param;
 524    pscreen->context_create = nv30_context_create;
 525    pscreen->is_format_supported = nv30_screen_is_format_supported;
 526    nv30_resource_screen_init(pscreen);
 527    nouveau_screen_init_vdec(&screen->base);
 528
 529    screen->base.fence.emit = nv30_screen_fence_emit;
 530    screen->base.fence.update = nv30_screen_fence_update;
 531
 532    ret = nouveau_screen_init(&screen->base, dev);
 533    if (ret)
 534       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 535
 536    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 537    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 538    if (oclass == NV40_3D_CLASS) {
 539       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 540       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 541    }
 542
 543    fifo = screen->base.channel->data;
 544    push = screen->base.pushbuf;
 545    push->rsvd_kick = 16;
 546
 547    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 548                             NULL, 0, &screen->null);
 549    if (ret)
 550       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 551
 552    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 553     * this means that the address pointed at by the DMA object must
 554     * be 4KiB aligned, which means this object needs to be the first
 555     * one allocated on the channel.
 556     */
 557    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 558                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 559                             .length = 32 }, sizeof(struct nv04_notify),
 560                             &screen->fence);
 561    if (ret)
 562       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 563
 564    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 565    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 566                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 567                             .length = 32 }, sizeof(struct nv04_notify),
 568                             &screen->ntfy);
 569    if (ret)
 570       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 571
 572    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 573     * the remainder of the "notifier block" assigned by the kernel for
 574     * use as query objects
 575     */
 576    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 577                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 578                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 579                             &screen->query);
 580    if (ret)
 581       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 582
 583    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 584    if (ret)
 585       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 586
 587    LIST_INITHEAD(&screen->queries);
 588
 589    /* Vertex program resources (code/data), currently 6 of the constant
 590     * slots are reserved to implement user clipping planes
 591     */
 592    if (oclass < NV40_3D_CLASS) {
 593       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 594       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 595    } else {
 596       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 597       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 598    }
 599
 600    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 601    if (ret == 0)
 602       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 603    if (ret)
 604       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 605
 606    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 607                             NULL, 0, &screen->eng3d);
 608    if (ret)
 609       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 610
 611    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 612    PUSH_DATA (push, screen->eng3d->handle);
 613    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 614    PUSH_DATA (push, screen->ntfy->handle);
 615    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 616    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 617    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 618    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 619    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 620    PUSH_DATA (push, fifo->vram);     /* ZETA */
 621    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 622    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 623    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 624    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 625    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 626    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 627    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 628       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 629       PUSH_DATA (push, 0x00100000);
 630       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 631       PUSH_DATA (push, 3);
 632
 633       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 634       PUSH_DATA (push, 0);
 635       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 636       PUSH_DATA (push, fui(0.0));
 637       PUSH_DATA (push, fui(0.0));
 638       PUSH_DATA (push, fui(1.0));
 639       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 640       for (i = 0; i < 16; i++)
 641          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 642
 643       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 644       PUSH_DATA (push, 0);
 645    } else {
 646       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 647       PUSH_DATA (push, fifo->vram);
 648       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 649
 650       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 651       PUSH_DATA (push, 0x00000004);
 652
 653       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 654       PUSH_DATA (push, 0x00000010);
 655       PUSH_DATA (push, 0x01000100);
 656       PUSH_DATA (push, 0xff800006);
 657
 658       /* vtxprog output routing */
 659       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 660       PUSH_DATA (push, 0x06144321);
 661       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 662       PUSH_DATA (push, 0xedcba987);
 663       PUSH_DATA (push, 0x0000006f);
 664       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 665       PUSH_DATA (push, 0x00171615);
 666       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 667       PUSH_DATA (push, 0x001b1a19);
 668
 669       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 670       PUSH_DATA (push, 0x0020ffff);
 671       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 672       PUSH_DATA (push, 0x01d300d4);
 673
 674       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 675       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 676    }
 677
 678    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 679                             NULL, 0, &screen->m2mf);
 680    if (ret)
 681       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 682
 683    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 684    PUSH_DATA (push, screen->m2mf->handle);
 685    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 686    PUSH_DATA (push, screen->ntfy->handle);
 687
 688    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 689                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 690    if (ret)
 691       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 692
 693    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 694    PUSH_DATA (push, screen->surf2d->handle);
 695    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 696    PUSH_DATA (push, screen->ntfy->handle);
 697
 698    if (dev->chipset < 0x40)
 699       oclass = NV30_SURFACE_SWZ_CLASS;
 700    else
 701       oclass = NV40_SURFACE_SWZ_CLASS;
 702
 703    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 704                             NULL, 0, &screen->swzsurf);
 705    if (ret)
 706       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 707
 708    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 709    PUSH_DATA (push, screen->swzsurf->handle);
 710    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 711    PUSH_DATA (push, screen->ntfy->handle);
 712
 713    if (dev->chipset < 0x40)
 714       oclass = NV30_SIFM_CLASS;
 715    else
 716       oclass = NV40_SIFM_CLASS;
 717
 718    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 719                             NULL, 0, &screen->sifm);
 720    if (ret)
 721       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 722
 723    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 724    PUSH_DATA (push, screen->sifm->handle);
 725    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 726    PUSH_DATA (push, screen->ntfy->handle);
 727    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 728    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 729
 730    nouveau_pushbuf_kick(push, push->channel);
 731
 732    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 733    return &screen->base;
 734 }