src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_USER_INDEX_BUFFERS:
  95    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  99    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 161    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 162    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 163    case PIPE_CAP_CLIP_HALFZ:
 164    case PIPE_CAP_VERTEXID_NOBASE:
 165    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 166    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 167    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 168    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 169    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 170    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 171    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 172    case PIPE_CAP_TGSI_TXQS:
 173       return 0;
 174
 175    case PIPE_CAP_VENDOR_ID:
 176       return 0x10de;
 177    case PIPE_CAP_DEVICE_ID: {
 178       uint64_t device_id;
 179       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 180          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 181          return -1;
 182       }
 183       return device_id;
 184    }
 185    case PIPE_CAP_ACCELERATED:
 186       return 1;
 187    case PIPE_CAP_VIDEO_MEMORY:
 188       return dev->vram_size >> 20;
 189    case PIPE_CAP_UMA:
 190       return 0;
 191    }
 192
 193    debug_printf("unknown param %d\n", param);
 194    return 0;
 195 }
 196
 197 static float
 198 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 199 {
 200    struct nv30_screen *screen = nv30_screen(pscreen);
 201    struct nouveau_object *eng3d = screen->eng3d;
 202
 203    switch (param) {
 204    case PIPE_CAPF_MAX_LINE_WIDTH:
 205    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 206       return 10.0;
 207    case PIPE_CAPF_MAX_POINT_WIDTH:
 208    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 209       return 64.0;
 210    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 211       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 212    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 213       return 15.0;
 214    default:
 215       debug_printf("unknown paramf %d\n", param);
 216       return 0;
 217    }
 218 }
 219
 220 static int
 221 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 222                              enum pipe_shader_cap param)
 223 {
 224    struct nv30_screen *screen = nv30_screen(pscreen);
 225    struct nouveau_object *eng3d = screen->eng3d;
 226
 227    switch (shader) {
 228    case PIPE_SHADER_VERTEX:
 229       switch (param) {
 230       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 231       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 232          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 233       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 234       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 235          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 236       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 237          return 0;
 238       case PIPE_SHADER_CAP_MAX_INPUTS:
 239       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 240          return 16;
 241       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 242          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 243       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 244          return 1;
 245       case PIPE_SHADER_CAP_MAX_TEMPS:
 246          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 247       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 248       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 249          return 0;
 250       case PIPE_SHADER_CAP_MAX_PREDS:
 251       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 252       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 253       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 254       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 255       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 256       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 257       case PIPE_SHADER_CAP_SUBROUTINES:
 258       case PIPE_SHADER_CAP_INTEGERS:
 259       case PIPE_SHADER_CAP_DOUBLES:
 260       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 261       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 262       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 263       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 264          return 0;
 265       default:
 266          debug_printf("unknown vertex shader param %d\n", param);
 267          return 0;
 268       }
 269       break;
 270    case PIPE_SHADER_FRAGMENT:
 271       switch (param) {
 272       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 273       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 274       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 275       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 276          return 4096;
 277       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 278          return 0;
 279       case PIPE_SHADER_CAP_MAX_INPUTS:
 280          return 8; /* should be possible to do 10 with nv4x */
 281       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 282          return 4;
 283       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 284          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 285       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 286          return 1;
 287       case PIPE_SHADER_CAP_MAX_TEMPS:
 288          return 32;
 289       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 290       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 291          return 16;
 292       case PIPE_SHADER_CAP_MAX_PREDS:
 293       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 294       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 295       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 296       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 297       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 298       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 299       case PIPE_SHADER_CAP_SUBROUTINES:
 300       case PIPE_SHADER_CAP_DOUBLES:
 301       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 302       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 303       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 304       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 305          return 0;
 306       default:
 307          debug_printf("unknown fragment shader param %d\n", param);
 308          return 0;
 309       }
 310       break;
 311    default:
 312       return 0;
 313    }
 314 }
 315
 316 static boolean
 317 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 318                                 enum pipe_format format,
 319                                 enum pipe_texture_target target,
 320                                 unsigned sample_count,
 321                                 unsigned bindings)
 322 {
 323    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 324       return false;
 325
 326    if (!(0x00000017 & (1 << sample_count)))
 327       return false;
 328
 329    if (!util_format_is_supported(format, bindings)) {
 330       return false;
 331    }
 332
 333    /* transfers & shared are always supported */
 334    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 335                  PIPE_BIND_TRANSFER_WRITE |
 336                  PIPE_BIND_SHARED);
 337
 338    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 339 }
 340
 341 static void
 342 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 343 {
 344    struct nv30_screen *screen = nv30_screen(pscreen);
 345    struct nouveau_pushbuf *push = screen->base.pushbuf;
 346
 347    *sequence = ++screen->base.fence.sequence;
 348
 349    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 350    PUSH_DATA (push, 0);
 351    PUSH_DATA (push, *sequence);
 352 }
 353
 354 static uint32_t
 355 nv30_screen_fence_update(struct pipe_screen *pscreen)
 356 {
 357    struct nv30_screen *screen = nv30_screen(pscreen);
 358    struct nv04_notify *fence = screen->fence->data;
 359    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 360 }
 361
 362 static void
 363 nv30_screen_destroy(struct pipe_screen *pscreen)
 364 {
 365    struct nv30_screen *screen = nv30_screen(pscreen);
 366
 367    if (!nouveau_drm_screen_unref(&screen->base))
 368       return;
 369
 370    if (screen->base.fence.current) {
 371       struct nouveau_fence *current = NULL;
 372
 373       /* nouveau_fence_wait will create a new current fence, so wait on the
 374        * _current_ one, and remove both.
 375        */
 376       nouveau_fence_ref(screen->base.fence.current, &current);
 377       nouveau_fence_wait(current);
 378       nouveau_fence_ref(NULL, &current);
 379       nouveau_fence_ref(NULL, &screen->base.fence.current);
 380    }
 381
 382    nouveau_bo_ref(NULL, &screen->notify);
 383
 384    nouveau_heap_destroy(&screen->query_heap);
 385    nouveau_heap_destroy(&screen->vp_exec_heap);
 386    nouveau_heap_destroy(&screen->vp_data_heap);
 387
 388    nouveau_object_del(&screen->query);
 389    nouveau_object_del(&screen->fence);
 390    nouveau_object_del(&screen->ntfy);
 391
 392    nouveau_object_del(&screen->sifm);
 393    nouveau_object_del(&screen->swzsurf);
 394    nouveau_object_del(&screen->surf2d);
 395    nouveau_object_del(&screen->m2mf);
 396    nouveau_object_del(&screen->eng3d);
 397    nouveau_object_del(&screen->null);
 398
 399    nouveau_screen_fini(&screen->base);
 400    FREE(screen);
 401 }
 402
 403 #define FAIL_SCREEN_INIT(str, err)                    \
 404    do {                                               \
 405       NOUVEAU_ERR(str, err);                          \
 406       nv30_screen_destroy(pscreen);                   \
 407       return NULL;                                    \
 408    } while(0)
 409
 410 struct pipe_screen *
 411 nv30_screen_create(struct nouveau_device *dev)
 412 {
 413    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 414    struct pipe_screen *pscreen;
 415    struct nouveau_pushbuf *push;
 416    struct nv04_fifo *fifo;
 417    unsigned oclass = 0;
 418    int ret, i;
 419
 420    if (!screen)
 421       return NULL;
 422
 423    switch (dev->chipset & 0xf0) {
 424    case 0x30:
 425       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 426          oclass = NV30_3D_CLASS;
 427       else
 428       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 429          oclass = NV34_3D_CLASS;
 430       else
 431       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 432          oclass = NV35_3D_CLASS;
 433       break;
 434    case 0x40:
 435       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 436          oclass = NV40_3D_CLASS;
 437       else
 438       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 439          oclass = NV44_3D_CLASS;
 440       break;
 441    case 0x60:
 442       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 443          oclass = NV44_3D_CLASS;
 444       break;
 445    default:
 446       break;
 447    }
 448
 449    if (!oclass) {
 450       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 451       FREE(screen);
 452       return NULL;
 453    }
 454
 455    /*
 456     * Some modern apps try to use msaa without keeping in mind the
 457     * restrictions on videomem of older cards. Resulting in dmesg saying:
 458     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 459     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 460     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 461     *
 462     * Because we are running out of video memory, after which the program
 463     * using the msaa visual freezes, and eventually the entire system freezes.
 464     *
 465     * To work around this we do not allow msaa visauls by default and allow
 466     * the user to override this via NV30_MAX_MSAA.
 467     */
 468    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 469    if (screen->max_sample_count > 4)
 470       screen->max_sample_count = 4;
 471
 472    pscreen = &screen->base.base;
 473    pscreen->destroy = nv30_screen_destroy;
 474    pscreen->get_param = nv30_screen_get_param;
 475    pscreen->get_paramf = nv30_screen_get_paramf;
 476    pscreen->get_shader_param = nv30_screen_get_shader_param;
 477    pscreen->context_create = nv30_context_create;
 478    pscreen->is_format_supported = nv30_screen_is_format_supported;
 479    nv30_resource_screen_init(pscreen);
 480    nouveau_screen_init_vdec(&screen->base);
 481
 482    screen->base.fence.emit = nv30_screen_fence_emit;
 483    screen->base.fence.update = nv30_screen_fence_update;
 484
 485    ret = nouveau_screen_init(&screen->base, dev);
 486    if (ret)
 487       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 488
 489    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 490    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 491    if (oclass == NV40_3D_CLASS) {
 492       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 493       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 494    }
 495
 496    fifo = screen->base.channel->data;
 497    push = screen->base.pushbuf;
 498    push->rsvd_kick = 16;
 499
 500    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 501                             NULL, 0, &screen->null);
 502    if (ret)
 503       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 504
 505    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 506     * this means that the address pointed at by the DMA object must
 507     * be 4KiB aligned, which means this object needs to be the first
 508     * one allocated on the channel.
 509     */
 510    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 511                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 512                             .length = 32 }, sizeof(struct nv04_notify),
 513                             &screen->fence);
 514    if (ret)
 515       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 516
 517    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 518    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 519                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 520                             .length = 32 }, sizeof(struct nv04_notify),
 521                             &screen->ntfy);
 522    if (ret)
 523       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 524
 525    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 526     * the remainder of the "notifier block" assigned by the kernel for
 527     * use as query objects
 528     */
 529    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 530                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 531                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 532                             &screen->query);
 533    if (ret)
 534       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 535
 536    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 537    if (ret)
 538       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 539
 540    LIST_INITHEAD(&screen->queries);
 541
 542    /* Vertex program resources (code/data), currently 6 of the constant
 543     * slots are reserved to implement user clipping planes
 544     */
 545    if (oclass < NV40_3D_CLASS) {
 546       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 547       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 548    } else {
 549       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 550       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 551    }
 552
 553    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 554    if (ret == 0)
 555       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 556    if (ret)
 557       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 558
 559    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 560                             NULL, 0, &screen->eng3d);
 561    if (ret)
 562       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 563
 564    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 565    PUSH_DATA (push, screen->eng3d->handle);
 566    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 567    PUSH_DATA (push, screen->ntfy->handle);
 568    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 569    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 570    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 571    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 572    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 573    PUSH_DATA (push, fifo->vram);     /* ZETA */
 574    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 575    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 576    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 577    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 578    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 579    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 580    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 581       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 582       PUSH_DATA (push, 0x00100000);
 583       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 584       PUSH_DATA (push, 3);
 585
 586       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 587       PUSH_DATA (push, 0);
 588       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 589       PUSH_DATA (push, fui(0.0));
 590       PUSH_DATA (push, fui(0.0));
 591       PUSH_DATA (push, fui(1.0));
 592       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 593       for (i = 0; i < 16; i++)
 594          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 595
 596       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 597       PUSH_DATA (push, 0);
 598    } else {
 599       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 600       PUSH_DATA (push, fifo->vram);
 601       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 602
 603       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 604       PUSH_DATA (push, 0x00000004);
 605
 606       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 607       PUSH_DATA (push, 0x00000010);
 608       PUSH_DATA (push, 0x01000100);
 609       PUSH_DATA (push, 0xff800006);
 610
 611       /* vtxprog output routing */
 612       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 613       PUSH_DATA (push, 0x06144321);
 614       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 615       PUSH_DATA (push, 0xedcba987);
 616       PUSH_DATA (push, 0x0000006f);
 617       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 618       PUSH_DATA (push, 0x00171615);
 619       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 620       PUSH_DATA (push, 0x001b1a19);
 621
 622       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 623       PUSH_DATA (push, 0x0020ffff);
 624       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 625       PUSH_DATA (push, 0x01d300d4);
 626
 627       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 628       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 629    }
 630
 631    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 632                             NULL, 0, &screen->m2mf);
 633    if (ret)
 634       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 635
 636    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 637    PUSH_DATA (push, screen->m2mf->handle);
 638    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 639    PUSH_DATA (push, screen->ntfy->handle);
 640
 641    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 642                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 643    if (ret)
 644       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 645
 646    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 647    PUSH_DATA (push, screen->surf2d->handle);
 648    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 649    PUSH_DATA (push, screen->ntfy->handle);
 650
 651    if (dev->chipset < 0x40)
 652       oclass = NV30_SURFACE_SWZ_CLASS;
 653    else
 654       oclass = NV40_SURFACE_SWZ_CLASS;
 655
 656    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 657                             NULL, 0, &screen->swzsurf);
 658    if (ret)
 659       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 660
 661    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 662    PUSH_DATA (push, screen->swzsurf->handle);
 663    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 664    PUSH_DATA (push, screen->ntfy->handle);
 665
 666    if (dev->chipset < 0x40)
 667       oclass = NV30_SIFM_CLASS;
 668    else
 669       oclass = NV40_SIFM_CLASS;
 670
 671    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 672                             NULL, 0, &screen->sifm);
 673    if (ret)
 674       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 675
 676    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 677    PUSH_DATA (push, screen->sifm->handle);
 678    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 679    PUSH_DATA (push, screen->ntfy->handle);
 680    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 681    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 682
 683    nouveau_pushbuf_kick(push, push->channel);
 684
 685    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 686    return pscreen;
 687 }