src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
  68       return 120;
  69    case PIPE_CAP_ENDIANNESS:
  70       return PIPE_ENDIAN_LITTLE;
  71    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  72       return 16;
  73    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  74       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  75    case PIPE_CAP_MAX_VIEWPORTS:
  76       return 1;
  77    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  78       return 2048;
  79    /* supported capabilities */
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SWIZZLE:
  86    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  87    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  91    case PIPE_CAP_TGSI_TEXCOORD:
  92    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  93    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  94    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  95    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
  98       return 1;
  99    /* nv35 capabilities */
 100    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 101       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 102    /* nv4x capabilities */
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_NPOT_TEXTURES:
 105    case PIPE_CAP_CONDITIONAL_RENDER:
 106    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 107    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 108    case PIPE_CAP_PRIMITIVE_RESTART:
 109       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 110    /* unsupported */
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112    case PIPE_CAP_SM3:
 113    case PIPE_CAP_INDEP_BLEND_ENABLE:
 114    case PIPE_CAP_INDEP_BLEND_FUNC:
 115    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 116    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 117    case PIPE_CAP_TGSI_INSTANCEID:
 118    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 162    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 163    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_CLIP_HALFZ:
 166    case PIPE_CAP_VERTEXID_NOBASE:
 167    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_TGSI_TXQS:
 175    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 176    case PIPE_CAP_SHAREABLE_SHADERS:
 177    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 178    case PIPE_CAP_CLEAR_TEXTURE:
 179    case PIPE_CAP_DRAW_PARAMETERS:
 180    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 181    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 182    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 183    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184    case PIPE_CAP_INVALIDATE_BUFFER:
 185    case PIPE_CAP_GENERATE_MIPMAP:
 186    case PIPE_CAP_STRING_MARKER:
 187    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 188    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 189    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 190    case PIPE_CAP_QUERY_MEMORY_INFO:
 191    case PIPE_CAP_PCI_GROUP:
 192    case PIPE_CAP_PCI_BUS:
 193    case PIPE_CAP_PCI_DEVICE:
 194    case PIPE_CAP_PCI_FUNCTION:
 195    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 196    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 197    case PIPE_CAP_CULL_DISTANCE:
 198    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 199    case PIPE_CAP_TGSI_VOTE:
 200    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 201    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 202    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 203    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 204    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 205    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 206    case PIPE_CAP_NATIVE_FENCE_FD:
 207    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 208    case PIPE_CAP_TGSI_FS_FBFETCH:
 209    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 210    case PIPE_CAP_DOUBLES:
 211    case PIPE_CAP_INT64:
 212    case PIPE_CAP_INT64_DIVMOD:
 213    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 214    case PIPE_CAP_TGSI_CLOCK:
 215    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 216    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 217    case PIPE_CAP_TGSI_BALLOT:
 218    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 219    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 220    case PIPE_CAP_POST_DEPTH_COVERAGE:
 221    case PIPE_CAP_BINDLESS_TEXTURE:
 222    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 223    case PIPE_CAP_QUERY_SO_OVERFLOW:
 224    case PIPE_CAP_MEMOBJ:
 225    case PIPE_CAP_LOAD_CONSTBUF:
 226    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 227    case PIPE_CAP_TILE_RASTER_ORDER:
 228    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 229    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 230    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 231    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 232    case PIPE_CAP_FENCE_SIGNAL:
 233    case PIPE_CAP_CONSTBUF0_FLAGS:
 234    case PIPE_CAP_PACKED_UNIFORMS:
 235    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 236    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 237    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 238    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 239    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 240    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 241    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 242       return 0;
 243
 244    case PIPE_CAP_MAX_GS_INVOCATIONS:
 245       return 32;
 246    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 247       return 1 << 27;
 248    case PIPE_CAP_VENDOR_ID:
 249       return 0x10de;
 250    case PIPE_CAP_DEVICE_ID: {
 251       uint64_t device_id;
 252       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 253          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 254          return -1;
 255       }
 256       return device_id;
 257    }
 258    case PIPE_CAP_ACCELERATED:
 259       return 1;
 260    case PIPE_CAP_VIDEO_MEMORY:
 261       return dev->vram_size >> 20;
 262    case PIPE_CAP_UMA:
 263       return 0;
 264    }
 265
 266    debug_printf("unknown param %d\n", param);
 267    return 0;
 268 }
 269
 270 static float
 271 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 272 {
 273    struct nv30_screen *screen = nv30_screen(pscreen);
 274    struct nouveau_object *eng3d = screen->eng3d;
 275
 276    switch (param) {
 277    case PIPE_CAPF_MAX_LINE_WIDTH:
 278    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 279       return 10.0;
 280    case PIPE_CAPF_MAX_POINT_WIDTH:
 281    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 282       return 64.0;
 283    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 284       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 285    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 286       return 15.0;
 287    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 288    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 289    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 290       return 0.0;
 291    default:
 292       debug_printf("unknown paramf %d\n", param);
 293       return 0;
 294    }
 295 }
 296
 297 static int
 298 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 299                              enum pipe_shader_type shader,
 300                              enum pipe_shader_cap param)
 301 {
 302    struct nv30_screen *screen = nv30_screen(pscreen);
 303    struct nouveau_object *eng3d = screen->eng3d;
 304
 305    switch (shader) {
 306    case PIPE_SHADER_VERTEX:
 307       switch (param) {
 308       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 309       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 310          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 311       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 312       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 313          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 314       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 315          return 0;
 316       case PIPE_SHADER_CAP_MAX_INPUTS:
 317       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 318          return 16;
 319       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 320          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 321       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 322          return 1;
 323       case PIPE_SHADER_CAP_MAX_TEMPS:
 324          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 325       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 326          return 32;
 327       case PIPE_SHADER_CAP_PREFERRED_IR:
 328          return PIPE_SHADER_IR_TGSI;
 329       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 330       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 331          return 0;
 332       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 333       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 334       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 335       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 336       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 337       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 338       case PIPE_SHADER_CAP_SUBROUTINES:
 339       case PIPE_SHADER_CAP_INTEGERS:
 340       case PIPE_SHADER_CAP_INT64_ATOMICS:
 341       case PIPE_SHADER_CAP_FP16:
 342       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 343       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 344       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 345       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 346       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 347       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 348       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 349       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 350       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 351       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 352       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 353       case PIPE_SHADER_CAP_SCALAR_ISA:
 354          return 0;
 355       default:
 356          debug_printf("unknown vertex shader param %d\n", param);
 357          return 0;
 358       }
 359       break;
 360    case PIPE_SHADER_FRAGMENT:
 361       switch (param) {
 362       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 363       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 364       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 365       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 366          return 4096;
 367       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 368          return 0;
 369       case PIPE_SHADER_CAP_MAX_INPUTS:
 370          return 8; /* should be possible to do 10 with nv4x */
 371       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 372          return 4;
 373       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 374          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 375       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 376          return 1;
 377       case PIPE_SHADER_CAP_MAX_TEMPS:
 378          return 32;
 379       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 380       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 381          return 16;
 382       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 383          return 32;
 384       case PIPE_SHADER_CAP_PREFERRED_IR:
 385          return PIPE_SHADER_IR_TGSI;
 386       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 387       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 388       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 389       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 390       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 391       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 392       case PIPE_SHADER_CAP_SUBROUTINES:
 393       case PIPE_SHADER_CAP_INTEGERS:
 394       case PIPE_SHADER_CAP_FP16:
 395       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 396       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 397       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 398       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 399       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 400       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 401       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 402       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 403       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 404       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 405       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 406       case PIPE_SHADER_CAP_SCALAR_ISA:
 407          return 0;
 408       default:
 409          debug_printf("unknown fragment shader param %d\n", param);
 410          return 0;
 411       }
 412       break;
 413    default:
 414       return 0;
 415    }
 416 }
 417
 418 static boolean
 419 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 420                                 enum pipe_format format,
 421                                 enum pipe_texture_target target,
 422                                 unsigned sample_count,
 423                                 unsigned storage_sample_count,
 424                                 unsigned bindings)
 425 {
 426    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 427       return false;
 428
 429    if (!(0x00000017 & (1 << sample_count)))
 430       return false;
 431
 432    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 433       return false;
 434
 435    /* shared is always supported */
 436    bindings &= ~PIPE_BIND_SHARED;
 437
 438    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 439 }
 440
 441 static void
 442 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 443 {
 444    struct nv30_screen *screen = nv30_screen(pscreen);
 445    struct nouveau_pushbuf *push = screen->base.pushbuf;
 446
 447    *sequence = ++screen->base.fence.sequence;
 448
 449    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 450    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 451               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 452    PUSH_DATA (push, 0);
 453    PUSH_DATA (push, *sequence);
 454 }
 455
 456 static uint32_t
 457 nv30_screen_fence_update(struct pipe_screen *pscreen)
 458 {
 459    struct nv30_screen *screen = nv30_screen(pscreen);
 460    struct nv04_notify *fence = screen->fence->data;
 461    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 462 }
 463
 464 static void
 465 nv30_screen_destroy(struct pipe_screen *pscreen)
 466 {
 467    struct nv30_screen *screen = nv30_screen(pscreen);
 468
 469    if (!nouveau_drm_screen_unref(&screen->base))
 470       return;
 471
 472    if (screen->base.fence.current) {
 473       struct nouveau_fence *current = NULL;
 474
 475       /* nouveau_fence_wait will create a new current fence, so wait on the
 476        * _current_ one, and remove both.
 477        */
 478       nouveau_fence_ref(screen->base.fence.current, &current);
 479       nouveau_fence_wait(current, NULL);
 480       nouveau_fence_ref(NULL, &current);
 481       nouveau_fence_ref(NULL, &screen->base.fence.current);
 482    }
 483
 484    nouveau_bo_ref(NULL, &screen->notify);
 485
 486    nouveau_heap_destroy(&screen->query_heap);
 487    nouveau_heap_destroy(&screen->vp_exec_heap);
 488    nouveau_heap_destroy(&screen->vp_data_heap);
 489
 490    nouveau_object_del(&screen->query);
 491    nouveau_object_del(&screen->fence);
 492    nouveau_object_del(&screen->ntfy);
 493
 494    nouveau_object_del(&screen->sifm);
 495    nouveau_object_del(&screen->swzsurf);
 496    nouveau_object_del(&screen->surf2d);
 497    nouveau_object_del(&screen->m2mf);
 498    nouveau_object_del(&screen->eng3d);
 499    nouveau_object_del(&screen->null);
 500
 501    nouveau_screen_fini(&screen->base);
 502    FREE(screen);
 503 }
 504
 505 #define FAIL_SCREEN_INIT(str, err)                    \
 506    do {                                               \
 507       NOUVEAU_ERR(str, err);                          \
 508       screen->base.base.context_create = NULL;        \
 509       return &screen->base;                           \
 510    } while(0)
 511
 512 struct nouveau_screen *
 513 nv30_screen_create(struct nouveau_device *dev)
 514 {
 515    struct nv30_screen *screen;
 516    struct pipe_screen *pscreen;
 517    struct nouveau_pushbuf *push;
 518    struct nv04_fifo *fifo;
 519    unsigned oclass = 0;
 520    int ret, i;
 521
 522    switch (dev->chipset & 0xf0) {
 523    case 0x30:
 524       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 525          oclass = NV30_3D_CLASS;
 526       else
 527       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 528          oclass = NV34_3D_CLASS;
 529       else
 530       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 531          oclass = NV35_3D_CLASS;
 532       break;
 533    case 0x40:
 534       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 535          oclass = NV40_3D_CLASS;
 536       else
 537       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 538          oclass = NV44_3D_CLASS;
 539       break;
 540    case 0x60:
 541       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 542          oclass = NV44_3D_CLASS;
 543       break;
 544    default:
 545       break;
 546    }
 547
 548    if (!oclass) {
 549       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 550       return NULL;
 551    }
 552
 553    screen = CALLOC_STRUCT(nv30_screen);
 554    if (!screen)
 555       return NULL;
 556
 557    pscreen = &screen->base.base;
 558    pscreen->destroy = nv30_screen_destroy;
 559
 560    /*
 561     * Some modern apps try to use msaa without keeping in mind the
 562     * restrictions on videomem of older cards. Resulting in dmesg saying:
 563     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 564     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 565     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 566     *
 567     * Because we are running out of video memory, after which the program
 568     * using the msaa visual freezes, and eventually the entire system freezes.
 569     *
 570     * To work around this we do not allow msaa visauls by default and allow
 571     * the user to override this via NV30_MAX_MSAA.
 572     */
 573    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 574    if (screen->max_sample_count > 4)
 575       screen->max_sample_count = 4;
 576
 577    pscreen->get_param = nv30_screen_get_param;
 578    pscreen->get_paramf = nv30_screen_get_paramf;
 579    pscreen->get_shader_param = nv30_screen_get_shader_param;
 580    pscreen->context_create = nv30_context_create;
 581    pscreen->is_format_supported = nv30_screen_is_format_supported;
 582    nv30_resource_screen_init(pscreen);
 583    nouveau_screen_init_vdec(&screen->base);
 584
 585    screen->base.fence.emit = nv30_screen_fence_emit;
 586    screen->base.fence.update = nv30_screen_fence_update;
 587
 588    ret = nouveau_screen_init(&screen->base, dev);
 589    if (ret)
 590       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 591
 592    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 593    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 594    if (oclass == NV40_3D_CLASS) {
 595       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 596       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 597    }
 598
 599    fifo = screen->base.channel->data;
 600    push = screen->base.pushbuf;
 601    push->rsvd_kick = 16;
 602
 603    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 604                             NULL, 0, &screen->null);
 605    if (ret)
 606       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 607
 608    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 609     * this means that the address pointed at by the DMA object must
 610     * be 4KiB aligned, which means this object needs to be the first
 611     * one allocated on the channel.
 612     */
 613    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 614                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 615                             .length = 32 }, sizeof(struct nv04_notify),
 616                             &screen->fence);
 617    if (ret)
 618       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 619
 620    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 621    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 622                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 623                             .length = 32 }, sizeof(struct nv04_notify),
 624                             &screen->ntfy);
 625    if (ret)
 626       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 627
 628    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 629     * the remainder of the "notifier block" assigned by the kernel for
 630     * use as query objects
 631     */
 632    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 633                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 634                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 635                             &screen->query);
 636    if (ret)
 637       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 638
 639    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 640    if (ret)
 641       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 642
 643    LIST_INITHEAD(&screen->queries);
 644
 645    /* Vertex program resources (code/data), currently 6 of the constant
 646     * slots are reserved to implement user clipping planes
 647     */
 648    if (oclass < NV40_3D_CLASS) {
 649       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 650       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 651    } else {
 652       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 653       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 654    }
 655
 656    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 657    if (ret == 0)
 658       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 659    if (ret)
 660       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 661
 662    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 663                             NULL, 0, &screen->eng3d);
 664    if (ret)
 665       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 666
 667    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 668    PUSH_DATA (push, screen->eng3d->handle);
 669    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 670    PUSH_DATA (push, screen->ntfy->handle);
 671    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 672    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 673    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 674    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 675    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 676    PUSH_DATA (push, fifo->vram);     /* ZETA */
 677    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 678    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 679    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 680    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 681    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 682    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 683    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 684       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 685       PUSH_DATA (push, 0x00100000);
 686       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 687       PUSH_DATA (push, 3);
 688
 689       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 690       PUSH_DATA (push, 0);
 691       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 692       PUSH_DATA (push, fui(0.0));
 693       PUSH_DATA (push, fui(0.0));
 694       PUSH_DATA (push, fui(1.0));
 695       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 696       for (i = 0; i < 16; i++)
 697          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 698
 699       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 700       PUSH_DATA (push, 0);
 701    } else {
 702       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 703       PUSH_DATA (push, fifo->vram);
 704       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 705
 706       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 707       PUSH_DATA (push, 0x00000004);
 708
 709       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 710       PUSH_DATA (push, 0x00000010);
 711       PUSH_DATA (push, 0x01000100);
 712       PUSH_DATA (push, 0xff800006);
 713
 714       /* vtxprog output routing */
 715       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 716       PUSH_DATA (push, 0x06144321);
 717       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 718       PUSH_DATA (push, 0xedcba987);
 719       PUSH_DATA (push, 0x0000006f);
 720       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 721       PUSH_DATA (push, 0x00171615);
 722       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 723       PUSH_DATA (push, 0x001b1a19);
 724
 725       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 726       PUSH_DATA (push, 0x0020ffff);
 727       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 728       PUSH_DATA (push, 0x01d300d4);
 729
 730       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 731       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 732    }
 733
 734    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 735                             NULL, 0, &screen->m2mf);
 736    if (ret)
 737       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 738
 739    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 740    PUSH_DATA (push, screen->m2mf->handle);
 741    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 742    PUSH_DATA (push, screen->ntfy->handle);
 743
 744    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 745                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 746    if (ret)
 747       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 748
 749    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 750    PUSH_DATA (push, screen->surf2d->handle);
 751    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 752    PUSH_DATA (push, screen->ntfy->handle);
 753
 754    if (dev->chipset < 0x40)
 755       oclass = NV30_SURFACE_SWZ_CLASS;
 756    else
 757       oclass = NV40_SURFACE_SWZ_CLASS;
 758
 759    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 760                             NULL, 0, &screen->swzsurf);
 761    if (ret)
 762       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 763
 764    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 765    PUSH_DATA (push, screen->swzsurf->handle);
 766    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 767    PUSH_DATA (push, screen->ntfy->handle);
 768
 769    if (dev->chipset < 0x40)
 770       oclass = NV30_SIFM_CLASS;
 771    else
 772       oclass = NV40_SIFM_CLASS;
 773
 774    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 775                             NULL, 0, &screen->sifm);
 776    if (ret)
 777       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 778
 779    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 780    PUSH_DATA (push, screen->sifm->handle);
 781    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 782    PUSH_DATA (push, screen->ntfy->handle);
 783    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 784    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 785
 786    nouveau_pushbuf_kick(push, push->channel);
 787
 788    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 789    return &screen->base;
 790 }