2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
50 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
52 struct nv30_screen
*screen
= nv30_screen(pscreen
);
53 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS
:
59 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
66 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
68 case PIPE_CAP_ENDIANNESS
:
69 return PIPE_ENDIAN_LITTLE
;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
72 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
73 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
74 case PIPE_CAP_MAX_VIEWPORTS
:
76 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
78 /* supported capabilities */
79 case PIPE_CAP_TWO_SIDED_STENCIL
:
80 case PIPE_CAP_ANISOTROPIC_FILTER
:
81 case PIPE_CAP_POINT_SPRITE
:
82 case PIPE_CAP_OCCLUSION_QUERY
:
83 case PIPE_CAP_QUERY_TIME_ELAPSED
:
84 case PIPE_CAP_QUERY_TIMESTAMP
:
85 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
86 case PIPE_CAP_TEXTURE_SWIZZLE
:
87 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
88 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
89 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
90 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
91 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
92 case PIPE_CAP_TGSI_TEXCOORD
:
93 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
94 case PIPE_CAP_USER_INDEX_BUFFERS
:
95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
96 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
97 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
98 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
99 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
101 /* nv35 capabilities */
102 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
103 return eng3d
->oclass
== NV35_3D_CLASS
|| eng3d
->oclass
>= NV40_3D_CLASS
;
104 /* nv4x capabilities */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
106 case PIPE_CAP_NPOT_TEXTURES
:
107 case PIPE_CAP_CONDITIONAL_RENDER
:
108 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
109 case PIPE_CAP_PRIMITIVE_RESTART
:
110 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
112 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
114 case PIPE_CAP_INDEP_BLEND_ENABLE
:
115 case PIPE_CAP_INDEP_BLEND_FUNC
:
116 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
117 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
118 case PIPE_CAP_TGSI_INSTANCEID
:
119 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
120 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
121 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
122 case PIPE_CAP_MIN_TEXEL_OFFSET
:
123 case PIPE_CAP_MAX_TEXEL_OFFSET
:
124 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
128 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
129 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
130 case PIPE_CAP_MAX_VERTEX_STREAMS
:
131 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
132 case PIPE_CAP_TEXTURE_BARRIER
:
133 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
135 case PIPE_CAP_CUBE_MAP_ARRAY
:
136 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
137 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
138 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
139 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
140 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
141 case PIPE_CAP_START_INSTANCE
:
142 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
143 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
144 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
145 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
146 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
147 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
148 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
149 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
150 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
151 case PIPE_CAP_TEXTURE_GATHER_SM5
:
152 case PIPE_CAP_FAKE_SW_MSAA
:
153 case PIPE_CAP_TEXTURE_QUERY_LOD
:
154 case PIPE_CAP_SAMPLE_SHADING
:
155 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
156 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
157 case PIPE_CAP_USER_VERTEX_BUFFERS
:
158 case PIPE_CAP_COMPUTE
:
159 case PIPE_CAP_DRAW_INDIRECT
:
160 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
161 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
162 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
163 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
164 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
165 case PIPE_CAP_CLIP_HALFZ
:
166 case PIPE_CAP_VERTEXID_NOBASE
:
167 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
168 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
169 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
170 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
172 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
173 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
174 case PIPE_CAP_TGSI_TXQS
:
175 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
176 case PIPE_CAP_SHAREABLE_SHADERS
:
177 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
178 case PIPE_CAP_CLEAR_TEXTURE
:
179 case PIPE_CAP_DRAW_PARAMETERS
:
180 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
181 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
182 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
185 case PIPE_CAP_VENDOR_ID
:
187 case PIPE_CAP_DEVICE_ID
: {
189 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
190 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
195 case PIPE_CAP_ACCELERATED
:
197 case PIPE_CAP_VIDEO_MEMORY
:
198 return dev
->vram_size
>> 20;
203 debug_printf("unknown param %d\n", param
);
208 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
210 struct nv30_screen
*screen
= nv30_screen(pscreen
);
211 struct nouveau_object
*eng3d
= screen
->eng3d
;
214 case PIPE_CAPF_MAX_LINE_WIDTH
:
215 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
217 case PIPE_CAPF_MAX_POINT_WIDTH
:
218 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
220 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
221 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
222 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
225 debug_printf("unknown paramf %d\n", param
);
231 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
232 enum pipe_shader_cap param
)
234 struct nv30_screen
*screen
= nv30_screen(pscreen
);
235 struct nouveau_object
*eng3d
= screen
->eng3d
;
238 case PIPE_SHADER_VERTEX
:
240 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
241 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
242 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
243 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
244 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
245 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
246 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
248 case PIPE_SHADER_CAP_MAX_INPUTS
:
249 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
251 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
252 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
253 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
255 case PIPE_SHADER_CAP_MAX_TEMPS
:
256 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
257 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
258 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
260 case PIPE_SHADER_CAP_MAX_PREDS
:
261 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
262 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
263 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
264 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
265 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
266 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
267 case PIPE_SHADER_CAP_SUBROUTINES
:
268 case PIPE_SHADER_CAP_INTEGERS
:
269 case PIPE_SHADER_CAP_DOUBLES
:
270 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
271 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
272 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
273 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
274 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
276 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
279 debug_printf("unknown vertex shader param %d\n", param
);
283 case PIPE_SHADER_FRAGMENT
:
285 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
286 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
287 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
288 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
290 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
292 case PIPE_SHADER_CAP_MAX_INPUTS
:
293 return 8; /* should be possible to do 10 with nv4x */
294 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
296 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
297 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32) * sizeof(float[4]);
298 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
300 case PIPE_SHADER_CAP_MAX_TEMPS
:
302 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
303 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
305 case PIPE_SHADER_CAP_MAX_PREDS
:
306 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
307 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
308 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
309 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
310 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
311 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
312 case PIPE_SHADER_CAP_SUBROUTINES
:
313 case PIPE_SHADER_CAP_DOUBLES
:
314 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
315 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
316 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
317 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
318 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
320 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
323 debug_printf("unknown fragment shader param %d\n", param
);
333 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
334 enum pipe_format format
,
335 enum pipe_texture_target target
,
336 unsigned sample_count
,
339 if (sample_count
> nv30_screen(pscreen
)->max_sample_count
)
342 if (!(0x00000017 & (1 << sample_count
)))
345 if (!util_format_is_supported(format
, bindings
)) {
349 /* transfers & shared are always supported */
350 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
351 PIPE_BIND_TRANSFER_WRITE
|
354 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
358 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
360 struct nv30_screen
*screen
= nv30_screen(pscreen
);
361 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
363 *sequence
= ++screen
->base
.fence
.sequence
;
365 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 3);
366 PUSH_DATA (push
, NV30_3D_FENCE_OFFSET
|
367 (2 /* size */ << 18) | (7 /* subchan */ << 13));
369 PUSH_DATA (push
, *sequence
);
373 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
375 struct nv30_screen
*screen
= nv30_screen(pscreen
);
376 struct nv04_notify
*fence
= screen
->fence
->data
;
377 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
381 nv30_screen_destroy(struct pipe_screen
*pscreen
)
383 struct nv30_screen
*screen
= nv30_screen(pscreen
);
385 if (!nouveau_drm_screen_unref(&screen
->base
))
388 if (screen
->base
.fence
.current
) {
389 struct nouveau_fence
*current
= NULL
;
391 /* nouveau_fence_wait will create a new current fence, so wait on the
392 * _current_ one, and remove both.
394 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
395 nouveau_fence_wait(current
, NULL
);
396 nouveau_fence_ref(NULL
, ¤t
);
397 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
400 nouveau_bo_ref(NULL
, &screen
->notify
);
402 nouveau_heap_destroy(&screen
->query_heap
);
403 nouveau_heap_destroy(&screen
->vp_exec_heap
);
404 nouveau_heap_destroy(&screen
->vp_data_heap
);
406 nouveau_object_del(&screen
->query
);
407 nouveau_object_del(&screen
->fence
);
408 nouveau_object_del(&screen
->ntfy
);
410 nouveau_object_del(&screen
->sifm
);
411 nouveau_object_del(&screen
->swzsurf
);
412 nouveau_object_del(&screen
->surf2d
);
413 nouveau_object_del(&screen
->m2mf
);
414 nouveau_object_del(&screen
->eng3d
);
415 nouveau_object_del(&screen
->null
);
417 nouveau_screen_fini(&screen
->base
);
421 #define FAIL_SCREEN_INIT(str, err) \
423 NOUVEAU_ERR(str, err); \
424 screen->base.base.context_create = NULL; \
425 return &screen->base; \
428 struct nouveau_screen
*
429 nv30_screen_create(struct nouveau_device
*dev
)
431 struct nv30_screen
*screen
;
432 struct pipe_screen
*pscreen
;
433 struct nouveau_pushbuf
*push
;
434 struct nv04_fifo
*fifo
;
438 switch (dev
->chipset
& 0xf0) {
440 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
441 oclass
= NV30_3D_CLASS
;
443 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
444 oclass
= NV34_3D_CLASS
;
446 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
447 oclass
= NV35_3D_CLASS
;
450 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
451 oclass
= NV40_3D_CLASS
;
453 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
454 oclass
= NV44_3D_CLASS
;
457 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
458 oclass
= NV44_3D_CLASS
;
465 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
469 screen
= CALLOC_STRUCT(nv30_screen
);
473 pscreen
= &screen
->base
.base
;
474 pscreen
->destroy
= nv30_screen_destroy
;
477 * Some modern apps try to use msaa without keeping in mind the
478 * restrictions on videomem of older cards. Resulting in dmesg saying:
479 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
480 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
481 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
483 * Because we are running out of video memory, after which the program
484 * using the msaa visual freezes, and eventually the entire system freezes.
486 * To work around this we do not allow msaa visauls by default and allow
487 * the user to override this via NV30_MAX_MSAA.
489 screen
->max_sample_count
= debug_get_num_option("NV30_MAX_MSAA", 0);
490 if (screen
->max_sample_count
> 4)
491 screen
->max_sample_count
= 4;
493 pscreen
->get_param
= nv30_screen_get_param
;
494 pscreen
->get_paramf
= nv30_screen_get_paramf
;
495 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
496 pscreen
->context_create
= nv30_context_create
;
497 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
498 nv30_resource_screen_init(pscreen
);
499 nouveau_screen_init_vdec(&screen
->base
);
501 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
502 screen
->base
.fence
.update
= nv30_screen_fence_update
;
504 ret
= nouveau_screen_init(&screen
->base
, dev
);
506 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
508 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
509 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
510 if (oclass
== NV40_3D_CLASS
) {
511 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
512 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
515 fifo
= screen
->base
.channel
->data
;
516 push
= screen
->base
.pushbuf
;
517 push
->rsvd_kick
= 16;
519 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
520 NULL
, 0, &screen
->null
);
522 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
524 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
525 * this means that the address pointed at by the DMA object must
526 * be 4KiB aligned, which means this object needs to be the first
527 * one allocated on the channel.
529 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
530 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
531 .length
= 32 }, sizeof(struct nv04_notify
),
534 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
536 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
537 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
538 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
539 .length
= 32 }, sizeof(struct nv04_notify
),
542 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
544 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
545 * the remainder of the "notifier block" assigned by the kernel for
546 * use as query objects
548 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
549 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
550 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
553 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
555 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
557 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
559 LIST_INITHEAD(&screen
->queries
);
561 /* Vertex program resources (code/data), currently 6 of the constant
562 * slots are reserved to implement user clipping planes
564 if (oclass
< NV40_3D_CLASS
) {
565 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
566 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
568 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
569 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
572 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
574 ret
= nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
576 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
578 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
579 NULL
, 0, &screen
->eng3d
);
581 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
583 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
584 PUSH_DATA (push
, screen
->eng3d
->handle
);
585 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
586 PUSH_DATA (push
, screen
->ntfy
->handle
);
587 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
588 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
589 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
590 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
591 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
592 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
593 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
594 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
595 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
596 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
597 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
598 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
599 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
600 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
601 PUSH_DATA (push
, 0x00100000);
602 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
605 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
607 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
608 PUSH_DATA (push
, fui(0.0));
609 PUSH_DATA (push
, fui(0.0));
610 PUSH_DATA (push
, fui(1.0));
611 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
612 for (i
= 0; i
< 16; i
++)
613 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
615 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
618 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
619 PUSH_DATA (push
, fifo
->vram
);
620 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
622 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
623 PUSH_DATA (push
, 0x00000004);
625 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
626 PUSH_DATA (push
, 0x00000010);
627 PUSH_DATA (push
, 0x01000100);
628 PUSH_DATA (push
, 0xff800006);
630 /* vtxprog output routing */
631 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
632 PUSH_DATA (push
, 0x06144321);
633 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
634 PUSH_DATA (push
, 0xedcba987);
635 PUSH_DATA (push
, 0x0000006f);
636 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
637 PUSH_DATA (push
, 0x00171615);
638 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
639 PUSH_DATA (push
, 0x001b1a19);
641 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
642 PUSH_DATA (push
, 0x0020ffff);
643 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
644 PUSH_DATA (push
, 0x01d300d4);
646 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
647 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
650 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
651 NULL
, 0, &screen
->m2mf
);
653 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
655 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
656 PUSH_DATA (push
, screen
->m2mf
->handle
);
657 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
658 PUSH_DATA (push
, screen
->ntfy
->handle
);
660 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
661 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
663 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
665 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
666 PUSH_DATA (push
, screen
->surf2d
->handle
);
667 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
668 PUSH_DATA (push
, screen
->ntfy
->handle
);
670 if (dev
->chipset
< 0x40)
671 oclass
= NV30_SURFACE_SWZ_CLASS
;
673 oclass
= NV40_SURFACE_SWZ_CLASS
;
675 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
676 NULL
, 0, &screen
->swzsurf
);
678 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
680 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
681 PUSH_DATA (push
, screen
->swzsurf
->handle
);
682 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
683 PUSH_DATA (push
, screen
->ntfy
->handle
);
685 if (dev
->chipset
< 0x40)
686 oclass
= NV30_SIFM_CLASS
;
688 oclass
= NV40_SIFM_CLASS
;
690 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
691 NULL
, 0, &screen
->sifm
);
693 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
695 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
696 PUSH_DATA (push
, screen
->sifm
->handle
);
697 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
698 PUSH_DATA (push
, screen
->ntfy
->handle
);
699 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
700 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
702 nouveau_pushbuf_kick(push
, push
->channel
);
704 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
705 return &screen
->base
;