src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  95    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  99    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 123    case PIPE_CAP_MIN_TEXEL_OFFSET:
 124    case PIPE_CAP_MAX_TEXEL_OFFSET:
 125    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 129    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 130    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 131    case PIPE_CAP_MAX_VERTEX_STREAMS:
 132    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 133    case PIPE_CAP_TEXTURE_BARRIER:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 136    case PIPE_CAP_CUBE_MAP_ARRAY:
 137    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 138    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 139    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 140    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 141    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 142    case PIPE_CAP_START_INSTANCE:
 143    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 147    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 148    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 151    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 152    case PIPE_CAP_TEXTURE_GATHER_SM5:
 153    case PIPE_CAP_FAKE_SW_MSAA:
 154    case PIPE_CAP_TEXTURE_QUERY_LOD:
 155    case PIPE_CAP_SAMPLE_SHADING:
 156    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 157    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 158    case PIPE_CAP_USER_VERTEX_BUFFERS:
 159    case PIPE_CAP_COMPUTE:
 160    case PIPE_CAP_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 162    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 163    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 164    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 165    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 166    case PIPE_CAP_CLIP_HALFZ:
 167    case PIPE_CAP_VERTEXID_NOBASE:
 168    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 169    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 170    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 171    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 172    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 173    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 174    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 175    case PIPE_CAP_TGSI_TXQS:
 176    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 177    case PIPE_CAP_SHAREABLE_SHADERS:
 178    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 179    case PIPE_CAP_CLEAR_TEXTURE:
 180    case PIPE_CAP_DRAW_PARAMETERS:
 181    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 182    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 183    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 184    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 185    case PIPE_CAP_INVALIDATE_BUFFER:
 186    case PIPE_CAP_GENERATE_MIPMAP:
 187    case PIPE_CAP_STRING_MARKER:
 188    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 189    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 190    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 191    case PIPE_CAP_QUERY_MEMORY_INFO:
 192    case PIPE_CAP_PCI_GROUP:
 193    case PIPE_CAP_PCI_BUS:
 194    case PIPE_CAP_PCI_DEVICE:
 195    case PIPE_CAP_PCI_FUNCTION:
 196    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 197    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 200    case PIPE_CAP_TGSI_VOTE:
 201    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 202    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 203    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 204    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 205    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 206    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 207    case PIPE_CAP_NATIVE_FENCE_FD:
 208    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 209    case PIPE_CAP_TGSI_FS_FBFETCH:
 210    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 211    case PIPE_CAP_DOUBLES:
 212    case PIPE_CAP_INT64:
 213    case PIPE_CAP_INT64_DIVMOD:
 214    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 215    case PIPE_CAP_TGSI_CLOCK:
 216    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 217    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 218    case PIPE_CAP_TGSI_BALLOT:
 219    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 220    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 221    case PIPE_CAP_POST_DEPTH_COVERAGE:
 222    case PIPE_CAP_BINDLESS_TEXTURE:
 223    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 224    case PIPE_CAP_QUERY_SO_OVERFLOW:
 225    case PIPE_CAP_MEMOBJ:
 226    case PIPE_CAP_LOAD_CONSTBUF:
 227    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 228    case PIPE_CAP_TILE_RASTER_ORDER:
 229    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 230    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 231       return 0;
 232
 233    case PIPE_CAP_VENDOR_ID:
 234       return 0x10de;
 235    case PIPE_CAP_DEVICE_ID: {
 236       uint64_t device_id;
 237       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 238          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 239          return -1;
 240       }
 241       return device_id;
 242    }
 243    case PIPE_CAP_ACCELERATED:
 244       return 1;
 245    case PIPE_CAP_VIDEO_MEMORY:
 246       return dev->vram_size >> 20;
 247    case PIPE_CAP_UMA:
 248       return 0;
 249    }
 250
 251    debug_printf("unknown param %d\n", param);
 252    return 0;
 253 }
 254
 255 static float
 256 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 257 {
 258    struct nv30_screen *screen = nv30_screen(pscreen);
 259    struct nouveau_object *eng3d = screen->eng3d;
 260
 261    switch (param) {
 262    case PIPE_CAPF_MAX_LINE_WIDTH:
 263    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 264       return 10.0;
 265    case PIPE_CAPF_MAX_POINT_WIDTH:
 266    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 267       return 64.0;
 268    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 269       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 270    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 271       return 15.0;
 272    default:
 273       debug_printf("unknown paramf %d\n", param);
 274       return 0;
 275    }
 276 }
 277
 278 static int
 279 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 280                              enum pipe_shader_type shader,
 281                              enum pipe_shader_cap param)
 282 {
 283    struct nv30_screen *screen = nv30_screen(pscreen);
 284    struct nouveau_object *eng3d = screen->eng3d;
 285
 286    switch (shader) {
 287    case PIPE_SHADER_VERTEX:
 288       switch (param) {
 289       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 290       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 291          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 292       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 293       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 294          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 295       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 296          return 0;
 297       case PIPE_SHADER_CAP_MAX_INPUTS:
 298       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 299          return 16;
 300       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 301          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 302       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 303          return 1;
 304       case PIPE_SHADER_CAP_MAX_TEMPS:
 305          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 306       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 307          return 32;
 308       case PIPE_SHADER_CAP_PREFERRED_IR:
 309          return PIPE_SHADER_IR_TGSI;
 310       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 311       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 312          return 0;
 313       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 314       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 315       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 316       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 317       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 318       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 319       case PIPE_SHADER_CAP_SUBROUTINES:
 320       case PIPE_SHADER_CAP_INTEGERS:
 321       case PIPE_SHADER_CAP_INT64_ATOMICS:
 322       case PIPE_SHADER_CAP_FP16:
 323       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 324       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 325       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 326       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 327       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 328       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 329       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 330       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 331       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 332       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 333       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 334          return 0;
 335       default:
 336          debug_printf("unknown vertex shader param %d\n", param);
 337          return 0;
 338       }
 339       break;
 340    case PIPE_SHADER_FRAGMENT:
 341       switch (param) {
 342       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 343       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 344       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 345       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 346          return 4096;
 347       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 348          return 0;
 349       case PIPE_SHADER_CAP_MAX_INPUTS:
 350          return 8; /* should be possible to do 10 with nv4x */
 351       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 352          return 4;
 353       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 354          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 355       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 356          return 1;
 357       case PIPE_SHADER_CAP_MAX_TEMPS:
 358          return 32;
 359       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 360       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 361          return 16;
 362       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 363          return 32;
 364       case PIPE_SHADER_CAP_PREFERRED_IR:
 365          return PIPE_SHADER_IR_TGSI;
 366       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 367       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 368       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 370       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 371       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 372       case PIPE_SHADER_CAP_SUBROUTINES:
 373       case PIPE_SHADER_CAP_INTEGERS:
 374       case PIPE_SHADER_CAP_FP16:
 375       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 376       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 377       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 378       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 379       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 380       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 381       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 382       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 383       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 384          return 0;
 385       default:
 386          debug_printf("unknown fragment shader param %d\n", param);
 387          return 0;
 388       }
 389       break;
 390    default:
 391       return 0;
 392    }
 393 }
 394
 395 static boolean
 396 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 397                                 enum pipe_format format,
 398                                 enum pipe_texture_target target,
 399                                 unsigned sample_count,
 400                                 unsigned bindings)
 401 {
 402    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 403       return false;
 404
 405    if (!(0x00000017 & (1 << sample_count)))
 406       return false;
 407
 408    if (!util_format_is_supported(format, bindings)) {
 409       return false;
 410    }
 411
 412    /* shared is always supported */
 413    bindings &= ~PIPE_BIND_SHARED;
 414
 415    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 416 }
 417
 418 static void
 419 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 420 {
 421    struct nv30_screen *screen = nv30_screen(pscreen);
 422    struct nouveau_pushbuf *push = screen->base.pushbuf;
 423
 424    *sequence = ++screen->base.fence.sequence;
 425
 426    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 427    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 428               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 429    PUSH_DATA (push, 0);
 430    PUSH_DATA (push, *sequence);
 431 }
 432
 433 static uint32_t
 434 nv30_screen_fence_update(struct pipe_screen *pscreen)
 435 {
 436    struct nv30_screen *screen = nv30_screen(pscreen);
 437    struct nv04_notify *fence = screen->fence->data;
 438    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 439 }
 440
 441 static void
 442 nv30_screen_destroy(struct pipe_screen *pscreen)
 443 {
 444    struct nv30_screen *screen = nv30_screen(pscreen);
 445
 446    if (!nouveau_drm_screen_unref(&screen->base))
 447       return;
 448
 449    if (screen->base.fence.current) {
 450       struct nouveau_fence *current = NULL;
 451
 452       /* nouveau_fence_wait will create a new current fence, so wait on the
 453        * _current_ one, and remove both.
 454        */
 455       nouveau_fence_ref(screen->base.fence.current, &current);
 456       nouveau_fence_wait(current, NULL);
 457       nouveau_fence_ref(NULL, &current);
 458       nouveau_fence_ref(NULL, &screen->base.fence.current);
 459    }
 460
 461    nouveau_bo_ref(NULL, &screen->notify);
 462
 463    nouveau_heap_destroy(&screen->query_heap);
 464    nouveau_heap_destroy(&screen->vp_exec_heap);
 465    nouveau_heap_destroy(&screen->vp_data_heap);
 466
 467    nouveau_object_del(&screen->query);
 468    nouveau_object_del(&screen->fence);
 469    nouveau_object_del(&screen->ntfy);
 470
 471    nouveau_object_del(&screen->sifm);
 472    nouveau_object_del(&screen->swzsurf);
 473    nouveau_object_del(&screen->surf2d);
 474    nouveau_object_del(&screen->m2mf);
 475    nouveau_object_del(&screen->eng3d);
 476    nouveau_object_del(&screen->null);
 477
 478    nouveau_screen_fini(&screen->base);
 479    FREE(screen);
 480 }
 481
 482 #define FAIL_SCREEN_INIT(str, err)                    \
 483    do {                                               \
 484       NOUVEAU_ERR(str, err);                          \
 485       screen->base.base.context_create = NULL;        \
 486       return &screen->base;                           \
 487    } while(0)
 488
 489 struct nouveau_screen *
 490 nv30_screen_create(struct nouveau_device *dev)
 491 {
 492    struct nv30_screen *screen;
 493    struct pipe_screen *pscreen;
 494    struct nouveau_pushbuf *push;
 495    struct nv04_fifo *fifo;
 496    unsigned oclass = 0;
 497    int ret, i;
 498
 499    switch (dev->chipset & 0xf0) {
 500    case 0x30:
 501       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 502          oclass = NV30_3D_CLASS;
 503       else
 504       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 505          oclass = NV34_3D_CLASS;
 506       else
 507       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 508          oclass = NV35_3D_CLASS;
 509       break;
 510    case 0x40:
 511       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 512          oclass = NV40_3D_CLASS;
 513       else
 514       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 515          oclass = NV44_3D_CLASS;
 516       break;
 517    case 0x60:
 518       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 519          oclass = NV44_3D_CLASS;
 520       break;
 521    default:
 522       break;
 523    }
 524
 525    if (!oclass) {
 526       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 527       return NULL;
 528    }
 529
 530    screen = CALLOC_STRUCT(nv30_screen);
 531    if (!screen)
 532       return NULL;
 533
 534    pscreen = &screen->base.base;
 535    pscreen->destroy = nv30_screen_destroy;
 536
 537    /*
 538     * Some modern apps try to use msaa without keeping in mind the
 539     * restrictions on videomem of older cards. Resulting in dmesg saying:
 540     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 541     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 542     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 543     *
 544     * Because we are running out of video memory, after which the program
 545     * using the msaa visual freezes, and eventually the entire system freezes.
 546     *
 547     * To work around this we do not allow msaa visauls by default and allow
 548     * the user to override this via NV30_MAX_MSAA.
 549     */
 550    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 551    if (screen->max_sample_count > 4)
 552       screen->max_sample_count = 4;
 553
 554    pscreen->get_param = nv30_screen_get_param;
 555    pscreen->get_paramf = nv30_screen_get_paramf;
 556    pscreen->get_shader_param = nv30_screen_get_shader_param;
 557    pscreen->context_create = nv30_context_create;
 558    pscreen->is_format_supported = nv30_screen_is_format_supported;
 559    nv30_resource_screen_init(pscreen);
 560    nouveau_screen_init_vdec(&screen->base);
 561
 562    screen->base.fence.emit = nv30_screen_fence_emit;
 563    screen->base.fence.update = nv30_screen_fence_update;
 564
 565    ret = nouveau_screen_init(&screen->base, dev);
 566    if (ret)
 567       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 568
 569    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 570    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 571    if (oclass == NV40_3D_CLASS) {
 572       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 573       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 574    }
 575
 576    fifo = screen->base.channel->data;
 577    push = screen->base.pushbuf;
 578    push->rsvd_kick = 16;
 579
 580    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 581                             NULL, 0, &screen->null);
 582    if (ret)
 583       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 584
 585    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 586     * this means that the address pointed at by the DMA object must
 587     * be 4KiB aligned, which means this object needs to be the first
 588     * one allocated on the channel.
 589     */
 590    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 591                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 592                             .length = 32 }, sizeof(struct nv04_notify),
 593                             &screen->fence);
 594    if (ret)
 595       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 596
 597    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 598    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 599                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 600                             .length = 32 }, sizeof(struct nv04_notify),
 601                             &screen->ntfy);
 602    if (ret)
 603       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 604
 605    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 606     * the remainder of the "notifier block" assigned by the kernel for
 607     * use as query objects
 608     */
 609    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 610                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 611                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 612                             &screen->query);
 613    if (ret)
 614       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 615
 616    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 617    if (ret)
 618       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 619
 620    LIST_INITHEAD(&screen->queries);
 621
 622    /* Vertex program resources (code/data), currently 6 of the constant
 623     * slots are reserved to implement user clipping planes
 624     */
 625    if (oclass < NV40_3D_CLASS) {
 626       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 627       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 628    } else {
 629       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 630       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 631    }
 632
 633    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 634    if (ret == 0)
 635       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 636    if (ret)
 637       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 638
 639    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 640                             NULL, 0, &screen->eng3d);
 641    if (ret)
 642       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 643
 644    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 645    PUSH_DATA (push, screen->eng3d->handle);
 646    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 647    PUSH_DATA (push, screen->ntfy->handle);
 648    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 649    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 650    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 651    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 652    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 653    PUSH_DATA (push, fifo->vram);     /* ZETA */
 654    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 655    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 656    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 657    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 658    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 659    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 660    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 661       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 662       PUSH_DATA (push, 0x00100000);
 663       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 664       PUSH_DATA (push, 3);
 665
 666       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 667       PUSH_DATA (push, 0);
 668       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 669       PUSH_DATA (push, fui(0.0));
 670       PUSH_DATA (push, fui(0.0));
 671       PUSH_DATA (push, fui(1.0));
 672       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 673       for (i = 0; i < 16; i++)
 674          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 675
 676       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 677       PUSH_DATA (push, 0);
 678    } else {
 679       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 680       PUSH_DATA (push, fifo->vram);
 681       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 682
 683       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 684       PUSH_DATA (push, 0x00000004);
 685
 686       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 687       PUSH_DATA (push, 0x00000010);
 688       PUSH_DATA (push, 0x01000100);
 689       PUSH_DATA (push, 0xff800006);
 690
 691       /* vtxprog output routing */
 692       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 693       PUSH_DATA (push, 0x06144321);
 694       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 695       PUSH_DATA (push, 0xedcba987);
 696       PUSH_DATA (push, 0x0000006f);
 697       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 698       PUSH_DATA (push, 0x00171615);
 699       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 700       PUSH_DATA (push, 0x001b1a19);
 701
 702       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 703       PUSH_DATA (push, 0x0020ffff);
 704       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 705       PUSH_DATA (push, 0x01d300d4);
 706
 707       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 708       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 709    }
 710
 711    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 712                             NULL, 0, &screen->m2mf);
 713    if (ret)
 714       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 715
 716    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 717    PUSH_DATA (push, screen->m2mf->handle);
 718    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 719    PUSH_DATA (push, screen->ntfy->handle);
 720
 721    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 722                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 723    if (ret)
 724       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 725
 726    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 727    PUSH_DATA (push, screen->surf2d->handle);
 728    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 729    PUSH_DATA (push, screen->ntfy->handle);
 730
 731    if (dev->chipset < 0x40)
 732       oclass = NV30_SURFACE_SWZ_CLASS;
 733    else
 734       oclass = NV40_SURFACE_SWZ_CLASS;
 735
 736    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 737                             NULL, 0, &screen->swzsurf);
 738    if (ret)
 739       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 740
 741    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 742    PUSH_DATA (push, screen->swzsurf->handle);
 743    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 744    PUSH_DATA (push, screen->ntfy->handle);
 745
 746    if (dev->chipset < 0x40)
 747       oclass = NV30_SIFM_CLASS;
 748    else
 749       oclass = NV40_SIFM_CLASS;
 750
 751    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 752                             NULL, 0, &screen->sifm);
 753    if (ret)
 754       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 755
 756    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 757    PUSH_DATA (push, screen->sifm->handle);
 758    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 759    PUSH_DATA (push, screen->ntfy->handle);
 760    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 761    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 762
 763    nouveau_pushbuf_kick(push, push->channel);
 764
 765    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 766    return &screen->base;
 767 }