2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
50 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
52 struct nv30_screen
*screen
= nv30_screen(pscreen
);
53 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS
:
59 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
66 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
68 case PIPE_CAP_ENDIANNESS
:
69 return PIPE_ENDIAN_LITTLE
;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
72 case PIPE_CAP_MAX_VIEWPORTS
:
74 /* supported capabilities */
75 case PIPE_CAP_TWO_SIDED_STENCIL
:
76 case PIPE_CAP_ANISOTROPIC_FILTER
:
77 case PIPE_CAP_POINT_SPRITE
:
78 case PIPE_CAP_OCCLUSION_QUERY
:
79 case PIPE_CAP_QUERY_TIME_ELAPSED
:
80 case PIPE_CAP_QUERY_TIMESTAMP
:
81 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
82 case PIPE_CAP_TEXTURE_SWIZZLE
:
83 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
84 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
85 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
86 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
87 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
88 case PIPE_CAP_TGSI_TEXCOORD
:
89 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
90 case PIPE_CAP_USER_INDEX_BUFFERS
:
91 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
92 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
93 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
94 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
95 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
97 /* nv4x capabilities */
98 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
99 case PIPE_CAP_NPOT_TEXTURES
:
100 case PIPE_CAP_CONDITIONAL_RENDER
:
101 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
102 case PIPE_CAP_PRIMITIVE_RESTART
:
103 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
107 case PIPE_CAP_INDEP_BLEND_ENABLE
:
108 case PIPE_CAP_INDEP_BLEND_FUNC
:
109 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
110 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
111 case PIPE_CAP_TGSI_INSTANCEID
:
112 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
113 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
114 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
115 case PIPE_CAP_MIN_TEXEL_OFFSET
:
116 case PIPE_CAP_MAX_TEXEL_OFFSET
:
117 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
118 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
119 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
120 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
121 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
122 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
123 case PIPE_CAP_MAX_VERTEX_STREAMS
:
124 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
125 case PIPE_CAP_TEXTURE_BARRIER
:
126 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
127 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
128 case PIPE_CAP_CUBE_MAP_ARRAY
:
129 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
130 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
131 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
132 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
133 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
134 case PIPE_CAP_START_INSTANCE
:
135 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
136 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
137 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
138 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
139 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
140 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
141 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
142 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
143 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
144 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
145 case PIPE_CAP_TEXTURE_GATHER_SM5
:
146 case PIPE_CAP_FAKE_SW_MSAA
:
147 case PIPE_CAP_TEXTURE_QUERY_LOD
:
148 case PIPE_CAP_SAMPLE_SHADING
:
149 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
150 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
151 case PIPE_CAP_USER_VERTEX_BUFFERS
:
152 case PIPE_CAP_COMPUTE
:
153 case PIPE_CAP_DRAW_INDIRECT
:
154 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
157 case PIPE_CAP_VENDOR_ID
:
159 case PIPE_CAP_DEVICE_ID
: {
161 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
162 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
167 case PIPE_CAP_ACCELERATED
:
169 case PIPE_CAP_VIDEO_MEMORY
:
170 return dev
->vram_size
>> 20;
175 debug_printf("unknown param %d\n", param
);
180 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
182 struct nv30_screen
*screen
= nv30_screen(pscreen
);
183 struct nouveau_object
*eng3d
= screen
->eng3d
;
186 case PIPE_CAPF_MAX_LINE_WIDTH
:
187 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
189 case PIPE_CAPF_MAX_POINT_WIDTH
:
190 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
192 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
193 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
194 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
197 debug_printf("unknown paramf %d\n", param
);
203 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
204 enum pipe_shader_cap param
)
206 struct nv30_screen
*screen
= nv30_screen(pscreen
);
207 struct nouveau_object
*eng3d
= screen
->eng3d
;
210 case PIPE_SHADER_VERTEX
:
212 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
213 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
214 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
215 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
216 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
217 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
218 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
220 case PIPE_SHADER_CAP_MAX_INPUTS
:
222 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
223 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
224 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
226 case PIPE_SHADER_CAP_MAX_TEMPS
:
227 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
228 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
229 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
231 case PIPE_SHADER_CAP_MAX_PREDS
:
232 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
233 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
234 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
235 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
236 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
237 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
238 case PIPE_SHADER_CAP_SUBROUTINES
:
239 case PIPE_SHADER_CAP_INTEGERS
:
242 debug_printf("unknown vertex shader param %d\n", param
);
246 case PIPE_SHADER_FRAGMENT
:
248 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
249 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
250 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
251 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
253 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
255 case PIPE_SHADER_CAP_MAX_INPUTS
:
256 return 8; /* should be possible to do 10 with nv4x */
257 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
258 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32) * sizeof(float[4]);
259 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
261 case PIPE_SHADER_CAP_MAX_TEMPS
:
263 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
264 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
266 case PIPE_SHADER_CAP_MAX_PREDS
:
267 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
268 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
269 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
270 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
271 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
272 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
273 case PIPE_SHADER_CAP_SUBROUTINES
:
276 debug_printf("unknown fragment shader param %d\n", param
);
286 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
287 enum pipe_format format
,
288 enum pipe_texture_target target
,
289 unsigned sample_count
,
292 if (sample_count
> 4)
294 if (!(0x00000017 & (1 << sample_count
)))
297 if (!util_format_is_supported(format
, bindings
)) {
301 /* transfers & shared are always supported */
302 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
303 PIPE_BIND_TRANSFER_WRITE
|
306 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
310 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
312 struct nv30_screen
*screen
= nv30_screen(pscreen
);
313 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
315 *sequence
= ++screen
->base
.fence
.sequence
;
317 BEGIN_NV04(push
, NV30_3D(FENCE_OFFSET
), 2);
319 PUSH_DATA (push
, *sequence
);
323 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
325 struct nv30_screen
*screen
= nv30_screen(pscreen
);
326 struct nv04_notify
*fence
= screen
->fence
->data
;
327 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
331 nv30_screen_destroy(struct pipe_screen
*pscreen
)
333 struct nv30_screen
*screen
= nv30_screen(pscreen
);
335 if (!nouveau_drm_screen_unref(&screen
->base
))
338 if (screen
->base
.fence
.current
) {
339 struct nouveau_fence
*current
= NULL
;
341 /* nouveau_fence_wait will create a new current fence, so wait on the
342 * _current_ one, and remove both.
344 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
345 nouveau_fence_wait(current
);
346 nouveau_fence_ref(NULL
, ¤t
);
347 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
350 nouveau_bo_ref(NULL
, &screen
->notify
);
352 nouveau_heap_destroy(&screen
->query_heap
);
353 nouveau_heap_destroy(&screen
->vp_exec_heap
);
354 nouveau_heap_destroy(&screen
->vp_data_heap
);
356 nouveau_object_del(&screen
->query
);
357 nouveau_object_del(&screen
->fence
);
358 nouveau_object_del(&screen
->ntfy
);
360 nouveau_object_del(&screen
->sifm
);
361 nouveau_object_del(&screen
->swzsurf
);
362 nouveau_object_del(&screen
->surf2d
);
363 nouveau_object_del(&screen
->m2mf
);
364 nouveau_object_del(&screen
->eng3d
);
365 nouveau_object_del(&screen
->null
);
367 nouveau_screen_fini(&screen
->base
);
371 #define FAIL_SCREEN_INIT(str, err) \
373 NOUVEAU_ERR(str, err); \
374 nv30_screen_destroy(pscreen); \
379 nv30_screen_create(struct nouveau_device
*dev
)
381 struct nv30_screen
*screen
= CALLOC_STRUCT(nv30_screen
);
382 struct pipe_screen
*pscreen
;
383 struct nouveau_pushbuf
*push
;
384 struct nv04_fifo
*fifo
;
391 switch (dev
->chipset
& 0xf0) {
393 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
394 oclass
= NV30_3D_CLASS
;
396 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
397 oclass
= NV34_3D_CLASS
;
399 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
400 oclass
= NV35_3D_CLASS
;
403 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
404 oclass
= NV40_3D_CLASS
;
406 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
407 oclass
= NV44_3D_CLASS
;
410 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
411 oclass
= NV44_3D_CLASS
;
418 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
423 pscreen
= &screen
->base
.base
;
424 pscreen
->destroy
= nv30_screen_destroy
;
425 pscreen
->get_param
= nv30_screen_get_param
;
426 pscreen
->get_paramf
= nv30_screen_get_paramf
;
427 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
428 pscreen
->context_create
= nv30_context_create
;
429 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
430 nv30_resource_screen_init(pscreen
);
431 nouveau_screen_init_vdec(&screen
->base
);
433 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
434 screen
->base
.fence
.update
= nv30_screen_fence_update
;
436 ret
= nouveau_screen_init(&screen
->base
, dev
);
438 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
440 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
441 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
442 if (oclass
== NV40_3D_CLASS
) {
443 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
444 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
447 fifo
= screen
->base
.channel
->data
;
448 push
= screen
->base
.pushbuf
;
449 push
->rsvd_kick
= 16;
451 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
452 NULL
, 0, &screen
->null
);
454 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
456 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
457 * this means that the address pointed at by the DMA object must
458 * be 4KiB aligned, which means this object needs to be the first
459 * one allocated on the channel.
461 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
462 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
463 .length
= 32 }, sizeof(struct nv04_notify
),
466 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
468 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
469 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
470 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
471 .length
= 32 }, sizeof(struct nv04_notify
),
474 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
476 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
477 * the remainder of the "notifier block" assigned by the kernel for
478 * use as query objects
480 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
481 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
482 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
485 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
487 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
489 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
491 LIST_INITHEAD(&screen
->queries
);
493 /* Vertex program resources (code/data), currently 6 of the constant
494 * slots are reserved to implement user clipping planes
496 if (oclass
< NV40_3D_CLASS
) {
497 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
498 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
500 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
501 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
504 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
506 nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
508 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
510 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
511 NULL
, 0, &screen
->eng3d
);
513 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
515 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
516 PUSH_DATA (push
, screen
->eng3d
->handle
);
517 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
518 PUSH_DATA (push
, screen
->ntfy
->handle
);
519 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
520 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
521 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
522 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
523 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
524 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
525 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
526 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
527 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
528 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
529 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
530 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
531 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
532 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
533 PUSH_DATA (push
, 0x00100000);
534 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
537 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
539 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
540 PUSH_DATA (push
, fui(0.0));
541 PUSH_DATA (push
, fui(0.0));
542 PUSH_DATA (push
, fui(1.0));
543 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
544 for (i
= 0; i
< 16; i
++)
545 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
547 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
550 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
551 PUSH_DATA (push
, fifo
->vram
);
552 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
554 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
555 PUSH_DATA (push
, 0x00000004);
557 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
558 PUSH_DATA (push
, 0x00000010);
559 PUSH_DATA (push
, 0x01000100);
560 PUSH_DATA (push
, 0xff800006);
562 /* vtxprog output routing */
563 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
564 PUSH_DATA (push
, 0x06144321);
565 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
566 PUSH_DATA (push
, 0xedcba987);
567 PUSH_DATA (push
, 0x0000006f);
568 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
569 PUSH_DATA (push
, 0x00171615);
570 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
571 PUSH_DATA (push
, 0x001b1a19);
573 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
574 PUSH_DATA (push
, 0x0020ffff);
575 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
576 PUSH_DATA (push
, 0x01d300d4);
578 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
579 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
582 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
583 NULL
, 0, &screen
->m2mf
);
585 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
587 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
588 PUSH_DATA (push
, screen
->m2mf
->handle
);
589 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
590 PUSH_DATA (push
, screen
->ntfy
->handle
);
592 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
593 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
595 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
597 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
598 PUSH_DATA (push
, screen
->surf2d
->handle
);
599 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
600 PUSH_DATA (push
, screen
->ntfy
->handle
);
602 if (dev
->chipset
< 0x40)
603 oclass
= NV30_SURFACE_SWZ_CLASS
;
605 oclass
= NV40_SURFACE_SWZ_CLASS
;
607 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
608 NULL
, 0, &screen
->swzsurf
);
610 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
612 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
613 PUSH_DATA (push
, screen
->swzsurf
->handle
);
614 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
615 PUSH_DATA (push
, screen
->ntfy
->handle
);
617 if (dev
->chipset
< 0x40)
618 oclass
= NV30_SIFM_CLASS
;
620 oclass
= NV40_SIFM_CLASS
;
622 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
623 NULL
, 0, &screen
->sifm
);
625 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
627 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
628 PUSH_DATA (push
, screen
->sifm
->handle
);
629 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
630 PUSH_DATA (push
, screen
->ntfy
->handle
);
631 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
632 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
634 nouveau_pushbuf_kick(push
, push
->channel
);
636 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);