src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    /* supported capabilities */
  66    case PIPE_CAP_TWO_SIDED_STENCIL:
  67    case PIPE_CAP_ANISOTROPIC_FILTER:
  68    case PIPE_CAP_POINT_SPRITE:
  69    case PIPE_CAP_OCCLUSION_QUERY:
  70    case PIPE_CAP_QUERY_TIME_ELAPSED:
  71    case PIPE_CAP_QUERY_TIMESTAMP:
  72    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  73    case PIPE_CAP_TEXTURE_SWIZZLE:
  74    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  75    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  77    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  78    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79    case PIPE_CAP_TGSI_TEXCOORD:
  80    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  81    case PIPE_CAP_USER_INDEX_BUFFERS:
  82       return 1;
  83    case PIPE_CAP_USER_VERTEX_BUFFERS:
  84       return 0;
  85    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  86       return 16;
  87    /* nv4x capabilities */
  88    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  89    case PIPE_CAP_NPOT_TEXTURES:
  90    case PIPE_CAP_CONDITIONAL_RENDER:
  91    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  92    case PIPE_CAP_PRIMITIVE_RESTART:
  93       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  94    /* unsupported */
  95    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  96    case PIPE_CAP_SM3:
  97    case PIPE_CAP_INDEP_BLEND_ENABLE:
  98    case PIPE_CAP_INDEP_BLEND_FUNC:
  99    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 100    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 101    case PIPE_CAP_TGSI_INSTANCEID:
 102    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 103    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 104    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 108    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 109    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 110    case PIPE_CAP_TEXTURE_BARRIER:
 111    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113    case PIPE_CAP_CUBE_MAP_ARRAY:
 114    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 115    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 116    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 117    case PIPE_CAP_START_INSTANCE:
 118    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 119    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 120    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 121    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 122    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 123    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 124    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 125    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 126    case PIPE_CAP_TGSI_VS_LAYER:
 127       return 0;
 128    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 129    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 130    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 131    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 132       return 1;
 133    case PIPE_CAP_ENDIANNESS:
 134       return PIPE_ENDIAN_LITTLE;
 135    default:
 136       debug_printf("unknown param %d\n", param);
 137       return 0;
 138    }
 139 }
 140
 141 static float
 142 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 143 {
 144    struct nv30_screen *screen = nv30_screen(pscreen);
 145    struct nouveau_object *eng3d = screen->eng3d;
 146
 147    switch (param) {
 148    case PIPE_CAPF_MAX_LINE_WIDTH:
 149    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 150       return 10.0;
 151    case PIPE_CAPF_MAX_POINT_WIDTH:
 152    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 153       return 64.0;
 154    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 155       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 156    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 157       return 15.0;
 158    default:
 159       debug_printf("unknown paramf %d\n", param);
 160       return 0;
 161    }
 162 }
 163
 164 static int
 165 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 166                              enum pipe_shader_cap param)
 167 {
 168    struct nv30_screen *screen = nv30_screen(pscreen);
 169    struct nouveau_object *eng3d = screen->eng3d;
 170
 171    switch (shader) {
 172    case PIPE_SHADER_VERTEX:
 173       switch (param) {
 174       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 175       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 176          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 177       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 178       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 179          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 180       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 181          return 0;
 182       case PIPE_SHADER_CAP_MAX_INPUTS:
 183          return 16;
 184       case PIPE_SHADER_CAP_MAX_CONSTS:
 185          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 186       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 187          return 1;
 188       case PIPE_SHADER_CAP_MAX_TEMPS:
 189          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 190       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 191       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 192          return 0;
 193       case PIPE_SHADER_CAP_MAX_ADDRS:
 194          return 2;
 195       case PIPE_SHADER_CAP_MAX_PREDS:
 196       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 197       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 198       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 199       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 200       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 201       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 202       case PIPE_SHADER_CAP_SUBROUTINES:
 203       case PIPE_SHADER_CAP_INTEGERS:
 204          return 0;
 205       default:
 206          debug_printf("unknown vertex shader param %d\n", param);
 207          return 0;
 208       }
 209       break;
 210    case PIPE_SHADER_FRAGMENT:
 211       switch (param) {
 212       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 213       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 214       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 215       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 216          return 4096;
 217       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 218          return 0;
 219       case PIPE_SHADER_CAP_MAX_INPUTS:
 220          return 8; /* should be possible to do 10 with nv4x */
 221       case PIPE_SHADER_CAP_MAX_CONSTS:
 222          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 223       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 224          return 1;
 225       case PIPE_SHADER_CAP_MAX_TEMPS:
 226          return 32;
 227       case PIPE_SHADER_CAP_MAX_ADDRS:
 228          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 229       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 230       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 231          return 16;
 232       case PIPE_SHADER_CAP_MAX_PREDS:
 233       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 234       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 235       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 236       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 237       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 238       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 239       case PIPE_SHADER_CAP_SUBROUTINES:
 240          return 0;
 241       default:
 242          debug_printf("unknown fragment shader param %d\n", param);
 243          return 0;
 244       }
 245       break;
 246    default:
 247       return 0;
 248    }
 249 }
 250
 251 static boolean
 252 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 253                                 enum pipe_format format,
 254                                 enum pipe_texture_target target,
 255                                 unsigned sample_count,
 256                                 unsigned bindings)
 257 {
 258    if (sample_count > 4)
 259       return FALSE;
 260    if (!(0x00000017 & (1 << sample_count)))
 261       return FALSE;
 262
 263    if (!util_format_is_supported(format, bindings)) {
 264       return FALSE;
 265    }
 266
 267    /* transfers & shared are always supported */
 268    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 269                  PIPE_BIND_TRANSFER_WRITE |
 270                  PIPE_BIND_SHARED);
 271
 272    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 273 }
 274
 275 static void
 276 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 277 {
 278    struct nv30_screen *screen = nv30_screen(pscreen);
 279    struct nouveau_pushbuf *push = screen->base.pushbuf;
 280
 281    *sequence = ++screen->base.fence.sequence;
 282
 283    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 284    PUSH_DATA (push, 0);
 285    PUSH_DATA (push, *sequence);
 286 }
 287
 288 static uint32_t
 289 nv30_screen_fence_update(struct pipe_screen *pscreen)
 290 {
 291    struct nv30_screen *screen = nv30_screen(pscreen);
 292    struct nv04_notify *fence = screen->fence->data;
 293    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 294 }
 295
 296 static void
 297 nv30_screen_destroy(struct pipe_screen *pscreen)
 298 {
 299    struct nv30_screen *screen = nv30_screen(pscreen);
 300
 301    if (screen->base.fence.current &&
 302        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 303       nouveau_fence_wait(screen->base.fence.current);
 304       nouveau_fence_ref (NULL, &screen->base.fence.current);
 305    }
 306
 307    nouveau_object_del(&screen->query);
 308    nouveau_object_del(&screen->fence);
 309    nouveau_object_del(&screen->ntfy);
 310
 311    nouveau_object_del(&screen->sifm);
 312    nouveau_object_del(&screen->swzsurf);
 313    nouveau_object_del(&screen->surf2d);
 314    nouveau_object_del(&screen->m2mf);
 315    nouveau_object_del(&screen->eng3d);
 316    nouveau_object_del(&screen->null);
 317
 318    nouveau_screen_fini(&screen->base);
 319    FREE(screen);
 320 }
 321
 322 #define FAIL_SCREEN_INIT(str, err)                    \
 323    do {                                               \
 324       NOUVEAU_ERR(str, err);                          \
 325       nv30_screen_destroy(pscreen);                   \
 326       return NULL;                                    \
 327    } while(0)
 328
 329 struct pipe_screen *
 330 nv30_screen_create(struct nouveau_device *dev)
 331 {
 332    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 333    struct pipe_screen *pscreen;
 334    struct nouveau_pushbuf *push;
 335    struct nv04_fifo *fifo;
 336    unsigned oclass = 0;
 337    int ret, i;
 338
 339    if (!screen)
 340       return NULL;
 341
 342    switch (dev->chipset & 0xf0) {
 343    case 0x30:
 344       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 345          oclass = NV30_3D_CLASS;
 346       else
 347       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 348          oclass = NV34_3D_CLASS;
 349       else
 350       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 351          oclass = NV35_3D_CLASS;
 352       break;
 353    case 0x40:
 354       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 355          oclass = NV40_3D_CLASS;
 356       else
 357       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 358          oclass = NV44_3D_CLASS;
 359       break;
 360    case 0x60:
 361       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 362          oclass = NV44_3D_CLASS;
 363       break;
 364    default:
 365       break;
 366    }
 367
 368    if (!oclass) {
 369       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 370       FREE(screen);
 371       return NULL;
 372    }
 373
 374    pscreen = &screen->base.base;
 375    pscreen->destroy = nv30_screen_destroy;
 376    pscreen->get_param = nv30_screen_get_param;
 377    pscreen->get_paramf = nv30_screen_get_paramf;
 378    pscreen->get_shader_param = nv30_screen_get_shader_param;
 379    pscreen->context_create = nv30_context_create;
 380    pscreen->is_format_supported = nv30_screen_is_format_supported;
 381    nv30_resource_screen_init(pscreen);
 382    nouveau_screen_init_vdec(&screen->base);
 383
 384    screen->base.fence.emit = nv30_screen_fence_emit;
 385    screen->base.fence.update = nv30_screen_fence_update;
 386
 387    ret = nouveau_screen_init(&screen->base, dev);
 388    if (ret)
 389       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 390
 391    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 392    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 393    if (oclass == NV40_3D_CLASS) {
 394       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 395       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 396    }
 397
 398    fifo = screen->base.channel->data;
 399    push = screen->base.pushbuf;
 400    push->rsvd_kick = 16;
 401
 402    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 403                             NULL, 0, &screen->null);
 404    if (ret)
 405       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 406
 407    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 408     * this means that the address pointed at by the DMA object must
 409     * be 4KiB aligned, which means this object needs to be the first
 410     * one allocated on the channel.
 411     */
 412    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 413                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 414                             .length = 32 }, sizeof(struct nv04_notify),
 415                             &screen->fence);
 416    if (ret)
 417       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 418
 419    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 420    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 421                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 422                             .length = 32 }, sizeof(struct nv04_notify),
 423                             &screen->ntfy);
 424    if (ret)
 425       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 426
 427    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 428     * the remainder of the "notifier block" assigned by the kernel for
 429     * use as query objects
 430     */
 431    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 432                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 433                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 434                             &screen->query);
 435    if (ret)
 436       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 437
 438    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 439    if (ret)
 440       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 441
 442    LIST_INITHEAD(&screen->queries);
 443
 444    /* Vertex program resources (code/data), currently 6 of the constant
 445     * slots are reserved to implement user clipping planes
 446     */
 447    if (oclass < NV40_3D_CLASS) {
 448       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 449       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 450    } else {
 451       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 452       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 453    }
 454
 455    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 456    if (ret == 0)
 457       nouveau_bo_map(screen->notify, 0, screen->base.client);
 458    if (ret)
 459       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 460
 461    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 462                             NULL, 0, &screen->eng3d);
 463    if (ret)
 464       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 465
 466    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 467    PUSH_DATA (push, screen->eng3d->handle);
 468    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 469    PUSH_DATA (push, screen->ntfy->handle);
 470    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 471    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 472    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 473    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 474    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 475    PUSH_DATA (push, fifo->vram);     /* ZETA */
 476    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 477    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 478    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 479    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 480    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 481    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 482    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 483       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 484       PUSH_DATA (push, 0x00100000);
 485       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 486       PUSH_DATA (push, 3);
 487
 488       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 489       PUSH_DATA (push, 0);
 490       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 491       PUSH_DATA (push, fui(0.0));
 492       PUSH_DATA (push, fui(0.0));
 493       PUSH_DATA (push, fui(1.0));
 494       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 495       for (i = 0; i < 16; i++)
 496          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 497
 498       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 499       PUSH_DATA (push, 0);
 500    } else {
 501       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 502       PUSH_DATA (push, fifo->vram);
 503       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 504
 505       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 506       PUSH_DATA (push, 0x00000004);
 507
 508       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 509       PUSH_DATA (push, 0x00000010);
 510       PUSH_DATA (push, 0x01000100);
 511       PUSH_DATA (push, 0xff800006);
 512
 513       /* vtxprog output routing */
 514       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 515       PUSH_DATA (push, 0x06144321);
 516       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 517       PUSH_DATA (push, 0xedcba987);
 518       PUSH_DATA (push, 0x0000006f);
 519       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 520       PUSH_DATA (push, 0x00171615);
 521       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 522       PUSH_DATA (push, 0x001b1a19);
 523
 524       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 525       PUSH_DATA (push, 0x0020ffff);
 526       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 527       PUSH_DATA (push, 0x01d300d4);
 528
 529       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 530       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 531    }
 532
 533    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 534                             NULL, 0, &screen->m2mf);
 535    if (ret)
 536       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 537
 538    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 539    PUSH_DATA (push, screen->m2mf->handle);
 540    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 541    PUSH_DATA (push, screen->ntfy->handle);
 542
 543    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 544                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 545    if (ret)
 546       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 547
 548    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 549    PUSH_DATA (push, screen->surf2d->handle);
 550    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 551    PUSH_DATA (push, screen->ntfy->handle);
 552
 553    if (dev->chipset < 0x40)
 554       oclass = NV30_SURFACE_SWZ_CLASS;
 555    else
 556       oclass = NV40_SURFACE_SWZ_CLASS;
 557
 558    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 559                             NULL, 0, &screen->swzsurf);
 560    if (ret)
 561       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 562
 563    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 564    PUSH_DATA (push, screen->swzsurf->handle);
 565    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 566    PUSH_DATA (push, screen->ntfy->handle);
 567
 568    if (dev->chipset < 0x40)
 569       oclass = NV30_SIFM_CLASS;
 570    else
 571       oclass = NV40_SIFM_CLASS;
 572
 573    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 574                             NULL, 0, &screen->sifm);
 575    if (ret)
 576       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 577
 578    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 579    PUSH_DATA (push, screen->sifm->handle);
 580    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 581    PUSH_DATA (push, screen->ntfy->handle);
 582    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 583    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 584
 585    nouveau_pushbuf_kick(push, push->channel);
 586
 587    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 588    return pscreen;
 589 }