src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_USER_INDEX_BUFFERS:
  95    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  99    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 162    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 163    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_CLIP_HALFZ:
 166    case PIPE_CAP_VERTEXID_NOBASE:
 167    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_TGSI_TXQS:
 175    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 176    case PIPE_CAP_SHAREABLE_SHADERS:
 177    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 178    case PIPE_CAP_CLEAR_TEXTURE:
 179    case PIPE_CAP_DRAW_PARAMETERS:
 180    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 181    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 182    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 183    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184    case PIPE_CAP_INVALIDATE_BUFFER:
 185    case PIPE_CAP_GENERATE_MIPMAP:
 186       return 0;
 187
 188    case PIPE_CAP_VENDOR_ID:
 189       return 0x10de;
 190    case PIPE_CAP_DEVICE_ID: {
 191       uint64_t device_id;
 192       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 193          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 194          return -1;
 195       }
 196       return device_id;
 197    }
 198    case PIPE_CAP_ACCELERATED:
 199       return 1;
 200    case PIPE_CAP_VIDEO_MEMORY:
 201       return dev->vram_size >> 20;
 202    case PIPE_CAP_UMA:
 203       return 0;
 204    }
 205
 206    debug_printf("unknown param %d\n", param);
 207    return 0;
 208 }
 209
 210 static float
 211 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 212 {
 213    struct nv30_screen *screen = nv30_screen(pscreen);
 214    struct nouveau_object *eng3d = screen->eng3d;
 215
 216    switch (param) {
 217    case PIPE_CAPF_MAX_LINE_WIDTH:
 218    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 219       return 10.0;
 220    case PIPE_CAPF_MAX_POINT_WIDTH:
 221    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 222       return 64.0;
 223    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 224       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 225    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 226       return 15.0;
 227    default:
 228       debug_printf("unknown paramf %d\n", param);
 229       return 0;
 230    }
 231 }
 232
 233 static int
 234 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 235                              enum pipe_shader_cap param)
 236 {
 237    struct nv30_screen *screen = nv30_screen(pscreen);
 238    struct nouveau_object *eng3d = screen->eng3d;
 239
 240    switch (shader) {
 241    case PIPE_SHADER_VERTEX:
 242       switch (param) {
 243       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 244       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 245          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 246       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 247       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 248          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 249       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 250          return 0;
 251       case PIPE_SHADER_CAP_MAX_INPUTS:
 252       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 253          return 16;
 254       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 255          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 256       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 257          return 1;
 258       case PIPE_SHADER_CAP_MAX_TEMPS:
 259          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 260       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 261       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 262          return 0;
 263       case PIPE_SHADER_CAP_MAX_PREDS:
 264       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 265       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 266       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 267       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 268       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 269       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 270       case PIPE_SHADER_CAP_SUBROUTINES:
 271       case PIPE_SHADER_CAP_INTEGERS:
 272       case PIPE_SHADER_CAP_DOUBLES:
 273       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 274       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 275       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 276       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 277       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 278          return 0;
 279       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 280          return 32;
 281       default:
 282          debug_printf("unknown vertex shader param %d\n", param);
 283          return 0;
 284       }
 285       break;
 286    case PIPE_SHADER_FRAGMENT:
 287       switch (param) {
 288       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 289       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 290       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 291       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 292          return 4096;
 293       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 294          return 0;
 295       case PIPE_SHADER_CAP_MAX_INPUTS:
 296          return 8; /* should be possible to do 10 with nv4x */
 297       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 298          return 4;
 299       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 300          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 301       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 302          return 1;
 303       case PIPE_SHADER_CAP_MAX_TEMPS:
 304          return 32;
 305       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 306       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 307          return 16;
 308       case PIPE_SHADER_CAP_MAX_PREDS:
 309       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 310       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 311       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 312       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 313       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 314       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 315       case PIPE_SHADER_CAP_SUBROUTINES:
 316       case PIPE_SHADER_CAP_DOUBLES:
 317       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 318       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 319       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 320       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 321       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 322          return 0;
 323       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 324          return 32;
 325       default:
 326          debug_printf("unknown fragment shader param %d\n", param);
 327          return 0;
 328       }
 329       break;
 330    default:
 331       return 0;
 332    }
 333 }
 334
 335 static boolean
 336 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 337                                 enum pipe_format format,
 338                                 enum pipe_texture_target target,
 339                                 unsigned sample_count,
 340                                 unsigned bindings)
 341 {
 342    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 343       return false;
 344
 345    if (!(0x00000017 & (1 << sample_count)))
 346       return false;
 347
 348    if (!util_format_is_supported(format, bindings)) {
 349       return false;
 350    }
 351
 352    /* transfers & shared are always supported */
 353    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 354                  PIPE_BIND_TRANSFER_WRITE |
 355                  PIPE_BIND_SHARED);
 356
 357    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 358 }
 359
 360 static void
 361 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 362 {
 363    struct nv30_screen *screen = nv30_screen(pscreen);
 364    struct nouveau_pushbuf *push = screen->base.pushbuf;
 365
 366    *sequence = ++screen->base.fence.sequence;
 367
 368    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 369    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 370               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 371    PUSH_DATA (push, 0);
 372    PUSH_DATA (push, *sequence);
 373 }
 374
 375 static uint32_t
 376 nv30_screen_fence_update(struct pipe_screen *pscreen)
 377 {
 378    struct nv30_screen *screen = nv30_screen(pscreen);
 379    struct nv04_notify *fence = screen->fence->data;
 380    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 381 }
 382
 383 static void
 384 nv30_screen_destroy(struct pipe_screen *pscreen)
 385 {
 386    struct nv30_screen *screen = nv30_screen(pscreen);
 387
 388    if (!nouveau_drm_screen_unref(&screen->base))
 389       return;
 390
 391    if (screen->base.fence.current) {
 392       struct nouveau_fence *current = NULL;
 393
 394       /* nouveau_fence_wait will create a new current fence, so wait on the
 395        * _current_ one, and remove both.
 396        */
 397       nouveau_fence_ref(screen->base.fence.current, &current);
 398       nouveau_fence_wait(current, NULL);
 399       nouveau_fence_ref(NULL, &current);
 400       nouveau_fence_ref(NULL, &screen->base.fence.current);
 401    }
 402
 403    nouveau_bo_ref(NULL, &screen->notify);
 404
 405    nouveau_heap_destroy(&screen->query_heap);
 406    nouveau_heap_destroy(&screen->vp_exec_heap);
 407    nouveau_heap_destroy(&screen->vp_data_heap);
 408
 409    nouveau_object_del(&screen->query);
 410    nouveau_object_del(&screen->fence);
 411    nouveau_object_del(&screen->ntfy);
 412
 413    nouveau_object_del(&screen->sifm);
 414    nouveau_object_del(&screen->swzsurf);
 415    nouveau_object_del(&screen->surf2d);
 416    nouveau_object_del(&screen->m2mf);
 417    nouveau_object_del(&screen->eng3d);
 418    nouveau_object_del(&screen->null);
 419
 420    nouveau_screen_fini(&screen->base);
 421    FREE(screen);
 422 }
 423
 424 #define FAIL_SCREEN_INIT(str, err)                    \
 425    do {                                               \
 426       NOUVEAU_ERR(str, err);                          \
 427       screen->base.base.context_create = NULL;        \
 428       return &screen->base;                           \
 429    } while(0)
 430
 431 struct nouveau_screen *
 432 nv30_screen_create(struct nouveau_device *dev)
 433 {
 434    struct nv30_screen *screen;
 435    struct pipe_screen *pscreen;
 436    struct nouveau_pushbuf *push;
 437    struct nv04_fifo *fifo;
 438    unsigned oclass = 0;
 439    int ret, i;
 440
 441    switch (dev->chipset & 0xf0) {
 442    case 0x30:
 443       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 444          oclass = NV30_3D_CLASS;
 445       else
 446       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 447          oclass = NV34_3D_CLASS;
 448       else
 449       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 450          oclass = NV35_3D_CLASS;
 451       break;
 452    case 0x40:
 453       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 454          oclass = NV40_3D_CLASS;
 455       else
 456       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 457          oclass = NV44_3D_CLASS;
 458       break;
 459    case 0x60:
 460       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 461          oclass = NV44_3D_CLASS;
 462       break;
 463    default:
 464       break;
 465    }
 466
 467    if (!oclass) {
 468       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 469       return NULL;
 470    }
 471
 472    screen = CALLOC_STRUCT(nv30_screen);
 473    if (!screen)
 474       return NULL;
 475
 476    pscreen = &screen->base.base;
 477    pscreen->destroy = nv30_screen_destroy;
 478
 479    /*
 480     * Some modern apps try to use msaa without keeping in mind the
 481     * restrictions on videomem of older cards. Resulting in dmesg saying:
 482     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 483     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 484     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 485     *
 486     * Because we are running out of video memory, after which the program
 487     * using the msaa visual freezes, and eventually the entire system freezes.
 488     *
 489     * To work around this we do not allow msaa visauls by default and allow
 490     * the user to override this via NV30_MAX_MSAA.
 491     */
 492    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 493    if (screen->max_sample_count > 4)
 494       screen->max_sample_count = 4;
 495
 496    pscreen->get_param = nv30_screen_get_param;
 497    pscreen->get_paramf = nv30_screen_get_paramf;
 498    pscreen->get_shader_param = nv30_screen_get_shader_param;
 499    pscreen->context_create = nv30_context_create;
 500    pscreen->is_format_supported = nv30_screen_is_format_supported;
 501    nv30_resource_screen_init(pscreen);
 502    nouveau_screen_init_vdec(&screen->base);
 503
 504    screen->base.fence.emit = nv30_screen_fence_emit;
 505    screen->base.fence.update = nv30_screen_fence_update;
 506
 507    ret = nouveau_screen_init(&screen->base, dev);
 508    if (ret)
 509       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 510
 511    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 512    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 513    if (oclass == NV40_3D_CLASS) {
 514       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 515       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 516    }
 517
 518    fifo = screen->base.channel->data;
 519    push = screen->base.pushbuf;
 520    push->rsvd_kick = 16;
 521
 522    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 523                             NULL, 0, &screen->null);
 524    if (ret)
 525       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 526
 527    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 528     * this means that the address pointed at by the DMA object must
 529     * be 4KiB aligned, which means this object needs to be the first
 530     * one allocated on the channel.
 531     */
 532    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 533                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 534                             .length = 32 }, sizeof(struct nv04_notify),
 535                             &screen->fence);
 536    if (ret)
 537       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 538
 539    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 540    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 541                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 542                             .length = 32 }, sizeof(struct nv04_notify),
 543                             &screen->ntfy);
 544    if (ret)
 545       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 546
 547    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 548     * the remainder of the "notifier block" assigned by the kernel for
 549     * use as query objects
 550     */
 551    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 552                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 553                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 554                             &screen->query);
 555    if (ret)
 556       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 557
 558    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 559    if (ret)
 560       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 561
 562    LIST_INITHEAD(&screen->queries);
 563
 564    /* Vertex program resources (code/data), currently 6 of the constant
 565     * slots are reserved to implement user clipping planes
 566     */
 567    if (oclass < NV40_3D_CLASS) {
 568       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 569       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 570    } else {
 571       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 572       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 573    }
 574
 575    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 576    if (ret == 0)
 577       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 578    if (ret)
 579       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 580
 581    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 582                             NULL, 0, &screen->eng3d);
 583    if (ret)
 584       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 585
 586    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 587    PUSH_DATA (push, screen->eng3d->handle);
 588    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 589    PUSH_DATA (push, screen->ntfy->handle);
 590    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 591    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 592    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 593    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 594    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 595    PUSH_DATA (push, fifo->vram);     /* ZETA */
 596    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 597    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 598    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 599    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 600    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 601    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 602    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 603       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 604       PUSH_DATA (push, 0x00100000);
 605       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 606       PUSH_DATA (push, 3);
 607
 608       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 609       PUSH_DATA (push, 0);
 610       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 611       PUSH_DATA (push, fui(0.0));
 612       PUSH_DATA (push, fui(0.0));
 613       PUSH_DATA (push, fui(1.0));
 614       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 615       for (i = 0; i < 16; i++)
 616          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 617
 618       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 619       PUSH_DATA (push, 0);
 620    } else {
 621       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 622       PUSH_DATA (push, fifo->vram);
 623       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 624
 625       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 626       PUSH_DATA (push, 0x00000004);
 627
 628       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 629       PUSH_DATA (push, 0x00000010);
 630       PUSH_DATA (push, 0x01000100);
 631       PUSH_DATA (push, 0xff800006);
 632
 633       /* vtxprog output routing */
 634       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 635       PUSH_DATA (push, 0x06144321);
 636       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 637       PUSH_DATA (push, 0xedcba987);
 638       PUSH_DATA (push, 0x0000006f);
 639       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 640       PUSH_DATA (push, 0x00171615);
 641       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 642       PUSH_DATA (push, 0x001b1a19);
 643
 644       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 645       PUSH_DATA (push, 0x0020ffff);
 646       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 647       PUSH_DATA (push, 0x01d300d4);
 648
 649       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 650       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 651    }
 652
 653    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 654                             NULL, 0, &screen->m2mf);
 655    if (ret)
 656       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 657
 658    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 659    PUSH_DATA (push, screen->m2mf->handle);
 660    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 661    PUSH_DATA (push, screen->ntfy->handle);
 662
 663    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 664                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 665    if (ret)
 666       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 667
 668    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 669    PUSH_DATA (push, screen->surf2d->handle);
 670    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 671    PUSH_DATA (push, screen->ntfy->handle);
 672
 673    if (dev->chipset < 0x40)
 674       oclass = NV30_SURFACE_SWZ_CLASS;
 675    else
 676       oclass = NV40_SURFACE_SWZ_CLASS;
 677
 678    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 679                             NULL, 0, &screen->swzsurf);
 680    if (ret)
 681       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 682
 683    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 684    PUSH_DATA (push, screen->swzsurf->handle);
 685    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 686    PUSH_DATA (push, screen->ntfy->handle);
 687
 688    if (dev->chipset < 0x40)
 689       oclass = NV30_SIFM_CLASS;
 690    else
 691       oclass = NV40_SIFM_CLASS;
 692
 693    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 694                             NULL, 0, &screen->sifm);
 695    if (ret)
 696       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 697
 698    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 699    PUSH_DATA (push, screen->sifm->handle);
 700    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 701    PUSH_DATA (push, screen->ntfy->handle);
 702    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 703    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 704
 705    nouveau_pushbuf_kick(push, push->channel);
 706
 707    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 708    return &screen->base;
 709 }