src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
  68       return 120;
  69    case PIPE_CAP_ENDIANNESS:
  70       return PIPE_ENDIAN_LITTLE;
  71    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  72       return 16;
  73    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  74       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  75    case PIPE_CAP_MAX_VIEWPORTS:
  76       return 1;
  77    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  78       return 2048;
  79    /* supported capabilities */
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SWIZZLE:
  86    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  87    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  91    case PIPE_CAP_TGSI_TEXCOORD:
  92    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  93    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  94    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  95    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
  98       return 1;
  99    /* nv35 capabilities */
 100    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 101       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 102    /* nv4x capabilities */
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_NPOT_TEXTURES:
 105    case PIPE_CAP_CONDITIONAL_RENDER:
 106    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 107    case PIPE_CAP_PRIMITIVE_RESTART:
 108       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 109    /* unsupported */
 110    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 111    case PIPE_CAP_SM3:
 112    case PIPE_CAP_INDEP_BLEND_ENABLE:
 113    case PIPE_CAP_INDEP_BLEND_FUNC:
 114    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 115    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 116    case PIPE_CAP_TGSI_INSTANCEID:
 117    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 121    case PIPE_CAP_MIN_TEXEL_OFFSET:
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 128    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 129    case PIPE_CAP_MAX_VERTEX_STREAMS:
 130    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 134    case PIPE_CAP_CUBE_MAP_ARRAY:
 135    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 136    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 137    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 138    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 139    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 140    case PIPE_CAP_START_INSTANCE:
 141    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 142    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 143    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 144    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 145    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 146    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 147    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 148    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 149    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 150    case PIPE_CAP_TEXTURE_GATHER_SM5:
 151    case PIPE_CAP_FAKE_SW_MSAA:
 152    case PIPE_CAP_TEXTURE_QUERY_LOD:
 153    case PIPE_CAP_SAMPLE_SHADING:
 154    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 155    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 156    case PIPE_CAP_USER_VERTEX_BUFFERS:
 157    case PIPE_CAP_COMPUTE:
 158    case PIPE_CAP_DRAW_INDIRECT:
 159    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 161    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 162    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 163    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 164    case PIPE_CAP_CLIP_HALFZ:
 165    case PIPE_CAP_VERTEXID_NOBASE:
 166    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 167    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 168    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 169    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 170    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 171    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 172    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 173    case PIPE_CAP_TGSI_TXQS:
 174    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 175    case PIPE_CAP_SHAREABLE_SHADERS:
 176    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 177    case PIPE_CAP_CLEAR_TEXTURE:
 178    case PIPE_CAP_DRAW_PARAMETERS:
 179    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 180    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 181    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 182    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 183    case PIPE_CAP_INVALIDATE_BUFFER:
 184    case PIPE_CAP_GENERATE_MIPMAP:
 185    case PIPE_CAP_STRING_MARKER:
 186    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 187    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 188    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 189    case PIPE_CAP_QUERY_MEMORY_INFO:
 190    case PIPE_CAP_PCI_GROUP:
 191    case PIPE_CAP_PCI_BUS:
 192    case PIPE_CAP_PCI_DEVICE:
 193    case PIPE_CAP_PCI_FUNCTION:
 194    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 195    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 196    case PIPE_CAP_CULL_DISTANCE:
 197    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 198    case PIPE_CAP_TGSI_VOTE:
 199    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 200    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 201    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 202    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 203    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 204    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 205    case PIPE_CAP_NATIVE_FENCE_FD:
 206    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 207    case PIPE_CAP_TGSI_FS_FBFETCH:
 208    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 209    case PIPE_CAP_DOUBLES:
 210    case PIPE_CAP_INT64:
 211    case PIPE_CAP_INT64_DIVMOD:
 212    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 213    case PIPE_CAP_TGSI_CLOCK:
 214    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 215    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 216    case PIPE_CAP_TGSI_BALLOT:
 217    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 218    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 219    case PIPE_CAP_POST_DEPTH_COVERAGE:
 220    case PIPE_CAP_BINDLESS_TEXTURE:
 221    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 222    case PIPE_CAP_QUERY_SO_OVERFLOW:
 223    case PIPE_CAP_MEMOBJ:
 224    case PIPE_CAP_LOAD_CONSTBUF:
 225    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 226    case PIPE_CAP_TILE_RASTER_ORDER:
 227    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 228    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 229    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 230    case PIPE_CAP_FENCE_SIGNAL:
 231    case PIPE_CAP_CONSTBUF0_FLAGS:
 232    case PIPE_CAP_PACKED_UNIFORMS:
 233    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 234    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 235    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 236    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 237    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 238    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 239    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 240       return 0;
 241
 242    case PIPE_CAP_VENDOR_ID:
 243       return 0x10de;
 244    case PIPE_CAP_DEVICE_ID: {
 245       uint64_t device_id;
 246       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 247          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 248          return -1;
 249       }
 250       return device_id;
 251    }
 252    case PIPE_CAP_ACCELERATED:
 253       return 1;
 254    case PIPE_CAP_VIDEO_MEMORY:
 255       return dev->vram_size >> 20;
 256    case PIPE_CAP_UMA:
 257       return 0;
 258    }
 259
 260    debug_printf("unknown param %d\n", param);
 261    return 0;
 262 }
 263
 264 static float
 265 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 266 {
 267    struct nv30_screen *screen = nv30_screen(pscreen);
 268    struct nouveau_object *eng3d = screen->eng3d;
 269
 270    switch (param) {
 271    case PIPE_CAPF_MAX_LINE_WIDTH:
 272    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 273       return 10.0;
 274    case PIPE_CAPF_MAX_POINT_WIDTH:
 275    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 276       return 64.0;
 277    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 278       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 279    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 280       return 15.0;
 281    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 282    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 283    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 284       return 0.0;
 285    default:
 286       debug_printf("unknown paramf %d\n", param);
 287       return 0;
 288    }
 289 }
 290
 291 static int
 292 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 293                              enum pipe_shader_type shader,
 294                              enum pipe_shader_cap param)
 295 {
 296    struct nv30_screen *screen = nv30_screen(pscreen);
 297    struct nouveau_object *eng3d = screen->eng3d;
 298
 299    switch (shader) {
 300    case PIPE_SHADER_VERTEX:
 301       switch (param) {
 302       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 303       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 304          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 305       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 306       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 307          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 308       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 309          return 0;
 310       case PIPE_SHADER_CAP_MAX_INPUTS:
 311       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 312          return 16;
 313       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 314          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 315       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 316          return 1;
 317       case PIPE_SHADER_CAP_MAX_TEMPS:
 318          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 319       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 320          return 32;
 321       case PIPE_SHADER_CAP_PREFERRED_IR:
 322          return PIPE_SHADER_IR_TGSI;
 323       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 324       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 325          return 0;
 326       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 327       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 328       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 329       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 330       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 331       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 332       case PIPE_SHADER_CAP_SUBROUTINES:
 333       case PIPE_SHADER_CAP_INTEGERS:
 334       case PIPE_SHADER_CAP_INT64_ATOMICS:
 335       case PIPE_SHADER_CAP_FP16:
 336       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 337       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 338       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 339       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 340       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 341       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 342       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 343       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 344       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 345       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 346       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 347          return 0;
 348       default:
 349          debug_printf("unknown vertex shader param %d\n", param);
 350          return 0;
 351       }
 352       break;
 353    case PIPE_SHADER_FRAGMENT:
 354       switch (param) {
 355       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 356       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 357       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 358       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 359          return 4096;
 360       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 361          return 0;
 362       case PIPE_SHADER_CAP_MAX_INPUTS:
 363          return 8; /* should be possible to do 10 with nv4x */
 364       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 365          return 4;
 366       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 367          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 368       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 369          return 1;
 370       case PIPE_SHADER_CAP_MAX_TEMPS:
 371          return 32;
 372       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 373       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 374          return 16;
 375       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 376          return 32;
 377       case PIPE_SHADER_CAP_PREFERRED_IR:
 378          return PIPE_SHADER_IR_TGSI;
 379       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 380       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 381       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 382       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 383       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 384       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 385       case PIPE_SHADER_CAP_SUBROUTINES:
 386       case PIPE_SHADER_CAP_INTEGERS:
 387       case PIPE_SHADER_CAP_FP16:
 388       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 389       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 390       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 391       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 392       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 393       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 394       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 395       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 396       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 397       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 398       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 399          return 0;
 400       default:
 401          debug_printf("unknown fragment shader param %d\n", param);
 402          return 0;
 403       }
 404       break;
 405    default:
 406       return 0;
 407    }
 408 }
 409
 410 static boolean
 411 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 412                                 enum pipe_format format,
 413                                 enum pipe_texture_target target,
 414                                 unsigned sample_count,
 415                                 unsigned bindings)
 416 {
 417    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 418       return false;
 419
 420    if (!(0x00000017 & (1 << sample_count)))
 421       return false;
 422
 423    if (!util_format_is_supported(format, bindings)) {
 424       return false;
 425    }
 426
 427    /* shared is always supported */
 428    bindings &= ~PIPE_BIND_SHARED;
 429
 430    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 431 }
 432
 433 static void
 434 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 435 {
 436    struct nv30_screen *screen = nv30_screen(pscreen);
 437    struct nouveau_pushbuf *push = screen->base.pushbuf;
 438
 439    *sequence = ++screen->base.fence.sequence;
 440
 441    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 442    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 443               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 444    PUSH_DATA (push, 0);
 445    PUSH_DATA (push, *sequence);
 446 }
 447
 448 static uint32_t
 449 nv30_screen_fence_update(struct pipe_screen *pscreen)
 450 {
 451    struct nv30_screen *screen = nv30_screen(pscreen);
 452    struct nv04_notify *fence = screen->fence->data;
 453    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 454 }
 455
 456 static void
 457 nv30_screen_destroy(struct pipe_screen *pscreen)
 458 {
 459    struct nv30_screen *screen = nv30_screen(pscreen);
 460
 461    if (!nouveau_drm_screen_unref(&screen->base))
 462       return;
 463
 464    if (screen->base.fence.current) {
 465       struct nouveau_fence *current = NULL;
 466
 467       /* nouveau_fence_wait will create a new current fence, so wait on the
 468        * _current_ one, and remove both.
 469        */
 470       nouveau_fence_ref(screen->base.fence.current, &current);
 471       nouveau_fence_wait(current, NULL);
 472       nouveau_fence_ref(NULL, &current);
 473       nouveau_fence_ref(NULL, &screen->base.fence.current);
 474    }
 475
 476    nouveau_bo_ref(NULL, &screen->notify);
 477
 478    nouveau_heap_destroy(&screen->query_heap);
 479    nouveau_heap_destroy(&screen->vp_exec_heap);
 480    nouveau_heap_destroy(&screen->vp_data_heap);
 481
 482    nouveau_object_del(&screen->query);
 483    nouveau_object_del(&screen->fence);
 484    nouveau_object_del(&screen->ntfy);
 485
 486    nouveau_object_del(&screen->sifm);
 487    nouveau_object_del(&screen->swzsurf);
 488    nouveau_object_del(&screen->surf2d);
 489    nouveau_object_del(&screen->m2mf);
 490    nouveau_object_del(&screen->eng3d);
 491    nouveau_object_del(&screen->null);
 492
 493    nouveau_screen_fini(&screen->base);
 494    FREE(screen);
 495 }
 496
 497 #define FAIL_SCREEN_INIT(str, err)                    \
 498    do {                                               \
 499       NOUVEAU_ERR(str, err);                          \
 500       screen->base.base.context_create = NULL;        \
 501       return &screen->base;                           \
 502    } while(0)
 503
 504 struct nouveau_screen *
 505 nv30_screen_create(struct nouveau_device *dev)
 506 {
 507    struct nv30_screen *screen;
 508    struct pipe_screen *pscreen;
 509    struct nouveau_pushbuf *push;
 510    struct nv04_fifo *fifo;
 511    unsigned oclass = 0;
 512    int ret, i;
 513
 514    switch (dev->chipset & 0xf0) {
 515    case 0x30:
 516       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 517          oclass = NV30_3D_CLASS;
 518       else
 519       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 520          oclass = NV34_3D_CLASS;
 521       else
 522       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 523          oclass = NV35_3D_CLASS;
 524       break;
 525    case 0x40:
 526       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 527          oclass = NV40_3D_CLASS;
 528       else
 529       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 530          oclass = NV44_3D_CLASS;
 531       break;
 532    case 0x60:
 533       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 534          oclass = NV44_3D_CLASS;
 535       break;
 536    default:
 537       break;
 538    }
 539
 540    if (!oclass) {
 541       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 542       return NULL;
 543    }
 544
 545    screen = CALLOC_STRUCT(nv30_screen);
 546    if (!screen)
 547       return NULL;
 548
 549    pscreen = &screen->base.base;
 550    pscreen->destroy = nv30_screen_destroy;
 551
 552    /*
 553     * Some modern apps try to use msaa without keeping in mind the
 554     * restrictions on videomem of older cards. Resulting in dmesg saying:
 555     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 556     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 557     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 558     *
 559     * Because we are running out of video memory, after which the program
 560     * using the msaa visual freezes, and eventually the entire system freezes.
 561     *
 562     * To work around this we do not allow msaa visauls by default and allow
 563     * the user to override this via NV30_MAX_MSAA.
 564     */
 565    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 566    if (screen->max_sample_count > 4)
 567       screen->max_sample_count = 4;
 568
 569    pscreen->get_param = nv30_screen_get_param;
 570    pscreen->get_paramf = nv30_screen_get_paramf;
 571    pscreen->get_shader_param = nv30_screen_get_shader_param;
 572    pscreen->context_create = nv30_context_create;
 573    pscreen->is_format_supported = nv30_screen_is_format_supported;
 574    nv30_resource_screen_init(pscreen);
 575    nouveau_screen_init_vdec(&screen->base);
 576
 577    screen->base.fence.emit = nv30_screen_fence_emit;
 578    screen->base.fence.update = nv30_screen_fence_update;
 579
 580    ret = nouveau_screen_init(&screen->base, dev);
 581    if (ret)
 582       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 583
 584    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 585    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 586    if (oclass == NV40_3D_CLASS) {
 587       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 588       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 589    }
 590
 591    fifo = screen->base.channel->data;
 592    push = screen->base.pushbuf;
 593    push->rsvd_kick = 16;
 594
 595    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 596                             NULL, 0, &screen->null);
 597    if (ret)
 598       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 599
 600    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 601     * this means that the address pointed at by the DMA object must
 602     * be 4KiB aligned, which means this object needs to be the first
 603     * one allocated on the channel.
 604     */
 605    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 606                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 607                             .length = 32 }, sizeof(struct nv04_notify),
 608                             &screen->fence);
 609    if (ret)
 610       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 611
 612    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 613    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 614                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 615                             .length = 32 }, sizeof(struct nv04_notify),
 616                             &screen->ntfy);
 617    if (ret)
 618       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 619
 620    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 621     * the remainder of the "notifier block" assigned by the kernel for
 622     * use as query objects
 623     */
 624    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 625                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 626                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 627                             &screen->query);
 628    if (ret)
 629       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 630
 631    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 632    if (ret)
 633       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 634
 635    LIST_INITHEAD(&screen->queries);
 636
 637    /* Vertex program resources (code/data), currently 6 of the constant
 638     * slots are reserved to implement user clipping planes
 639     */
 640    if (oclass < NV40_3D_CLASS) {
 641       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 642       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 643    } else {
 644       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 645       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 646    }
 647
 648    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 649    if (ret == 0)
 650       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 651    if (ret)
 652       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 653
 654    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 655                             NULL, 0, &screen->eng3d);
 656    if (ret)
 657       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 658
 659    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 660    PUSH_DATA (push, screen->eng3d->handle);
 661    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 662    PUSH_DATA (push, screen->ntfy->handle);
 663    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 664    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 665    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 666    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 667    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 668    PUSH_DATA (push, fifo->vram);     /* ZETA */
 669    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 670    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 671    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 672    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 673    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 674    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 675    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 676       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 677       PUSH_DATA (push, 0x00100000);
 678       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 679       PUSH_DATA (push, 3);
 680
 681       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 682       PUSH_DATA (push, 0);
 683       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 684       PUSH_DATA (push, fui(0.0));
 685       PUSH_DATA (push, fui(0.0));
 686       PUSH_DATA (push, fui(1.0));
 687       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 688       for (i = 0; i < 16; i++)
 689          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 690
 691       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 692       PUSH_DATA (push, 0);
 693    } else {
 694       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 695       PUSH_DATA (push, fifo->vram);
 696       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 697
 698       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 699       PUSH_DATA (push, 0x00000004);
 700
 701       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 702       PUSH_DATA (push, 0x00000010);
 703       PUSH_DATA (push, 0x01000100);
 704       PUSH_DATA (push, 0xff800006);
 705
 706       /* vtxprog output routing */
 707       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 708       PUSH_DATA (push, 0x06144321);
 709       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 710       PUSH_DATA (push, 0xedcba987);
 711       PUSH_DATA (push, 0x0000006f);
 712       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 713       PUSH_DATA (push, 0x00171615);
 714       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 715       PUSH_DATA (push, 0x001b1a19);
 716
 717       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 718       PUSH_DATA (push, 0x0020ffff);
 719       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 720       PUSH_DATA (push, 0x01d300d4);
 721
 722       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 723       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 724    }
 725
 726    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 727                             NULL, 0, &screen->m2mf);
 728    if (ret)
 729       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 730
 731    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 732    PUSH_DATA (push, screen->m2mf->handle);
 733    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 734    PUSH_DATA (push, screen->ntfy->handle);
 735
 736    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 737                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 738    if (ret)
 739       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 740
 741    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 742    PUSH_DATA (push, screen->surf2d->handle);
 743    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 744    PUSH_DATA (push, screen->ntfy->handle);
 745
 746    if (dev->chipset < 0x40)
 747       oclass = NV30_SURFACE_SWZ_CLASS;
 748    else
 749       oclass = NV40_SURFACE_SWZ_CLASS;
 750
 751    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 752                             NULL, 0, &screen->swzsurf);
 753    if (ret)
 754       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 755
 756    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 757    PUSH_DATA (push, screen->swzsurf->handle);
 758    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 759    PUSH_DATA (push, screen->ntfy->handle);
 760
 761    if (dev->chipset < 0x40)
 762       oclass = NV30_SIFM_CLASS;
 763    else
 764       oclass = NV40_SIFM_CLASS;
 765
 766    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 767                             NULL, 0, &screen->sifm);
 768    if (ret)
 769       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 770
 771    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 772    PUSH_DATA (push, screen->sifm->handle);
 773    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 774    PUSH_DATA (push, screen->ntfy->handle);
 775    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 776    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 777
 778    nouveau_pushbuf_kick(push, push->channel);
 779
 780    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 781    return &screen->base;
 782 }