src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_USER_INDEX_BUFFERS:
  95    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  99    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 100       return 1;
 101    /* nv4x capabilities */
 102    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_CONDITIONAL_RENDER:
 105    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 106    case PIPE_CAP_PRIMITIVE_RESTART:
 107       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 108    /* unsupported */
 109    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 110    case PIPE_CAP_SM3:
 111    case PIPE_CAP_INDEP_BLEND_ENABLE:
 112    case PIPE_CAP_INDEP_BLEND_FUNC:
 113    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 114    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 115    case PIPE_CAP_TGSI_INSTANCEID:
 116    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 117    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 118    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120    case PIPE_CAP_MAX_TEXEL_OFFSET:
 121    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 122    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 125    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 126    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 127    case PIPE_CAP_MAX_VERTEX_STREAMS:
 128    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 129    case PIPE_CAP_TEXTURE_BARRIER:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 132    case PIPE_CAP_CUBE_MAP_ARRAY:
 133    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 134    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 135    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 136    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 137    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 138    case PIPE_CAP_START_INSTANCE:
 139    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 140    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 141    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 142    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 143    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 144    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 145    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 146    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 147    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 148    case PIPE_CAP_TEXTURE_GATHER_SM5:
 149    case PIPE_CAP_FAKE_SW_MSAA:
 150    case PIPE_CAP_TEXTURE_QUERY_LOD:
 151    case PIPE_CAP_SAMPLE_SHADING:
 152    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 153    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 154    case PIPE_CAP_USER_VERTEX_BUFFERS:
 155    case PIPE_CAP_COMPUTE:
 156    case PIPE_CAP_DRAW_INDIRECT:
 157    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 158    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 159    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 160    case PIPE_CAP_CLIP_HALFZ:
 161    case PIPE_CAP_VERTEXID_NOBASE:
 162    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 163    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 164    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 165    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 166       return 0;
 167
 168    case PIPE_CAP_VENDOR_ID:
 169       return 0x10de;
 170    case PIPE_CAP_DEVICE_ID: {
 171       uint64_t device_id;
 172       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 173          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 174          return -1;
 175       }
 176       return device_id;
 177    }
 178    case PIPE_CAP_ACCELERATED:
 179       return 1;
 180    case PIPE_CAP_VIDEO_MEMORY:
 181       return dev->vram_size >> 20;
 182    case PIPE_CAP_UMA:
 183       return 0;
 184    }
 185
 186    debug_printf("unknown param %d\n", param);
 187    return 0;
 188 }
 189
 190 static float
 191 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 192 {
 193    struct nv30_screen *screen = nv30_screen(pscreen);
 194    struct nouveau_object *eng3d = screen->eng3d;
 195
 196    switch (param) {
 197    case PIPE_CAPF_MAX_LINE_WIDTH:
 198    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 199       return 10.0;
 200    case PIPE_CAPF_MAX_POINT_WIDTH:
 201    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 202       return 64.0;
 203    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 204       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 205    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 206       return 15.0;
 207    default:
 208       debug_printf("unknown paramf %d\n", param);
 209       return 0;
 210    }
 211 }
 212
 213 static int
 214 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 215                              enum pipe_shader_cap param)
 216 {
 217    struct nv30_screen *screen = nv30_screen(pscreen);
 218    struct nouveau_object *eng3d = screen->eng3d;
 219
 220    switch (shader) {
 221    case PIPE_SHADER_VERTEX:
 222       switch (param) {
 223       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 224       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 225          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 226       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 227       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 228          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 229       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 230          return 0;
 231       case PIPE_SHADER_CAP_MAX_INPUTS:
 232       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 233          return 16;
 234       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 235          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 236       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 237          return 1;
 238       case PIPE_SHADER_CAP_MAX_TEMPS:
 239          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 240       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 241       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 242          return 0;
 243       case PIPE_SHADER_CAP_MAX_PREDS:
 244       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 245       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 246       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 247       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 248       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 249       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 250       case PIPE_SHADER_CAP_SUBROUTINES:
 251       case PIPE_SHADER_CAP_INTEGERS:
 252       case PIPE_SHADER_CAP_DOUBLES:
 253       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 254       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 255       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 256       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 257          return 0;
 258       default:
 259          debug_printf("unknown vertex shader param %d\n", param);
 260          return 0;
 261       }
 262       break;
 263    case PIPE_SHADER_FRAGMENT:
 264       switch (param) {
 265       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 266       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 267       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 268       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 269          return 4096;
 270       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 271          return 0;
 272       case PIPE_SHADER_CAP_MAX_INPUTS:
 273          return 8; /* should be possible to do 10 with nv4x */
 274       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 275          return 4;
 276       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 277          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 278       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 279          return 1;
 280       case PIPE_SHADER_CAP_MAX_TEMPS:
 281          return 32;
 282       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 283       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 284          return 16;
 285       case PIPE_SHADER_CAP_MAX_PREDS:
 286       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 287       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 288       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 289       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 290       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 291       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 292       case PIPE_SHADER_CAP_SUBROUTINES:
 293       case PIPE_SHADER_CAP_DOUBLES:
 294       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 295       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 296       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 297       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 298          return 0;
 299       default:
 300          debug_printf("unknown fragment shader param %d\n", param);
 301          return 0;
 302       }
 303       break;
 304    default:
 305       return 0;
 306    }
 307 }
 308
 309 static boolean
 310 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 311                                 enum pipe_format format,
 312                                 enum pipe_texture_target target,
 313                                 unsigned sample_count,
 314                                 unsigned bindings)
 315 {
 316    if (sample_count > 4)
 317       return FALSE;
 318    if (!(0x00000017 & (1 << sample_count)))
 319       return FALSE;
 320
 321    if (!util_format_is_supported(format, bindings)) {
 322       return FALSE;
 323    }
 324
 325    /* transfers & shared are always supported */
 326    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 327                  PIPE_BIND_TRANSFER_WRITE |
 328                  PIPE_BIND_SHARED);
 329
 330    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 331 }
 332
 333 static void
 334 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 335 {
 336    struct nv30_screen *screen = nv30_screen(pscreen);
 337    struct nouveau_pushbuf *push = screen->base.pushbuf;
 338
 339    *sequence = ++screen->base.fence.sequence;
 340
 341    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 342    PUSH_DATA (push, 0);
 343    PUSH_DATA (push, *sequence);
 344 }
 345
 346 static uint32_t
 347 nv30_screen_fence_update(struct pipe_screen *pscreen)
 348 {
 349    struct nv30_screen *screen = nv30_screen(pscreen);
 350    struct nv04_notify *fence = screen->fence->data;
 351    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 352 }
 353
 354 static void
 355 nv30_screen_destroy(struct pipe_screen *pscreen)
 356 {
 357    struct nv30_screen *screen = nv30_screen(pscreen);
 358
 359    if (!nouveau_drm_screen_unref(&screen->base))
 360       return;
 361
 362    if (screen->base.fence.current) {
 363       struct nouveau_fence *current = NULL;
 364
 365       /* nouveau_fence_wait will create a new current fence, so wait on the
 366        * _current_ one, and remove both.
 367        */
 368       nouveau_fence_ref(screen->base.fence.current, &current);
 369       nouveau_fence_wait(current);
 370       nouveau_fence_ref(NULL, &current);
 371       nouveau_fence_ref(NULL, &screen->base.fence.current);
 372    }
 373
 374    nouveau_bo_ref(NULL, &screen->notify);
 375
 376    nouveau_heap_destroy(&screen->query_heap);
 377    nouveau_heap_destroy(&screen->vp_exec_heap);
 378    nouveau_heap_destroy(&screen->vp_data_heap);
 379
 380    nouveau_object_del(&screen->query);
 381    nouveau_object_del(&screen->fence);
 382    nouveau_object_del(&screen->ntfy);
 383
 384    nouveau_object_del(&screen->sifm);
 385    nouveau_object_del(&screen->swzsurf);
 386    nouveau_object_del(&screen->surf2d);
 387    nouveau_object_del(&screen->m2mf);
 388    nouveau_object_del(&screen->eng3d);
 389    nouveau_object_del(&screen->null);
 390
 391    nouveau_screen_fini(&screen->base);
 392    FREE(screen);
 393 }
 394
 395 #define FAIL_SCREEN_INIT(str, err)                    \
 396    do {                                               \
 397       NOUVEAU_ERR(str, err);                          \
 398       nv30_screen_destroy(pscreen);                   \
 399       return NULL;                                    \
 400    } while(0)
 401
 402 struct pipe_screen *
 403 nv30_screen_create(struct nouveau_device *dev)
 404 {
 405    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 406    struct pipe_screen *pscreen;
 407    struct nouveau_pushbuf *push;
 408    struct nv04_fifo *fifo;
 409    unsigned oclass = 0;
 410    int ret, i;
 411
 412    if (!screen)
 413       return NULL;
 414
 415    switch (dev->chipset & 0xf0) {
 416    case 0x30:
 417       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 418          oclass = NV30_3D_CLASS;
 419       else
 420       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 421          oclass = NV34_3D_CLASS;
 422       else
 423       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 424          oclass = NV35_3D_CLASS;
 425       break;
 426    case 0x40:
 427       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 428          oclass = NV40_3D_CLASS;
 429       else
 430       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 431          oclass = NV44_3D_CLASS;
 432       break;
 433    case 0x60:
 434       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 435          oclass = NV44_3D_CLASS;
 436       break;
 437    default:
 438       break;
 439    }
 440
 441    if (!oclass) {
 442       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 443       FREE(screen);
 444       return NULL;
 445    }
 446
 447    pscreen = &screen->base.base;
 448    pscreen->destroy = nv30_screen_destroy;
 449    pscreen->get_param = nv30_screen_get_param;
 450    pscreen->get_paramf = nv30_screen_get_paramf;
 451    pscreen->get_shader_param = nv30_screen_get_shader_param;
 452    pscreen->context_create = nv30_context_create;
 453    pscreen->is_format_supported = nv30_screen_is_format_supported;
 454    nv30_resource_screen_init(pscreen);
 455    nouveau_screen_init_vdec(&screen->base);
 456
 457    screen->base.fence.emit = nv30_screen_fence_emit;
 458    screen->base.fence.update = nv30_screen_fence_update;
 459
 460    ret = nouveau_screen_init(&screen->base, dev);
 461    if (ret)
 462       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 463
 464    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 465    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 466    if (oclass == NV40_3D_CLASS) {
 467       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 468       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 469    }
 470
 471    fifo = screen->base.channel->data;
 472    push = screen->base.pushbuf;
 473    push->rsvd_kick = 16;
 474
 475    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 476                             NULL, 0, &screen->null);
 477    if (ret)
 478       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 479
 480    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 481     * this means that the address pointed at by the DMA object must
 482     * be 4KiB aligned, which means this object needs to be the first
 483     * one allocated on the channel.
 484     */
 485    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 486                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 487                             .length = 32 }, sizeof(struct nv04_notify),
 488                             &screen->fence);
 489    if (ret)
 490       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 491
 492    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 493    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 494                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 495                             .length = 32 }, sizeof(struct nv04_notify),
 496                             &screen->ntfy);
 497    if (ret)
 498       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 499
 500    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 501     * the remainder of the "notifier block" assigned by the kernel for
 502     * use as query objects
 503     */
 504    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 505                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 506                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 507                             &screen->query);
 508    if (ret)
 509       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 510
 511    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 512    if (ret)
 513       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 514
 515    LIST_INITHEAD(&screen->queries);
 516
 517    /* Vertex program resources (code/data), currently 6 of the constant
 518     * slots are reserved to implement user clipping planes
 519     */
 520    if (oclass < NV40_3D_CLASS) {
 521       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 522       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 523    } else {
 524       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 525       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 526    }
 527
 528    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 529    if (ret == 0)
 530       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 531    if (ret)
 532       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 533
 534    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 535                             NULL, 0, &screen->eng3d);
 536    if (ret)
 537       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 538
 539    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 540    PUSH_DATA (push, screen->eng3d->handle);
 541    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 542    PUSH_DATA (push, screen->ntfy->handle);
 543    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 544    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 545    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 546    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 547    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 548    PUSH_DATA (push, fifo->vram);     /* ZETA */
 549    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 550    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 551    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 552    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 553    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 554    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 555    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 556       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 557       PUSH_DATA (push, 0x00100000);
 558       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 559       PUSH_DATA (push, 3);
 560
 561       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 562       PUSH_DATA (push, 0);
 563       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 564       PUSH_DATA (push, fui(0.0));
 565       PUSH_DATA (push, fui(0.0));
 566       PUSH_DATA (push, fui(1.0));
 567       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 568       for (i = 0; i < 16; i++)
 569          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 570
 571       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 572       PUSH_DATA (push, 0);
 573    } else {
 574       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 575       PUSH_DATA (push, fifo->vram);
 576       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 577
 578       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 579       PUSH_DATA (push, 0x00000004);
 580
 581       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 582       PUSH_DATA (push, 0x00000010);
 583       PUSH_DATA (push, 0x01000100);
 584       PUSH_DATA (push, 0xff800006);
 585
 586       /* vtxprog output routing */
 587       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 588       PUSH_DATA (push, 0x06144321);
 589       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 590       PUSH_DATA (push, 0xedcba987);
 591       PUSH_DATA (push, 0x0000006f);
 592       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 593       PUSH_DATA (push, 0x00171615);
 594       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 595       PUSH_DATA (push, 0x001b1a19);
 596
 597       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 598       PUSH_DATA (push, 0x0020ffff);
 599       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 600       PUSH_DATA (push, 0x01d300d4);
 601
 602       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 603       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 604    }
 605
 606    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 607                             NULL, 0, &screen->m2mf);
 608    if (ret)
 609       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 610
 611    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 612    PUSH_DATA (push, screen->m2mf->handle);
 613    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 614    PUSH_DATA (push, screen->ntfy->handle);
 615
 616    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 617                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 618    if (ret)
 619       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 620
 621    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 622    PUSH_DATA (push, screen->surf2d->handle);
 623    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 624    PUSH_DATA (push, screen->ntfy->handle);
 625
 626    if (dev->chipset < 0x40)
 627       oclass = NV30_SURFACE_SWZ_CLASS;
 628    else
 629       oclass = NV40_SURFACE_SWZ_CLASS;
 630
 631    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 632                             NULL, 0, &screen->swzsurf);
 633    if (ret)
 634       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 635
 636    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 637    PUSH_DATA (push, screen->swzsurf->handle);
 638    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 639    PUSH_DATA (push, screen->ntfy->handle);
 640
 641    if (dev->chipset < 0x40)
 642       oclass = NV30_SIFM_CLASS;
 643    else
 644       oclass = NV40_SIFM_CLASS;
 645
 646    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 647                             NULL, 0, &screen->sifm);
 648    if (ret)
 649       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 650
 651    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 652    PUSH_DATA (push, screen->sifm->handle);
 653    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 654    PUSH_DATA (push, screen->ntfy->handle);
 655    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 656    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 657
 658    nouveau_pushbuf_kick(push, push->channel);
 659
 660    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 661    return pscreen;
 662 }