src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MAX_VIEWPORTS:
  73       return 1;
  74    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  75       return 2048;
  76    /* supported capabilities */
  77    case PIPE_CAP_TWO_SIDED_STENCIL:
  78    case PIPE_CAP_ANISOTROPIC_FILTER:
  79    case PIPE_CAP_POINT_SPRITE:
  80    case PIPE_CAP_OCCLUSION_QUERY:
  81    case PIPE_CAP_QUERY_TIME_ELAPSED:
  82    case PIPE_CAP_QUERY_TIMESTAMP:
  83    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  84    case PIPE_CAP_TEXTURE_SWIZZLE:
  85    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  86    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  87    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  88    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  89    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  90    case PIPE_CAP_TGSI_TEXCOORD:
  91    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  92    case PIPE_CAP_USER_INDEX_BUFFERS:
  93    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  94    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  95    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  98       return 1;
  99    /* nv4x capabilities */
 100    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 101    case PIPE_CAP_NPOT_TEXTURES:
 102    case PIPE_CAP_CONDITIONAL_RENDER:
 103    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104    case PIPE_CAP_PRIMITIVE_RESTART:
 105       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 106    /* unsupported */
 107    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 108    case PIPE_CAP_SM3:
 109    case PIPE_CAP_INDEP_BLEND_ENABLE:
 110    case PIPE_CAP_INDEP_BLEND_FUNC:
 111    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 112    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 113    case PIPE_CAP_TGSI_INSTANCEID:
 114    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 115    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 116    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 117    case PIPE_CAP_MIN_TEXEL_OFFSET:
 118    case PIPE_CAP_MAX_TEXEL_OFFSET:
 119    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 120    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125    case PIPE_CAP_MAX_VERTEX_STREAMS:
 126    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 127    case PIPE_CAP_TEXTURE_BARRIER:
 128    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 130    case PIPE_CAP_CUBE_MAP_ARRAY:
 131    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 132    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 133    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 134    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 135    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 136    case PIPE_CAP_START_INSTANCE:
 137    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 138    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 139    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 140    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 141    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 142    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 143    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 144    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 145    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 146    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 147    case PIPE_CAP_TEXTURE_GATHER_SM5:
 148    case PIPE_CAP_FAKE_SW_MSAA:
 149    case PIPE_CAP_TEXTURE_QUERY_LOD:
 150    case PIPE_CAP_SAMPLE_SHADING:
 151    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 152    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 153    case PIPE_CAP_USER_VERTEX_BUFFERS:
 154    case PIPE_CAP_COMPUTE:
 155    case PIPE_CAP_DRAW_INDIRECT:
 156    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 157    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 158    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 159    case PIPE_CAP_CLIP_HALFZ:
 160       return 0;
 161
 162    case PIPE_CAP_VENDOR_ID:
 163       return 0x10de;
 164    case PIPE_CAP_DEVICE_ID: {
 165       uint64_t device_id;
 166       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 167          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 168          return -1;
 169       }
 170       return device_id;
 171    }
 172    case PIPE_CAP_ACCELERATED:
 173       return 1;
 174    case PIPE_CAP_VIDEO_MEMORY:
 175       return dev->vram_size >> 20;
 176    case PIPE_CAP_UMA:
 177       return 0;
 178    }
 179
 180    debug_printf("unknown param %d\n", param);
 181    return 0;
 182 }
 183
 184 static float
 185 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 186 {
 187    struct nv30_screen *screen = nv30_screen(pscreen);
 188    struct nouveau_object *eng3d = screen->eng3d;
 189
 190    switch (param) {
 191    case PIPE_CAPF_MAX_LINE_WIDTH:
 192    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 193       return 10.0;
 194    case PIPE_CAPF_MAX_POINT_WIDTH:
 195    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 196       return 64.0;
 197    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 198       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 199    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 200       return 15.0;
 201    default:
 202       debug_printf("unknown paramf %d\n", param);
 203       return 0;
 204    }
 205 }
 206
 207 static int
 208 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 209                              enum pipe_shader_cap param)
 210 {
 211    struct nv30_screen *screen = nv30_screen(pscreen);
 212    struct nouveau_object *eng3d = screen->eng3d;
 213
 214    switch (shader) {
 215    case PIPE_SHADER_VERTEX:
 216       switch (param) {
 217       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 218       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 219          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 220       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 221       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 222          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 223       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 224          return 0;
 225       case PIPE_SHADER_CAP_MAX_INPUTS:
 226       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 227          return 16;
 228       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 229          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 230       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 231          return 1;
 232       case PIPE_SHADER_CAP_MAX_TEMPS:
 233          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 234       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 235       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 236          return 0;
 237       case PIPE_SHADER_CAP_MAX_PREDS:
 238       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 239       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 240       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 241       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 242       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 243       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 244       case PIPE_SHADER_CAP_SUBROUTINES:
 245       case PIPE_SHADER_CAP_INTEGERS:
 246          return 0;
 247       default:
 248          debug_printf("unknown vertex shader param %d\n", param);
 249          return 0;
 250       }
 251       break;
 252    case PIPE_SHADER_FRAGMENT:
 253       switch (param) {
 254       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 255       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 256       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 257       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 258          return 4096;
 259       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 260          return 0;
 261       case PIPE_SHADER_CAP_MAX_INPUTS:
 262          return 8; /* should be possible to do 10 with nv4x */
 263       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 264          return 4;
 265       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 266          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 267       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 268          return 1;
 269       case PIPE_SHADER_CAP_MAX_TEMPS:
 270          return 32;
 271       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 272       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 273          return 16;
 274       case PIPE_SHADER_CAP_MAX_PREDS:
 275       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 276       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 277       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 278       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 279       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 280       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 281       case PIPE_SHADER_CAP_SUBROUTINES:
 282          return 0;
 283       default:
 284          debug_printf("unknown fragment shader param %d\n", param);
 285          return 0;
 286       }
 287       break;
 288    default:
 289       return 0;
 290    }
 291 }
 292
 293 static boolean
 294 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 295                                 enum pipe_format format,
 296                                 enum pipe_texture_target target,
 297                                 unsigned sample_count,
 298                                 unsigned bindings)
 299 {
 300    if (sample_count > 4)
 301       return FALSE;
 302    if (!(0x00000017 & (1 << sample_count)))
 303       return FALSE;
 304
 305    if (!util_format_is_supported(format, bindings)) {
 306       return FALSE;
 307    }
 308
 309    /* transfers & shared are always supported */
 310    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 311                  PIPE_BIND_TRANSFER_WRITE |
 312                  PIPE_BIND_SHARED);
 313
 314    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 315 }
 316
 317 static void
 318 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 319 {
 320    struct nv30_screen *screen = nv30_screen(pscreen);
 321    struct nouveau_pushbuf *push = screen->base.pushbuf;
 322
 323    *sequence = ++screen->base.fence.sequence;
 324
 325    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 326    PUSH_DATA (push, 0);
 327    PUSH_DATA (push, *sequence);
 328 }
 329
 330 static uint32_t
 331 nv30_screen_fence_update(struct pipe_screen *pscreen)
 332 {
 333    struct nv30_screen *screen = nv30_screen(pscreen);
 334    struct nv04_notify *fence = screen->fence->data;
 335    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 336 }
 337
 338 static void
 339 nv30_screen_destroy(struct pipe_screen *pscreen)
 340 {
 341    struct nv30_screen *screen = nv30_screen(pscreen);
 342
 343    if (!nouveau_drm_screen_unref(&screen->base))
 344       return;
 345
 346    if (screen->base.fence.current) {
 347       struct nouveau_fence *current = NULL;
 348
 349       /* nouveau_fence_wait will create a new current fence, so wait on the
 350        * _current_ one, and remove both.
 351        */
 352       nouveau_fence_ref(screen->base.fence.current, &current);
 353       nouveau_fence_wait(current);
 354       nouveau_fence_ref(NULL, &current);
 355       nouveau_fence_ref(NULL, &screen->base.fence.current);
 356    }
 357
 358    nouveau_bo_ref(NULL, &screen->notify);
 359
 360    nouveau_heap_destroy(&screen->query_heap);
 361    nouveau_heap_destroy(&screen->vp_exec_heap);
 362    nouveau_heap_destroy(&screen->vp_data_heap);
 363
 364    nouveau_object_del(&screen->query);
 365    nouveau_object_del(&screen->fence);
 366    nouveau_object_del(&screen->ntfy);
 367
 368    nouveau_object_del(&screen->sifm);
 369    nouveau_object_del(&screen->swzsurf);
 370    nouveau_object_del(&screen->surf2d);
 371    nouveau_object_del(&screen->m2mf);
 372    nouveau_object_del(&screen->eng3d);
 373    nouveau_object_del(&screen->null);
 374
 375    nouveau_screen_fini(&screen->base);
 376    FREE(screen);
 377 }
 378
 379 #define FAIL_SCREEN_INIT(str, err)                    \
 380    do {                                               \
 381       NOUVEAU_ERR(str, err);                          \
 382       nv30_screen_destroy(pscreen);                   \
 383       return NULL;                                    \
 384    } while(0)
 385
 386 struct pipe_screen *
 387 nv30_screen_create(struct nouveau_device *dev)
 388 {
 389    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 390    struct pipe_screen *pscreen;
 391    struct nouveau_pushbuf *push;
 392    struct nv04_fifo *fifo;
 393    unsigned oclass = 0;
 394    int ret, i;
 395
 396    if (!screen)
 397       return NULL;
 398
 399    switch (dev->chipset & 0xf0) {
 400    case 0x30:
 401       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 402          oclass = NV30_3D_CLASS;
 403       else
 404       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 405          oclass = NV34_3D_CLASS;
 406       else
 407       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 408          oclass = NV35_3D_CLASS;
 409       break;
 410    case 0x40:
 411       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 412          oclass = NV40_3D_CLASS;
 413       else
 414       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 415          oclass = NV44_3D_CLASS;
 416       break;
 417    case 0x60:
 418       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 419          oclass = NV44_3D_CLASS;
 420       break;
 421    default:
 422       break;
 423    }
 424
 425    if (!oclass) {
 426       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 427       FREE(screen);
 428       return NULL;
 429    }
 430
 431    pscreen = &screen->base.base;
 432    pscreen->destroy = nv30_screen_destroy;
 433    pscreen->get_param = nv30_screen_get_param;
 434    pscreen->get_paramf = nv30_screen_get_paramf;
 435    pscreen->get_shader_param = nv30_screen_get_shader_param;
 436    pscreen->context_create = nv30_context_create;
 437    pscreen->is_format_supported = nv30_screen_is_format_supported;
 438    nv30_resource_screen_init(pscreen);
 439    nouveau_screen_init_vdec(&screen->base);
 440
 441    screen->base.fence.emit = nv30_screen_fence_emit;
 442    screen->base.fence.update = nv30_screen_fence_update;
 443
 444    ret = nouveau_screen_init(&screen->base, dev);
 445    if (ret)
 446       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 447
 448    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 449    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 450    if (oclass == NV40_3D_CLASS) {
 451       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 452       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 453    }
 454
 455    fifo = screen->base.channel->data;
 456    push = screen->base.pushbuf;
 457    push->rsvd_kick = 16;
 458
 459    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 460                             NULL, 0, &screen->null);
 461    if (ret)
 462       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 463
 464    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 465     * this means that the address pointed at by the DMA object must
 466     * be 4KiB aligned, which means this object needs to be the first
 467     * one allocated on the channel.
 468     */
 469    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 470                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 471                             .length = 32 }, sizeof(struct nv04_notify),
 472                             &screen->fence);
 473    if (ret)
 474       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 475
 476    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 477    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 478                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 479                             .length = 32 }, sizeof(struct nv04_notify),
 480                             &screen->ntfy);
 481    if (ret)
 482       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 483
 484    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 485     * the remainder of the "notifier block" assigned by the kernel for
 486     * use as query objects
 487     */
 488    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 489                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 490                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 491                             &screen->query);
 492    if (ret)
 493       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 494
 495    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 496    if (ret)
 497       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 498
 499    LIST_INITHEAD(&screen->queries);
 500
 501    /* Vertex program resources (code/data), currently 6 of the constant
 502     * slots are reserved to implement user clipping planes
 503     */
 504    if (oclass < NV40_3D_CLASS) {
 505       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 506       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 507    } else {
 508       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 509       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 510    }
 511
 512    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 513    if (ret == 0)
 514       nouveau_bo_map(screen->notify, 0, screen->base.client);
 515    if (ret)
 516       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 517
 518    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 519                             NULL, 0, &screen->eng3d);
 520    if (ret)
 521       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 522
 523    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 524    PUSH_DATA (push, screen->eng3d->handle);
 525    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 526    PUSH_DATA (push, screen->ntfy->handle);
 527    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 528    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 529    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 530    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 531    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 532    PUSH_DATA (push, fifo->vram);     /* ZETA */
 533    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 534    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 535    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 536    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 537    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 538    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 539    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 540       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 541       PUSH_DATA (push, 0x00100000);
 542       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 543       PUSH_DATA (push, 3);
 544
 545       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 546       PUSH_DATA (push, 0);
 547       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 548       PUSH_DATA (push, fui(0.0));
 549       PUSH_DATA (push, fui(0.0));
 550       PUSH_DATA (push, fui(1.0));
 551       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 552       for (i = 0; i < 16; i++)
 553          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 554
 555       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 556       PUSH_DATA (push, 0);
 557    } else {
 558       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 559       PUSH_DATA (push, fifo->vram);
 560       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 561
 562       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 563       PUSH_DATA (push, 0x00000004);
 564
 565       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 566       PUSH_DATA (push, 0x00000010);
 567       PUSH_DATA (push, 0x01000100);
 568       PUSH_DATA (push, 0xff800006);
 569
 570       /* vtxprog output routing */
 571       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 572       PUSH_DATA (push, 0x06144321);
 573       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 574       PUSH_DATA (push, 0xedcba987);
 575       PUSH_DATA (push, 0x0000006f);
 576       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 577       PUSH_DATA (push, 0x00171615);
 578       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 579       PUSH_DATA (push, 0x001b1a19);
 580
 581       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 582       PUSH_DATA (push, 0x0020ffff);
 583       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 584       PUSH_DATA (push, 0x01d300d4);
 585
 586       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 587       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 588    }
 589
 590    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 591                             NULL, 0, &screen->m2mf);
 592    if (ret)
 593       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 594
 595    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 596    PUSH_DATA (push, screen->m2mf->handle);
 597    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 598    PUSH_DATA (push, screen->ntfy->handle);
 599
 600    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 601                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 602    if (ret)
 603       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 604
 605    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 606    PUSH_DATA (push, screen->surf2d->handle);
 607    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 608    PUSH_DATA (push, screen->ntfy->handle);
 609
 610    if (dev->chipset < 0x40)
 611       oclass = NV30_SURFACE_SWZ_CLASS;
 612    else
 613       oclass = NV40_SURFACE_SWZ_CLASS;
 614
 615    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 616                             NULL, 0, &screen->swzsurf);
 617    if (ret)
 618       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 619
 620    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 621    PUSH_DATA (push, screen->swzsurf->handle);
 622    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 623    PUSH_DATA (push, screen->ntfy->handle);
 624
 625    if (dev->chipset < 0x40)
 626       oclass = NV30_SIFM_CLASS;
 627    else
 628       oclass = NV40_SIFM_CLASS;
 629
 630    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 631                             NULL, 0, &screen->sifm);
 632    if (ret)
 633       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 634
 635    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 636    PUSH_DATA (push, screen->sifm->handle);
 637    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 638    PUSH_DATA (push, screen->ntfy->handle);
 639    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 640    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 641
 642    nouveau_pushbuf_kick(push, push->channel);
 643
 644    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 645    return pscreen;
 646 }