src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    /* supported capabilities */
  66    case PIPE_CAP_TWO_SIDED_STENCIL:
  67    case PIPE_CAP_ANISOTROPIC_FILTER:
  68    case PIPE_CAP_POINT_SPRITE:
  69    case PIPE_CAP_OCCLUSION_QUERY:
  70    case PIPE_CAP_QUERY_TIME_ELAPSED:
  71    case PIPE_CAP_QUERY_TIMESTAMP:
  72    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  73    case PIPE_CAP_TEXTURE_SWIZZLE:
  74    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  75    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  77    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  78    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79    case PIPE_CAP_TGSI_TEXCOORD:
  80    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  81    case PIPE_CAP_USER_INDEX_BUFFERS:
  82    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  83       return 1;
  84    case PIPE_CAP_USER_VERTEX_BUFFERS:
  85       return 0;
  86    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  87       return 16;
  88    case PIPE_CAP_MAX_VIEWPORTS:
  89       return 1;
  90    /* nv4x capabilities */
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_CONDITIONAL_RENDER:
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_PRIMITIVE_RESTART:
  96       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  97    /* unsupported */
  98    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  99    case PIPE_CAP_SM3:
 100    case PIPE_CAP_INDEP_BLEND_ENABLE:
 101    case PIPE_CAP_INDEP_BLEND_FUNC:
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 104    case PIPE_CAP_TGSI_INSTANCEID:
 105    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 106    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 107    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 108    case PIPE_CAP_MIN_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 111    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 114    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 115    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 116    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 117    case PIPE_CAP_TEXTURE_BARRIER:
 118    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 120    case PIPE_CAP_CUBE_MAP_ARRAY:
 121    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 123    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 124    case PIPE_CAP_START_INSTANCE:
 125    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 128    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 129    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER:
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135    case PIPE_CAP_TEXTURE_GATHER_SM5:
 136    case PIPE_CAP_FAKE_SW_MSAA:
 137    case PIPE_CAP_TEXTURE_QUERY_LOD:
 138    case PIPE_CAP_SAMPLE_SHADING:
 139    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 140    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 141       return 0;
 142    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 143    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 144    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 145    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 146       return 1;
 147    case PIPE_CAP_ENDIANNESS:
 148       return PIPE_ENDIAN_LITTLE;
 149    default:
 150       debug_printf("unknown param %d\n", param);
 151       return 0;
 152    }
 153 }
 154
 155 static float
 156 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 157 {
 158    struct nv30_screen *screen = nv30_screen(pscreen);
 159    struct nouveau_object *eng3d = screen->eng3d;
 160
 161    switch (param) {
 162    case PIPE_CAPF_MAX_LINE_WIDTH:
 163    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 164       return 10.0;
 165    case PIPE_CAPF_MAX_POINT_WIDTH:
 166    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 167       return 64.0;
 168    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 169       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 170    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 171       return 15.0;
 172    default:
 173       debug_printf("unknown paramf %d\n", param);
 174       return 0;
 175    }
 176 }
 177
 178 static int
 179 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 180                              enum pipe_shader_cap param)
 181 {
 182    struct nv30_screen *screen = nv30_screen(pscreen);
 183    struct nouveau_object *eng3d = screen->eng3d;
 184
 185    switch (shader) {
 186    case PIPE_SHADER_VERTEX:
 187       switch (param) {
 188       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 189       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 190          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 191       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 192       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 193          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 194       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 195          return 0;
 196       case PIPE_SHADER_CAP_MAX_INPUTS:
 197          return 16;
 198       case PIPE_SHADER_CAP_MAX_CONSTS:
 199          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 200       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 201          return 1;
 202       case PIPE_SHADER_CAP_MAX_TEMPS:
 203          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 204       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 205       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 206          return 0;
 207       case PIPE_SHADER_CAP_MAX_ADDRS:
 208          return 2;
 209       case PIPE_SHADER_CAP_MAX_PREDS:
 210       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 211       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 212       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 213       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 214       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 215       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 216       case PIPE_SHADER_CAP_SUBROUTINES:
 217       case PIPE_SHADER_CAP_INTEGERS:
 218          return 0;
 219       default:
 220          debug_printf("unknown vertex shader param %d\n", param);
 221          return 0;
 222       }
 223       break;
 224    case PIPE_SHADER_FRAGMENT:
 225       switch (param) {
 226       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 227       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 228       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 229       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 230          return 4096;
 231       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 232          return 0;
 233       case PIPE_SHADER_CAP_MAX_INPUTS:
 234          return 8; /* should be possible to do 10 with nv4x */
 235       case PIPE_SHADER_CAP_MAX_CONSTS:
 236          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 237       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 238          return 1;
 239       case PIPE_SHADER_CAP_MAX_TEMPS:
 240          return 32;
 241       case PIPE_SHADER_CAP_MAX_ADDRS:
 242          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 243       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 244       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 245          return 16;
 246       case PIPE_SHADER_CAP_MAX_PREDS:
 247       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 248       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 249       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 250       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 251       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 252       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 253       case PIPE_SHADER_CAP_SUBROUTINES:
 254          return 0;
 255       default:
 256          debug_printf("unknown fragment shader param %d\n", param);
 257          return 0;
 258       }
 259       break;
 260    default:
 261       return 0;
 262    }
 263 }
 264
 265 static boolean
 266 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 267                                 enum pipe_format format,
 268                                 enum pipe_texture_target target,
 269                                 unsigned sample_count,
 270                                 unsigned bindings)
 271 {
 272    if (sample_count > 4)
 273       return FALSE;
 274    if (!(0x00000017 & (1 << sample_count)))
 275       return FALSE;
 276
 277    if (!util_format_is_supported(format, bindings)) {
 278       return FALSE;
 279    }
 280
 281    /* transfers & shared are always supported */
 282    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 283                  PIPE_BIND_TRANSFER_WRITE |
 284                  PIPE_BIND_SHARED);
 285
 286    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 287 }
 288
 289 static void
 290 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 291 {
 292    struct nv30_screen *screen = nv30_screen(pscreen);
 293    struct nouveau_pushbuf *push = screen->base.pushbuf;
 294
 295    *sequence = ++screen->base.fence.sequence;
 296
 297    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 298    PUSH_DATA (push, 0);
 299    PUSH_DATA (push, *sequence);
 300 }
 301
 302 static uint32_t
 303 nv30_screen_fence_update(struct pipe_screen *pscreen)
 304 {
 305    struct nv30_screen *screen = nv30_screen(pscreen);
 306    struct nv04_notify *fence = screen->fence->data;
 307    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 308 }
 309
 310 static void
 311 nv30_screen_destroy(struct pipe_screen *pscreen)
 312 {
 313    struct nv30_screen *screen = nv30_screen(pscreen);
 314
 315    if (!nouveau_drm_screen_unref(&screen->base))
 316       return;
 317
 318    if (screen->base.fence.current) {
 319       struct nouveau_fence *current = NULL;
 320
 321       /* nouveau_fence_wait will create a new current fence, so wait on the
 322        * _current_ one, and remove both.
 323        */
 324       nouveau_fence_ref(screen->base.fence.current, &current);
 325       nouveau_fence_wait(current);
 326       nouveau_fence_ref(NULL, &current);
 327       nouveau_fence_ref(NULL, &screen->base.fence.current);
 328    }
 329
 330    nouveau_bo_ref(NULL, &screen->notify);
 331
 332    nouveau_heap_destroy(&screen->query_heap);
 333    nouveau_heap_destroy(&screen->vp_exec_heap);
 334    nouveau_heap_destroy(&screen->vp_data_heap);
 335
 336    nouveau_object_del(&screen->query);
 337    nouveau_object_del(&screen->fence);
 338    nouveau_object_del(&screen->ntfy);
 339
 340    nouveau_object_del(&screen->sifm);
 341    nouveau_object_del(&screen->swzsurf);
 342    nouveau_object_del(&screen->surf2d);
 343    nouveau_object_del(&screen->m2mf);
 344    nouveau_object_del(&screen->eng3d);
 345    nouveau_object_del(&screen->null);
 346
 347    nouveau_screen_fini(&screen->base);
 348    FREE(screen);
 349 }
 350
 351 #define FAIL_SCREEN_INIT(str, err)                    \
 352    do {                                               \
 353       NOUVEAU_ERR(str, err);                          \
 354       nv30_screen_destroy(pscreen);                   \
 355       return NULL;                                    \
 356    } while(0)
 357
 358 struct pipe_screen *
 359 nv30_screen_create(struct nouveau_device *dev)
 360 {
 361    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 362    struct pipe_screen *pscreen;
 363    struct nouveau_pushbuf *push;
 364    struct nv04_fifo *fifo;
 365    unsigned oclass = 0;
 366    int ret, i;
 367
 368    if (!screen)
 369       return NULL;
 370
 371    switch (dev->chipset & 0xf0) {
 372    case 0x30:
 373       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 374          oclass = NV30_3D_CLASS;
 375       else
 376       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 377          oclass = NV34_3D_CLASS;
 378       else
 379       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 380          oclass = NV35_3D_CLASS;
 381       break;
 382    case 0x40:
 383       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 384          oclass = NV40_3D_CLASS;
 385       else
 386       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 387          oclass = NV44_3D_CLASS;
 388       break;
 389    case 0x60:
 390       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 391          oclass = NV44_3D_CLASS;
 392       break;
 393    default:
 394       break;
 395    }
 396
 397    if (!oclass) {
 398       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 399       FREE(screen);
 400       return NULL;
 401    }
 402
 403    pscreen = &screen->base.base;
 404    pscreen->destroy = nv30_screen_destroy;
 405    pscreen->get_param = nv30_screen_get_param;
 406    pscreen->get_paramf = nv30_screen_get_paramf;
 407    pscreen->get_shader_param = nv30_screen_get_shader_param;
 408    pscreen->context_create = nv30_context_create;
 409    pscreen->is_format_supported = nv30_screen_is_format_supported;
 410    nv30_resource_screen_init(pscreen);
 411    nouveau_screen_init_vdec(&screen->base);
 412
 413    screen->base.fence.emit = nv30_screen_fence_emit;
 414    screen->base.fence.update = nv30_screen_fence_update;
 415
 416    ret = nouveau_screen_init(&screen->base, dev);
 417    if (ret)
 418       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 419
 420    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 421    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 422    if (oclass == NV40_3D_CLASS) {
 423       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 424       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 425    }
 426
 427    fifo = screen->base.channel->data;
 428    push = screen->base.pushbuf;
 429    push->rsvd_kick = 16;
 430
 431    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 432                             NULL, 0, &screen->null);
 433    if (ret)
 434       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 435
 436    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 437     * this means that the address pointed at by the DMA object must
 438     * be 4KiB aligned, which means this object needs to be the first
 439     * one allocated on the channel.
 440     */
 441    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 442                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 443                             .length = 32 }, sizeof(struct nv04_notify),
 444                             &screen->fence);
 445    if (ret)
 446       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 447
 448    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 449    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 450                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 451                             .length = 32 }, sizeof(struct nv04_notify),
 452                             &screen->ntfy);
 453    if (ret)
 454       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 455
 456    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 457     * the remainder of the "notifier block" assigned by the kernel for
 458     * use as query objects
 459     */
 460    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 461                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 462                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 463                             &screen->query);
 464    if (ret)
 465       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 466
 467    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 468    if (ret)
 469       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 470
 471    LIST_INITHEAD(&screen->queries);
 472
 473    /* Vertex program resources (code/data), currently 6 of the constant
 474     * slots are reserved to implement user clipping planes
 475     */
 476    if (oclass < NV40_3D_CLASS) {
 477       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 478       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 479    } else {
 480       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 481       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 482    }
 483
 484    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 485    if (ret == 0)
 486       nouveau_bo_map(screen->notify, 0, screen->base.client);
 487    if (ret)
 488       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 489
 490    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 491                             NULL, 0, &screen->eng3d);
 492    if (ret)
 493       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 494
 495    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 496    PUSH_DATA (push, screen->eng3d->handle);
 497    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 498    PUSH_DATA (push, screen->ntfy->handle);
 499    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 500    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 501    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 502    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 503    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 504    PUSH_DATA (push, fifo->vram);     /* ZETA */
 505    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 506    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 507    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 508    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 509    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 510    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 511    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 512       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 513       PUSH_DATA (push, 0x00100000);
 514       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 515       PUSH_DATA (push, 3);
 516
 517       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 518       PUSH_DATA (push, 0);
 519       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 520       PUSH_DATA (push, fui(0.0));
 521       PUSH_DATA (push, fui(0.0));
 522       PUSH_DATA (push, fui(1.0));
 523       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 524       for (i = 0; i < 16; i++)
 525          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 526
 527       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 528       PUSH_DATA (push, 0);
 529    } else {
 530       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 531       PUSH_DATA (push, fifo->vram);
 532       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 533
 534       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 535       PUSH_DATA (push, 0x00000004);
 536
 537       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 538       PUSH_DATA (push, 0x00000010);
 539       PUSH_DATA (push, 0x01000100);
 540       PUSH_DATA (push, 0xff800006);
 541
 542       /* vtxprog output routing */
 543       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 544       PUSH_DATA (push, 0x06144321);
 545       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 546       PUSH_DATA (push, 0xedcba987);
 547       PUSH_DATA (push, 0x0000006f);
 548       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 549       PUSH_DATA (push, 0x00171615);
 550       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 551       PUSH_DATA (push, 0x001b1a19);
 552
 553       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 554       PUSH_DATA (push, 0x0020ffff);
 555       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 556       PUSH_DATA (push, 0x01d300d4);
 557
 558       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 559       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 560    }
 561
 562    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 563                             NULL, 0, &screen->m2mf);
 564    if (ret)
 565       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 566
 567    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 568    PUSH_DATA (push, screen->m2mf->handle);
 569    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 570    PUSH_DATA (push, screen->ntfy->handle);
 571
 572    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 573                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 574    if (ret)
 575       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 576
 577    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 578    PUSH_DATA (push, screen->surf2d->handle);
 579    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 580    PUSH_DATA (push, screen->ntfy->handle);
 581
 582    if (dev->chipset < 0x40)
 583       oclass = NV30_SURFACE_SWZ_CLASS;
 584    else
 585       oclass = NV40_SURFACE_SWZ_CLASS;
 586
 587    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 588                             NULL, 0, &screen->swzsurf);
 589    if (ret)
 590       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 591
 592    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 593    PUSH_DATA (push, screen->swzsurf->handle);
 594    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 595    PUSH_DATA (push, screen->ntfy->handle);
 596
 597    if (dev->chipset < 0x40)
 598       oclass = NV30_SIFM_CLASS;
 599    else
 600       oclass = NV40_SIFM_CLASS;
 601
 602    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 603                             NULL, 0, &screen->sifm);
 604    if (ret)
 605       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 606
 607    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 608    PUSH_DATA (push, screen->sifm->handle);
 609    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 610    PUSH_DATA (push, screen->ntfy->handle);
 611    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 612    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 613
 614    nouveau_pushbuf_kick(push, push->channel);
 615
 616    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 617    return pscreen;
 618 }