gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesa
[mesa.git] / src / gallium / drivers / nouveau / nv30 / nv30_screen.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
30
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
35
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
41
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
48
49 static int
50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
51 {
52 struct nv30_screen *screen = nv30_screen(pscreen);
53 struct nouveau_object *eng3d = screen->eng3d;
54 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
55
56 switch (param) {
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS:
59 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
61 return 13;
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
63 return 10;
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
65 return 13;
66 case PIPE_CAP_GLSL_FEATURE_LEVEL:
67 return 120;
68 case PIPE_CAP_ENDIANNESS:
69 return PIPE_ENDIAN_LITTLE;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
71 return 16;
72 case PIPE_CAP_MAX_VIEWPORTS:
73 return 1;
74 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
75 return 2048;
76 /* supported capabilities */
77 case PIPE_CAP_TWO_SIDED_STENCIL:
78 case PIPE_CAP_ANISOTROPIC_FILTER:
79 case PIPE_CAP_POINT_SPRITE:
80 case PIPE_CAP_OCCLUSION_QUERY:
81 case PIPE_CAP_QUERY_TIME_ELAPSED:
82 case PIPE_CAP_QUERY_TIMESTAMP:
83 case PIPE_CAP_TEXTURE_SHADOW_MAP:
84 case PIPE_CAP_TEXTURE_SWIZZLE:
85 case PIPE_CAP_DEPTH_CLIP_DISABLE:
86 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
87 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
88 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
89 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
90 case PIPE_CAP_TGSI_TEXCOORD:
91 case PIPE_CAP_USER_CONSTANT_BUFFERS:
92 case PIPE_CAP_USER_INDEX_BUFFERS:
93 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
94 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
95 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
96 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
97 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
98 return 1;
99 /* nv4x capabilities */
100 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
101 case PIPE_CAP_NPOT_TEXTURES:
102 case PIPE_CAP_CONDITIONAL_RENDER:
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_PRIMITIVE_RESTART:
105 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
106 /* unsupported */
107 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
108 case PIPE_CAP_SM3:
109 case PIPE_CAP_INDEP_BLEND_ENABLE:
110 case PIPE_CAP_INDEP_BLEND_FUNC:
111 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
112 case PIPE_CAP_SHADER_STENCIL_EXPORT:
113 case PIPE_CAP_TGSI_INSTANCEID:
114 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
115 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
116 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
117 case PIPE_CAP_MIN_TEXEL_OFFSET:
118 case PIPE_CAP_MAX_TEXEL_OFFSET:
119 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
120 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
121 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
122 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
123 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
124 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
125 case PIPE_CAP_MAX_VERTEX_STREAMS:
126 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
127 case PIPE_CAP_TEXTURE_BARRIER:
128 case PIPE_CAP_SEAMLESS_CUBE_MAP:
129 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
130 case PIPE_CAP_CUBE_MAP_ARRAY:
131 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
132 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
133 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
134 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
135 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
136 case PIPE_CAP_START_INSTANCE:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
139 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
140 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
141 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
142 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
143 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
144 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
145 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
146 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
147 case PIPE_CAP_TEXTURE_GATHER_SM5:
148 case PIPE_CAP_FAKE_SW_MSAA:
149 case PIPE_CAP_TEXTURE_QUERY_LOD:
150 case PIPE_CAP_SAMPLE_SHADING:
151 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
152 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
153 case PIPE_CAP_USER_VERTEX_BUFFERS:
154 case PIPE_CAP_COMPUTE:
155 case PIPE_CAP_DRAW_INDIRECT:
156 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
157 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
158 case PIPE_CAP_SAMPLER_VIEW_TARGET:
159 return 0;
160
161 case PIPE_CAP_VENDOR_ID:
162 return 0x10de;
163 case PIPE_CAP_DEVICE_ID: {
164 uint64_t device_id;
165 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
166 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
167 return -1;
168 }
169 return device_id;
170 }
171 case PIPE_CAP_ACCELERATED:
172 return 1;
173 case PIPE_CAP_VIDEO_MEMORY:
174 return dev->vram_size >> 20;
175 case PIPE_CAP_UMA:
176 return 0;
177 }
178
179 debug_printf("unknown param %d\n", param);
180 return 0;
181 }
182
183 static float
184 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
185 {
186 struct nv30_screen *screen = nv30_screen(pscreen);
187 struct nouveau_object *eng3d = screen->eng3d;
188
189 switch (param) {
190 case PIPE_CAPF_MAX_LINE_WIDTH:
191 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
192 return 10.0;
193 case PIPE_CAPF_MAX_POINT_WIDTH:
194 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
195 return 64.0;
196 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
197 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
198 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
199 return 15.0;
200 default:
201 debug_printf("unknown paramf %d\n", param);
202 return 0;
203 }
204 }
205
206 static int
207 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
208 enum pipe_shader_cap param)
209 {
210 struct nv30_screen *screen = nv30_screen(pscreen);
211 struct nouveau_object *eng3d = screen->eng3d;
212
213 switch (shader) {
214 case PIPE_SHADER_VERTEX:
215 switch (param) {
216 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
217 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
218 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
219 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
220 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
221 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
222 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
223 return 0;
224 case PIPE_SHADER_CAP_MAX_INPUTS:
225 case PIPE_SHADER_CAP_MAX_OUTPUTS:
226 return 16;
227 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
228 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
229 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
230 return 1;
231 case PIPE_SHADER_CAP_MAX_TEMPS:
232 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
233 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
234 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
235 return 0;
236 case PIPE_SHADER_CAP_MAX_PREDS:
237 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
238 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
239 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
240 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
241 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
242 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
243 case PIPE_SHADER_CAP_SUBROUTINES:
244 case PIPE_SHADER_CAP_INTEGERS:
245 return 0;
246 default:
247 debug_printf("unknown vertex shader param %d\n", param);
248 return 0;
249 }
250 break;
251 case PIPE_SHADER_FRAGMENT:
252 switch (param) {
253 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
254 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
255 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
256 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
257 return 4096;
258 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
259 return 0;
260 case PIPE_SHADER_CAP_MAX_INPUTS:
261 return 8; /* should be possible to do 10 with nv4x */
262 case PIPE_SHADER_CAP_MAX_OUTPUTS:
263 return 4;
264 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
265 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
266 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
267 return 1;
268 case PIPE_SHADER_CAP_MAX_TEMPS:
269 return 32;
270 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
271 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
272 return 16;
273 case PIPE_SHADER_CAP_MAX_PREDS:
274 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
275 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
276 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
277 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
278 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
279 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
280 case PIPE_SHADER_CAP_SUBROUTINES:
281 return 0;
282 default:
283 debug_printf("unknown fragment shader param %d\n", param);
284 return 0;
285 }
286 break;
287 default:
288 return 0;
289 }
290 }
291
292 static boolean
293 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
294 enum pipe_format format,
295 enum pipe_texture_target target,
296 unsigned sample_count,
297 unsigned bindings)
298 {
299 if (sample_count > 4)
300 return FALSE;
301 if (!(0x00000017 & (1 << sample_count)))
302 return FALSE;
303
304 if (!util_format_is_supported(format, bindings)) {
305 return FALSE;
306 }
307
308 /* transfers & shared are always supported */
309 bindings &= ~(PIPE_BIND_TRANSFER_READ |
310 PIPE_BIND_TRANSFER_WRITE |
311 PIPE_BIND_SHARED);
312
313 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
314 }
315
316 static void
317 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
318 {
319 struct nv30_screen *screen = nv30_screen(pscreen);
320 struct nouveau_pushbuf *push = screen->base.pushbuf;
321
322 *sequence = ++screen->base.fence.sequence;
323
324 BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
325 PUSH_DATA (push, 0);
326 PUSH_DATA (push, *sequence);
327 }
328
329 static uint32_t
330 nv30_screen_fence_update(struct pipe_screen *pscreen)
331 {
332 struct nv30_screen *screen = nv30_screen(pscreen);
333 struct nv04_notify *fence = screen->fence->data;
334 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
335 }
336
337 static void
338 nv30_screen_destroy(struct pipe_screen *pscreen)
339 {
340 struct nv30_screen *screen = nv30_screen(pscreen);
341
342 if (!nouveau_drm_screen_unref(&screen->base))
343 return;
344
345 if (screen->base.fence.current) {
346 struct nouveau_fence *current = NULL;
347
348 /* nouveau_fence_wait will create a new current fence, so wait on the
349 * _current_ one, and remove both.
350 */
351 nouveau_fence_ref(screen->base.fence.current, &current);
352 nouveau_fence_wait(current);
353 nouveau_fence_ref(NULL, &current);
354 nouveau_fence_ref(NULL, &screen->base.fence.current);
355 }
356
357 nouveau_bo_ref(NULL, &screen->notify);
358
359 nouveau_heap_destroy(&screen->query_heap);
360 nouveau_heap_destroy(&screen->vp_exec_heap);
361 nouveau_heap_destroy(&screen->vp_data_heap);
362
363 nouveau_object_del(&screen->query);
364 nouveau_object_del(&screen->fence);
365 nouveau_object_del(&screen->ntfy);
366
367 nouveau_object_del(&screen->sifm);
368 nouveau_object_del(&screen->swzsurf);
369 nouveau_object_del(&screen->surf2d);
370 nouveau_object_del(&screen->m2mf);
371 nouveau_object_del(&screen->eng3d);
372 nouveau_object_del(&screen->null);
373
374 nouveau_screen_fini(&screen->base);
375 FREE(screen);
376 }
377
378 #define FAIL_SCREEN_INIT(str, err) \
379 do { \
380 NOUVEAU_ERR(str, err); \
381 nv30_screen_destroy(pscreen); \
382 return NULL; \
383 } while(0)
384
385 struct pipe_screen *
386 nv30_screen_create(struct nouveau_device *dev)
387 {
388 struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
389 struct pipe_screen *pscreen;
390 struct nouveau_pushbuf *push;
391 struct nv04_fifo *fifo;
392 unsigned oclass = 0;
393 int ret, i;
394
395 if (!screen)
396 return NULL;
397
398 switch (dev->chipset & 0xf0) {
399 case 0x30:
400 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
401 oclass = NV30_3D_CLASS;
402 else
403 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
404 oclass = NV34_3D_CLASS;
405 else
406 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
407 oclass = NV35_3D_CLASS;
408 break;
409 case 0x40:
410 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
411 oclass = NV40_3D_CLASS;
412 else
413 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
414 oclass = NV44_3D_CLASS;
415 break;
416 case 0x60:
417 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
418 oclass = NV44_3D_CLASS;
419 break;
420 default:
421 break;
422 }
423
424 if (!oclass) {
425 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
426 FREE(screen);
427 return NULL;
428 }
429
430 pscreen = &screen->base.base;
431 pscreen->destroy = nv30_screen_destroy;
432 pscreen->get_param = nv30_screen_get_param;
433 pscreen->get_paramf = nv30_screen_get_paramf;
434 pscreen->get_shader_param = nv30_screen_get_shader_param;
435 pscreen->context_create = nv30_context_create;
436 pscreen->is_format_supported = nv30_screen_is_format_supported;
437 nv30_resource_screen_init(pscreen);
438 nouveau_screen_init_vdec(&screen->base);
439
440 screen->base.fence.emit = nv30_screen_fence_emit;
441 screen->base.fence.update = nv30_screen_fence_update;
442
443 ret = nouveau_screen_init(&screen->base, dev);
444 if (ret)
445 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
446
447 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
448 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
449 if (oclass == NV40_3D_CLASS) {
450 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
451 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
452 }
453
454 fifo = screen->base.channel->data;
455 push = screen->base.pushbuf;
456 push->rsvd_kick = 16;
457
458 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
459 NULL, 0, &screen->null);
460 if (ret)
461 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
462
463 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
464 * this means that the address pointed at by the DMA object must
465 * be 4KiB aligned, which means this object needs to be the first
466 * one allocated on the channel.
467 */
468 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
469 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
470 .length = 32 }, sizeof(struct nv04_notify),
471 &screen->fence);
472 if (ret)
473 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
474
475 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
476 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
477 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
478 .length = 32 }, sizeof(struct nv04_notify),
479 &screen->ntfy);
480 if (ret)
481 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
482
483 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
484 * the remainder of the "notifier block" assigned by the kernel for
485 * use as query objects
486 */
487 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
488 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
489 .length = 4096 - 128 }, sizeof(struct nv04_notify),
490 &screen->query);
491 if (ret)
492 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
493
494 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
495 if (ret)
496 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
497
498 LIST_INITHEAD(&screen->queries);
499
500 /* Vertex program resources (code/data), currently 6 of the constant
501 * slots are reserved to implement user clipping planes
502 */
503 if (oclass < NV40_3D_CLASS) {
504 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
505 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
506 } else {
507 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
508 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
509 }
510
511 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
512 if (ret == 0)
513 nouveau_bo_map(screen->notify, 0, screen->base.client);
514 if (ret)
515 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
516
517 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
518 NULL, 0, &screen->eng3d);
519 if (ret)
520 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
521
522 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
523 PUSH_DATA (push, screen->eng3d->handle);
524 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
525 PUSH_DATA (push, screen->ntfy->handle);
526 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
527 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
528 PUSH_DATA (push, fifo->vram); /* COLOR1 */
529 PUSH_DATA (push, screen->null->handle); /* UNK190 */
530 PUSH_DATA (push, fifo->vram); /* COLOR0 */
531 PUSH_DATA (push, fifo->vram); /* ZETA */
532 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
533 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
534 PUSH_DATA (push, screen->fence->handle); /* FENCE */
535 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
536 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
537 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
538 if (screen->eng3d->oclass < NV40_3D_CLASS) {
539 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
540 PUSH_DATA (push, 0x00100000);
541 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
542 PUSH_DATA (push, 3);
543
544 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
545 PUSH_DATA (push, 0);
546 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
547 PUSH_DATA (push, fui(0.0));
548 PUSH_DATA (push, fui(0.0));
549 PUSH_DATA (push, fui(1.0));
550 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
551 for (i = 0; i < 16; i++)
552 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
553
554 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
555 PUSH_DATA (push, 0);
556 } else {
557 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
558 PUSH_DATA (push, fifo->vram);
559 PUSH_DATA (push, fifo->vram); /* COLOR3 */
560
561 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
562 PUSH_DATA (push, 0x00000004);
563
564 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
565 PUSH_DATA (push, 0x00000010);
566 PUSH_DATA (push, 0x01000100);
567 PUSH_DATA (push, 0xff800006);
568
569 /* vtxprog output routing */
570 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
571 PUSH_DATA (push, 0x06144321);
572 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
573 PUSH_DATA (push, 0xedcba987);
574 PUSH_DATA (push, 0x0000006f);
575 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
576 PUSH_DATA (push, 0x00171615);
577 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
578 PUSH_DATA (push, 0x001b1a19);
579
580 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
581 PUSH_DATA (push, 0x0020ffff);
582 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
583 PUSH_DATA (push, 0x01d300d4);
584
585 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
586 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
587 }
588
589 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
590 NULL, 0, &screen->m2mf);
591 if (ret)
592 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
593
594 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
595 PUSH_DATA (push, screen->m2mf->handle);
596 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
597 PUSH_DATA (push, screen->ntfy->handle);
598
599 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
600 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
601 if (ret)
602 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
603
604 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
605 PUSH_DATA (push, screen->surf2d->handle);
606 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
607 PUSH_DATA (push, screen->ntfy->handle);
608
609 if (dev->chipset < 0x40)
610 oclass = NV30_SURFACE_SWZ_CLASS;
611 else
612 oclass = NV40_SURFACE_SWZ_CLASS;
613
614 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
615 NULL, 0, &screen->swzsurf);
616 if (ret)
617 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
618
619 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
620 PUSH_DATA (push, screen->swzsurf->handle);
621 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
622 PUSH_DATA (push, screen->ntfy->handle);
623
624 if (dev->chipset < 0x40)
625 oclass = NV30_SIFM_CLASS;
626 else
627 oclass = NV40_SIFM_CLASS;
628
629 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
630 NULL, 0, &screen->sifm);
631 if (ret)
632 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
633
634 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
635 PUSH_DATA (push, screen->sifm->handle);
636 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
637 PUSH_DATA (push, screen->ntfy->handle);
638 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
639 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
640
641 nouveau_pushbuf_kick(push, push->channel);
642
643 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
644 return pscreen;
645 }