2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
50 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
52 struct nv30_screen
*screen
= nv30_screen(pscreen
);
53 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS
:
59 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
66 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
68 case PIPE_CAP_ENDIANNESS
:
69 return PIPE_ENDIAN_LITTLE
;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
72 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
73 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
74 case PIPE_CAP_MAX_VIEWPORTS
:
76 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
78 /* supported capabilities */
79 case PIPE_CAP_TWO_SIDED_STENCIL
:
80 case PIPE_CAP_ANISOTROPIC_FILTER
:
81 case PIPE_CAP_POINT_SPRITE
:
82 case PIPE_CAP_OCCLUSION_QUERY
:
83 case PIPE_CAP_QUERY_TIME_ELAPSED
:
84 case PIPE_CAP_QUERY_TIMESTAMP
:
85 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
86 case PIPE_CAP_TEXTURE_SWIZZLE
:
87 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
88 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
89 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
90 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
91 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
92 case PIPE_CAP_TGSI_TEXCOORD
:
93 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
94 case PIPE_CAP_USER_INDEX_BUFFERS
:
95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
96 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
97 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
98 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
99 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
101 /* nv35 capabilities */
102 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
103 return eng3d
->oclass
== NV35_3D_CLASS
|| eng3d
->oclass
>= NV40_3D_CLASS
;
104 /* nv4x capabilities */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
106 case PIPE_CAP_NPOT_TEXTURES
:
107 case PIPE_CAP_CONDITIONAL_RENDER
:
108 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
109 case PIPE_CAP_PRIMITIVE_RESTART
:
110 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
112 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
114 case PIPE_CAP_INDEP_BLEND_ENABLE
:
115 case PIPE_CAP_INDEP_BLEND_FUNC
:
116 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
117 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
118 case PIPE_CAP_TGSI_INSTANCEID
:
119 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
120 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
121 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
122 case PIPE_CAP_MIN_TEXEL_OFFSET
:
123 case PIPE_CAP_MAX_TEXEL_OFFSET
:
124 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
128 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
129 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
130 case PIPE_CAP_MAX_VERTEX_STREAMS
:
131 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
132 case PIPE_CAP_TEXTURE_BARRIER
:
133 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
135 case PIPE_CAP_CUBE_MAP_ARRAY
:
136 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
137 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
138 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
139 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
140 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
141 case PIPE_CAP_START_INSTANCE
:
142 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
143 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
144 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
145 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
146 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
147 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
148 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
149 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
150 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
151 case PIPE_CAP_TEXTURE_GATHER_SM5
:
152 case PIPE_CAP_FAKE_SW_MSAA
:
153 case PIPE_CAP_TEXTURE_QUERY_LOD
:
154 case PIPE_CAP_SAMPLE_SHADING
:
155 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
156 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
157 case PIPE_CAP_USER_VERTEX_BUFFERS
:
158 case PIPE_CAP_COMPUTE
:
159 case PIPE_CAP_DRAW_INDIRECT
:
160 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
161 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
162 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
163 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
164 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
165 case PIPE_CAP_CLIP_HALFZ
:
166 case PIPE_CAP_VERTEXID_NOBASE
:
167 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
168 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
169 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
170 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
172 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
173 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
174 case PIPE_CAP_TGSI_TXQS
:
175 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
176 case PIPE_CAP_SHAREABLE_SHADERS
:
177 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
178 case PIPE_CAP_CLEAR_TEXTURE
:
179 case PIPE_CAP_DRAW_PARAMETERS
:
180 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
181 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
182 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
183 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
184 case PIPE_CAP_INVALIDATE_BUFFER
:
185 case PIPE_CAP_GENERATE_MIPMAP
:
186 case PIPE_CAP_STRING_MARKER
:
187 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
188 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
191 case PIPE_CAP_VENDOR_ID
:
193 case PIPE_CAP_DEVICE_ID
: {
195 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
196 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
201 case PIPE_CAP_ACCELERATED
:
203 case PIPE_CAP_VIDEO_MEMORY
:
204 return dev
->vram_size
>> 20;
209 debug_printf("unknown param %d\n", param
);
214 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
216 struct nv30_screen
*screen
= nv30_screen(pscreen
);
217 struct nouveau_object
*eng3d
= screen
->eng3d
;
220 case PIPE_CAPF_MAX_LINE_WIDTH
:
221 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
223 case PIPE_CAPF_MAX_POINT_WIDTH
:
224 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
226 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
227 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
228 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
231 debug_printf("unknown paramf %d\n", param
);
237 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
238 enum pipe_shader_cap param
)
240 struct nv30_screen
*screen
= nv30_screen(pscreen
);
241 struct nouveau_object
*eng3d
= screen
->eng3d
;
244 case PIPE_SHADER_VERTEX
:
246 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
247 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
248 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
249 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
250 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
251 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
252 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
254 case PIPE_SHADER_CAP_MAX_INPUTS
:
255 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
257 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
258 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
259 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
261 case PIPE_SHADER_CAP_MAX_TEMPS
:
262 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
263 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
264 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
266 case PIPE_SHADER_CAP_MAX_PREDS
:
267 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
268 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
269 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
270 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
271 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
272 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
273 case PIPE_SHADER_CAP_SUBROUTINES
:
274 case PIPE_SHADER_CAP_INTEGERS
:
275 case PIPE_SHADER_CAP_DOUBLES
:
276 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
277 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
278 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
279 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
280 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
282 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
285 debug_printf("unknown vertex shader param %d\n", param
);
289 case PIPE_SHADER_FRAGMENT
:
291 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
292 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
293 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
294 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
296 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
298 case PIPE_SHADER_CAP_MAX_INPUTS
:
299 return 8; /* should be possible to do 10 with nv4x */
300 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
302 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
303 return ((eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32) * sizeof(float[4]);
304 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
306 case PIPE_SHADER_CAP_MAX_TEMPS
:
308 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
309 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
311 case PIPE_SHADER_CAP_MAX_PREDS
:
312 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
313 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
314 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
315 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
316 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
317 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
318 case PIPE_SHADER_CAP_SUBROUTINES
:
319 case PIPE_SHADER_CAP_DOUBLES
:
320 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
321 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
322 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
323 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
324 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
326 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
329 debug_printf("unknown fragment shader param %d\n", param
);
339 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
340 enum pipe_format format
,
341 enum pipe_texture_target target
,
342 unsigned sample_count
,
345 if (sample_count
> nv30_screen(pscreen
)->max_sample_count
)
348 if (!(0x00000017 & (1 << sample_count
)))
351 if (!util_format_is_supported(format
, bindings
)) {
355 /* transfers & shared are always supported */
356 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
357 PIPE_BIND_TRANSFER_WRITE
|
360 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
364 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
366 struct nv30_screen
*screen
= nv30_screen(pscreen
);
367 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
369 *sequence
= ++screen
->base
.fence
.sequence
;
371 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 3);
372 PUSH_DATA (push
, NV30_3D_FENCE_OFFSET
|
373 (2 /* size */ << 18) | (7 /* subchan */ << 13));
375 PUSH_DATA (push
, *sequence
);
379 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
381 struct nv30_screen
*screen
= nv30_screen(pscreen
);
382 struct nv04_notify
*fence
= screen
->fence
->data
;
383 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
387 nv30_screen_destroy(struct pipe_screen
*pscreen
)
389 struct nv30_screen
*screen
= nv30_screen(pscreen
);
391 if (!nouveau_drm_screen_unref(&screen
->base
))
394 if (screen
->base
.fence
.current
) {
395 struct nouveau_fence
*current
= NULL
;
397 /* nouveau_fence_wait will create a new current fence, so wait on the
398 * _current_ one, and remove both.
400 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
401 nouveau_fence_wait(current
, NULL
);
402 nouveau_fence_ref(NULL
, ¤t
);
403 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
406 nouveau_bo_ref(NULL
, &screen
->notify
);
408 nouveau_heap_destroy(&screen
->query_heap
);
409 nouveau_heap_destroy(&screen
->vp_exec_heap
);
410 nouveau_heap_destroy(&screen
->vp_data_heap
);
412 nouveau_object_del(&screen
->query
);
413 nouveau_object_del(&screen
->fence
);
414 nouveau_object_del(&screen
->ntfy
);
416 nouveau_object_del(&screen
->sifm
);
417 nouveau_object_del(&screen
->swzsurf
);
418 nouveau_object_del(&screen
->surf2d
);
419 nouveau_object_del(&screen
->m2mf
);
420 nouveau_object_del(&screen
->eng3d
);
421 nouveau_object_del(&screen
->null
);
423 nouveau_screen_fini(&screen
->base
);
427 #define FAIL_SCREEN_INIT(str, err) \
429 NOUVEAU_ERR(str, err); \
430 screen->base.base.context_create = NULL; \
431 return &screen->base; \
434 struct nouveau_screen
*
435 nv30_screen_create(struct nouveau_device
*dev
)
437 struct nv30_screen
*screen
;
438 struct pipe_screen
*pscreen
;
439 struct nouveau_pushbuf
*push
;
440 struct nv04_fifo
*fifo
;
444 switch (dev
->chipset
& 0xf0) {
446 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
447 oclass
= NV30_3D_CLASS
;
449 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
450 oclass
= NV34_3D_CLASS
;
452 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
453 oclass
= NV35_3D_CLASS
;
456 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
457 oclass
= NV40_3D_CLASS
;
459 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
460 oclass
= NV44_3D_CLASS
;
463 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
464 oclass
= NV44_3D_CLASS
;
471 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
475 screen
= CALLOC_STRUCT(nv30_screen
);
479 pscreen
= &screen
->base
.base
;
480 pscreen
->destroy
= nv30_screen_destroy
;
483 * Some modern apps try to use msaa without keeping in mind the
484 * restrictions on videomem of older cards. Resulting in dmesg saying:
485 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
486 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
487 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
489 * Because we are running out of video memory, after which the program
490 * using the msaa visual freezes, and eventually the entire system freezes.
492 * To work around this we do not allow msaa visauls by default and allow
493 * the user to override this via NV30_MAX_MSAA.
495 screen
->max_sample_count
= debug_get_num_option("NV30_MAX_MSAA", 0);
496 if (screen
->max_sample_count
> 4)
497 screen
->max_sample_count
= 4;
499 pscreen
->get_param
= nv30_screen_get_param
;
500 pscreen
->get_paramf
= nv30_screen_get_paramf
;
501 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
502 pscreen
->context_create
= nv30_context_create
;
503 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
504 nv30_resource_screen_init(pscreen
);
505 nouveau_screen_init_vdec(&screen
->base
);
507 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
508 screen
->base
.fence
.update
= nv30_screen_fence_update
;
510 ret
= nouveau_screen_init(&screen
->base
, dev
);
512 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
514 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
515 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
516 if (oclass
== NV40_3D_CLASS
) {
517 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
518 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
521 fifo
= screen
->base
.channel
->data
;
522 push
= screen
->base
.pushbuf
;
523 push
->rsvd_kick
= 16;
525 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
526 NULL
, 0, &screen
->null
);
528 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
530 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
531 * this means that the address pointed at by the DMA object must
532 * be 4KiB aligned, which means this object needs to be the first
533 * one allocated on the channel.
535 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
536 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
537 .length
= 32 }, sizeof(struct nv04_notify
),
540 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
542 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
543 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
544 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
545 .length
= 32 }, sizeof(struct nv04_notify
),
548 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
550 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
551 * the remainder of the "notifier block" assigned by the kernel for
552 * use as query objects
554 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
555 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
556 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
559 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
561 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
563 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
565 LIST_INITHEAD(&screen
->queries
);
567 /* Vertex program resources (code/data), currently 6 of the constant
568 * slots are reserved to implement user clipping planes
570 if (oclass
< NV40_3D_CLASS
) {
571 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
572 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
574 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
575 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
578 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
580 ret
= nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
582 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
584 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
585 NULL
, 0, &screen
->eng3d
);
587 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
589 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
590 PUSH_DATA (push
, screen
->eng3d
->handle
);
591 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
592 PUSH_DATA (push
, screen
->ntfy
->handle
);
593 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
594 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
595 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
596 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
597 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
598 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
599 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
600 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
601 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
602 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
603 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
604 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
605 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
606 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
607 PUSH_DATA (push
, 0x00100000);
608 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
611 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
613 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
614 PUSH_DATA (push
, fui(0.0));
615 PUSH_DATA (push
, fui(0.0));
616 PUSH_DATA (push
, fui(1.0));
617 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
618 for (i
= 0; i
< 16; i
++)
619 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
621 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
624 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
625 PUSH_DATA (push
, fifo
->vram
);
626 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
628 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
629 PUSH_DATA (push
, 0x00000004);
631 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
632 PUSH_DATA (push
, 0x00000010);
633 PUSH_DATA (push
, 0x01000100);
634 PUSH_DATA (push
, 0xff800006);
636 /* vtxprog output routing */
637 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
638 PUSH_DATA (push
, 0x06144321);
639 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
640 PUSH_DATA (push
, 0xedcba987);
641 PUSH_DATA (push
, 0x0000006f);
642 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
643 PUSH_DATA (push
, 0x00171615);
644 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
645 PUSH_DATA (push
, 0x001b1a19);
647 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
648 PUSH_DATA (push
, 0x0020ffff);
649 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
650 PUSH_DATA (push
, 0x01d300d4);
652 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
653 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
656 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
657 NULL
, 0, &screen
->m2mf
);
659 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
661 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
662 PUSH_DATA (push
, screen
->m2mf
->handle
);
663 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
664 PUSH_DATA (push
, screen
->ntfy
->handle
);
666 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
667 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
669 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
671 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
672 PUSH_DATA (push
, screen
->surf2d
->handle
);
673 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
674 PUSH_DATA (push
, screen
->ntfy
->handle
);
676 if (dev
->chipset
< 0x40)
677 oclass
= NV30_SURFACE_SWZ_CLASS
;
679 oclass
= NV40_SURFACE_SWZ_CLASS
;
681 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
682 NULL
, 0, &screen
->swzsurf
);
684 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
686 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
687 PUSH_DATA (push
, screen
->swzsurf
->handle
);
688 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
689 PUSH_DATA (push
, screen
->ntfy
->handle
);
691 if (dev
->chipset
< 0x40)
692 oclass
= NV30_SIFM_CLASS
;
694 oclass
= NV40_SIFM_CLASS
;
696 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
697 NULL
, 0, &screen
->sifm
);
699 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
701 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
702 PUSH_DATA (push
, screen
->sifm
->handle
);
703 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
704 PUSH_DATA (push
, screen
->ntfy
->handle
);
705 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
706 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
708 nouveau_pushbuf_kick(push
, push
->channel
);
710 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
711 return &screen
->base
;