src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_screen.h"
  31
  32 #include "nv_object.xml.h"
  33 #include "nv_m2mf.xml.h"
  34 #include "nv30/nv30-40_3d.xml.h"
  35 #include "nv30/nv01_2d.xml.h"
  36
  37 #include "nouveau_fence.h"
  38 #include "nv30/nv30_screen.h"
  39 #include "nv30/nv30_context.h"
  40 #include "nv30/nv30_resource.h"
  41 #include "nv30/nv30_format.h"
  42
  43 #define RANKINE_0397_CHIPSET 0x00000003
  44 #define RANKINE_0497_CHIPSET 0x000001e0
  45 #define RANKINE_0697_CHIPSET 0x00000010
  46 #define CURIE_4097_CHIPSET   0x00000baf
  47 #define CURIE_4497_CHIPSET   0x00005450
  48 #define CURIE_4497_CHIPSET6X 0x00000088
  49
  50 static int
  51 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53    struct nv30_screen *screen = nv30_screen(pscreen);
  54    struct nouveau_object *eng3d = screen->eng3d;
  55    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  56
  57    switch (param) {
  58    /* non-boolean capabilities */
  59    case PIPE_CAP_MAX_RENDER_TARGETS:
  60       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  61    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  62       return 4096;
  63    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  64       return 10;
  65    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  66       return 13;
  67    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  68    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
  69       return 120;
  70    case PIPE_CAP_ENDIANNESS:
  71       return PIPE_ENDIAN_LITTLE;
  72    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  73       return 16;
  74    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  75       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  76    case PIPE_CAP_MAX_VIEWPORTS:
  77       return 1;
  78    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  79       return 2048;
  80    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
  81       return 8 * 1024 * 1024;
  82    case PIPE_CAP_MAX_VARYINGS:
  83       return 8;
  84
  85    /* supported capabilities */
  86    case PIPE_CAP_ANISOTROPIC_FILTER:
  87    case PIPE_CAP_POINT_SPRITE:
  88    case PIPE_CAP_OCCLUSION_QUERY:
  89    case PIPE_CAP_QUERY_TIME_ELAPSED:
  90    case PIPE_CAP_QUERY_TIMESTAMP:
  91    case PIPE_CAP_TEXTURE_SWIZZLE:
  92    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  93    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  94    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  95    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  96    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  97    case PIPE_CAP_TGSI_TEXCOORD:
  98    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  99    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 100    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 101    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 102    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 103    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 104       return 1;
 105    /* nv35 capabilities */
 106    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 107       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 108    /* nv4x capabilities */
 109    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 110    case PIPE_CAP_NPOT_TEXTURES:
 111    case PIPE_CAP_CONDITIONAL_RENDER:
 112    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 113    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 114    case PIPE_CAP_PRIMITIVE_RESTART:
 115       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 116    /* unsupported */
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 118    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 119    case PIPE_CAP_SM3:
 120    case PIPE_CAP_INDEP_BLEND_ENABLE:
 121    case PIPE_CAP_INDEP_BLEND_FUNC:
 122    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 123    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 124    case PIPE_CAP_TGSI_INSTANCEID:
 125    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 127    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 128    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 129    case PIPE_CAP_MIN_TEXEL_OFFSET:
 130    case PIPE_CAP_MAX_TEXEL_OFFSET:
 131    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 132    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 133    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 134    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 135    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 136    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 137    case PIPE_CAP_MAX_VERTEX_STREAMS:
 138    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 139    case PIPE_CAP_TEXTURE_BARRIER:
 140    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 141    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 142    case PIPE_CAP_CUBE_MAP_ARRAY:
 143    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 144    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 145    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 146    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 147    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 148    case PIPE_CAP_START_INSTANCE:
 149    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 150    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 151    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 152    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 153    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 154    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 155    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 156    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 157    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 158    case PIPE_CAP_TEXTURE_GATHER_SM5:
 159    case PIPE_CAP_FAKE_SW_MSAA:
 160    case PIPE_CAP_TEXTURE_QUERY_LOD:
 161    case PIPE_CAP_SAMPLE_SHADING:
 162    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 163    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 164    case PIPE_CAP_USER_VERTEX_BUFFERS:
 165    case PIPE_CAP_COMPUTE:
 166    case PIPE_CAP_DRAW_INDIRECT:
 167    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 168    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 169    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 170    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 171    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 172    case PIPE_CAP_CLIP_HALFZ:
 173    case PIPE_CAP_VERTEXID_NOBASE:
 174    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 175    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 176    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 177    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 178    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 179    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 180    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 181    case PIPE_CAP_TGSI_TXQS:
 182    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 183    case PIPE_CAP_SHAREABLE_SHADERS:
 184    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 185    case PIPE_CAP_CLEAR_TEXTURE:
 186    case PIPE_CAP_DRAW_PARAMETERS:
 187    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 188    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 189    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 190    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 191    case PIPE_CAP_INVALIDATE_BUFFER:
 192    case PIPE_CAP_GENERATE_MIPMAP:
 193    case PIPE_CAP_STRING_MARKER:
 194    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 195    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 196    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 197    case PIPE_CAP_QUERY_MEMORY_INFO:
 198    case PIPE_CAP_PCI_GROUP:
 199    case PIPE_CAP_PCI_BUS:
 200    case PIPE_CAP_PCI_DEVICE:
 201    case PIPE_CAP_PCI_FUNCTION:
 202    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 203    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 204    case PIPE_CAP_CULL_DISTANCE:
 205    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 206    case PIPE_CAP_TGSI_VOTE:
 207    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 208    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 209    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 210    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 211    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 212    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 213    case PIPE_CAP_NATIVE_FENCE_FD:
 214    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 215    case PIPE_CAP_FBFETCH:
 216    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 217    case PIPE_CAP_DOUBLES:
 218    case PIPE_CAP_INT64:
 219    case PIPE_CAP_INT64_DIVMOD:
 220    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 221    case PIPE_CAP_TGSI_CLOCK:
 222    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 223    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 224    case PIPE_CAP_TGSI_BALLOT:
 225    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 226    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 227    case PIPE_CAP_POST_DEPTH_COVERAGE:
 228    case PIPE_CAP_BINDLESS_TEXTURE:
 229    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 230    case PIPE_CAP_QUERY_SO_OVERFLOW:
 231    case PIPE_CAP_MEMOBJ:
 232    case PIPE_CAP_LOAD_CONSTBUF:
 233    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 234    case PIPE_CAP_TILE_RASTER_ORDER:
 235    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 236    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 237    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 238    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 239    case PIPE_CAP_FENCE_SIGNAL:
 240    case PIPE_CAP_CONSTBUF0_FLAGS:
 241    case PIPE_CAP_PACKED_UNIFORMS:
 242    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 243    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 244    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 245    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 246    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 247    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 248    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 249    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 250    case PIPE_CAP_TGSI_DIV:
 251       return 0;
 252
 253    case PIPE_CAP_MAX_GS_INVOCATIONS:
 254       return 32;
 255    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 256       return 1 << 27;
 257    case PIPE_CAP_VENDOR_ID:
 258       return 0x10de;
 259    case PIPE_CAP_DEVICE_ID: {
 260       uint64_t device_id;
 261       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 262          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 263          return -1;
 264       }
 265       return device_id;
 266    }
 267    case PIPE_CAP_ACCELERATED:
 268       return 1;
 269    case PIPE_CAP_VIDEO_MEMORY:
 270       return dev->vram_size >> 20;
 271    case PIPE_CAP_UMA:
 272       return 0;
 273    default:
 274       return u_pipe_screen_get_param_defaults(pscreen, param);
 275    }
 276 }
 277
 278 static float
 279 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 280 {
 281    struct nv30_screen *screen = nv30_screen(pscreen);
 282    struct nouveau_object *eng3d = screen->eng3d;
 283
 284    switch (param) {
 285    case PIPE_CAPF_MAX_LINE_WIDTH:
 286    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 287       return 10.0;
 288    case PIPE_CAPF_MAX_POINT_WIDTH:
 289    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 290       return 64.0;
 291    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 292       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 293    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 294       return 15.0;
 295    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 296    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 297    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 298       return 0.0;
 299    default:
 300       debug_printf("unknown paramf %d\n", param);
 301       return 0;
 302    }
 303 }
 304
 305 static int
 306 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 307                              enum pipe_shader_type shader,
 308                              enum pipe_shader_cap param)
 309 {
 310    struct nv30_screen *screen = nv30_screen(pscreen);
 311    struct nouveau_object *eng3d = screen->eng3d;
 312
 313    switch (shader) {
 314    case PIPE_SHADER_VERTEX:
 315       switch (param) {
 316       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 317       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 318          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 319       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 320       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 321          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 322       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 323          return 0;
 324       case PIPE_SHADER_CAP_MAX_INPUTS:
 325       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 326          return 16;
 327       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 328          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 329       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 330          return 1;
 331       case PIPE_SHADER_CAP_MAX_TEMPS:
 332          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 333       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 334          return 32;
 335       case PIPE_SHADER_CAP_PREFERRED_IR:
 336          return PIPE_SHADER_IR_TGSI;
 337       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 338       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 339          return 0;
 340       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 341       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 342       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 343       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 344       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 345       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 346       case PIPE_SHADER_CAP_SUBROUTINES:
 347       case PIPE_SHADER_CAP_INTEGERS:
 348       case PIPE_SHADER_CAP_INT64_ATOMICS:
 349       case PIPE_SHADER_CAP_FP16:
 350       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 351       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 352       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 353       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 354       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 355       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 356       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 357       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 358       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 359       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 360       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 361       case PIPE_SHADER_CAP_SCALAR_ISA:
 362          return 0;
 363       default:
 364          debug_printf("unknown vertex shader param %d\n", param);
 365          return 0;
 366       }
 367       break;
 368    case PIPE_SHADER_FRAGMENT:
 369       switch (param) {
 370       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 371       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 372       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 373       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 374          return 4096;
 375       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 376          return 0;
 377       case PIPE_SHADER_CAP_MAX_INPUTS:
 378          return 8; /* should be possible to do 10 with nv4x */
 379       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 380          return 4;
 381       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 382          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 383       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 384          return 1;
 385       case PIPE_SHADER_CAP_MAX_TEMPS:
 386          return 32;
 387       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 388       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 389          return 16;
 390       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 391          return 32;
 392       case PIPE_SHADER_CAP_PREFERRED_IR:
 393          return PIPE_SHADER_IR_TGSI;
 394       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 395       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 396       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 397       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 398       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 399       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 400       case PIPE_SHADER_CAP_SUBROUTINES:
 401       case PIPE_SHADER_CAP_INTEGERS:
 402       case PIPE_SHADER_CAP_FP16:
 403       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 404       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 405       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 406       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 407       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 408       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 409       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 410       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 411       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 412       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 413       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 414       case PIPE_SHADER_CAP_SCALAR_ISA:
 415          return 0;
 416       default:
 417          debug_printf("unknown fragment shader param %d\n", param);
 418          return 0;
 419       }
 420       break;
 421    default:
 422       return 0;
 423    }
 424 }
 425
 426 static boolean
 427 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 428                                 enum pipe_format format,
 429                                 enum pipe_texture_target target,
 430                                 unsigned sample_count,
 431                                 unsigned storage_sample_count,
 432                                 unsigned bindings)
 433 {
 434    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 435       return false;
 436
 437    if (!(0x00000017 & (1 << sample_count)))
 438       return false;
 439
 440    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 441       return false;
 442
 443    /* No way to render to a swizzled 3d texture. We don't necessarily know if
 444     * it's swizzled or not here, but we have to assume anyways.
 445     */
 446    if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
 447       return false;
 448
 449    /* shared is always supported */
 450    bindings &= ~PIPE_BIND_SHARED;
 451
 452    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 453 }
 454
 455 static void
 456 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 457 {
 458    struct nv30_screen *screen = nv30_screen(pscreen);
 459    struct nouveau_pushbuf *push = screen->base.pushbuf;
 460
 461    *sequence = ++screen->base.fence.sequence;
 462
 463    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 464    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 465               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 466    PUSH_DATA (push, 0);
 467    PUSH_DATA (push, *sequence);
 468 }
 469
 470 static uint32_t
 471 nv30_screen_fence_update(struct pipe_screen *pscreen)
 472 {
 473    struct nv30_screen *screen = nv30_screen(pscreen);
 474    struct nv04_notify *fence = screen->fence->data;
 475    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 476 }
 477
 478 static void
 479 nv30_screen_destroy(struct pipe_screen *pscreen)
 480 {
 481    struct nv30_screen *screen = nv30_screen(pscreen);
 482
 483    if (!nouveau_drm_screen_unref(&screen->base))
 484       return;
 485
 486    if (screen->base.fence.current) {
 487       struct nouveau_fence *current = NULL;
 488
 489       /* nouveau_fence_wait will create a new current fence, so wait on the
 490        * _current_ one, and remove both.
 491        */
 492       nouveau_fence_ref(screen->base.fence.current, &current);
 493       nouveau_fence_wait(current, NULL);
 494       nouveau_fence_ref(NULL, &current);
 495       nouveau_fence_ref(NULL, &screen->base.fence.current);
 496    }
 497
 498    nouveau_bo_ref(NULL, &screen->notify);
 499
 500    nouveau_heap_destroy(&screen->query_heap);
 501    nouveau_heap_destroy(&screen->vp_exec_heap);
 502    nouveau_heap_destroy(&screen->vp_data_heap);
 503
 504    nouveau_object_del(&screen->query);
 505    nouveau_object_del(&screen->fence);
 506    nouveau_object_del(&screen->ntfy);
 507
 508    nouveau_object_del(&screen->sifm);
 509    nouveau_object_del(&screen->swzsurf);
 510    nouveau_object_del(&screen->surf2d);
 511    nouveau_object_del(&screen->m2mf);
 512    nouveau_object_del(&screen->eng3d);
 513    nouveau_object_del(&screen->null);
 514
 515    nouveau_screen_fini(&screen->base);
 516    FREE(screen);
 517 }
 518
 519 #define FAIL_SCREEN_INIT(str, err)                    \
 520    do {                                               \
 521       NOUVEAU_ERR(str, err);                          \
 522       screen->base.base.context_create = NULL;        \
 523       return &screen->base;                           \
 524    } while(0)
 525
 526 struct nouveau_screen *
 527 nv30_screen_create(struct nouveau_device *dev)
 528 {
 529    struct nv30_screen *screen;
 530    struct pipe_screen *pscreen;
 531    struct nouveau_pushbuf *push;
 532    struct nv04_fifo *fifo;
 533    unsigned oclass = 0;
 534    int ret, i;
 535
 536    switch (dev->chipset & 0xf0) {
 537    case 0x30:
 538       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 539          oclass = NV30_3D_CLASS;
 540       else
 541       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 542          oclass = NV34_3D_CLASS;
 543       else
 544       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 545          oclass = NV35_3D_CLASS;
 546       break;
 547    case 0x40:
 548       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 549          oclass = NV40_3D_CLASS;
 550       else
 551       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 552          oclass = NV44_3D_CLASS;
 553       break;
 554    case 0x60:
 555       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 556          oclass = NV44_3D_CLASS;
 557       break;
 558    default:
 559       break;
 560    }
 561
 562    if (!oclass) {
 563       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 564       return NULL;
 565    }
 566
 567    screen = CALLOC_STRUCT(nv30_screen);
 568    if (!screen)
 569       return NULL;
 570
 571    pscreen = &screen->base.base;
 572    pscreen->destroy = nv30_screen_destroy;
 573
 574    /*
 575     * Some modern apps try to use msaa without keeping in mind the
 576     * restrictions on videomem of older cards. Resulting in dmesg saying:
 577     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 578     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 579     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 580     *
 581     * Because we are running out of video memory, after which the program
 582     * using the msaa visual freezes, and eventually the entire system freezes.
 583     *
 584     * To work around this we do not allow msaa visauls by default and allow
 585     * the user to override this via NV30_MAX_MSAA.
 586     */
 587    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 588    if (screen->max_sample_count > 4)
 589       screen->max_sample_count = 4;
 590
 591    pscreen->get_param = nv30_screen_get_param;
 592    pscreen->get_paramf = nv30_screen_get_paramf;
 593    pscreen->get_shader_param = nv30_screen_get_shader_param;
 594    pscreen->context_create = nv30_context_create;
 595    pscreen->is_format_supported = nv30_screen_is_format_supported;
 596    nv30_resource_screen_init(pscreen);
 597    nouveau_screen_init_vdec(&screen->base);
 598
 599    screen->base.fence.emit = nv30_screen_fence_emit;
 600    screen->base.fence.update = nv30_screen_fence_update;
 601
 602    ret = nouveau_screen_init(&screen->base, dev);
 603    if (ret)
 604       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 605
 606    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 607    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 608    if (oclass == NV40_3D_CLASS) {
 609       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 610       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 611    }
 612
 613    fifo = screen->base.channel->data;
 614    push = screen->base.pushbuf;
 615    push->rsvd_kick = 16;
 616
 617    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 618                             NULL, 0, &screen->null);
 619    if (ret)
 620       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 621
 622    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 623     * this means that the address pointed at by the DMA object must
 624     * be 4KiB aligned, which means this object needs to be the first
 625     * one allocated on the channel.
 626     */
 627    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 628                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 629                             .length = 32 }, sizeof(struct nv04_notify),
 630                             &screen->fence);
 631    if (ret)
 632       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 633
 634    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 635    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 636                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 637                             .length = 32 }, sizeof(struct nv04_notify),
 638                             &screen->ntfy);
 639    if (ret)
 640       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 641
 642    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 643     * the remainder of the "notifier block" assigned by the kernel for
 644     * use as query objects
 645     */
 646    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 647                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 648                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 649                             &screen->query);
 650    if (ret)
 651       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 652
 653    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 654    if (ret)
 655       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 656
 657    LIST_INITHEAD(&screen->queries);
 658
 659    /* Vertex program resources (code/data), currently 6 of the constant
 660     * slots are reserved to implement user clipping planes
 661     */
 662    if (oclass < NV40_3D_CLASS) {
 663       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 664       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 665    } else {
 666       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 667       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 668    }
 669
 670    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 671    if (ret == 0)
 672       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 673    if (ret)
 674       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 675
 676    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 677                             NULL, 0, &screen->eng3d);
 678    if (ret)
 679       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 680
 681    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 682    PUSH_DATA (push, screen->eng3d->handle);
 683    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 684    PUSH_DATA (push, screen->ntfy->handle);
 685    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 686    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 687    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 688    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 689    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 690    PUSH_DATA (push, fifo->vram);     /* ZETA */
 691    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 692    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 693    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 694    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 695    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 696    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 697    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 698       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 699       PUSH_DATA (push, 0x00100000);
 700       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 701       PUSH_DATA (push, 3);
 702
 703       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 704       PUSH_DATA (push, 0);
 705       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 706       PUSH_DATA (push, fui(0.0));
 707       PUSH_DATA (push, fui(0.0));
 708       PUSH_DATA (push, fui(1.0));
 709       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 710       for (i = 0; i < 16; i++)
 711          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 712
 713       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 714       PUSH_DATA (push, 0);
 715    } else {
 716       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 717       PUSH_DATA (push, fifo->vram);
 718       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 719
 720       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 721       PUSH_DATA (push, 0x00000004);
 722
 723       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 724       PUSH_DATA (push, 0x00000010);
 725       PUSH_DATA (push, 0x01000100);
 726       PUSH_DATA (push, 0xff800006);
 727
 728       /* vtxprog output routing */
 729       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 730       PUSH_DATA (push, 0x06144321);
 731       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 732       PUSH_DATA (push, 0xedcba987);
 733       PUSH_DATA (push, 0x0000006f);
 734       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 735       PUSH_DATA (push, 0x00171615);
 736       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 737       PUSH_DATA (push, 0x001b1a19);
 738
 739       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 740       PUSH_DATA (push, 0x0020ffff);
 741       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 742       PUSH_DATA (push, 0x01d300d4);
 743
 744       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 745       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 746    }
 747
 748    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 749                             NULL, 0, &screen->m2mf);
 750    if (ret)
 751       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 752
 753    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 754    PUSH_DATA (push, screen->m2mf->handle);
 755    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 756    PUSH_DATA (push, screen->ntfy->handle);
 757
 758    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 759                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 760    if (ret)
 761       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 762
 763    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 764    PUSH_DATA (push, screen->surf2d->handle);
 765    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 766    PUSH_DATA (push, screen->ntfy->handle);
 767
 768    if (dev->chipset < 0x40)
 769       oclass = NV30_SURFACE_SWZ_CLASS;
 770    else
 771       oclass = NV40_SURFACE_SWZ_CLASS;
 772
 773    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 774                             NULL, 0, &screen->swzsurf);
 775    if (ret)
 776       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 777
 778    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 779    PUSH_DATA (push, screen->swzsurf->handle);
 780    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 781    PUSH_DATA (push, screen->ntfy->handle);
 782
 783    if (dev->chipset < 0x40)
 784       oclass = NV30_SIFM_CLASS;
 785    else
 786       oclass = NV40_SIFM_CLASS;
 787
 788    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 789                             NULL, 0, &screen->sifm);
 790    if (ret)
 791       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 792
 793    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 794    PUSH_DATA (push, screen->sifm->handle);
 795    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 796    PUSH_DATA (push, screen->ntfy->handle);
 797    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 798    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 799
 800    nouveau_pushbuf_kick(push, push->channel);
 801
 802    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 803    return &screen->base;
 804 }