src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MAX_VIEWPORTS:
  73       return 1;
  74    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  75       return 2048;
  76    /* supported capabilities */
  77    case PIPE_CAP_TWO_SIDED_STENCIL:
  78    case PIPE_CAP_ANISOTROPIC_FILTER:
  79    case PIPE_CAP_POINT_SPRITE:
  80    case PIPE_CAP_OCCLUSION_QUERY:
  81    case PIPE_CAP_QUERY_TIME_ELAPSED:
  82    case PIPE_CAP_QUERY_TIMESTAMP:
  83    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  84    case PIPE_CAP_TEXTURE_SWIZZLE:
  85    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  86    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  87    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  88    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  89    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  90    case PIPE_CAP_TGSI_TEXCOORD:
  91    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  92    case PIPE_CAP_USER_INDEX_BUFFERS:
  93    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  94    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  95    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  98       return 1;
  99    /* nv4x capabilities */
 100    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 101    case PIPE_CAP_NPOT_TEXTURES:
 102    case PIPE_CAP_CONDITIONAL_RENDER:
 103    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104    case PIPE_CAP_PRIMITIVE_RESTART:
 105       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 106    /* unsupported */
 107    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 108    case PIPE_CAP_SM3:
 109    case PIPE_CAP_INDEP_BLEND_ENABLE:
 110    case PIPE_CAP_INDEP_BLEND_FUNC:
 111    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 112    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 113    case PIPE_CAP_TGSI_INSTANCEID:
 114    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 115    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 116    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 117    case PIPE_CAP_MIN_TEXEL_OFFSET:
 118    case PIPE_CAP_MAX_TEXEL_OFFSET:
 119    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 120    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125    case PIPE_CAP_MAX_VERTEX_STREAMS:
 126    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 127    case PIPE_CAP_TEXTURE_BARRIER:
 128    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 130    case PIPE_CAP_CUBE_MAP_ARRAY:
 131    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 132    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 133    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 134    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 135    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 136    case PIPE_CAP_START_INSTANCE:
 137    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 138    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 139    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 140    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 141    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 142    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 143    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 144    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 145    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 146    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 147    case PIPE_CAP_TEXTURE_GATHER_SM5:
 148    case PIPE_CAP_FAKE_SW_MSAA:
 149    case PIPE_CAP_TEXTURE_QUERY_LOD:
 150    case PIPE_CAP_SAMPLE_SHADING:
 151    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 152    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 153    case PIPE_CAP_USER_VERTEX_BUFFERS:
 154    case PIPE_CAP_COMPUTE:
 155    case PIPE_CAP_DRAW_INDIRECT:
 156    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 157    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 158    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 159    case PIPE_CAP_CLIP_HALFZ:
 160    case PIPE_CAP_VERTEXID_NOBASE:
 161       return 0;
 162
 163    case PIPE_CAP_VENDOR_ID:
 164       return 0x10de;
 165    case PIPE_CAP_DEVICE_ID: {
 166       uint64_t device_id;
 167       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 168          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 169          return -1;
 170       }
 171       return device_id;
 172    }
 173    case PIPE_CAP_ACCELERATED:
 174       return 1;
 175    case PIPE_CAP_VIDEO_MEMORY:
 176       return dev->vram_size >> 20;
 177    case PIPE_CAP_UMA:
 178       return 0;
 179    }
 180
 181    debug_printf("unknown param %d\n", param);
 182    return 0;
 183 }
 184
 185 static float
 186 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 187 {
 188    struct nv30_screen *screen = nv30_screen(pscreen);
 189    struct nouveau_object *eng3d = screen->eng3d;
 190
 191    switch (param) {
 192    case PIPE_CAPF_MAX_LINE_WIDTH:
 193    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 194       return 10.0;
 195    case PIPE_CAPF_MAX_POINT_WIDTH:
 196    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 197       return 64.0;
 198    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 199       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 200    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 201       return 15.0;
 202    default:
 203       debug_printf("unknown paramf %d\n", param);
 204       return 0;
 205    }
 206 }
 207
 208 static int
 209 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 210                              enum pipe_shader_cap param)
 211 {
 212    struct nv30_screen *screen = nv30_screen(pscreen);
 213    struct nouveau_object *eng3d = screen->eng3d;
 214
 215    switch (shader) {
 216    case PIPE_SHADER_VERTEX:
 217       switch (param) {
 218       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 219       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 220          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 221       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 222       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 223          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 224       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 225          return 0;
 226       case PIPE_SHADER_CAP_MAX_INPUTS:
 227       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 228          return 16;
 229       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 230          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 231       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 232          return 1;
 233       case PIPE_SHADER_CAP_MAX_TEMPS:
 234          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 235       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 236       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 237          return 0;
 238       case PIPE_SHADER_CAP_MAX_PREDS:
 239       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 240       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 241       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 242       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 243       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 244       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 245       case PIPE_SHADER_CAP_SUBROUTINES:
 246       case PIPE_SHADER_CAP_INTEGERS:
 247          return 0;
 248       default:
 249          debug_printf("unknown vertex shader param %d\n", param);
 250          return 0;
 251       }
 252       break;
 253    case PIPE_SHADER_FRAGMENT:
 254       switch (param) {
 255       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 256       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 257       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 258       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 259          return 4096;
 260       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 261          return 0;
 262       case PIPE_SHADER_CAP_MAX_INPUTS:
 263          return 8; /* should be possible to do 10 with nv4x */
 264       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 265          return 4;
 266       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 267          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 268       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 269          return 1;
 270       case PIPE_SHADER_CAP_MAX_TEMPS:
 271          return 32;
 272       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 273       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 274          return 16;
 275       case PIPE_SHADER_CAP_MAX_PREDS:
 276       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 277       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 278       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 279       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 280       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 281       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 282       case PIPE_SHADER_CAP_SUBROUTINES:
 283          return 0;
 284       default:
 285          debug_printf("unknown fragment shader param %d\n", param);
 286          return 0;
 287       }
 288       break;
 289    default:
 290       return 0;
 291    }
 292 }
 293
 294 static boolean
 295 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 296                                 enum pipe_format format,
 297                                 enum pipe_texture_target target,
 298                                 unsigned sample_count,
 299                                 unsigned bindings)
 300 {
 301    if (sample_count > 4)
 302       return FALSE;
 303    if (!(0x00000017 & (1 << sample_count)))
 304       return FALSE;
 305
 306    if (!util_format_is_supported(format, bindings)) {
 307       return FALSE;
 308    }
 309
 310    /* transfers & shared are always supported */
 311    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 312                  PIPE_BIND_TRANSFER_WRITE |
 313                  PIPE_BIND_SHARED);
 314
 315    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 316 }
 317
 318 static void
 319 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 320 {
 321    struct nv30_screen *screen = nv30_screen(pscreen);
 322    struct nouveau_pushbuf *push = screen->base.pushbuf;
 323
 324    *sequence = ++screen->base.fence.sequence;
 325
 326    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 327    PUSH_DATA (push, 0);
 328    PUSH_DATA (push, *sequence);
 329 }
 330
 331 static uint32_t
 332 nv30_screen_fence_update(struct pipe_screen *pscreen)
 333 {
 334    struct nv30_screen *screen = nv30_screen(pscreen);
 335    struct nv04_notify *fence = screen->fence->data;
 336    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 337 }
 338
 339 static void
 340 nv30_screen_destroy(struct pipe_screen *pscreen)
 341 {
 342    struct nv30_screen *screen = nv30_screen(pscreen);
 343
 344    if (!nouveau_drm_screen_unref(&screen->base))
 345       return;
 346
 347    if (screen->base.fence.current) {
 348       struct nouveau_fence *current = NULL;
 349
 350       /* nouveau_fence_wait will create a new current fence, so wait on the
 351        * _current_ one, and remove both.
 352        */
 353       nouveau_fence_ref(screen->base.fence.current, &current);
 354       nouveau_fence_wait(current);
 355       nouveau_fence_ref(NULL, &current);
 356       nouveau_fence_ref(NULL, &screen->base.fence.current);
 357    }
 358
 359    nouveau_bo_ref(NULL, &screen->notify);
 360
 361    nouveau_heap_destroy(&screen->query_heap);
 362    nouveau_heap_destroy(&screen->vp_exec_heap);
 363    nouveau_heap_destroy(&screen->vp_data_heap);
 364
 365    nouveau_object_del(&screen->query);
 366    nouveau_object_del(&screen->fence);
 367    nouveau_object_del(&screen->ntfy);
 368
 369    nouveau_object_del(&screen->sifm);
 370    nouveau_object_del(&screen->swzsurf);
 371    nouveau_object_del(&screen->surf2d);
 372    nouveau_object_del(&screen->m2mf);
 373    nouveau_object_del(&screen->eng3d);
 374    nouveau_object_del(&screen->null);
 375
 376    nouveau_screen_fini(&screen->base);
 377    FREE(screen);
 378 }
 379
 380 #define FAIL_SCREEN_INIT(str, err)                    \
 381    do {                                               \
 382       NOUVEAU_ERR(str, err);                          \
 383       nv30_screen_destroy(pscreen);                   \
 384       return NULL;                                    \
 385    } while(0)
 386
 387 struct pipe_screen *
 388 nv30_screen_create(struct nouveau_device *dev)
 389 {
 390    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 391    struct pipe_screen *pscreen;
 392    struct nouveau_pushbuf *push;
 393    struct nv04_fifo *fifo;
 394    unsigned oclass = 0;
 395    int ret, i;
 396
 397    if (!screen)
 398       return NULL;
 399
 400    switch (dev->chipset & 0xf0) {
 401    case 0x30:
 402       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 403          oclass = NV30_3D_CLASS;
 404       else
 405       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 406          oclass = NV34_3D_CLASS;
 407       else
 408       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 409          oclass = NV35_3D_CLASS;
 410       break;
 411    case 0x40:
 412       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 413          oclass = NV40_3D_CLASS;
 414       else
 415       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 416          oclass = NV44_3D_CLASS;
 417       break;
 418    case 0x60:
 419       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 420          oclass = NV44_3D_CLASS;
 421       break;
 422    default:
 423       break;
 424    }
 425
 426    if (!oclass) {
 427       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 428       FREE(screen);
 429       return NULL;
 430    }
 431
 432    pscreen = &screen->base.base;
 433    pscreen->destroy = nv30_screen_destroy;
 434    pscreen->get_param = nv30_screen_get_param;
 435    pscreen->get_paramf = nv30_screen_get_paramf;
 436    pscreen->get_shader_param = nv30_screen_get_shader_param;
 437    pscreen->context_create = nv30_context_create;
 438    pscreen->is_format_supported = nv30_screen_is_format_supported;
 439    nv30_resource_screen_init(pscreen);
 440    nouveau_screen_init_vdec(&screen->base);
 441
 442    screen->base.fence.emit = nv30_screen_fence_emit;
 443    screen->base.fence.update = nv30_screen_fence_update;
 444
 445    ret = nouveau_screen_init(&screen->base, dev);
 446    if (ret)
 447       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 448
 449    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 450    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 451    if (oclass == NV40_3D_CLASS) {
 452       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 453       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 454    }
 455
 456    fifo = screen->base.channel->data;
 457    push = screen->base.pushbuf;
 458    push->rsvd_kick = 16;
 459
 460    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 461                             NULL, 0, &screen->null);
 462    if (ret)
 463       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 464
 465    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 466     * this means that the address pointed at by the DMA object must
 467     * be 4KiB aligned, which means this object needs to be the first
 468     * one allocated on the channel.
 469     */
 470    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 471                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 472                             .length = 32 }, sizeof(struct nv04_notify),
 473                             &screen->fence);
 474    if (ret)
 475       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 476
 477    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 478    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 479                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 480                             .length = 32 }, sizeof(struct nv04_notify),
 481                             &screen->ntfy);
 482    if (ret)
 483       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 484
 485    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 486     * the remainder of the "notifier block" assigned by the kernel for
 487     * use as query objects
 488     */
 489    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 490                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 491                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 492                             &screen->query);
 493    if (ret)
 494       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 495
 496    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 497    if (ret)
 498       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 499
 500    LIST_INITHEAD(&screen->queries);
 501
 502    /* Vertex program resources (code/data), currently 6 of the constant
 503     * slots are reserved to implement user clipping planes
 504     */
 505    if (oclass < NV40_3D_CLASS) {
 506       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 507       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 508    } else {
 509       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 510       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 511    }
 512
 513    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 514    if (ret == 0)
 515       nouveau_bo_map(screen->notify, 0, screen->base.client);
 516    if (ret)
 517       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 518
 519    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 520                             NULL, 0, &screen->eng3d);
 521    if (ret)
 522       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 523
 524    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 525    PUSH_DATA (push, screen->eng3d->handle);
 526    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 527    PUSH_DATA (push, screen->ntfy->handle);
 528    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 529    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 530    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 531    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 532    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 533    PUSH_DATA (push, fifo->vram);     /* ZETA */
 534    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 535    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 536    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 537    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 538    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 539    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 540    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 541       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 542       PUSH_DATA (push, 0x00100000);
 543       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 544       PUSH_DATA (push, 3);
 545
 546       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 547       PUSH_DATA (push, 0);
 548       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 549       PUSH_DATA (push, fui(0.0));
 550       PUSH_DATA (push, fui(0.0));
 551       PUSH_DATA (push, fui(1.0));
 552       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 553       for (i = 0; i < 16; i++)
 554          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 555
 556       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 557       PUSH_DATA (push, 0);
 558    } else {
 559       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 560       PUSH_DATA (push, fifo->vram);
 561       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 562
 563       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 564       PUSH_DATA (push, 0x00000004);
 565
 566       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 567       PUSH_DATA (push, 0x00000010);
 568       PUSH_DATA (push, 0x01000100);
 569       PUSH_DATA (push, 0xff800006);
 570
 571       /* vtxprog output routing */
 572       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 573       PUSH_DATA (push, 0x06144321);
 574       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 575       PUSH_DATA (push, 0xedcba987);
 576       PUSH_DATA (push, 0x0000006f);
 577       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 578       PUSH_DATA (push, 0x00171615);
 579       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 580       PUSH_DATA (push, 0x001b1a19);
 581
 582       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 583       PUSH_DATA (push, 0x0020ffff);
 584       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 585       PUSH_DATA (push, 0x01d300d4);
 586
 587       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 588       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 589    }
 590
 591    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 592                             NULL, 0, &screen->m2mf);
 593    if (ret)
 594       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 595
 596    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 597    PUSH_DATA (push, screen->m2mf->handle);
 598    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 599    PUSH_DATA (push, screen->ntfy->handle);
 600
 601    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 602                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 603    if (ret)
 604       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 605
 606    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 607    PUSH_DATA (push, screen->surf2d->handle);
 608    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 609    PUSH_DATA (push, screen->ntfy->handle);
 610
 611    if (dev->chipset < 0x40)
 612       oclass = NV30_SURFACE_SWZ_CLASS;
 613    else
 614       oclass = NV40_SURFACE_SWZ_CLASS;
 615
 616    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 617                             NULL, 0, &screen->swzsurf);
 618    if (ret)
 619       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 620
 621    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 622    PUSH_DATA (push, screen->swzsurf->handle);
 623    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 624    PUSH_DATA (push, screen->ntfy->handle);
 625
 626    if (dev->chipset < 0x40)
 627       oclass = NV30_SIFM_CLASS;
 628    else
 629       oclass = NV40_SIFM_CLASS;
 630
 631    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 632                             NULL, 0, &screen->sifm);
 633    if (ret)
 634       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 635
 636    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 637    PUSH_DATA (push, screen->sifm->handle);
 638    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 639    PUSH_DATA (push, screen->ntfy->handle);
 640    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 641    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 642
 643    nouveau_pushbuf_kick(push, push->channel);
 644
 645    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 646    return pscreen;
 647 }