gallium: introduce PIPE_CAP_LOAD_CONSTBUF
[mesa.git] / src / gallium / drivers / nouveau / nv30 / nv30_screen.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
30
31 #include "nv_object.xml.h"
32 #include "nv_m2mf.xml.h"
33 #include "nv30/nv30-40_3d.xml.h"
34 #include "nv30/nv01_2d.xml.h"
35
36 #include "nouveau_fence.h"
37 #include "nv30/nv30_screen.h"
38 #include "nv30/nv30_context.h"
39 #include "nv30/nv30_resource.h"
40 #include "nv30/nv30_format.h"
41
42 #define RANKINE_0397_CHIPSET 0x00000003
43 #define RANKINE_0497_CHIPSET 0x000001e0
44 #define RANKINE_0697_CHIPSET 0x00000010
45 #define CURIE_4097_CHIPSET 0x00000baf
46 #define CURIE_4497_CHIPSET 0x00005450
47 #define CURIE_4497_CHIPSET6X 0x00000088
48
49 static int
50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
51 {
52 struct nv30_screen *screen = nv30_screen(pscreen);
53 struct nouveau_object *eng3d = screen->eng3d;
54 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
55
56 switch (param) {
57 /* non-boolean capabilities */
58 case PIPE_CAP_MAX_RENDER_TARGETS:
59 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
60 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
61 return 13;
62 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
63 return 10;
64 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
65 return 13;
66 case PIPE_CAP_GLSL_FEATURE_LEVEL:
67 return 120;
68 case PIPE_CAP_ENDIANNESS:
69 return PIPE_ENDIAN_LITTLE;
70 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
71 return 16;
72 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
73 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
74 case PIPE_CAP_MAX_VIEWPORTS:
75 return 1;
76 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
77 return 2048;
78 /* supported capabilities */
79 case PIPE_CAP_TWO_SIDED_STENCIL:
80 case PIPE_CAP_ANISOTROPIC_FILTER:
81 case PIPE_CAP_POINT_SPRITE:
82 case PIPE_CAP_OCCLUSION_QUERY:
83 case PIPE_CAP_QUERY_TIME_ELAPSED:
84 case PIPE_CAP_QUERY_TIMESTAMP:
85 case PIPE_CAP_TEXTURE_SHADOW_MAP:
86 case PIPE_CAP_TEXTURE_SWIZZLE:
87 case PIPE_CAP_DEPTH_CLIP_DISABLE:
88 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
89 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
90 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
91 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
92 case PIPE_CAP_TGSI_TEXCOORD:
93 case PIPE_CAP_USER_CONSTANT_BUFFERS:
94 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
95 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
96 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
97 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
98 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
99 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
100 return 1;
101 /* nv35 capabilities */
102 case PIPE_CAP_DEPTH_BOUNDS_TEST:
103 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
104 /* nv4x capabilities */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106 case PIPE_CAP_NPOT_TEXTURES:
107 case PIPE_CAP_CONDITIONAL_RENDER:
108 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
109 case PIPE_CAP_PRIMITIVE_RESTART:
110 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
111 /* unsupported */
112 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
113 case PIPE_CAP_SM3:
114 case PIPE_CAP_INDEP_BLEND_ENABLE:
115 case PIPE_CAP_INDEP_BLEND_FUNC:
116 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
117 case PIPE_CAP_SHADER_STENCIL_EXPORT:
118 case PIPE_CAP_TGSI_INSTANCEID:
119 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
120 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
121 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
122 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
123 case PIPE_CAP_MIN_TEXEL_OFFSET:
124 case PIPE_CAP_MAX_TEXEL_OFFSET:
125 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
126 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
128 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
129 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
130 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
131 case PIPE_CAP_MAX_VERTEX_STREAMS:
132 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
133 case PIPE_CAP_TEXTURE_BARRIER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
136 case PIPE_CAP_CUBE_MAP_ARRAY:
137 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
138 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
139 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
140 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
141 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
142 case PIPE_CAP_START_INSTANCE:
143 case PIPE_CAP_TEXTURE_MULTISAMPLE:
144 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
145 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
146 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
147 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
148 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
149 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
150 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
151 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
152 case PIPE_CAP_TEXTURE_GATHER_SM5:
153 case PIPE_CAP_FAKE_SW_MSAA:
154 case PIPE_CAP_TEXTURE_QUERY_LOD:
155 case PIPE_CAP_SAMPLE_SHADING:
156 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
157 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
158 case PIPE_CAP_USER_VERTEX_BUFFERS:
159 case PIPE_CAP_COMPUTE:
160 case PIPE_CAP_DRAW_INDIRECT:
161 case PIPE_CAP_MULTI_DRAW_INDIRECT:
162 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
163 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
164 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
165 case PIPE_CAP_SAMPLER_VIEW_TARGET:
166 case PIPE_CAP_CLIP_HALFZ:
167 case PIPE_CAP_VERTEXID_NOBASE:
168 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
169 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
170 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
171 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
172 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
173 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
174 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
175 case PIPE_CAP_TGSI_TXQS:
176 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
177 case PIPE_CAP_SHAREABLE_SHADERS:
178 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
179 case PIPE_CAP_CLEAR_TEXTURE:
180 case PIPE_CAP_DRAW_PARAMETERS:
181 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
182 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
183 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
184 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
185 case PIPE_CAP_INVALIDATE_BUFFER:
186 case PIPE_CAP_GENERATE_MIPMAP:
187 case PIPE_CAP_STRING_MARKER:
188 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
189 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
190 case PIPE_CAP_QUERY_BUFFER_OBJECT:
191 case PIPE_CAP_QUERY_MEMORY_INFO:
192 case PIPE_CAP_PCI_GROUP:
193 case PIPE_CAP_PCI_BUS:
194 case PIPE_CAP_PCI_DEVICE:
195 case PIPE_CAP_PCI_FUNCTION:
196 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
197 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
198 case PIPE_CAP_CULL_DISTANCE:
199 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
200 case PIPE_CAP_TGSI_VOTE:
201 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
202 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
203 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
204 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
205 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
206 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
207 case PIPE_CAP_NATIVE_FENCE_FD:
208 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
209 case PIPE_CAP_TGSI_FS_FBFETCH:
210 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
211 case PIPE_CAP_DOUBLES:
212 case PIPE_CAP_INT64:
213 case PIPE_CAP_INT64_DIVMOD:
214 case PIPE_CAP_TGSI_TEX_TXF_LZ:
215 case PIPE_CAP_TGSI_CLOCK:
216 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
217 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
218 case PIPE_CAP_TGSI_BALLOT:
219 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
220 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
221 case PIPE_CAP_POST_DEPTH_COVERAGE:
222 case PIPE_CAP_BINDLESS_TEXTURE:
223 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
224 case PIPE_CAP_QUERY_SO_OVERFLOW:
225 case PIPE_CAP_MEMOBJ:
226 case PIPE_CAP_LOAD_CONSTBUF:
227 return 0;
228
229 case PIPE_CAP_VENDOR_ID:
230 return 0x10de;
231 case PIPE_CAP_DEVICE_ID: {
232 uint64_t device_id;
233 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
234 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
235 return -1;
236 }
237 return device_id;
238 }
239 case PIPE_CAP_ACCELERATED:
240 return 1;
241 case PIPE_CAP_VIDEO_MEMORY:
242 return dev->vram_size >> 20;
243 case PIPE_CAP_UMA:
244 return 0;
245 }
246
247 debug_printf("unknown param %d\n", param);
248 return 0;
249 }
250
251 static float
252 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
253 {
254 struct nv30_screen *screen = nv30_screen(pscreen);
255 struct nouveau_object *eng3d = screen->eng3d;
256
257 switch (param) {
258 case PIPE_CAPF_MAX_LINE_WIDTH:
259 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
260 return 10.0;
261 case PIPE_CAPF_MAX_POINT_WIDTH:
262 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
263 return 64.0;
264 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
265 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
266 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
267 return 15.0;
268 default:
269 debug_printf("unknown paramf %d\n", param);
270 return 0;
271 }
272 }
273
274 static int
275 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
276 enum pipe_shader_type shader,
277 enum pipe_shader_cap param)
278 {
279 struct nv30_screen *screen = nv30_screen(pscreen);
280 struct nouveau_object *eng3d = screen->eng3d;
281
282 switch (shader) {
283 case PIPE_SHADER_VERTEX:
284 switch (param) {
285 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
286 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
287 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
288 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
289 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
290 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
291 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
292 return 0;
293 case PIPE_SHADER_CAP_MAX_INPUTS:
294 case PIPE_SHADER_CAP_MAX_OUTPUTS:
295 return 16;
296 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
297 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
298 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
299 return 1;
300 case PIPE_SHADER_CAP_MAX_TEMPS:
301 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
302 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
303 return 32;
304 case PIPE_SHADER_CAP_PREFERRED_IR:
305 return PIPE_SHADER_IR_TGSI;
306 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
307 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
308 return 0;
309 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
310 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
311 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
312 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
313 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
314 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
315 case PIPE_SHADER_CAP_SUBROUTINES:
316 case PIPE_SHADER_CAP_INTEGERS:
317 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
318 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
319 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
320 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
321 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
322 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
323 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
324 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
325 return 0;
326 default:
327 debug_printf("unknown vertex shader param %d\n", param);
328 return 0;
329 }
330 break;
331 case PIPE_SHADER_FRAGMENT:
332 switch (param) {
333 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
334 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
335 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
336 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
337 return 4096;
338 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
339 return 0;
340 case PIPE_SHADER_CAP_MAX_INPUTS:
341 return 8; /* should be possible to do 10 with nv4x */
342 case PIPE_SHADER_CAP_MAX_OUTPUTS:
343 return 4;
344 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
345 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
346 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
347 return 1;
348 case PIPE_SHADER_CAP_MAX_TEMPS:
349 return 32;
350 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
351 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
352 return 16;
353 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
354 return 32;
355 case PIPE_SHADER_CAP_PREFERRED_IR:
356 return PIPE_SHADER_IR_TGSI;
357 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
358 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
359 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
360 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
361 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
362 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
363 case PIPE_SHADER_CAP_SUBROUTINES:
364 case PIPE_SHADER_CAP_INTEGERS:
365 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
366 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
367 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
368 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
369 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
370 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
371 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
372 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
373 return 0;
374 default:
375 debug_printf("unknown fragment shader param %d\n", param);
376 return 0;
377 }
378 break;
379 default:
380 return 0;
381 }
382 }
383
384 static boolean
385 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
386 enum pipe_format format,
387 enum pipe_texture_target target,
388 unsigned sample_count,
389 unsigned bindings)
390 {
391 if (sample_count > nv30_screen(pscreen)->max_sample_count)
392 return false;
393
394 if (!(0x00000017 & (1 << sample_count)))
395 return false;
396
397 if (!util_format_is_supported(format, bindings)) {
398 return false;
399 }
400
401 /* shared is always supported */
402 bindings &= ~PIPE_BIND_SHARED;
403
404 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
405 }
406
407 static void
408 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
409 {
410 struct nv30_screen *screen = nv30_screen(pscreen);
411 struct nouveau_pushbuf *push = screen->base.pushbuf;
412
413 *sequence = ++screen->base.fence.sequence;
414
415 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
416 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
417 (2 /* size */ << 18) | (7 /* subchan */ << 13));
418 PUSH_DATA (push, 0);
419 PUSH_DATA (push, *sequence);
420 }
421
422 static uint32_t
423 nv30_screen_fence_update(struct pipe_screen *pscreen)
424 {
425 struct nv30_screen *screen = nv30_screen(pscreen);
426 struct nv04_notify *fence = screen->fence->data;
427 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
428 }
429
430 static void
431 nv30_screen_destroy(struct pipe_screen *pscreen)
432 {
433 struct nv30_screen *screen = nv30_screen(pscreen);
434
435 if (!nouveau_drm_screen_unref(&screen->base))
436 return;
437
438 if (screen->base.fence.current) {
439 struct nouveau_fence *current = NULL;
440
441 /* nouveau_fence_wait will create a new current fence, so wait on the
442 * _current_ one, and remove both.
443 */
444 nouveau_fence_ref(screen->base.fence.current, &current);
445 nouveau_fence_wait(current, NULL);
446 nouveau_fence_ref(NULL, &current);
447 nouveau_fence_ref(NULL, &screen->base.fence.current);
448 }
449
450 nouveau_bo_ref(NULL, &screen->notify);
451
452 nouveau_heap_destroy(&screen->query_heap);
453 nouveau_heap_destroy(&screen->vp_exec_heap);
454 nouveau_heap_destroy(&screen->vp_data_heap);
455
456 nouveau_object_del(&screen->query);
457 nouveau_object_del(&screen->fence);
458 nouveau_object_del(&screen->ntfy);
459
460 nouveau_object_del(&screen->sifm);
461 nouveau_object_del(&screen->swzsurf);
462 nouveau_object_del(&screen->surf2d);
463 nouveau_object_del(&screen->m2mf);
464 nouveau_object_del(&screen->eng3d);
465 nouveau_object_del(&screen->null);
466
467 nouveau_screen_fini(&screen->base);
468 FREE(screen);
469 }
470
471 #define FAIL_SCREEN_INIT(str, err) \
472 do { \
473 NOUVEAU_ERR(str, err); \
474 screen->base.base.context_create = NULL; \
475 return &screen->base; \
476 } while(0)
477
478 struct nouveau_screen *
479 nv30_screen_create(struct nouveau_device *dev)
480 {
481 struct nv30_screen *screen;
482 struct pipe_screen *pscreen;
483 struct nouveau_pushbuf *push;
484 struct nv04_fifo *fifo;
485 unsigned oclass = 0;
486 int ret, i;
487
488 switch (dev->chipset & 0xf0) {
489 case 0x30:
490 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
491 oclass = NV30_3D_CLASS;
492 else
493 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
494 oclass = NV34_3D_CLASS;
495 else
496 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
497 oclass = NV35_3D_CLASS;
498 break;
499 case 0x40:
500 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
501 oclass = NV40_3D_CLASS;
502 else
503 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
504 oclass = NV44_3D_CLASS;
505 break;
506 case 0x60:
507 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
508 oclass = NV44_3D_CLASS;
509 break;
510 default:
511 break;
512 }
513
514 if (!oclass) {
515 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
516 return NULL;
517 }
518
519 screen = CALLOC_STRUCT(nv30_screen);
520 if (!screen)
521 return NULL;
522
523 pscreen = &screen->base.base;
524 pscreen->destroy = nv30_screen_destroy;
525
526 /*
527 * Some modern apps try to use msaa without keeping in mind the
528 * restrictions on videomem of older cards. Resulting in dmesg saying:
529 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
530 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
531 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
532 *
533 * Because we are running out of video memory, after which the program
534 * using the msaa visual freezes, and eventually the entire system freezes.
535 *
536 * To work around this we do not allow msaa visauls by default and allow
537 * the user to override this via NV30_MAX_MSAA.
538 */
539 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
540 if (screen->max_sample_count > 4)
541 screen->max_sample_count = 4;
542
543 pscreen->get_param = nv30_screen_get_param;
544 pscreen->get_paramf = nv30_screen_get_paramf;
545 pscreen->get_shader_param = nv30_screen_get_shader_param;
546 pscreen->context_create = nv30_context_create;
547 pscreen->is_format_supported = nv30_screen_is_format_supported;
548 nv30_resource_screen_init(pscreen);
549 nouveau_screen_init_vdec(&screen->base);
550
551 screen->base.fence.emit = nv30_screen_fence_emit;
552 screen->base.fence.update = nv30_screen_fence_update;
553
554 ret = nouveau_screen_init(&screen->base, dev);
555 if (ret)
556 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
557
558 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
559 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
560 if (oclass == NV40_3D_CLASS) {
561 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
562 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
563 }
564
565 fifo = screen->base.channel->data;
566 push = screen->base.pushbuf;
567 push->rsvd_kick = 16;
568
569 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
570 NULL, 0, &screen->null);
571 if (ret)
572 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
573
574 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
575 * this means that the address pointed at by the DMA object must
576 * be 4KiB aligned, which means this object needs to be the first
577 * one allocated on the channel.
578 */
579 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
580 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
581 .length = 32 }, sizeof(struct nv04_notify),
582 &screen->fence);
583 if (ret)
584 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
585
586 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
587 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
588 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
589 .length = 32 }, sizeof(struct nv04_notify),
590 &screen->ntfy);
591 if (ret)
592 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
593
594 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
595 * the remainder of the "notifier block" assigned by the kernel for
596 * use as query objects
597 */
598 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
599 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
600 .length = 4096 - 128 }, sizeof(struct nv04_notify),
601 &screen->query);
602 if (ret)
603 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
604
605 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
606 if (ret)
607 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
608
609 LIST_INITHEAD(&screen->queries);
610
611 /* Vertex program resources (code/data), currently 6 of the constant
612 * slots are reserved to implement user clipping planes
613 */
614 if (oclass < NV40_3D_CLASS) {
615 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
616 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
617 } else {
618 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
619 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
620 }
621
622 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
623 if (ret == 0)
624 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
625 if (ret)
626 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
627
628 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
629 NULL, 0, &screen->eng3d);
630 if (ret)
631 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
632
633 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
634 PUSH_DATA (push, screen->eng3d->handle);
635 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
636 PUSH_DATA (push, screen->ntfy->handle);
637 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
638 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
639 PUSH_DATA (push, fifo->vram); /* COLOR1 */
640 PUSH_DATA (push, screen->null->handle); /* UNK190 */
641 PUSH_DATA (push, fifo->vram); /* COLOR0 */
642 PUSH_DATA (push, fifo->vram); /* ZETA */
643 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
644 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
645 PUSH_DATA (push, screen->fence->handle); /* FENCE */
646 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
647 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
648 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
649 if (screen->eng3d->oclass < NV40_3D_CLASS) {
650 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
651 PUSH_DATA (push, 0x00100000);
652 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
653 PUSH_DATA (push, 3);
654
655 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
656 PUSH_DATA (push, 0);
657 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
658 PUSH_DATA (push, fui(0.0));
659 PUSH_DATA (push, fui(0.0));
660 PUSH_DATA (push, fui(1.0));
661 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
662 for (i = 0; i < 16; i++)
663 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
664
665 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
666 PUSH_DATA (push, 0);
667 } else {
668 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
669 PUSH_DATA (push, fifo->vram);
670 PUSH_DATA (push, fifo->vram); /* COLOR3 */
671
672 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
673 PUSH_DATA (push, 0x00000004);
674
675 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
676 PUSH_DATA (push, 0x00000010);
677 PUSH_DATA (push, 0x01000100);
678 PUSH_DATA (push, 0xff800006);
679
680 /* vtxprog output routing */
681 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
682 PUSH_DATA (push, 0x06144321);
683 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
684 PUSH_DATA (push, 0xedcba987);
685 PUSH_DATA (push, 0x0000006f);
686 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
687 PUSH_DATA (push, 0x00171615);
688 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
689 PUSH_DATA (push, 0x001b1a19);
690
691 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
692 PUSH_DATA (push, 0x0020ffff);
693 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
694 PUSH_DATA (push, 0x01d300d4);
695
696 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
697 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
698 }
699
700 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
701 NULL, 0, &screen->m2mf);
702 if (ret)
703 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
704
705 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
706 PUSH_DATA (push, screen->m2mf->handle);
707 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
708 PUSH_DATA (push, screen->ntfy->handle);
709
710 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
711 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
712 if (ret)
713 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
714
715 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
716 PUSH_DATA (push, screen->surf2d->handle);
717 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
718 PUSH_DATA (push, screen->ntfy->handle);
719
720 if (dev->chipset < 0x40)
721 oclass = NV30_SURFACE_SWZ_CLASS;
722 else
723 oclass = NV40_SURFACE_SWZ_CLASS;
724
725 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
726 NULL, 0, &screen->swzsurf);
727 if (ret)
728 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
729
730 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
731 PUSH_DATA (push, screen->swzsurf->handle);
732 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
733 PUSH_DATA (push, screen->ntfy->handle);
734
735 if (dev->chipset < 0x40)
736 oclass = NV30_SIFM_CLASS;
737 else
738 oclass = NV40_SIFM_CLASS;
739
740 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
741 NULL, 0, &screen->sifm);
742 if (ret)
743 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
744
745 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
746 PUSH_DATA (push, screen->sifm->handle);
747 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
748 PUSH_DATA (push, screen->ntfy->handle);
749 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
750 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
751
752 nouveau_pushbuf_kick(push, push->channel);
753
754 nouveau_fence_new(&screen->base, &screen->base.fence.current);
755 return &screen->base;
756 }