src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  95    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  96    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  99       return 1;
 100    /* nv35 capabilities */
 101    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 102       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 103    /* nv4x capabilities */
 104    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 105    case PIPE_CAP_NPOT_TEXTURES:
 106    case PIPE_CAP_CONDITIONAL_RENDER:
 107    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 108    case PIPE_CAP_PRIMITIVE_RESTART:
 109       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 110    /* unsupported */
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112    case PIPE_CAP_SM3:
 113    case PIPE_CAP_INDEP_BLEND_ENABLE:
 114    case PIPE_CAP_INDEP_BLEND_FUNC:
 115    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 116    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 117    case PIPE_CAP_TGSI_INSTANCEID:
 118    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 162    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 163    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_CLIP_HALFZ:
 166    case PIPE_CAP_VERTEXID_NOBASE:
 167    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_TGSI_TXQS:
 175    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 176    case PIPE_CAP_SHAREABLE_SHADERS:
 177    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 178    case PIPE_CAP_CLEAR_TEXTURE:
 179    case PIPE_CAP_DRAW_PARAMETERS:
 180    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 181    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 182    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 183    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184    case PIPE_CAP_INVALIDATE_BUFFER:
 185    case PIPE_CAP_GENERATE_MIPMAP:
 186    case PIPE_CAP_STRING_MARKER:
 187    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 188    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 189    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 190    case PIPE_CAP_QUERY_MEMORY_INFO:
 191    case PIPE_CAP_PCI_GROUP:
 192    case PIPE_CAP_PCI_BUS:
 193    case PIPE_CAP_PCI_DEVICE:
 194    case PIPE_CAP_PCI_FUNCTION:
 195    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 196    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 197    case PIPE_CAP_CULL_DISTANCE:
 198    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 199    case PIPE_CAP_TGSI_VOTE:
 200    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 201    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 202    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 203    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 204    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 205    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 206    case PIPE_CAP_NATIVE_FENCE_FD:
 207    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 208    case PIPE_CAP_TGSI_FS_FBFETCH:
 209    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 210    case PIPE_CAP_DOUBLES:
 211    case PIPE_CAP_INT64:
 212    case PIPE_CAP_INT64_DIVMOD:
 213    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 214    case PIPE_CAP_TGSI_CLOCK:
 215       return 0;
 216
 217    case PIPE_CAP_VENDOR_ID:
 218       return 0x10de;
 219    case PIPE_CAP_DEVICE_ID: {
 220       uint64_t device_id;
 221       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 222          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 223          return -1;
 224       }
 225       return device_id;
 226    }
 227    case PIPE_CAP_ACCELERATED:
 228       return 1;
 229    case PIPE_CAP_VIDEO_MEMORY:
 230       return dev->vram_size >> 20;
 231    case PIPE_CAP_UMA:
 232       return 0;
 233    }
 234
 235    debug_printf("unknown param %d\n", param);
 236    return 0;
 237 }
 238
 239 static float
 240 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 241 {
 242    struct nv30_screen *screen = nv30_screen(pscreen);
 243    struct nouveau_object *eng3d = screen->eng3d;
 244
 245    switch (param) {
 246    case PIPE_CAPF_MAX_LINE_WIDTH:
 247    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 248       return 10.0;
 249    case PIPE_CAPF_MAX_POINT_WIDTH:
 250    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 251       return 64.0;
 252    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 253       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 254    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 255       return 15.0;
 256    default:
 257       debug_printf("unknown paramf %d\n", param);
 258       return 0;
 259    }
 260 }
 261
 262 static int
 263 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
 264                              enum pipe_shader_type shader,
 265                              enum pipe_shader_cap param)
 266 {
 267    struct nv30_screen *screen = nv30_screen(pscreen);
 268    struct nouveau_object *eng3d = screen->eng3d;
 269
 270    switch (shader) {
 271    case PIPE_SHADER_VERTEX:
 272       switch (param) {
 273       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 274       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 275          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 276       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 277       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 278          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 279       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 280          return 0;
 281       case PIPE_SHADER_CAP_MAX_INPUTS:
 282       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 283          return 16;
 284       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 285          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 286       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 287          return 1;
 288       case PIPE_SHADER_CAP_MAX_TEMPS:
 289          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 290       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 291          return 32;
 292       case PIPE_SHADER_CAP_PREFERRED_IR:
 293          return PIPE_SHADER_IR_TGSI;
 294       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 295       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 296          return 0;
 297       case PIPE_SHADER_CAP_MAX_PREDS:
 298       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 299       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 300       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 301       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 302       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 303       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 304       case PIPE_SHADER_CAP_SUBROUTINES:
 305       case PIPE_SHADER_CAP_INTEGERS:
 306       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 307       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 308       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 309       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 310       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 311       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 312       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 313          return 0;
 314       default:
 315          debug_printf("unknown vertex shader param %d\n", param);
 316          return 0;
 317       }
 318       break;
 319    case PIPE_SHADER_FRAGMENT:
 320       switch (param) {
 321       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 322       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 323       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 324       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 325          return 4096;
 326       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 327          return 0;
 328       case PIPE_SHADER_CAP_MAX_INPUTS:
 329          return 8; /* should be possible to do 10 with nv4x */
 330       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 331          return 4;
 332       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 333          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 334       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 335          return 1;
 336       case PIPE_SHADER_CAP_MAX_TEMPS:
 337          return 32;
 338       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 339       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 340          return 16;
 341       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 342          return 32;
 343       case PIPE_SHADER_CAP_PREFERRED_IR:
 344          return PIPE_SHADER_IR_TGSI;
 345       case PIPE_SHADER_CAP_MAX_PREDS:
 346       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 347       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 348       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 349       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 350       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 351       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 352       case PIPE_SHADER_CAP_SUBROUTINES:
 353       case PIPE_SHADER_CAP_INTEGERS:
 354       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 355       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 356       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 357       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 358       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 359       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 360       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 361          return 0;
 362       default:
 363          debug_printf("unknown fragment shader param %d\n", param);
 364          return 0;
 365       }
 366       break;
 367    default:
 368       return 0;
 369    }
 370 }
 371
 372 static boolean
 373 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 374                                 enum pipe_format format,
 375                                 enum pipe_texture_target target,
 376                                 unsigned sample_count,
 377                                 unsigned bindings)
 378 {
 379    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 380       return false;
 381
 382    if (!(0x00000017 & (1 << sample_count)))
 383       return false;
 384
 385    if (!util_format_is_supported(format, bindings)) {
 386       return false;
 387    }
 388
 389    /* shared is always supported */
 390    bindings &= ~PIPE_BIND_SHARED;
 391
 392    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 393 }
 394
 395 static void
 396 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 397 {
 398    struct nv30_screen *screen = nv30_screen(pscreen);
 399    struct nouveau_pushbuf *push = screen->base.pushbuf;
 400
 401    *sequence = ++screen->base.fence.sequence;
 402
 403    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 404    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 405               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 406    PUSH_DATA (push, 0);
 407    PUSH_DATA (push, *sequence);
 408 }
 409
 410 static uint32_t
 411 nv30_screen_fence_update(struct pipe_screen *pscreen)
 412 {
 413    struct nv30_screen *screen = nv30_screen(pscreen);
 414    struct nv04_notify *fence = screen->fence->data;
 415    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 416 }
 417
 418 static void
 419 nv30_screen_destroy(struct pipe_screen *pscreen)
 420 {
 421    struct nv30_screen *screen = nv30_screen(pscreen);
 422
 423    if (!nouveau_drm_screen_unref(&screen->base))
 424       return;
 425
 426    if (screen->base.fence.current) {
 427       struct nouveau_fence *current = NULL;
 428
 429       /* nouveau_fence_wait will create a new current fence, so wait on the
 430        * _current_ one, and remove both.
 431        */
 432       nouveau_fence_ref(screen->base.fence.current, &current);
 433       nouveau_fence_wait(current, NULL);
 434       nouveau_fence_ref(NULL, &current);
 435       nouveau_fence_ref(NULL, &screen->base.fence.current);
 436    }
 437
 438    nouveau_bo_ref(NULL, &screen->notify);
 439
 440    nouveau_heap_destroy(&screen->query_heap);
 441    nouveau_heap_destroy(&screen->vp_exec_heap);
 442    nouveau_heap_destroy(&screen->vp_data_heap);
 443
 444    nouveau_object_del(&screen->query);
 445    nouveau_object_del(&screen->fence);
 446    nouveau_object_del(&screen->ntfy);
 447
 448    nouveau_object_del(&screen->sifm);
 449    nouveau_object_del(&screen->swzsurf);
 450    nouveau_object_del(&screen->surf2d);
 451    nouveau_object_del(&screen->m2mf);
 452    nouveau_object_del(&screen->eng3d);
 453    nouveau_object_del(&screen->null);
 454
 455    nouveau_screen_fini(&screen->base);
 456    FREE(screen);
 457 }
 458
 459 #define FAIL_SCREEN_INIT(str, err)                    \
 460    do {                                               \
 461       NOUVEAU_ERR(str, err);                          \
 462       screen->base.base.context_create = NULL;        \
 463       return &screen->base;                           \
 464    } while(0)
 465
 466 struct nouveau_screen *
 467 nv30_screen_create(struct nouveau_device *dev)
 468 {
 469    struct nv30_screen *screen;
 470    struct pipe_screen *pscreen;
 471    struct nouveau_pushbuf *push;
 472    struct nv04_fifo *fifo;
 473    unsigned oclass = 0;
 474    int ret, i;
 475
 476    switch (dev->chipset & 0xf0) {
 477    case 0x30:
 478       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 479          oclass = NV30_3D_CLASS;
 480       else
 481       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 482          oclass = NV34_3D_CLASS;
 483       else
 484       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 485          oclass = NV35_3D_CLASS;
 486       break;
 487    case 0x40:
 488       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 489          oclass = NV40_3D_CLASS;
 490       else
 491       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 492          oclass = NV44_3D_CLASS;
 493       break;
 494    case 0x60:
 495       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 496          oclass = NV44_3D_CLASS;
 497       break;
 498    default:
 499       break;
 500    }
 501
 502    if (!oclass) {
 503       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 504       return NULL;
 505    }
 506
 507    screen = CALLOC_STRUCT(nv30_screen);
 508    if (!screen)
 509       return NULL;
 510
 511    pscreen = &screen->base.base;
 512    pscreen->destroy = nv30_screen_destroy;
 513
 514    /*
 515     * Some modern apps try to use msaa without keeping in mind the
 516     * restrictions on videomem of older cards. Resulting in dmesg saying:
 517     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 518     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 519     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 520     *
 521     * Because we are running out of video memory, after which the program
 522     * using the msaa visual freezes, and eventually the entire system freezes.
 523     *
 524     * To work around this we do not allow msaa visauls by default and allow
 525     * the user to override this via NV30_MAX_MSAA.
 526     */
 527    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 528    if (screen->max_sample_count > 4)
 529       screen->max_sample_count = 4;
 530
 531    pscreen->get_param = nv30_screen_get_param;
 532    pscreen->get_paramf = nv30_screen_get_paramf;
 533    pscreen->get_shader_param = nv30_screen_get_shader_param;
 534    pscreen->context_create = nv30_context_create;
 535    pscreen->is_format_supported = nv30_screen_is_format_supported;
 536    nv30_resource_screen_init(pscreen);
 537    nouveau_screen_init_vdec(&screen->base);
 538
 539    screen->base.fence.emit = nv30_screen_fence_emit;
 540    screen->base.fence.update = nv30_screen_fence_update;
 541
 542    ret = nouveau_screen_init(&screen->base, dev);
 543    if (ret)
 544       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 545
 546    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 547    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 548    if (oclass == NV40_3D_CLASS) {
 549       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 550       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 551    }
 552
 553    fifo = screen->base.channel->data;
 554    push = screen->base.pushbuf;
 555    push->rsvd_kick = 16;
 556
 557    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 558                             NULL, 0, &screen->null);
 559    if (ret)
 560       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 561
 562    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 563     * this means that the address pointed at by the DMA object must
 564     * be 4KiB aligned, which means this object needs to be the first
 565     * one allocated on the channel.
 566     */
 567    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 568                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 569                             .length = 32 }, sizeof(struct nv04_notify),
 570                             &screen->fence);
 571    if (ret)
 572       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 573
 574    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 575    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 576                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 577                             .length = 32 }, sizeof(struct nv04_notify),
 578                             &screen->ntfy);
 579    if (ret)
 580       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 581
 582    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 583     * the remainder of the "notifier block" assigned by the kernel for
 584     * use as query objects
 585     */
 586    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 587                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 588                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 589                             &screen->query);
 590    if (ret)
 591       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 592
 593    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 594    if (ret)
 595       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 596
 597    LIST_INITHEAD(&screen->queries);
 598
 599    /* Vertex program resources (code/data), currently 6 of the constant
 600     * slots are reserved to implement user clipping planes
 601     */
 602    if (oclass < NV40_3D_CLASS) {
 603       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 604       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 605    } else {
 606       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 607       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 608    }
 609
 610    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 611    if (ret == 0)
 612       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 613    if (ret)
 614       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 615
 616    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 617                             NULL, 0, &screen->eng3d);
 618    if (ret)
 619       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 620
 621    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 622    PUSH_DATA (push, screen->eng3d->handle);
 623    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 624    PUSH_DATA (push, screen->ntfy->handle);
 625    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 626    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 627    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 628    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 629    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 630    PUSH_DATA (push, fifo->vram);     /* ZETA */
 631    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 632    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 633    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 634    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 635    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 636    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 637    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 638       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 639       PUSH_DATA (push, 0x00100000);
 640       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 641       PUSH_DATA (push, 3);
 642
 643       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 644       PUSH_DATA (push, 0);
 645       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 646       PUSH_DATA (push, fui(0.0));
 647       PUSH_DATA (push, fui(0.0));
 648       PUSH_DATA (push, fui(1.0));
 649       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 650       for (i = 0; i < 16; i++)
 651          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 652
 653       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 654       PUSH_DATA (push, 0);
 655    } else {
 656       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 657       PUSH_DATA (push, fifo->vram);
 658       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 659
 660       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 661       PUSH_DATA (push, 0x00000004);
 662
 663       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 664       PUSH_DATA (push, 0x00000010);
 665       PUSH_DATA (push, 0x01000100);
 666       PUSH_DATA (push, 0xff800006);
 667
 668       /* vtxprog output routing */
 669       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 670       PUSH_DATA (push, 0x06144321);
 671       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 672       PUSH_DATA (push, 0xedcba987);
 673       PUSH_DATA (push, 0x0000006f);
 674       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 675       PUSH_DATA (push, 0x00171615);
 676       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 677       PUSH_DATA (push, 0x001b1a19);
 678
 679       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 680       PUSH_DATA (push, 0x0020ffff);
 681       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 682       PUSH_DATA (push, 0x01d300d4);
 683
 684       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 685       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 686    }
 687
 688    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 689                             NULL, 0, &screen->m2mf);
 690    if (ret)
 691       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 692
 693    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 694    PUSH_DATA (push, screen->m2mf->handle);
 695    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 696    PUSH_DATA (push, screen->ntfy->handle);
 697
 698    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 699                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 700    if (ret)
 701       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 702
 703    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 704    PUSH_DATA (push, screen->surf2d->handle);
 705    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 706    PUSH_DATA (push, screen->ntfy->handle);
 707
 708    if (dev->chipset < 0x40)
 709       oclass = NV30_SURFACE_SWZ_CLASS;
 710    else
 711       oclass = NV40_SURFACE_SWZ_CLASS;
 712
 713    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 714                             NULL, 0, &screen->swzsurf);
 715    if (ret)
 716       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 717
 718    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 719    PUSH_DATA (push, screen->swzsurf->handle);
 720    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 721    PUSH_DATA (push, screen->ntfy->handle);
 722
 723    if (dev->chipset < 0x40)
 724       oclass = NV30_SIFM_CLASS;
 725    else
 726       oclass = NV40_SIFM_CLASS;
 727
 728    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 729                             NULL, 0, &screen->sifm);
 730    if (ret)
 731       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 732
 733    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 734    PUSH_DATA (push, screen->sifm->handle);
 735    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 736    PUSH_DATA (push, screen->ntfy->handle);
 737    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 738    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 739
 740    nouveau_pushbuf_kick(push, push->channel);
 741
 742    nouveau_fence_new(&screen->base, &screen->base.fence.current);
 743    return &screen->base;
 744 }